Manufacturing method of heterojunction bipolar transistor (HBT) device

Abstract

The invention discloses a manufacturing method of an HBT (Heterojunction Bipolar Transistor) device, which comprises the following steps of: providing a substrate, forming an isolating layer in the substrate, forming a first dielectric layer on the substrate and the isolating layer, forming a first polycrystalline silicon layer on the first dielectric layer, forming a second dielectric layer on the first polycrystalline silicon layer, and forming a third dielectric layer on the second dielectric layer, a fourth dielectric layer is formed on the third dielectric layer; the first polycrystalline silicon layer, the second dielectric layer, the third dielectric layer and the fourth dielectric layer of the first target region form a first groove in the first target region; forming a fifth dielectric layer on the side wall of the first groove; the fourth dielectric layer and the first dielectric layer below the first groove are removed, a second groove is formed below the first groove, the substrate at the bottom of the second groove is exposed, and the width of the second groove is larger than that of the first groove; growing a monocrystalline silicon layer in the second groove; removing the fifth dielectric layer on the side wall of the first groove; and filling a germanium-silicon layer in the first groove and the second groove.

Description

Technical Field

[0001] The present application relates to the technical field of semiconductor devices and integrated circuits, and in particular to a method for manufacturing an HBT device. Background Art

[0002] Since traditional silicon (Si) material devices cannot meet the high performance and low cost requirements of radio frequency (RF) modules in the high frequency band in the modern communication field, and in order to be compatible with traditional silicon processing technology and reduce manufacturing costs, people have proposed silicon germanium (SiGe) / silicon devices. Among them, silicon germanium heterojunction bipolar transistor (HBT) devices have been widely used and studied because their high-frequency performance is better than that of silicon bipolar junction transistor (BJT) devices.

[0003] The related technology provides a SiGe HBT device manufactured based on a double-layer polysilicon self-aligned process. Devices using this structure have high requirements for silicon germanium epitaxial technology, and the external base connection area of ​​devices of this type of structure has two opposite directions of epitaxial growth during silicon germanium epitaxy, which easily forms pitting defects, thereby reducing the reliability and yield of the product. Summary of the invention

[0004] The present application provides a method for manufacturing an HBT device, which can solve the problem of void defects in SiGe HBT devices manufactured based on a double-layer polysilicon self-aligned process provided in the related art. The method comprises:

[0005] A substrate is provided, wherein an isolation layer is formed in the substrate, a first dielectric layer is formed on the substrate and the isolation layer, a first polysilicon layer is formed on the first dielectric layer, a second dielectric layer is formed on the first polysilicon layer, a third dielectric layer is formed on the second dielectric layer, a fourth dielectric layer is formed on the third dielectric layer, the first dielectric layer, the second dielectric layer and the fourth dielectric layer are formed of the same material, and the first dielectric layer and the third dielectric layer are formed of different materials;

[0006] Removing a first polysilicon layer, a second dielectric layer, a third dielectric layer, and a fourth dielectric layer in a first target area to form a first trench in the first target area, wherein the first target area is located in an area surrounded by the inner layer of the isolation layer;

[0007] forming a fifth dielectric layer on the sidewall of the first trench, wherein the fifth dielectric layer and the third dielectric layer are made of the same material;

[0008] removing the fourth dielectric layer and the first dielectric layer below the first trench, forming a second trench below the first trench, exposing the substrate at the bottom of the second trench, and having a width greater than that of the first trench;

[0009] Growing a single crystal silicon layer in the second trench and performing ion implantation on the single crystal silicon layer, wherein a top of the grown single crystal silicon layer is lower than an opening of the second trench;

[0010] removing the fifth dielectric layer on the sidewall of the first trench;

[0011] A silicon germanium layer is filled in the first trench and the second trench.

[0012] In some embodiments, the first dielectric layer, the second dielectric layer, and the fourth dielectric layer include silicon dioxide layers.

[0013] In some embodiments, the third dielectric layer and the fifth dielectric layer include silicon nitride layers.

[0014] In some embodiments, removing the fourth dielectric layer and the first dielectric layer below the first trench includes:

[0015] The fourth dielectric layer and the first dielectric layer under the first trench are removed by a wet etching process.

[0016] In some embodiments, removing the fifth dielectric layer from the sidewall of the first trench includes:

[0017] The fifth dielectric layer on the sidewall of the first trench is removed by a wet etching process.

[0018] In some embodiments, after filling the first trench and the second trench with a silicon germanium layer, the method further includes:

[0019] forming a sixth dielectric layer and a second polysilicon layer in sequence, wherein the sixth dielectric layer and the first dielectric layer are made of the same material;

[0020] removing the sixth dielectric layer and the second polysilicon layer above the third dielectric layer and above the germanium silicon layer;

[0021] forming a third polysilicon layer and a seventh dielectric layer in sequence, wherein the seventh dielectric layer and the first dielectric layer are made of the same material;

[0022] removing the third dielectric layer, the third polysilicon layer and the seventh dielectric layer in areas other than the second target area, wherein the second target area is located in the area surrounded by the inner layer of the isolation layer;

[0023] removing the first polysilicon layer and the first dielectric layer of a predetermined depth in other regions except a third target region, wherein the third target region is located in the region surrounded by the outer layer of the isolation layer, and the width of the third target region is greater than the width of the second target region;

[0024] The remaining seventh dielectric layer, the second dielectric layer in the areas other than the second target area, and the first dielectric layer in the areas other than the third target area are removed.

[0025] In some embodiments, removing the sixth dielectric layer and the second polysilicon layer above the third dielectric layer and above the germanium silicon layer comprises:

[0026] removing the second polysilicon layer above the sixth dielectric layer and above the germanium silicon layer by a dry etching process;

[0027] The sixth dielectric layer above the third dielectric layer and above the germanium silicon layer is removed by a wet etching process.

[0028] The technical solution of this application has at least the following advantages:

[0029] During the manufacturing process of the HBT device, a trench for filling the germanium silicon layer is formed by etching in the dielectric layer on the surface of the substrate, and then a portion of single crystal silicon is grown in the trench to form a main collector region. Then, the dielectric layer on the peripheral side of the trench is removed, and then the germanium silicon layer is filled in the trench. This filling method can reduce the difficulty of filling the germanium silicon layer, reduce the formation of voids, and improve the reliability and yield of the product to a certain extent. At the same time, the formed HBT device has a smaller connection resistance between the external base region and the base region structure because the germanium silicon layer is laterally connected to the peripheral polysilicon layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0031] Figure 1 is a flow chart of a method for manufacturing an HBT device provided by an exemplary embodiment of the present application;

[0032] Figures 2 to 7 is a schematic diagram of a manufacturing process of an HBT device provided by an exemplary embodiment of the present application;

[0033] Figure 8is a flow chart of a method for manufacturing an HBT device provided by an exemplary embodiment of the present application;

[0034] Figures 9 to 14 It is a schematic diagram of the manufacturing process of an HBT device provided by an exemplary embodiment of the present application. DETAILED DESCRIPTION

[0035] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in this application. Obviously, the described embodiments are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0036] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present application. In addition, the terms "first", "second", and "third" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.

[0037] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, it can also be the internal connection of two components, it can be a wireless connection, or it can be a wired connection. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0038] In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.

[0039] refer to Figure 1 , which shows a flow chart of a method for manufacturing an HBT device provided by an exemplary embodiment of the present application, such as Figure 1 As shown, the method includes:

[0040] Step S11, providing a substrate, in which an isolation layer is formed, a first dielectric layer is formed on the substrate and the isolation layer, a first polysilicon layer is formed on the first dielectric layer, a second dielectric layer is formed on the first polysilicon layer, a third dielectric layer is formed on the second dielectric layer, a fourth dielectric layer is formed on the third dielectric layer, the first dielectric layer, the second dielectric layer and the fourth dielectric layer are formed of the same material, and the first dielectric layer and the third dielectric layer are formed of different materials.

[0041] Step S12, removing the first polysilicon layer, the second dielectric layer, the third dielectric layer and the fourth dielectric layer in the first target area, forming a first trench in the first target area, and the first target area is located in the area surrounded by the inner layer of the isolation layer.

[0042] refer to Figure 2 , which shows a cross-sectional schematic diagram after the first groove is formed. Figure 2 As shown, an isolation layer 211 is formed in the substrate 210, a first dielectric layer 221 is formed on the substrate 210 and the isolation layer 211, a first polysilicon layer 231 is formed on the first dielectric layer 221, a second dielectric layer 222 is formed on the first polysilicon layer 231, a third dielectric layer 241 is formed on the second dielectric layer 222, and a fourth dielectric layer 223 is formed on the third dielectric layer 241. The first polysilicon layer 231, the second dielectric layer 222, the third dielectric layer 241 and the fourth dielectric layer 223 in the first target area (the area corresponding to the first trench 301) can be etched and removed by a photolithography process to form a first trench 301.

[0043] Among them, the first dielectric layer 221, the second dielectric layer 222 and the fourth dielectric layer 223 are made of the same material, and the first dielectric layer 221 and the third dielectric layer 241 are made of different materials. From a top-down perspective, the isolation layer 211 is in the shape of a ring (which can be a rectangular ring, an elliptical ring, a ring-shaped ring or an irregular ring), and the area surrounded by it includes an area surrounded by an inner layer and an area surrounded by an outer layer; optionally, the first dielectric layer 221, the second dielectric layer 222 and the fourth dielectric layer 223 include a silicon dioxide (SiO2) layer, and the third dielectric layer 241 includes a silicon nitride (Si3N4) layer.

[0044] Step S13, forming a fifth dielectric layer on the sidewall of the first trench, wherein the fifth dielectric layer and the third dielectric layer are made of the same material.

[0045] refer to Figure 3 , which shows a cross-sectional schematic diagram of forming a fifth dielectric layer on the sidewall of the first trench. Figure 3As shown, the fifth dielectric layer 242 may include a silicon nitride layer, which may be deposited by a chemical vapor deposition (CVD) process, and the silicon nitride layer above the fourth dielectric layer 223 and at the bottom of the trench may be removed by a dry etching process.

[0046] Step S14, removing the fourth dielectric layer and the first dielectric layer below the first trench, forming a second trench below the first trench, exposing the substrate at the bottom of the second trench, and having a width greater than that of the first trench.

[0047] refer to Figure 4 , which shows a cross-sectional schematic diagram after the second groove is formed. Figure 4 As shown, the fourth dielectric layer 223 and the first dielectric layer 221 under the first trench 301 can be removed by a wet etching process, so that a second trench 302 is formed under the first trench 301. Since the wet etching process is isotropic, it has a lateral etching rate during etching, and the width of the formed second trench 302 is greater than the width of the first trench 301. Due to the protection of the fifth dielectric layer 242, the sidewall of the first trench 301 will not be etched.

[0048] Step S15, growing a single crystal silicon layer in the second trench and performing ion implantation on the single crystal silicon layer, wherein the top of the grown single crystal silicon layer is lower than the opening of the second trench.

[0049] refer to Figure 5 , which shows a cross-sectional schematic diagram after a single crystal silicon layer is grown in the second trench and ion implanted into the single crystal silicon layer. Figure 5 As shown, a single crystal silicon layer 212 may be grown by a selective epitaxial growth (SEG) process and ion implanted into the single crystal silicon layer 212 to form a main collector region of the HBT device.

[0050] Step S16, removing the fifth dielectric layer on the sidewall of the first trench.

[0051] refer to Figure 6 , which shows a cross-sectional schematic diagram of the fifth dielectric layer after the sidewall of the first trench is removed. Figure 6 As shown, the fifth dielectric layer 242 on the sidewall of the first trench can be removed by a wet etching process, and after the wet etching, the third dielectric layer 241 is thinned.

[0052] Step S17, filling the first trench and the second trench with a silicon germanium layer.

[0053] refer to Figure 7 , which shows a cross-sectional schematic diagram after the first trench and the second trench are filled with a germanium silicon layer. Figure 7 As shown, the silicon germanium layer 250 can be filled by the SEG process, and the filled silicon germanium layer 250 is laterally connected to the first polysilicon layer 231 on both sides. Since single crystal silicon filling is performed in step S5 and the fifth dielectric layer of the side wall is removed in step S6, the side wall of the filled area is smoother and more vertical, so the area of ​​epitaxial growth from bottom to top in the vertical direction can be reduced, thereby reducing the probability of void formation.

[0054] To summarize, in the embodiment of the present application, during the manufacturing process of the HBT device, a groove for filling the germanium silicon layer is formed by etching in the dielectric layer on the surface of the substrate, and then a portion of single crystal silicon is grown in the groove to form a main collector region, and then the dielectric layer on the peripheral side of the groove is removed, and then the germanium silicon layer is filled in the groove. This filling method can reduce the difficulty of filling the germanium silicon layer, reduce the formation of voids, and improve the reliability and yield of the product to a certain extent. At the same time, the formed HBT device has a smaller connection resistance between the external base region and the base region structure because the germanium silicon layer is laterally connected to the peripheral polysilicon layer.

[0055] refer to Figure 8 , which shows a flow chart of a method for manufacturing an HBT device provided by an exemplary embodiment of the present application, which method can be Figure 1 The method performed after step S17 in the embodiment is as follows: Figure 8 As shown, the method includes:

[0056] Step S81 , forming a sixth dielectric layer and a second polysilicon layer in sequence, wherein the sixth dielectric layer and the first dielectric layer are made of the same material.

[0057] refer to Fig. 9 , which shows a cross-sectional schematic diagram after forming the sixth dielectric layer and the second polysilicon layer. Fig. 9 As shown, the sixth dielectric layer 223 may include a silicon dioxide layer, and the silicon dioxide layer may be deposited by a CVD process to form the sixth dielectric layer 223 , and the second polysilicon layer 232 may be formed by furnace deposition.

[0058] Step S82 , removing the sixth dielectric layer and the second polysilicon layer above the third dielectric layer and above the germanium silicon layer.

[0059] Exemplarily, step S82 includes but is not limited to: removing the second polysilicon layer above the sixth dielectric layer and above the germanium silicon layer by a dry etching process; and removing the sixth dielectric layer above the third dielectric layer and above the germanium silicon layer by a wet etching process.

[0060] refer to Fig.10 , which shows a cross-sectional schematic diagram after the second polysilicon layer above the sixth dielectric layer and the second polysilicon layer above the germanium silicon layer is removed by a dry etching process, for example, Fig.10 As shown, after the dry etching process, the second polysilicon layer 232 above the sixth dielectric layer 224 and the second polysilicon layer 232 above the silicon germanium layer 250 are removed.

[0061] refer to Fig.11 , which shows a cross-sectional schematic diagram after the sixth dielectric layer above the third dielectric layer and above the germanium silicon layer is removed by a wet etching process, exemplarily, as Fig.11 As shown, after wet etching, the sixth dielectric layer 224 above the third dielectric layer 241 and above the silicon germanium layer 250 is removed, and the remaining sixth dielectric layer 224 is located on the sidewall of the first polysilicon layer 231, and its cross section is L-shaped.

[0062] Step S83, forming a third polysilicon layer and a seventh dielectric layer in sequence, wherein the seventh dielectric layer and the first dielectric layer are made of the same material.

[0063] Step S84, removing the third dielectric layer, the third polysilicon layer and the seventh dielectric layer in areas other than the second target area, wherein the second target area is located in the area surrounded by the inner layer of the isolation layer.

[0064] refer to Fig.12 , which shows a cross-sectional schematic diagram after removing the third dielectric layer, the fourth dielectric layer, the third polysilicon layer and the seventh dielectric layer in areas other than the second target area. Fig.12 As shown, the third polysilicon layer 233 can be formed by deposition in a furnace tube, the seventh dielectric layer 225 can include a silicon dioxide layer, the silicon dioxide layer can be deposited by a PVD process to form the seventh dielectric layer 225, and the third dielectric layer 241, the third polysilicon layer 233 and the seventh dielectric layer 245 in areas other than the second target area can be etched away by a photolithography process, and the etching stops at the second dielectric layer 222.

[0065] Step S85, removing the first polysilicon layer and the first dielectric layer of a predetermined depth in areas other than the third target area, the third target area is located in the area surrounded by the outer layer of the isolation layer, and the width of the third target area is greater than that of the second target area.

[0066] refer to Fig.13 , which shows a cross-sectional schematic diagram after removing the first polysilicon layer in other areas except the third target area and the first dielectric layer at a predetermined depth. Fig.13 As shown, the first polysilicon layer 231 in other regions except the third target region and the first dielectric layer 221 at a predetermined depth can be etched away by a photolithography process, and the etching stops at a predetermined depth in the first dielectric layer 221 .

[0067] Step S86, removing the remaining seventh dielectric layer, the second dielectric layer in areas other than the second target area, and the first dielectric layer in areas other than the third target area.

[0068] refer to Fig.14 , which shows a cross-sectional schematic diagram after removing the remaining seventh dielectric layer, the second dielectric layer in areas other than the second target area, and the first dielectric layer in areas other than the third target area, for example, Fig.14 As shown, the remaining seventh dielectric layer 245 , the second dielectric layer 222 in areas other than the second target area, and the first dielectric layer 221 in areas other than the third target area may be removed by a wet etching process.

[0069] Obviously, the above embodiments are merely examples for the purpose of clear explanation, and are not intended to limit the implementation methods. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived therefrom are still within the scope of protection created by this application.

Claims

1. A method for manufacturing a HBT device, characterized in that: include: A substrate is provided, wherein an isolation layer is formed in the substrate, a first dielectric layer is formed on the substrate and the isolation layer, a first polysilicon layer is formed on the first dielectric layer, a second dielectric layer is formed on the first polysilicon layer, a third dielectric layer is formed on the second dielectric layer, a fourth dielectric layer is formed on the third dielectric layer, the first dielectric layer, the second dielectric layer and the fourth dielectric layer are formed of the same material, and the first dielectric layer and the third dielectric layer are formed of different materials; Removing a first polysilicon layer, a second dielectric layer, a third dielectric layer, and a fourth dielectric layer in a first target area to form a first trench in the first target area, wherein the first target area is located in an area surrounded by the inner layer of the isolation layer; forming a fifth dielectric layer on the sidewall of the first trench, wherein the fifth dielectric layer and the third dielectric layer are made of the same material; removing the fourth dielectric layer and the first dielectric layer below the first trench, forming a second trench below the first trench, exposing the substrate at the bottom of the second trench, and having a width greater than that of the first trench; Growing a single crystal silicon layer in the second trench and performing ion implantation on the single crystal silicon layer, wherein a top of the grown single crystal silicon layer is lower than an opening of the second trench; removing the fifth dielectric layer on the sidewall of the first trench; A silicon germanium layer is filled in the first trench and the second trench.

2. The method according to claim 1, characterized in that The first dielectric layer, the second dielectric layer, and the fourth dielectric layer include silicon dioxide layers.

3. The method according to claim 2, characterized in that The third dielectric layer and the fifth dielectric layer include silicon nitride layers.

4. The method according to claim 3, characterized in that The removing the fourth dielectric layer and the first dielectric layer below the first trench comprises: The fourth dielectric layer and the first dielectric layer under the first trench are removed by a wet etching process.

5. The method according to claim 4, characterized in that The removing the fifth dielectric layer from the sidewall of the first trench comprises: The fifth dielectric layer on the sidewall of the first trench is removed by a wet etching process.

6. The method according to any one of claims 1 to 5, characterized in that: After the first trench and the second trench are filled with a germanium silicon layer, the method further includes: forming a sixth dielectric layer and a second polysilicon layer in sequence, wherein the sixth dielectric layer and the first dielectric layer are made of the same material; removing the sixth dielectric layer and the second polysilicon layer above the third dielectric layer and above the germanium silicon layer; forming a third polysilicon layer and a seventh dielectric layer in sequence, wherein the seventh dielectric layer and the first dielectric layer are made of the same material; removing the third dielectric layer, the third polysilicon layer and the seventh dielectric layer in areas other than the second target area, wherein the second target area is located in the area surrounded by the inner layer of the isolation layer; Removing the first polysilicon layer and the first dielectric layer of a predetermined depth in other regions except a third target region, wherein the third target region is located in the region surrounded by the outer layer of the isolation layer, and the width of the third target region is greater than the width of the second target region; The remaining seventh dielectric layer, the second dielectric layer in the areas other than the second target area, and the first dielectric layer in the areas other than the third target area are removed.

7. The method according to claim 6, characterized in that The removing of the sixth dielectric layer and the second polysilicon layer above the third dielectric layer and above the germanium silicon layer comprises: removing the second polysilicon layer above the sixth dielectric layer and above the germanium silicon layer by a dry etching process; The sixth dielectric layer above the third dielectric layer and above the germanium silicon layer is removed by a wet etching process.

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