Memory and memory system

Abstract

The embodiment of the invention provides a memory and a memory system. The memory comprises a plurality of memory bank groups; the data driver groups are correspondingly connected with the memory bank groups; each data driver group comprises a plurality of data drivers, and each data driver group is used for receiving and transmitting a group of data of the memory bank group; a first data buffer group including a plurality of first data buffers; a first data bus tree circuit including a first master node, and a plurality of first connection lines connecting the first master node and each of the first data buffers; the first connection path is connected with the data driver and the first data buffer corresponding to the data driver; wherein the lengths of the first connection paths connected with the plurality of data drivers in the same data driver group are equal; the first connection path comprises a first connection line and a second connection line, and the second connection line is used for connecting the data driver and the first main node.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of semiconductor technology, and relate to, but are not limited to, a memory and a memory system. Background Art

[0002] With the continuous development of science and technology, semiconductor devices are widely used in various electronic devices and electronic products. For example, dynamic random access memory (DRAM), as a volatile memory, is a commonly used semiconductor memory device in computers.

[0003] To improve access speed, some memories can read a continuous segment of data from the storage area at once and output this continuous data to the data buffer via the data driver. However, inconsistent transmission times from the data driver to different data buffers can lead to a problem of excessively large data windows. Summary of the Invention

[0004] In view of this, embodiments of the present disclosure provide a memory and a memory system.

[0005] In a first aspect, an embodiment of the present disclosure provides a memory, including:

[0006] multiple memory bank groups;

[0007] a data driver group correspondingly connected to each of the memory bank groups;

[0008] Each of the data driver groups includes a plurality of data drivers, wherein each of the data drivers is configured to receive and transmit a group of data from the memory bank group;

[0009] A first data buffer group, comprising a plurality of first data buffers;

[0010] A first data bus tree circuit includes: a first master node, and a plurality of first connection lines connecting the first master node and each of the first data buffers;

[0011] a first connection path connecting the data driver and a first data buffer corresponding to the data driver; wherein the lengths of the first connection paths connecting multiple data drivers in the same data driver group are equal; and the first connection path includes: the first connection line and the second connection line, the second connection line being used to connect the data driver and the first main node.

[0012] In a second aspect, an embodiment of the present disclosure provides a memory system, including:

[0013] The memory according to any one of the above embodiments;

[0014] A memory controller is coupled to the memory and is used to control the memory.

[0015] In an embodiment of the present disclosure, a first data bus tree circuit is provided. The first data bus tree circuit includes a first main node and a first connecting line connecting the first main node and the first data buffer, so that the lengths of the first connecting paths connecting multiple data drivers in the same data driver group are equal. The first connecting path includes a first connecting line and a second connecting line connecting the data driver and the first main node. That is, the lengths of the data transmission paths from the multiple data drivers in the same data driver group to the first data buffer corresponding to the data drivers are all equal. This can improve the problem of different data transmission times caused by the different lengths of the data transmission paths between the multiple data drivers in the same data driver group and the corresponding first data buffers, so that the consistency of the time for data transmission from the multiple data drivers in the same data driver group to the first data buffer corresponding to the data driver can be improved, thereby reducing the data window and improving the data output speed. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 A partial circuit diagram of a memory provided for some embodiments;

[0017] Figure 2 A partial circuit diagram of a memory provided in an embodiment of the present disclosure Figure 1 ;

[0018] Figure 3a Schematic diagram of the first data buffer group provided in the embodiment of the present disclosure Figure 1 ;

[0019] Figure 3b Schematic diagram of the first data buffer group provided in the embodiment of the present disclosure Figure 2 ;

[0020] Figure 3c Schematic diagram 3 of a first data buffer group provided in an embodiment of the present disclosure;

[0021] Figure 4 A partial circuit diagram of a memory provided in an embodiment of the present disclosure Figure 2 ;

[0022] Figure 5 Schematic diagram 3 of a partial circuit of a memory provided by an embodiment of the present disclosure;

[0023] Figure 6 A schematic diagram of a circuit connection between a second repeater and a first AND gate provided in an embodiment of the present disclosure;

[0024] Figure 7A partial circuit diagram of a memory provided in an embodiment of the present disclosure Figure 4 ;

[0025] Figure 8 A schematic diagram of a memory system provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0026] The following, in conjunction with the accompanying drawings, provides a clear and complete description of the technical solutions in the embodiments of the present disclosure. It should be understood that the specific embodiments described herein are intended solely to illustrate the related applications and are not intended to limit those applications. It should also be noted that, for ease of description, only portions of the drawings related to the related applications are shown. Unless otherwise defined, all technical and scientific terms used herein have the same meanings as commonly understood by those skilled in the art to which the present disclosure relates. The terms used herein are for the purpose of describing the embodiments of the present disclosure only and are not intended to limit the present disclosure. In the following description, references to "some embodiments" describe a subset of all possible embodiments. However, it should be understood that "some embodiments" may refer to the same or different subsets of all possible embodiments and may be combined with each other without conflict. It should be noted that the terms "first," "second," and "third" in the embodiments of the present disclosure are used solely to distinguish similar objects and do not represent a specific ordering of the objects. It should be understood that "first," "second," and "third" may be interchanged in a specific order or sequential order, where permitted, to enable the embodiments of the present disclosure described herein to be implemented in an order other than that illustrated or described.

[0027] The embodiments provided herein are applicable to, but not limited to, dynamic random access memory (DRAM) and static random access memory (SRAM). DRAM includes, but is not limited to, double data rate SDRAM (DDR) and low power double data rate (LPDDR); for example, fourth-generation DDR (DDR4), fifth-generation DDR (DDR5), sixth-generation DDR (DDR6), fourth-generation LPDDR (LPDDR4), fifth-generation LPDDR (LPDDR5), and sixth-generation LPDDR (LPDDR6).

[0028] The embodiments of the present disclosure are described using DDR5 as an example, but it should be understood that the present disclosure is also applicable to other memories.

[0029] In some embodiments, the operation process of reading data from the memory can be as follows: the read command (READCMD) first enters the memory bank group (Bank Group, BG), and then the data is read out from the BG. The data is first transmitted to the input / output sense amplifier (Input / Output Sense Amplifier, IOSA), and then transmitted to the corresponding data driver (BusDriver, BD) group, and then transmitted to the data buffer group through the data driver group.

[0030] In some embodiments, the memory includes a plurality of data buffer groups, each data buffer group includes a plurality of data buffers, and the plurality of data buffers (eg, LDQ0 to LDQ7) in each data buffer group are arranged in the peripheral circuit as follows: Figure 1 shown.

[0031] The memory may further include a plurality of bank groups (BG), such as BGA to BGH, and the data buffer group is located in the peripheral circuit on one side of the BGE and BGF along the Y direction. Figure 1 As shown, LDQ7 and LDQ6 are arranged in the first column along the Y direction, LDQ5 and LDQ4 are arranged in the second column along the Y direction, LDQ1 and LDQ0 are arranged in the third column along the Y direction, and LDQ3 and LDQ2 are arranged in the fourth column along the Y direction. Furthermore, LDQ7, LDQ5, LDQ1, and LDQ3 are arranged in the first row along the X direction, and LDQ6, LDQ4, LDQ0, and LDQ2 are arranged in the second row along the X direction. The spacing between LDQ7 and LDQ5 along the X direction is a first spacing, the spacing between LDQ5 and LDQ1 along the X direction is a second spacing, and the spacing between LDQ1 and LDQ3 along the X direction is a third spacing.

[0032] The following will take the data transfer from BGA to the data buffer group as an example for explanation.

[0033] The data driver group corresponding to the BGA includes multiple data drivers, and the data driver group corresponding to the BGA is located in the peripheral circuit on one side of the BGA along the Y direction. The multiple data drivers are arranged along the X direction, and the spacing between each data driver along the X direction is the fourth spacing.

[0034] The multiple data drivers in the data driver group corresponding to the BGA are, from left to right: Bus Driver 37 (BD37, which can also be seen as a combination of Bus Driver 3 (BD3) and Bus Driver 7 (BD7)), Bus Driver 26 (which can also be seen as a combination of Bus Driver 2 and Bus Driver 6), Bus Driver 15 (which can also be seen as a combination of Bus Driver 1 and Bus Driver 5), and Bus Driver 04 (which can also be seen as a combination of Bus Driver 0 and Bus Driver 4). Bus Driver 37 is used to transmit data to LDQ 3 and LDQ 7, Bus Driver 26 is used to transmit data to LDQ 2 and LDQ 6, Bus Driver 15 is used to transmit data to LDQ 1 and LDQ 5, and Bus Driver 04 is used to transmit data to LDQ 0 and LDQ 4.

[0035] exist Figure 1 In the corresponding embodiment, the data line connecting the data driver and the corresponding LDQ includes a first line segment along the X direction and a second line segment along the Y direction. The length of the first line segment is the distance between the data driver and the corresponding LDQ in the X direction, and the length of the second line segment is the distance between the first line segment and the corresponding LDQ in the Y direction. Here, it can be assumed that the spacing between the first line segments extending from different data drivers and the corresponding LDQ in the Y direction is very small, so the lengths of the second line segments can be approximately equal.

[0036] Because the distances in the X direction between different LDQs and corresponding data drivers in the same row vary, the lengths of the data lines used to transmit data from different data drivers to the corresponding LDQs vary. Here, the length of the data line is equal to the sum of the lengths of the first and second segments. This results in inconsistent transmission times for data from different data drivers to the corresponding data buffers, leading to an excessively large data window. The data window refers to the time required for all data read from the BG to be transmitted to the data buffer group during a single read. This transmission time deviation caused by the data buffer arrangement is referred to as DQ SKEW (data buffer skew).

[0037] To solve one or more of the above problems, the present disclosure provides a memory, such as Figure 2 As shown, the memory includes:

[0038] multiple memory bank groups;

[0039] a data driver group connected to each memory bank group;

[0040] Each data driver group includes a plurality of data drivers, wherein each data driver is used to receive and transmit a group of data of the memory bank group;

[0041] A first data buffer group, comprising a plurality of first data buffers;

[0042] The first data bus tree circuit includes: a first master node 100, and a plurality of first connection lines 101 connecting the first master node 100 and each first data buffer;

[0043] A first connection path connects the data driver and the first data buffer corresponding to the data driver; wherein the lengths of the first connection paths connecting multiple data drivers in the same data driver group are equal; the first connection path includes: a first connection line 101 and a second connection line 102, and the second connection line 102 is used to connect the data driver and the first main node 100.

[0044] like Figure 2 As shown, the memory may include multiple memory bank groups, such as BGA to BGH. In some specific examples, each BG may include multiple memory banks, such as Bank0 to Bank3. Each bank may include one or more memory arrays. Operations such as activation, precharging, and data reading can be performed independently on each bank.

[0045] In some embodiments, the plurality of memory bank groups are sequentially arranged along the X direction, and the peripheral circuit may be disposed on one side of the plurality of memory bank groups along the Y direction.

[0046] In some embodiments, each memory bank group may include a first portion located on one side of the peripheral circuit along the Y direction and a second portion located on the other side of the peripheral circuit along the Y direction.

[0047] Each memory bank group is connected to a corresponding data driver group, which can be located in a peripheral circuit. Each data driver group includes multiple data drivers, each of which is used to receive one or more bits of data and perform operations such as data compression on the received data.

[0048] In some embodiments, one data driver group may include 16 data drivers, and each data driver may be used to transmit 1 bit of data.

[0049] In some embodiments, a data driver group may include 8 data drivers, that is, 2-bit data may be compressed together for transmission, and each data driver may be used to transmit 2-bit data.

[0050] In some embodiments, a data driver group may include four data drivers, that is, four bits of data may be compressed together for transmission, and each data driver may be used to transmit four bits of data.

[0051] In some embodiments, the burst lengths (BL) of the memory include, but are not limited to, 8 bits, 16 bits, and 32 bits. A burst refers to the continuous transmission of data between adjacent memory cells in the same row. The number of memory cells involved in the continuous transmission is the burst length. For a memory configured in x8 mode (8 data input and output ports) with a burst length of 16 bits, after a burst read command, a group of data with a length of 16 × 8 = 128 bits can be read from the memory.

[0052] like Figure 2 As shown, the embodiment of the present disclosure further includes a first data buffer group, which includes multiple first data buffers, for example, eight (LDQ0-LDQ7). The first data buffer group is used to output data or cache data. When the length of a group of data is 128 bits, and data is output from the eight first data buffers, each first data buffer can output 16 bits of data.

[0053] like Figure 2 As shown, the embodiment of the present disclosure further includes a first data bus tree circuit, which is used to connect the data driver and the first data buffer.

[0054] The data drivers and the first data buffers may correspond one-to-one or many-to-one. In some specific examples, the number of data drivers in the data driver group is eight, and the number of first data buffers in the first data buffer group is also eight. In this case, the correspondence between the data drivers and the first data buffers may be one-to-one. In other specific examples, the number of data drivers in the data driver group is four, and the number of first data buffer groups in the first data buffer group is eight. In this case, one data driver may correspond to two first data buffers in a one-to-two manner.

[0055] The embodiment of the present disclosure is described with the number of data drivers in the data driver group being 8 (Bus Driver0 to Bus Driver7). It is understood that the number is not limited thereto.

[0056] like Figure 2As shown, Bus Driver 3 is connected to LDQ3 via a first connection path, Bus Driver 7 is connected to LDQ7 via a first connection path, Bus Driver 2 is connected to LDQ2 via a first connection path, Bus Driver 6 is connected to LDQ6 via a first connection path, Bus Driver 1 is connected to LDQ1 via a first connection path, Bus Driver 5 is connected to LDQ5 via a first connection path, Bus Driver 4 is connected to LDQ4 via a first connection path, Bus Driver 3 is connected to LDQ3 via a first connection path, and Bus Driver 0 is connected to LDQ0 via a first connection path. Each first connection path includes a first connection line 101 and a second connection line 102. The first connection paths connecting multiple data drivers in the same data driver group have the same length.

[0057] In some embodiments, as Figure 2 As shown, the first data buffer group includes: a first data buffer array and a second data buffer array; the first data buffer array and the second data buffer array each include multiple first data buffers; the first data buffer array may include LDQ0, LDQ1, LDQ4 and LDQ5, and the second data buffer array may include LDQ2, LDQ3, LDQ6 and LDQ7.

[0058] The length of the first connection line 101 between each first data buffer in the first data buffer array and the first master node 100 is the first length, and the length of the first connection line 101 between each first data buffer in the second data buffer array and the first master node 100 is the second length, and the second length is greater than the first length.

[0059] The arrangement of the first main node and the first connection line may include various formations. Figure 3a 、 Figure 3b as well as Figure 3c Schematic diagrams of the arrangement of the first connecting line and the first main node are shown respectively.

[0060] like Figure 3aAs shown, the first master node 100 can be located at the center of the first data buffer group, the first connecting line 101 includes a first portion and a second portion, the first portion extends along the X direction, the second portion extends along the Y direction, the second portion of each first connecting line is equal, the first portion corresponding to each first data buffer in the first buffer array is equal, the first portion corresponding to each second data buffer in the second buffer array is equal, and the length of each first portion corresponding to each second data buffer in the second buffer array is greater than the length of the first portion corresponding to each first data buffer in the first buffer array. Or, as Figure 3b As shown, the first master node 100 may be located at the center of the first data buffer group, and the first master node is directly connected to the corresponding first data buffer with the shortest distance. Figure 3c As shown, the first master node 100 may include multiple ones.

[0061] In some embodiments, as Figure 2 As shown, each data driver group includes: a first driver array and a second driver array; the first driver array and the second driver array each include a plurality of data drivers; the plurality of data drivers in the first driver array are correspondingly connected to the plurality of first data buffers in the first data buffer array, and the plurality of data drivers in the second driver array are correspondingly connected to the plurality of first data buffers in the second data buffer array;

[0062] The length of the second connection line 102 between each data driver in the first driver array and the first main node 100 is the third length, and the length of the second connection line 102 between each data driver in the second driver array and the first main node 100 is the fourth length; the third length is greater than the fourth length, and the difference between the third length and the fourth length is equal to the difference between the second length and the first length.

[0063] like Figure 2 As shown, the first data driver array may include Bus Driver0, Bus Driver1, Bus Driver4, and Bus Driver5. The second data driver array may include Bus Driver2, Bus Driver3, Bus Driver6, and Bus Driver7.

[0064] It should be noted that the distance between Bus Driver0 and Bus Driver1 in the first data driver array is small and is therefore ignored in the present embodiment. The second connection lines corresponding to Bus Driver0 and Bus Driver1 are considered equal, and similarly, the second connection lines corresponding to Bus Driver2 and Bus Driver3 are considered equal.

[0065] The plurality of data drivers in the first driver array are connected to the plurality of first data buffers in the first buffer array, and a length of a first connection path connecting the data drivers in the first driver array is equal to the sum of the third length and the first length. The plurality of data drivers in the second driver array are connected to the plurality of first data buffers in the second buffer array, and a length of the first connection path connecting the data drivers in the second driver array is equal to the sum of the fourth length and the second length.

[0066] In some embodiments, if the memory includes a first driver array and a first buffer array, lengths of first connection paths between multiple data drivers in the same data driver group and corresponding first data buffers are equal and equal to the third length plus the first length.

[0067] In some embodiments, if the memory includes a second driver array and a second buffer array, the lengths of the first connection paths between the plurality of data drivers in the same data driver group and the corresponding first data buffers are equal and equal to the fourth length plus the second length.

[0068] In some embodiments, the memory includes a first driver array, a second driver array, a first buffer array, and a second buffer array.

[0069] Since the difference between the third length and the fourth length is equal to the difference between the second length and the first length, the sum of the third length plus the first length is equal to the sum of the fourth length plus the second length.

[0070] In this way, the lengths of the first connection paths between the multiple data drivers in the same data driver group and the corresponding first data buffers remain equal.

[0071] The disclosed embodiment utilizes a first data bus tree circuit to improve the problem of different lengths of first connection paths caused by different distances in the X direction between different LDQs in the same row and corresponding data drivers, so that the first connection lines 101 in different first connection paths are all led out from the first main node 100 and connected to the corresponding first data buffers.

[0072] It will be appreciated that in the disclosed embodiments, the first data bus tree circuit ensures that the lengths of the first connection lines 101 corresponding to the multiple first data buffers in the first data buffer array are all equal, and the lengths of the first connection lines 101 between the multiple first data buffers in the second data buffer array are all equal. Furthermore, by adjusting the arrangement of the data driver groups, the multiple data drivers in the first driver array are closely arranged in the X-direction (such that the spacing between them in the X-direction is negligible), and the multiple data drivers in the second driver array are closely arranged in the X-direction. Furthermore, the spacing between the second driver array and the first driver array is adjusted to the difference between the second length and the first length. This ensures that the length of the second connection line 102 between each data driver in the first driver array and the first master node 100 is the third length, and the length of the second connection line 102 between each data driver in the second driver array and the first master node 100 is the fourth length, with the difference between the third length and the fourth length being equal to the difference between the second length and the first length.

[0073] The length of the first connection path between multiple data drivers in the same data driver group and the corresponding first data buffers is equal to the first length plus the third length, or equal to the second length plus the fourth length. Thus, the lengths of the first connection paths between multiple data drivers in the same data driver group and the corresponding first data buffers are adjusted to the same length. This alleviates the problem of different data transmission times caused by different lengths of the first connection paths between multiple data drivers in the same data driver group and the corresponding first data buffers. This ensures that the time it takes for data to reach the corresponding first data buffers from different data drivers in the same data driver group is equal, reducing the time difference in data reaching the corresponding first data buffers from different data drivers in the same data driver group, thereby reducing the data window and improving data output speed.

[0074] In some embodiments, the plurality of memory bank groups include a first memory area and a second memory area arranged along a first direction; the memory further includes:

[0075] A second data buffer group, comprising a plurality of second data buffers;

[0076] The second data bus tree circuit includes: a second master node, and a plurality of third connection lines connecting the second master node and each second data buffer;

[0077] The first data buffer group is connected to the plurality of memory bank groups located in the first storage area and the plurality of memory bank groups located in the second storage area;

[0078] The second data buffer group is connected to the plurality of memory bank groups located in the second storage area;

[0079] The second connection path connects the data driver and the second data buffer corresponding to the data driver; wherein the lengths of the second connection paths connecting multiple data drivers in the same data driver group are equal; the second connection path includes: a third connection line and a fourth connection line, and the fourth connection line is used to connect the data driver and the second main node.

[0080] In the embodiment of the present disclosure, Figure 2 As shown in , the first storage area may include BGA to BGD, and the second storage area may include BGE to BGH. The second data buffer group is arranged on a side of the first data buffer group away from the first storage area along the X direction.

[0081] In some embodiments, as Figure 4 As shown, the second data buffer group includes:

[0082] A third buffer array and a fourth buffer array; each of the third buffer array and the fourth buffer array includes a plurality of second data buffers;

[0083] The length of the third connection line between each second data buffer in the third buffer array and the second master node 200 is the fifth length, and the length of the third connection line between each second data buffer in the fourth buffer array and the second master node 200 is the sixth length, which is greater than the fifth length.

[0084] In some specific examples, the difference between the sixth length and the fifth length is equal to the difference between the second length and the first length.

[0085] In some specific examples, the third data buffer array may include UDQ0 , UDQ1 , UDQ4 , and UDQ5 , and the fourth data buffer array may include UDQ2 , UDQ3 , UDQ6 , and UDQ7 .

[0086] For a memory that can be configured into X16 mode (16 data input and output ports), the memory can include a first data buffer group (including 8 first data buffers) and a second data buffer group (including 8 second data buffers), which are used to form a total of 16 data input and output ports.

[0087] The following description will be made by taking the data transmission in the BGE to the second data buffer group as an example.

[0088] like Figure 4As shown, Bus Driver 3 is connected to UDQ3 via a second connection path, Bus Driver 7 is connected to UDQ7 via a second connection path, Bus Driver 2 is connected to UDQ2 via a second connection path, Bus Driver 6 is connected to UDQ6 via a second connection path, Bus Driver 1 is connected to UDQ1 via a second connection path, Bus Driver 5 is connected to UDQ5 via a second connection path, Bus Driver 4 is connected to UDQ4 via a second connection path, Bus Driver 3 is connected to UDQ3 via a second connection path, and Bus Driver 0 is connected to UDQ0 via a second connection path. Each second connection path includes a third connection line and a fourth connection line. The second connection paths connecting multiple data drivers in the same data driver group have equal lengths.

[0089] In some embodiments, if the memory includes a first driver array and a third buffer array, the lengths of the first connection paths between the plurality of data drivers in the same data driver group and the corresponding second data buffers are equal and equal to the fifth length plus the first length.

[0090] In some embodiments, if the memory includes a second driver array and a fourth buffer array, the lengths of the first connection paths between the plurality of data drivers in the same data driver group and the corresponding second data buffers are equal and equal to the sixth length plus the second length.

[0091] In some embodiments, the memory includes a first driver array, a second driver array, a third buffer array, and a fourth buffer array.

[0092] Since the difference between the sixth length and the fifth length is equal to the difference between the second length and the first length, the sum of the fifth and sixth lengths plus the first length is equal to the sum of the sixth length plus the second length.

[0093] In this way, the lengths of the second connection paths between the multiple data drivers in the same data driver group and the corresponding second data buffers remain equal.

[0094] The embodiment of the present disclosure is further applicable to the X16 mode by providing a second data bus tree circuit and a second data buffer group.

[0095] In some embodiments, the second storage area includes a first sub-area (BGE and BGF) and a second sub-area (BGG and BGH) arranged along the first direction, and the first sub-area is located between the first storage area and the second sub-area. Figure 5 As shown, the memory also includes:

[0096] A first connecting node 301, a second connecting node 302, a third connecting node 303, and a fourth connecting node 304 are arranged along a second direction perpendicular to the first direction, and the first connecting node 301 and the second connecting node 302 are both located between the data driver group corresponding to the first sub-region and the data driver group corresponding to the second sub-region; the third connecting node 303 and the fourth connecting node 304 are arranged along the second direction perpendicular to the first direction, and the third connecting node 303 and the fourth connecting node 304 are both located on one side of the data driver group corresponding to the second sub-region, away from the data driver corresponding to the first sub-region, on either side along the first direction;

[0097] The second connection line 102 and the fourth connection line include: a first data bus segment 401, a second data bus segment 402, a third data bus segment 403, a fourth data bus segment 404, a fifth data bus segment 405, a sixth data bus segment 406, a seventh data bus segment 407, and an eighth data bus segment 408; wherein,

[0098] The first data bus segment 401, the second data bus segment 402, the fourth data bus segment 404, the fifth data bus segment 405, the sixth data bus segment 406, and the eighth data bus segment 408 all extend along a first direction, and the third data bus segment 403 and the seventh data bus segment 407 extend along a second direction perpendicular to the first direction; the first data bus segment 401 connects the first main node 100 and the data driver corresponding to the first storage area, the second data bus segment 402 connects the data driver corresponding to the first sub-area and the first connection node 301, and the third data bus segment 403 connects the data driver corresponding to the first sub-area and the first connection node 301. Line segment 403 connects the first connection node 301 and the second connection node 302; the fourth data bus segment 404 connects the first main node 100 and the second connection node 302; the fifth data bus segment 405 connects the second connection node 302 and the second main node 200; the sixth data bus segment 406 connects the third connection node 303 and the data driver corresponding to the second sub-area; the seventh data bus segment 407 connects the third connection node 303 and the fourth connection node 304; and the eighth data bus segment 408 connects the second main node 200 and the fourth connection node 304.

[0099] Here, the first direction can be Figure 5 The second direction may be as shown in the X direction. Figure 5 Y direction shown.

[0100] In some embodiments, data in the first storage area is transmitted to the corresponding first data buffer group via the first data bus segment 401 through the corresponding data driver group.

[0101] If the memory mode is X4 mode (4 data input and output ports), the data read from the first storage area can be transmitted to LDQ0 to DQ3 or LDQ4 to LDQ7 in the first data buffer group through the corresponding data driver via the first data bus segment 401.

[0102] If the memory mode is X8 mode (8 data input and output ports), the data read from the first storage area can be transmitted to LDQ0 to LDQ7 in the first data buffer group through the corresponding data driver via the first data bus segment 401.

[0103] If the memory mode is X16 mode, the data read from the first memory area can be transmitted to LDQ0 to LDQ7 in the first data buffer group through the corresponding data driver via the first data bus segment 401 .

[0104] In some embodiments, if the mode of the memory is X4 mode, the data in the first sub-area is transmitted to LDQ0 to DQ3 or LDQ4 to LDQ7 in the first data buffer group through the corresponding data driver group via the second data bus segment 402, the third data bus segment 403 and the fourth data bus segment 404.

[0105] If the memory mode is X8 mode, the data in the first sub-area is transmitted to LDQ0 to LDQ7 in the first data buffer group through the corresponding data driver group via the second data bus segment 402 , the third data bus segment 403 and the fourth data bus segment 404 .

[0106] In some embodiments, if the mode of the memory is X4 mode, the data in the second sub-area is transmitted through the corresponding data driver group via the sixth data bus segment 406, the seventh data bus segment 407, the eighth data bus segment 408, the fifth data bus segment 405 and the fourth data bus segment 404 to LDQ0 to DQ3 or LDQ4 to LDQ7 in the first data buffer group.

[0107] If the memory mode is X8 mode, the data in the second sub-area is transmitted to LDQ0 to LDQ7 in the first data buffer group through the corresponding data driver group via the sixth data bus segment 406, the seventh data bus segment 407, the eighth data bus segment 408, the fifth data bus segment 405 and the fourth data bus segment 404.

[0108] In some embodiments, if the memory mode is X16 mode, the data in the first sub-area is transmitted to the second data buffer group through the corresponding data driver group via the second data bus segment 402, the third data bus segment 403 and the fifth data bus segment 405; or,

[0109] If the memory mode is X16 mode, the data in the second sub-area is transmitted to the second data buffer group through the corresponding data driver group via the sixth data bus segment 406 , the seventh data bus segment 407 and the eighth data bus segment 408 .

[0110] In some embodiments, the first direction includes a first positive direction and a first negative direction, and the memory also includes at least one first repeater (not shown), which is connected to the first data bus segment 401 and is used to control the data of the first data bus segment 401 to be transmitted along the first positive direction.

[0111] In the disclosed embodiment, a first repeater can be provided after every two BGs in the first data bus segment 401. In practical applications, a first repeater can also be provided after one BG or after more data BGs, depending on actual circuit requirements. This way, the data can be transmitted over a distance of two BGs, thereby improving driving capability.

[0112] For example, a first repeater may be provided on the first data bus segment corresponding to between BGB and BGC, and a first repeater may be provided on the first data bus segment corresponding to between BGD and BGE.

[0113] The BGs between BGA and BGD are all transmitted to the corresponding first data buffer group via the first data bus segment 401. Since the data driver group corresponding to the BGA to BGD is located to the left of the first data buffer group, the data in the first data bus segment 401 needs to be transmitted along the first positive direction. Therefore, the data still needs to be transmitted in the first positive direction after passing through the first repeater.

[0114] In some specific examples, the first positive direction indicates a direction from the BGA to the BGH, and the first negative direction indicates a direction from the BGH to the BGA.

[0115] In some embodiments, the memory further includes a second repeater (not shown), the second repeater being connected to the fourth data bus segment 404 , and the second repeater being configured to control data on the fourth data bus segment 404 to be transmitted along the first negative direction.

[0116] In the X4 or X8 mode, data in the second storage area (BGE to BGH) is transmitted to the first data buffer group via the fourth data bus segment 404. Because the fourth data bus segment 404 is located to the right of the first data buffer group, data in the fourth data bus segment 404 must be transmitted in the first negative direction to be transferred to the first data buffer group. The second repeater can be used to control the data transmission direction so that the data is transmitted in the first negative direction when passing through the fourth data bus segment 404.

[0117] In some specific examples, the second repeater is set in a peripheral circuit, specifically, it can be set in a peripheral circuit corresponding to between the BGG and the BGF.

[0118] In some embodiments, as Figure 6 As shown, the memory further includes a first AND gate;

[0119] The output end of the first AND gate is connected to the second repeater;

[0120] The first input terminal of the first AND gate is used to receive a selection signal (for example, X16B);

[0121] When the selection signal is at the first level, the first AND gate is used to allow data on the fourth data bus segment 404 to be transmitted along the first negative direction;

[0122] When the selection signal is at the second level, the first AND gate is used to prohibit the data on the fourth data bus segment 404 from being transmitted along the first negative direction.

[0123] In the embodiment of the present disclosure, the first level may be a high level, and the second level may be a low level.

[0124] The first input terminal of the first AND gate is used to receive a selection signal. The selection signal at a first level may indicate that the memory is in X4 and X8 mode. The selection signal at a second level may indicate that the memory is in X16 mode.

[0125] When the selection signal indicates that the memory is in the X4 and X8 modes, the first AND gate controls the data to be transmitted along the first negative direction and output to the first data buffer group.

[0126] When the selection signal indicates that the memory is in the X16 mode, the first AND gate prohibits data from being transmitted in the first negative direction, and data is transmitted in the first positive direction through the fifth data bus segment 405 to the second data buffer group.

[0127] In some embodiments, the memory further comprises a first NAND gate;

[0128] The output end of the first NAND gate is connected to the second repeater;

[0129] The first input terminal of the first NAND gate is used to receive a selection signal (for example, X16);

[0130] When the selection signal is at the first level, the first AND gate is used to allow data on the fourth data bus segment 404 to be transmitted along the first negative direction;

[0131] When the selection signal is at the second level, the first AND gate is used to prohibit the data on the fourth data bus segment 404 from being transmitted along the first negative direction.

[0132] The first level may be a low level, and the second level may be a high level.

[0133] The first input terminal of the first NAND gate is used to receive a selection signal. The selection signal at a first level may indicate that the memory is in an X16 mode. The selection signal at a second level may indicate that the memory is in an X4\X8 mode.

[0134] When the selection signal indicates that the memory is in the X4 and X8 modes, the first NAND gate outputs data to the second repeater, and the data continues to be transmitted along the first negative direction and output to the first data buffer group.

[0135] At this time, the data in the first sub-area is transmitted to the first data buffer group through the corresponding data driver group via the second data bus segment 402, the third data bus segment 403 and the fourth data bus segment 404; and / or,

[0136] The data in the second sub-area is transmitted to the first data buffer group through the corresponding data driver group via the sixth data bus segment 406 , the seventh data bus segment 407 , the eighth data bus segment 408 , the fifth data bus segment 405 and the fourth data bus segment 404 .

[0137] When the selection signal indicates that the memory is in X16 mode, the first NAND gate prohibits data from being transmitted in the first negative direction, and data is transmitted in the first positive direction through the fifth data bus segment 405 to the second data buffer group.

[0138] At this time, the data in the first sub-area is transmitted to the second data buffer group through the corresponding data driver group via the second data bus segment 402, the third data bus segment 403 and the fifth data bus segment 405; and / or,

[0139] The data in the second sub-area is transmitted to the second data buffer group through the corresponding data driver group via the sixth data bus segment 406 , the seventh data bus segment 407 , and the eighth data bus segment 408 .

[0140] In some embodiments, the memory may further include two third repeaters, one third repeater connected to the third data bus segment 403, and the other third repeater connected to the seventh data bus segment 407, the third repeater connected to the third data bus segment 403 controls data transmission along the second negative direction, and the third repeater connected to the seventh data bus segment 407 controls data transmission along the second negative direction.

[0141] In some specific examples, the second direction includes a second positive direction and a second negative direction, where the second negative direction indicates Figure 7 LDQ1 in the figure points in the direction of LDQ0.

[0142] The combination of the first AND gate (or first NAND gate) and the aforementioned repeater can be thought of as an even number of tri-state gates or an odd number of inverters and a tri-state gate. The first AND gate (or first NAND gate) and the aforementioned repeater are only driven when the control signal received by the first AND gate is valid, or when the control signal received by the first NAND gate is invalid. Otherwise, they output a high-impedance state. For example, when reading data from BGD, the first repeater between the data driver corresponding to BGB and the data driver corresponding to BGC will be in a high-impedance state to shut off the outputs of BGA and BGB, thereby preventing interference with the output of BGD. The significance of the combination of the first AND gate (or first NAND gate) and the aforementioned repeater is to shut off unnecessary outputs ahead of the target BG transmission path to prevent interference with the target BG output.

[0143] from Figure 5 As can be seen in the figure, for a BGA in the case of X4, X8, or X16, data read from the BGA is transmitted to the first data buffer group via the first data bus segment 401 and the first data bus tree circuit. The length of the transmission path from the corresponding data driver group to the first master node 100 is equal to the width of 4.75 BGs (the width of a BG refers to the distance of the BG in the first direction). The width of 4.75 BGs = the width of the BGA + the width of the BGB + the width of the BGC + the width of the BGD + the width of the 0.75 BGE.

[0144] It should be noted that the transmission path here is counted from the leftmost side of each BG to the first main node of the first data bus tree circuit or the second main node of the second data bus tree circuit.

[0145] The length of the transmission path actually represents the length of the transmission time, and the impact of each repeater on the transmission speed is ignored here.

[0146] For a BGB, in the X4, X8, or X16 case, data read from the BGB is transmitted to the first data buffer group via the first data bus segment 401 and the first data bus tree circuit. The length of the transmission path from the corresponding data driver group to the first master node 100 in the X direction is equal to the width of 3.75 BGs. The width of 3.75 BGs = the width of the BGB + the width of the BGC + the width of the BGD + the width of the 0.75 BGE.

[0147] For a BGC, in the X4, X8, or X16 case, data read from the BGC is transmitted to the first data buffer group via the first data bus segment 401 and the first data bus tree circuit. The length of the transmission path from the corresponding data driver group to the first master node 100 in the X direction is equal to the width of 2.75 BGs. The width of 2.75 BGs = the width of the BGC + the width of the BGD + the width of 0.75 BGEs.

[0148] For the BGD, in the X4, X8, or X16 case, data read from the BGD is transmitted to the first data buffer group via the first data bus segment 401 and the first data bus tree circuit. The length of the transmission path from the corresponding data driver group to the first master node 100 in the X direction is equal to the width of 1.75 BGs. The width of 1.75 BGs = the width of the BGD + the width of 0.75 BGEs.

[0149] For the BGE, in the X4 or X8 case, data read from the BGE is transmitted to the first data buffer group via the second data bus segment 402, the first connection node 301, the second connection node 302, the fourth data bus segment 404, and the first data bus tree circuit. The length of this transmission path in the X direction from the corresponding data driver group to the first master node 100 is equal to the width of 3.25 BGs. The width of 3.25 BGs = the width of the BGE + the width of the BGF (second data bus segment 402) + the width of the BGF (fourth data bus segment 404) + the width of 0.25 BGEs.

[0150] For the BGE, in the X16 case, data read from the BGE is transmitted to the second data buffer group via the second data bus segment 402, the first connection node 301, the second connection node 302, the fifth data bus segment 405, and the second data bus tree circuit. The length of this transmission path in the X direction from the corresponding data driver group to the second master node 200 is equal to the width of 2.25 BGs. The width of 2.25 BGs = the width of the BGE + the width of the BGF (second data bus segment 402) + the width of 0.25 BGGs (fifth data bus segment 405).

[0151] For the BGF, in the X4 or X8 case, data read from the BGF is transmitted to the first data buffer group via the second data bus segment 402, the first connection node 301, the second connection node 302, the fourth data bus segment 404, and the first data bus tree circuit. The length of this transmission path in the X direction from the corresponding data driver group to the first master node 100 is equal to the width of 2.25 BGs. The width of 2.25 BGs = the width of the BGF (second data bus segment 402) + the width of the BGF (fourth data bus segment 404) + the width of 0.25 BGEs.

[0152] For the BGF, in the X16 case, data read from the BGF is transmitted to the second data buffer group via the second data bus segment 402, the first connection node 301, the second connection node 302, the fifth data bus segment 405, and the second data bus tree circuit. The length of this transmission path in the X direction from the corresponding data driver group to the second master node 200 is equal to the width of 1.25 BGs. 1.25 BGs = the width of the BGF (second data bus segment 402) + the width of 0.25 BGGs (fifth data bus segment 405).

[0153] For the BGG, in the X4 or X8 case, data read from the BGG is transmitted to the first data buffer group via the sixth data bus segment 406, the third connection node 303, the fourth connection node 304, the seventh data bus segment 407, the eighth data bus segment 408, the fifth data bus segment 405, the fourth data bus segment 404, and the first data bus tree circuit. The length of this transmission path in the X direction from the corresponding data driver group to the first master node 100 is equal to the width of 5.25 BGs. The width of 5.25 BGs = the width of the BGG (part of the sixth data bus segment 406) + the width of the BGH (part of the sixth data bus segment 406) + the width of the BGH (part of the eighth data bus segment 408) + the width of the BGG (part of the eighth data bus segment 408 and part of the fifth data bus segment 405) + the width of the BGF (part of the fourth data bus segment 404) + the width of 0.25 BGE (part of the fourth data bus segment 404).

[0154] For the BGG, in the X16 case, data read from the BGG is transmitted to the second data buffer group via the sixth data bus segment 406, the third connection node 303, the fourth connection node 304, the seventh data bus segment 407, the eighth data bus segment 408, and the second data bus tree circuit. The length of this transmission path in the X direction from the corresponding data driver group to the second master node 200 is equal to the width of 3.75 BGs. The width of 3.75 BGs = the width of the BGG (part of the sixth data bus segment 406) + the width of the BGH (part of the sixth data bus segment 406) + the width of the BGH (part of the eighth data bus segment 408) + the width of the BGG (part of the eighth data bus segment 408) + 0.75 of the width of the BGG (part of the eighth data bus segment 408).

[0155] For the BGH, in the X4 or X8 case, data read from the BGH is transmitted to the first data buffer group via the sixth data bus segment 406, the third connection node 303, the fourth connection node 304, the seventh data bus segment 407, the eighth data bus segment 408, the fifth data bus segment 405, the fourth data bus segment 404, and the first data bus tree circuit. The length of this transmission path in the X direction from the corresponding data driver group to the first master node 100 is equal to the width of 4.25 BGs. The width of 4.25 BGs = the width of the BGH (part of the sixth data bus segment 406) + the width of the BGH (part of the eighth data bus segment 408) + the width of the BGG (part of the eighth data bus segment 408 and part of the fifth data bus segment 405) + the width of the BGF (part of the fourth data bus segment 404) + the width of the 0.25 BGE (part of the fourth data bus segment 404).

[0156] For the BGH, in the X16 case, data read from the BGH is transmitted to the second data buffer group via the sixth data bus segment 406, the third connection node 303, the fourth connection node 304, the seventh data bus segment 407, the eighth data bus segment 408, and the second data bus tree circuit. The length of this transmission path in the X direction from the corresponding data driver group to the second master node 200 is equal to the width of 2.75 BGs. 2.75 BGs = the width of the BGH (part of the sixth data bus segment 406) + the width of the BGH (part of the eighth data bus segment 408) + the width of 0.75 BGG (part of the eighth data bus segment 408).

[0157] As can be seen, although the lengths of the first connection paths between the multiple data drivers in each data driver group and the corresponding first data buffer are equal, and the lengths of the second connection paths between the multiple data drivers in each data driver group and the corresponding second data buffer are equal, the lengths of the first connection paths for different BGs still vary, and the lengths of the second connection paths for different BGs also vary to a certain extent. This can cause inconsistent timing when data is read from different memory bank groups and transferred to the corresponding data buffers. This transmission time deviation caused by the different BG positions is called BG SKEW (memory bank group skew).

[0158] To solve the above problems, in some embodiments, Figure 7 As shown, the memory also includes multiple read command signal transmission lines, each memory bank group corresponds to a read command signal transmission line, the data lines corresponding to each memory bank group are equal in length, and the data lines include a read command signal transmission line and a first connection path.

[0159] In the embodiment of the present disclosure, before the read command reaches the BG, the read command signal line is set accordingly so that different storage body groups correspond to different read command signal transmission lines, and the read command signal transmission lines are used for corresponding compensation so that the lengths of the data lines corresponding to each storage body group are equal, thereby improving the differences in data transmission time of different storage body groups caused by the differences in the positions of different storage body groups, thereby further reducing the data window and improving the consistency of data transmission time of different storage body groups.

[0160] Specifically, the read command from Figure 7 The read circuit 600 in the DRAM then passes through the read command transmission line and into each BG center (the data processing center of the memory bank group) through vias 601 (vias) set in the peripheral circuit corresponding to each BG. The blank area between the data driver groups corresponding to each BG in the peripheral circuit is called the BG center.

[0161] It can be understood that the distance from the through hole 601 to the storage array area is the same.

[0162] like Figure 7 As shown, for a BGA in the x4, x8, or x16 configuration, the length of the read command signal transmission line through which the read command passes can be 3.25 BGs wide. This allows the total length of the line from the first master node 100 to the first and second buffer arrays to be 8 BGs wide. It's important to note that the difference in length from the first master node 100 to the first and second buffer arrays is already compensated for by the layout of the first and second driver arrays. Therefore, there's no need to consider the DQ skew caused by the first data buffer layout.

[0163] For BGB, in the case of X4 or X8 or X16, the length of the read command signal transmission line through which the read command passes can be a width of 4.25BG, so that the read command reaches the BGB and outputs the data in the BGB to the first main node 100. The line length is also 8BG in width.

[0164] For BGC, in the case of X4 or X8 or X16, the length of the read command signal transmission line through which the read command passes can be a width of 5.25BG, so that the read command reaches the BGC and outputs the data in the BGC to the first main node 100. The line length is also 8BG in width.

[0165] For BGD, in the case of X4 or X8 or X16, the length of the read command signal transmission line through which the read command passes can be 6.25BG in width, so that the read command reaches BGD and outputs the data in BGD to the first main node 100. The line length is also 8BG in width.

[0166] For BGE, in the case of X4 or X8, the length of the read command signal transmission line through which the read command passes can be 4.75 BG in width. In this way, the length of the line through which the read command reaches the BGE and outputs the data in the BGE to the first master node 100 is also 8 BG in width. For BGE, in the case of X16, the length of the read command signal transmission line through which the read command passes can be 5.75 BG in width. In this way, the length of the line through which the read command reaches the BGE and outputs the data in the BGE to the first master node 100 is also 8 BG in width.

[0167] For the BGF, in the case of X4 or X8, the length of the read command signal transmission line through which the read command passes can be 5.75BG in width, so that the read command reaches the BGF and the line length for outputting the data in the BGF to the first master node 100 is also 8BG in width. For the BGF, in the case of X16, the length of the read command signal transmission line through which the read command passes can be 6.75BG in width, so that the read command reaches the BGF and the line length for outputting the data in the BGF to the first master node 100 is also 8BG in width.

[0168] It should be noted that, compared with X4 or X8 mode, in X16 mode, BGE and BGF both compensate for the length of one BG, which can be Figure 7 The first read command signal transmission line ( Figure 7 The dotted path under the BGE in the figure is used for compensation.

[0169] For BGG, in the case of X4 or X8, the length of the read command signal transmission line through which the read command passes can be a width of 2.75BG, so that the length of the line through which the read command reaches the BGG and outputs the data in the BGG to the first master node 100 is also a width of 8BG. For BGG, in the case of X16, the length of the read command signal transmission line through which the read command passes can be a width of 4.25BG, so that the length of the line through which the read command reaches the BGG and outputs the data in the BGG to the first master node is also a width of 8BG.

[0170] For the BGH, in the case of X4 or X8, the length of the read command signal transmission line through which the read command passes can be 3.75 BGs in width. In this way, the length of the line through which the read command reaches the BGH and outputs the data in the BGH to the first master node 100 is also 8 BGs in width. For the BGH, in the case of X16, the length of the read command signal transmission line through which the read command passes can be 5.25 BGs in width. In this way, the length of the line through which the read command reaches the BGH and outputs the data in the BGH to the first master node is also 8 BGs in width.

[0171] It should be noted that compared with X4 or X8 mode, in X16 mode, BGG and BGH both compensate for the length of 1.5BG width, which can be explained by Figure 7 The second read command signal transmission line ( Figure 7 The dotted path under BGH in the figure is used for compensation.

[0172] The present disclosure provides a memory system 500, such as Figure 8 As shown, including:

[0173] The memory 510 as in any of the above embodiments;

[0174] The memory controller 520 is coupled to the memory 510 and is used to control the memory 510 .

[0175] The memory system 500 may include a memory controller 520 and one or more memories 510 .

[0176] The memory controller 520 may be configured to control operations such as reading, erasing, and programming of the memory 510; may also be configured to manage various functions related to data stored or to be stored in the memory 510, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc.; and may also be configured to process error correction codes for data read from or written to the memory 510. The present disclosure is not limited thereto, and the memory controller 520 may also perform any other suitable functions.

[0177] It should be understood that “some embodiments”, “one embodiment” or “an embodiment” mentioned throughout the specification means that specific features, structures or characteristics related to the embodiments are included in at least one embodiment of the present disclosure. Therefore, “in one embodiment” or “in an embodiment” appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present disclosure, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The serial numbers of the embodiments of the present disclosure are for description only and do not represent the advantages and disadvantages of the embodiments.

[0178] It should be noted that, in this document, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or apparatus comprising the element.

[0179] The above is only an embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of changes or replacements within the technical scope disclosed in the present disclosure, and they should all be covered by the protection scope of the present disclosure.

Claims

1. A memory, characterized in that: include: multiple memory bank groups; a data driver group connected corresponding to each of the storage bank groups; Each of the data driver groups includes a plurality of data drivers, wherein each of the data drivers is used to receive and transmit a group of data of the storage bank group; A first data buffer group, comprising a plurality of first data buffers; A first data bus tree circuit includes: a first master node, and a plurality of first connection lines connecting the first master node and each of the first data buffers; A first connection path connects the data driver and a first data buffer corresponding to the data driver; wherein the lengths of the first connection paths connecting multiple data drivers in the same data driver group are equal; the first connection path includes: the first connection line and the second connection line, and the second connection line is used to connect the data driver and the first main node.

2. The memory according to claim 1, characterized in that: The first data buffer group includes: a first data buffer array and a second data buffer array; the first data buffer array and the second data buffer array each include a plurality of the first data buffers; The length of the first connection line between each first data buffer in the first data buffer array and the first main node is a first length, the length of the first connection line between each first data buffer in the second data buffer array and the first main node is a second length, and the second length is greater than the first length.

3. The memory according to claim 2, characterized in that: Each of the data driver groups comprises: a first driver array and a second driver array; the first driver array and the second driver array each comprise a plurality of the data drivers; the plurality of the data drivers in the first driver array are correspondingly connected to the plurality of the first data buffers in the first data buffer array, and the plurality of the data drivers in the second driver array are correspondingly connected to the plurality of the first data buffers in the second data buffer array; The length of the second connection line between each data driver in the first driver array and the first main node is a third length, and the length of the second connection line between each data driver in the second driver array and the first main node is a fourth length; the third length is greater than the fourth length, and the difference between the third length and the fourth length is equal to the difference between the second length and the first length.

4. The memory according to any one of claims 1 to 3, characterized in that: The plurality of memory bank groups include a first storage area and a second storage area arranged along a first direction; the memory further includes: A second data buffer group, comprising a plurality of second data buffers; A second data bus tree circuit includes: a second master node, and a plurality of third connection lines connecting the second master node and each of the second data buffers; The first data buffer group is connected to a plurality of memory bank groups located in the first storage area and a plurality of memory bank groups located in the second storage area; The second data buffer group is connected to a plurality of memory bank groups located in the second storage area; A second connection path connects the data driver and a second data buffer corresponding to the data driver; wherein the lengths of the second connection paths connecting multiple data drivers in the same data driver group are equal; the second connection path includes: the third connection line and the fourth connection line, and the fourth connection line is used to connect the data driver and the second main node.

5. The memory according to claim 4, characterized in that: The second data buffer group includes: A third buffer array and a fourth buffer array; the third buffer array and the fourth buffer array each include a plurality of the second data buffers; The length of the third connection line between each second data buffer in the third buffer array and the second main node is the fifth length, the length of the third connection line between each second data buffer in the fourth buffer array and the second main node is the sixth length, and the sixth length is greater than the fifth length.

6. The memory according to claim 4, characterized in that: The second storage area includes a first sub-area and a second sub-area arranged along the first direction, the first sub-area is located between the first storage area and the second sub-area, and the memory further includes: a first connection node, a second connection node, a third connection node, and a fourth connection node, wherein the first connection node and the second connection node are arranged along a second direction perpendicular to the first direction, and the first connection node and the second connection node are both located between a data driver group corresponding to the first sub-region and a data driver group corresponding to the second sub-region; the third connection node and the fourth connection node are arranged along a second direction perpendicular to the first direction, and the third connection node and the fourth connection node are both located on one side of the data driver group corresponding to the second sub-region, away from the data driver corresponding to the first sub-region, on both sides along the first direction; The second connecting line and the fourth connecting line include: a first data bus segment, a second data bus segment, a third data bus segment, a fourth data bus segment, a fifth data bus segment, a sixth data bus segment, a seventh data bus segment, and an eighth data bus segment; wherein, The first data bus segment, the second data bus segment, the fourth data bus segment, the fifth data bus segment, the sixth data bus segment, and the eighth data bus segment all extend along the first direction, and the third data bus segment and the seventh data bus segment extend along a second direction perpendicular to the first direction; the first data bus segment connects the first main node and the data driver corresponding to the first storage area, the second data bus segment connects the data driver corresponding to the first sub-area and the first connection node, the third data bus segment connects the first connection node and the second connection node; the fourth data bus segment connects the first main node and the second connection node; the fifth data bus segment connects the second connection node and the second main node; the sixth data bus segment connects the third connection node and the data driver corresponding to the second sub-area; the seventh data bus segment connects the third connection node and the fourth connection node; the eighth data bus segment connects the second main node and the fourth connection node.

7. The memory according to claim 6, characterized in that: The data in the first storage area is transmitted to the corresponding first data buffer group through the first data bus segment by the corresponding data driver group.

8. The memory according to claim 6, characterized in that: The data in the first sub-area is transmitted to the first data buffer group through the corresponding data driver group via the second data bus segment, the third data bus segment and the fourth data bus segment; and / or, The data in the second sub-area is transmitted to the first data buffer group through the sixth data bus segment, the seventh data bus segment, the eighth data bus segment, the fifth data bus segment and the fourth data bus segment by the corresponding data driver group.

9. The memory according to claim 6, characterized in that: The data in the first sub-area is transmitted to the second data buffer group through the corresponding data driver group via the second data bus segment, the third data bus segment and the fifth data bus segment; and / or, The data in the second sub-area is transmitted to the second data buffer group through the sixth data bus segment, the seventh data bus segment, and the eighth data bus segment by the corresponding data driver group.

10. The memory according to claim 6, characterized in that: The first direction includes a first positive direction and a first negative direction. The memory further includes at least one first repeater. The first repeater is connected to the first data bus segment and is used to control data of the first data bus segment to be transmitted along the first positive direction.

11. The memory according to claim 10, characterized in that: The memory further includes a second repeater, the second repeater being connected to the fourth data bus segment, and the second repeater being used for controlling data on the fourth data bus segment to be transmitted along the first negative direction.

12. The memory according to claim 11, characterized in that: The memory further comprises a first AND gate; The output end of the first AND gate is connected to the second repeater; The first input terminal of the first AND gate is used to receive a selection signal; When the selection signal is at a first level, the first AND gate is used to allow data on the fourth data bus segment to be transmitted along the first negative direction; When the selection signal is at the second level, the first AND gate is used to prohibit data on the fourth data bus segment from being transmitted along the first negative direction.

13. The memory according to claim 1, characterized in that: The memory also includes a plurality of read command signal transmission lines, each storage body group corresponds to a read command signal transmission line, the data lines corresponding to each storage body group are of equal length, and the data lines include the read command signal transmission line and the first connection path.

14. A memory system, characterized in that: include: The memory as claimed in any one of claims 1 to 13; A storage controller is coupled to the memory and is used to control the memory.

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