Superconducting quantum chip packaging structure and flip packaging method of superconducting quantum chip

Abstract

According to the superconducting quantum chip packaging structure and the flip packaging method of the superconducting quantum chip, the SU-8 photoresist with the characteristics of high resolution, high aspect ratio and the like is used and serves as a supporting structure, and flip packaging of the superconducting quantum chip is achieved. Compared with the prior art, the flip packaging method has the advantages that personalized design of the supporting structure can be realized according to different circuit wiring layer structures, large-scale integration of the superconducting quantum chip is facilitated, manual operation is not needed in the operation process, the mechanical degree is high, and the manufacturing cost is low. The flip chip packaging efficiency of the superconductive quantum chip can be remarkably improved, so that the manufacturing cost of the superconductive quantum chip is reduced, a space for flip operation does not need to be reserved around a device during flip packaging, the process of flip packaging on the superconductive quantum chip with the size of 4 * 4mm or smaller can be realized, and the production efficiency of the superconductive quantum chip is improved. And large-scale integration of the superconducting quantum chip is facilitated.

Description

Technical Field

[0001] The present invention relates to the technical field of microelectronic component manufacturing, and in particular to a superconducting quantum chip packaging structure and a flip-chip packaging method for the superconducting quantum chip. Background Art

[0002] In the field of microelectronics manufacturing, SU-8 photoresist has become an important micro-nano processing material because of its excellent properties. SU-8 photoresist is a negative photoresist with high contrast based on epoxy resin material. It can overcome the problem that ordinary photoresist adopts insufficient aspect ratio of ultraviolet light lithography, and its unique molecular structure makes its light absorption very low in the range of near-ultraviolet light (365nm-400nm), so that the exposure amount obtained by the whole photoresist layer is uniform, and SU-8 photoresist will undergo cross-linking reaction after being subjected to ultraviolet radiation, thereby obtaining the required micron-level pattern. The above-mentioned excellent performance of SU-8 photoresist makes it gradually applied to fields such as micro-electromechanical systems (MEMS), chip packaging and micro-processing. At present, directly using SU-8 photoresist to prepare microstructures and micro parts with high aspect ratio has become a new technology in the field of micro-processing.

[0003] However, although SU-8 photoresist has a wide range of applications in the MEMS field, its use in the flip-chip packaging technology of superconducting quantum chips is relatively rare. At present, only the solution proposed by the University of Chicago team can achieve non-electrical flip-chip based on SU-8 photoresist, but its process flow is mostly manual operation, which only uses SU-8 photoresist to make a "fence" structure on the chip, and requires manual dispensing, with poor stability and unable to achieve a high degree of integration. In addition, the solution also requires a gap of at least 4mm around the device to facilitate the flip-chip operation. Therefore, it is not suitable for small-size, high-precision superconducting quantum chip manufacturing.

[0004] It should be noted that the above introduction to the technical background is only for the convenience of providing a clear and complete description of the technical solutions of the present application and for the convenience of understanding by those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art simply because they are described in the background technology section of the present application. Summary of the invention

[0005] In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide a superconducting quantum chip packaging structure and a flip-chip packaging method of a superconducting quantum chip, which are used to solve the problems of low mechanization, poor repeatability and inability to achieve high integration in the flip-chip packaging of superconducting quantum chips using SU-8 photoresist in the prior art, and at the same time, the flip-chip packaging technology of superconducting quantum chips using SU-8 photoresist in the prior art cannot be applied to the manufacture of small-size, high-precision superconducting quantum chips.

[0006] To achieve the above-mentioned purpose and other related purposes, a flip-chip packaging method for a superconducting quantum chip comprises the following steps:

[0007] A semiconductor wafer is provided, comprising a first surface and a second surface arranged opposite to each other, wherein a circuit wiring layer is formed on the first surface of the semiconductor wafer;

[0008] coating a negative photoresist on the first surface of the semiconductor wafer to form a first photoresist layer;

[0009] exposing and developing the first photoresist layer to form a supporting structure;

[0010] Re-coating a negative photoresist on the support structure and other areas without a circuit wiring layer to form a second photoresist layer and slicing the semiconductor wafer to obtain a superconducting quantum chip;

[0011] The second chip is placed together with the superconducting quantum chip, thereby realizing flip-chip packaging of the superconducting quantum chip.

[0012] Optionally, before exposing and developing the first photoresist layer, a step of making a pattern mask is further included, and the shape of the pattern mask should be adapted to different types of superconducting quantum chips.

[0013] Optionally, the first photoresist layer is exposed and developed to form a support structure, including: pre-baking the first photoresist layer, then exposing it to light, so that the first photoresist layer is divided into an exposure area and a non-exposure area, baking the first photoresist layer after the exposure to cause a cross-linking reaction in the photoresist material in the exposure area, and developing the semiconductor wafer to obtain a support structure corresponding to the exposure area.

[0014] Optionally, the developing operation includes at least the following steps: first, the semiconductor wafer is immersed in a developer for a first time, then the developer is replaced and the semiconductor wafer is immersed in a second time, then it is rinsed with deionized water and immersed in isopropyl alcohol for a set time, and finally the semiconductor wafer is placed in a nitrogen environment for surface drying.

[0015] Optionally, the thickness of the first photoresist layer is at least 10 microns.

[0016] Optionally, the second photoresist layer is thicker than the first photoresist layer.

[0017] Optionally, the first photoresist layer, the second photoresist layer and the support structure are made of the same material and are all SU-8 photoresist.

[0018] Optionally, bonding the second chip to the superconducting quantum chip includes: using a mechanical arm to absorb the superconducting quantum chip and the second chip and aligning and leveling them, then heating the mechanical arm to a first temperature so that the supporting structure softens appropriately, then continuing to heat up to a second temperature to apply pressure to the superconducting quantum chip and the second chip and maintaining it for a fixed time to bond the superconducting quantum chip and the second chip, and after bonding the second chip to the superconducting quantum chip, removing the bonding pressure and continuing to heat up to a third temperature and maintaining it for a fixed time.

[0019] Optionally, the second chip is a control chip.

[0020] The present invention also provides a superconducting quantum chip packaging structure, wherein the superconducting quantum chip packaging structure is obtained according to any of the above-mentioned flip-chip packaging methods for the superconducting quantum chip.

[0021] As described above, the superconducting quantum chip packaging structure and the flip-chip packaging method of the superconducting quantum chip of the present invention have the following beneficial effects compared with the prior art: the flip-chip packaging method utilizes the high resolution and high aspect ratio characteristics of SU-8 photoresist to realize the customization of the required flip-chip structure on a chip size of 4*4mm or smaller, and the method does not require manual operation, and can realize high-precision superconducting quantum chip manufacturing. The technical solution has a simple operation process and a high degree of mechanization, and can significantly improve the packaging efficiency of the superconducting quantum chip flip chip and reduce the manufacturing cost of the superconducting quantum chip. It can also realize personalized design of the support structure according to different circuit wiring layer structures, which is more conducive to the large-scale integration of superconducting quantum chips. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 A process flow chart showing a flip-chip packaging method for a superconducting quantum chip provided by an embodiment of the present invention.

[0023] Figure 2 Shown is a schematic diagram of the cross-sectional structure of a semiconductor wafer provided in the flip-chip packaging method of the present invention.

[0024] Figure 3 It is a schematic diagram showing the cross-sectional structure of the first photolithography layer formed in the flip-chip packaging method of the present invention.

[0025] Figure 4 It is a schematic diagram of the structure after placing the pattern mask in the flip chip packaging method of the present invention.

[0026] Figure 5 It is a schematic diagram of the cross-sectional structure after exposure and development in the flip chip packaging method of the present invention.

[0027] Figure 6 It is a schematic diagram of the cross-sectional structure of the chip after bonding in the flip chip packaging method of the present invention.

[0028] Figure 7 Shown is the pressure and temperature control curve during flip-chip bonding of the present invention.

[0029] Component number description

[0030] 101, semiconductor wafer; 102, circuit wiring layer; 103, first photoresist layer; 104, pattern mask; 105, supporting structure; 106, superconducting quantum chip; 107, second chip; S1-S5, steps. DETAILED DESCRIPTION

[0031] The following is a description of the implementation of the present invention by means of specific embodiments. Those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification.

[0032] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and therefore the illustrations only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0033] See also Figures 1 to 7 It should be noted that the structures, proportions, sizes, etc. illustrated in the drawings of this specification are only used to match the contents disclosed in the specification for people familiar with this technology to understand and read, and are not used to limit the limiting conditions for the implementation of the present invention, so they have no substantial technical significance. Any modification of the structure, change in the proportion relationship, or adjustment of the size should still fall within the scope of the technical content disclosed by the present invention without affecting the effects and purposes that can be achieved by the present invention. At the same time, the terms such as "upper", "lower", "left", "right", "middle", "first", "second", etc. cited in this specification are only for the convenience of description, and are not used to limit the scope of the implementation of the present invention. Changes or adjustments in their relative relationships should also be regarded as the scope of the implementation of the present invention without substantially changing the technical content.

[0034] The embodiment of the present invention provides a flip-chip packaging method for a superconducting quantum chip, such as Figure 1 As shown, it is a process flow chart of the flip chip packaging method, which includes the following steps:

[0035] S1: providing a semiconductor wafer, comprising a first surface and a second surface arranged opposite to each other, wherein a circuit wiring layer is formed on the first surface of the semiconductor wafer;

[0036] S2: coating a negative photoresist on the first surface of the semiconductor wafer to form a first photoresist layer;

[0037] S3: exposing and developing the first photoresist layer to form a support structure;

[0038] S4: coating the support structure and other areas without circuit wiring layers with negative photoresist again to form a second photoresist layer and slicing the semiconductor wafer to obtain a superconducting quantum chip;

[0039] S5: Bonding the second chip to the superconducting quantum chip, thereby realizing flip-chip packaging of the superconducting quantum chip.

[0040] The following is a further introduction to the flip-chip packaging method of the superconducting quantum chip with reference to the accompanying drawings, as follows:

[0041] In step S1, see Figure 1 and Figure 2 , a semiconductor wafer 101 is provided, comprising a first surface 1011 and a second surface 1012 arranged opposite to each other, wherein a circuit wiring layer 102 is formed on the first surface 1011 of the semiconductor wafer.

[0042] Specifically, Figure 1 and Figure 2 As shown, it is a schematic diagram of a cross-sectional structure of a semiconductor wafer 101, and the semiconductor wafer 101 includes a plurality of chip regions and a circuit wiring layer 102 located in the chip region. Before the circuit wiring is performed on the provided semiconductor wafer 101, it is also necessary to inspect it, including appearance inspection, electrical performance inspection, flatness inspection, size inspection, etc., so that the quality of the semiconductor wafer 101 can meet the requirements of subsequent process processing. The provided semiconductor wafer 101 can be prepared from silicon or other semiconductor materials using existing technology.

[0043] In step S2, see Figure 1 and Figure 3 A negative photoresist is coated on the first surface of the semiconductor wafer 101 to form a first photoresist layer 103 .

[0044] The photoresist type provided in the embodiment of the present invention can be SU-8 photoresist. Specifically, when forming the first photoresist layer 103 on the semiconductor wafer 101, the semiconductor wafer 101 after inspection and treatment can be placed in a coating machine carrier and its surface can be blown clean using a nitrogen gun, and then the vacuum system is turned on to allow the semiconductor wafer 101 to be adsorbed and fixed on the coating machine carrier, and a rubber-tipped dropper is used to drop an appropriate amount of photoresist material onto the first side of the semiconductor wafer on which the circuit wiring layer is prepared. Here, taking a two-inch wafer as an example, the coating machine is started to perform a coating operation at a speed of 3000 rpm, and the first photoresist layer 103 is formed on the first side of the semiconductor wafer 101, and the thickness of the first photoresist layer 103 finally formed is not less than 10 microns. Of course, when the size of the semiconductor wafer 101 changes, the rotation speed of the coating machine and the amount of photoresist can be appropriately adjusted to achieve the adjustment of the thickness of the first photoresist layer 103.

[0045] In step S3, see Figure 1 , Figure 4 and Figure 5 , the first photoresist layer 103 is exposed and developed to form a support structure 105.

[0046] As an example, before exposing and developing the first photoresist layer 103, a step of making a pattern mask 104 is also included, and the shape of the pattern mask 104 should be adapted to different types of superconducting quantum chips. In this embodiment, before exposing and developing the first photoresist layer 103, since the circuit wiring layer 102 structures on different types of superconducting quantum chips are different, it is also necessary to make pattern masks 104 with different patterns according to the circuit wiring layers 102 with different structures formed on the semiconductor wafer 101. Figure 4 As shown, the pattern mask 104 can cover the circuit wiring layer 102 on the semiconductor wafer 101, thereby exposing the blank area of ​​the first surface of the semiconductor wafer 101 without the circuit wiring layer 102. And the pattern mask 104 can be reused, so as to reduce the manufacturing cost of the superconducting quantum chip. The step of exposing and developing the first photoresist layer 103 to form the support structure 105 provided in the embodiment of the present invention includes: pre-baking the first photoresist layer 103, and then exposing it to divide the first photoresist layer 103 into an exposure area and a non-exposure area, baking the first photoresist layer 103 after the exposure treatment to make the photoresist material in the exposure area produce a cross-linking reaction, and developing the semiconductor wafer 101 to obtain the support structure 105 corresponding to the exposure area.

[0047] In this embodiment, after the photoresist is evenly coated on the semiconductor wafer 101, the semiconductor wafer 101 needs to be placed in a drying device with a base temperature of 75°C for pre-baking treatment. The first drying time is set to 3 minutes. After the first drying, the drying equipment is ramped up to 110°C, and the drying time is set to 7 minutes, so as to remove moisture and part of the solvent in the first photoresist layer 103.

[0048] After placing the pattern mask 104, the first photoresist layer 103 is exposed by using an ultraviolet lithography machine. The pattern mask can divide the first photoresist layer 103 into an exposure area and a non-exposure area, and the semiconductor wafer 101 is developed, so that the first photoresist layer 103 corresponding to the exposure area can be retained to form the support structure 104. Specifically, in this embodiment, the ultraviolet lithography machine model used is a SUSS MA6 ultraviolet lithography machine, and the exposure dose of the exposure process is at least 220mJ / cm 2 ; and the first photoresist layer 103 after the exposure treatment is baked for at least 6 seconds, so that the photoresist material in the exposed area is fully cross-linked. Figure 5 As shown, a developing solution is then used to perform a developing operation on the semiconductor wafer 101 , so that the first photoresist layer 103 corresponding to the exposed area can be retained to form a supporting structure 104 .

[0049] In another embodiment, the developing operation includes at least the following steps: first, the semiconductor wafer 101 is immersed in a developer for a first time, then the developer is replaced to immerse the semiconductor wafer 101 for a second time, then it is rinsed with deionized water and immersed in isopropyl alcohol for a set time, and finally the semiconductor wafer 101 is placed in a nitrogen environment for surface drying.

[0050] Specifically, after removing the pattern mask, the semiconductor wafer 101 after the exposure process is placed in a developer for immersion, the type of the developer is JFX-PMA SU8 photoresist developer, the immersion time is not less than 2 minutes, and then a new developer is replaced for a second immersion development, the second immersion time is not less than 30 seconds, and then the semiconductor wafer 101 is rinsed with deionized water and immersed again with an isopropyl alcohol solution, the immersion time is not less than 20 seconds, and finally the semiconductor wafer 101 is placed in a nitrogen environment for surface drying treatment, so that the first photoresist layer 103 corresponding to the exposure area can be retained to form a support structure 104.

[0051] In step S4, see Figure 1, negative photoresist is coated again on the support structure 104 and other areas without circuit wiring layers to form a second photoresist layer (not shown in the figure) and the semiconductor wafer 101 is sliced ​​to obtain the superconducting quantum chip 106.

[0052] In the production process of the chip, it is also necessary to cut the semiconductor wafer 101 into slices, so as to form a small-sized chip. However, in the process of cutting the semiconductor wafer 101, it is possible to produce debris, thereby damaging the chip, thereby reducing the production yield. Therefore, in order to prevent the above-mentioned damage from occurring, the first side of the semiconductor wafer 101 is coated with a negative photoresist again to form a second photoresist layer, and the second photoresist layer is used as a protective adhesive layer. The step of coating the second photoresist layer is the same as the step of forming the first photoresist layer 103, and no further description is given here. Since the first photoresist layer 103 uses SU-8 photoresist, in order to ensure that the supporting structure will not be damaged in the subsequent process of removing the photoresist, the photoresist type used in the second photoresist layer here is the same as that of the first photoresist layer 103, and the thickness of the second photoresist layer is greater than the thickness of the first photoresist layer 103, thereby realizing the protection of the semiconductor wafer 101 and the circuit wiring layer 102. After coating the second photoresist layer, the second photoresist layer is baked to solidify the photoresist, thereby facilitating the subsequent scribing and cutting operation. The developer used to remove the second photoresist layer is the same as that used to develop the first photoresist layer 103, and since the thickness of the second photoresist layer is greater than that of the first photoresist layer 103, the immersion time should be extended at this time to ensure that the protective glue layer can be completely removed.

[0053] In step S5, refer to Figure 1 and Figure 6 , bonding the second chip 107 to the superconducting quantum chip 106, thereby realizing flip-chip packaging of the superconducting quantum chip.

[0054] After the semiconductor wafer is diced and cut into small-sized superconducting quantum chips 106, it is necessary to flip-chip bond the superconducting quantum chip 106 with the second chip 107. The steps of flip-chip bonding are as follows: Use a robotic arm to adsorb the superconducting quantum chip 106 and the second chip 107. Use a microscope, laser leveler and other tools to level them, then heat the robotic arm to a first temperature to allow the support structure 105 to soften appropriately. After the temperature reaches the desired temperature, apply a certain pressure and continue to heat it to the second temperature and maintain it for a fixed time to achieve the bonding of the superconducting quantum chip 106 and the second chip 107. After the bonding is completed, remove the bonding pressure and continue to heat it to the third temperature and maintain it for a fixed time. Figure 7 As shown, it shows the pressure and temperature control curve during flip-chip bonding. Figure 7The green curve in the figure represents the change in the pressure applied by the robot arm of the FC-150 device to the superconducting quantum chip 106 and the second chip 107 over time during the bonding process; Figure 7 The yellow and red curves in Figure 7 ) represent the temperature variation curves of the superconducting quantum chip 106 and the second chip 107 over time during the bonding and process; Figure 7 It can be seen that by applying bonding pressure to the superconducting quantum chip 106 and the second chip 107 and heating them up, and removing the bonding pressure and heating them up again and maintaining them for a period of time after the initial bonding is completed, the mechanical strength of the flip-chip bonding structure can be increased.

[0055] Specifically, in this embodiment, the flip-chip bonding equipment used is a FC150 PLATINUM multifunctional flip-chip bonding machine. Since the temperature resistance of SU-8 photoresist is about 200°C, the parameters in the heat treatment process of the flip-chip packaging of the superconducting quantum chip 106 and the second chip 107 can be set to a first temperature of not less than 100°C, a second temperature of not less than 130°C, a holding time of the second temperature of not less than 3 minutes, a third temperature of not less than 140°C, and a holding time of the third temperature of not less than 2 minutes. Of course, in the actual bonding process, we can also choose different heat treatment processes according to the different heat resistance of different types of superconducting quantum chips, which is not limited here.

[0056] In another embodiment, the second chip 107 is a control chip. The above flip-chip packaging technology is used to achieve high-precision bonding between the superconducting quantum chip 106 and the control chip. The heat treatment process added during the bonding process can enhance the thermal stability and mechanical strength of the chip, and achieve electrical coupling and mechanical fixation between the superconducting quantum chip and the control chip.

[0057] Based on the same inventive concept, an embodiment of the present invention further provides a superconducting quantum chip packaging structure, including a structure prepared by the flip-chip packaging method of the superconducting quantum chip provided by any of the above embodiments.

[0058] In summary, the superconducting quantum chip packaging structure of the present invention and the flip-chip packaging method of the superconducting quantum chip, compared to the prior art, the flip-chip packaging method can realize the personalized design of the supporting structure according to different circuit wiring layer structures, which is more conducive to the large-scale integration of superconducting quantum chips, and the operation process is simple, the mechanization degree is high, and the superconducting quantum chip flip chip packaging efficiency can be significantly improved, and the manufacturing cost of superconducting quantum chips is reduced. And due to the high resolution, high aspect ratio and other characteristics of SU-8 photoresist, there is no need to reserve the space for flip operation around the device when performing flip-chip packaging, and the process of flip-chip packaging can be realized on superconducting quantum chips of 4*4mm or smaller sizes, which is more conducive to the large-scale integration of superconducting quantum chips, and the method does not need to be manually operated, and can realize high-precision superconducting quantum chip manufacturing. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.

[0059] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A flip-chip packaging method for a superconducting quantum chip, characterized in that: The following steps are involved: A semiconductor wafer is provided, comprising a first surface and a second surface arranged opposite to each other, wherein a circuit wiring layer is formed on the first surface of the semiconductor wafer; coating a negative photoresist on the first surface of the semiconductor wafer to form a first photoresist layer; exposing and developing the first photoresist layer to form a supporting structure; Re-coating a negative photoresist on the support structure and other areas without a circuit wiring layer to form a second photoresist layer and slicing the semiconductor wafer to obtain a superconducting quantum chip; The second chip is bonded to the superconducting quantum chip, thereby realizing flip-chip packaging of the superconducting quantum chip.

2. The flip chip packaging method according to claim 1, characterized in that: Before exposing and developing the first photoresist layer, a step of making a pattern mask is also included, and the shape of the pattern mask should be adapted to different types of superconducting quantum chips.

3. The flip chip packaging method according to claim 1, characterized in that: The steps of exposing and developing the first photoresist layer to form a support structure include: pre-baking the first photoresist layer, then exposing it to divide the first photoresist layer into an exposure area and a non-exposure area, baking the first photoresist layer after the exposure to cause a cross-linking reaction in the photoresist material in the exposure area, and developing the semiconductor wafer to obtain a support structure corresponding to the exposure area.

4. The flip chip packaging method according to claim 3, characterized in that: The development operation includes at least the following steps: first, the semiconductor wafer is immersed in a developer for a first time, then the developer is replaced and the semiconductor wafer is immersed in a second time, then it is rinsed with deionized water and immersed in isopropyl alcohol for a set time, and finally the semiconductor wafer is placed in a nitrogen environment for surface drying.

5. The flip chip packaging method according to claim 1, characterized in that: The thickness of the first photoresist layer is at least 10 microns.

6. The flip chip packaging method according to claim 1, characterized in that: The second photoresist layer has a thickness greater than that of the first photoresist layer.

7. The flip chip packaging method according to claim 1, characterized in that: The first photoresist layer, the second photoresist layer and the support structure are made of the same material, which is SU-8 photoresist.

8. The flip chip packaging method according to claim 1, characterized in that: Bonding the second chip to the superconducting quantum chip includes: using a mechanical arm to absorb the superconducting quantum chip and the second chip and aligning and leveling them, then heating the mechanical arm to a first temperature so that the support structure softens appropriately, then continuing to heat up to a second temperature to apply pressure to the superconducting quantum chip and the second chip and maintaining it for a fixed time to bond the superconducting quantum chip and the second chip, and after the second chip is bonded to the superconducting quantum chip, removing the bonding pressure and continuing to heat up to a third temperature and maintaining it for a fixed time.

9. The flip chip packaging method according to claim 1, characterized in that: The second chip is a control chip.

10. A superconducting quantum chip packaging structure obtained according to the flip-chip packaging method of a superconducting quantum chip according to any one of claims 1 to 9.

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