SPI communication module and SPI communication system

Abstract

The invention discloses an SPI communication module and an SPI communication system, and belongs to the technical field of integrated circuits, the SPI communication module comprises an SPI function module and a test module, and the test logic of the test module and the function logic of the SPI function module are mutually independent; the test module comprises a plurality of test registers; the plurality of test registers control the SPI communication module to work in a normal mode or a test mode based on the configuration of the CPU; when the SPI communication module works in a normal mode, the test module does not work, and the SPI function module normally performs a communication function; when the SPI communication module works in the test mode, the input signal and the output signal of the SPI function module can be monitored by performing read-write access on the plurality of test registers, so that the SPI communication module is tested. According to the design, a user can be helped to quickly position an error source, the test difficulty is reduced, the test efficiency is improved, and meanwhile, the test coverage rate is also improved.

Description

Technical Field

[0001] The invention belongs to the technical field of integrated circuits, and in particular relates to an SPI communication module and an SPI communication system. Background Art

[0002] SPI (Serial Peripheral interface) is a high-speed, full-duplex, synchronous communication bus that only occupies four wires on the chip pins, saving the chip pins and saving space on the PCB (Printed Circuit Board) layout. It is precisely because of this simple and easy-to-use feature that more and more chips integrate SPI communication modules, which can also be referred to as SPI modules. For SPI communication modules, good testability design can help chip designers test whether the SPI communication module works properly in the overall chip system, and can also quickly locate the problem when a fault occurs.

[0003] The current testability design is divided into boundary scan test, memory built-in self-test and scan test. Among them, the goal of boundary scan test is to interconnect IO-PAD (Input / Output-PAD) using JTAG (Joint Test Action Group) interface for easy testing; memory built-in self-test is mainly aimed at internal SRAM (Static Random-Access Memory) and other storage modules; scan test is to replace all triggers in the chip with scan triggers, these scan triggers are connected together to form a scan chain, in the test mode, the scan chain can be used to move test data in and out, to achieve control and observation of the circuit.

[0004] However, the above boundary scan test targets IO-PAD instead of internal communication module, the memory built-in self-test is mainly for SRAM and other memories, and the scan test mainly tests whether the triggers in all modules can work normally. It can be seen that the existing chip testability design cannot test the internal modules of the chip, nor can it monitor the ports of the internal modules. When the system has problems, it is impossible to quickly locate the source of the error, which affects the chip testing efficiency and also reduces the reliability of the chip. Summary of the invention

[0005] In order to solve the above problems existing in the prior art, the present invention provides an SPI communication module and an SPI communication system. The technical problem to be solved by the present invention is achieved by the following technical solutions:

[0006] In a first aspect, the present invention provides an SPI communication module, the SPI communication module includes an SPI function module and a test module, and the test logic of the test module is independent of the function logic of the SPI function module; wherein the test module includes a plurality of test registers, and the plurality of test registers are connected to the SPI function module;

[0007] A plurality of test registers are based on the configuration of a CPU (Central Processing Unit) to control the SPI communication module to work in a normal mode or a test mode; when the SPI communication module works in the normal mode, the test module does not work, and the SPI functional module performs the communication function normally; when the SPI communication module works in the test mode, the input signal and the output signal of the SPI functional module can be monitored by reading and writing accesses to the plurality of test registers, thereby realizing the test of the SPI communication module.

[0008] In a second aspect, the present invention proposes an SPI communication system, comprising a CPU chip, wherein an SPI communication module is integrated in the CPU chip, wherein the SPI communication module comprises an SPI functional module and a test module, and the test logic of the test module is independent of the functional logic of the SPI functional module; wherein the test module comprises a plurality of test registers, wherein the plurality of test registers are connected to the SPI functional module, and are also connected to the CPU core via an AMBA (Advanced Microcontroller Bus Architecture) bus;

[0009] Based on the instructions issued by the host computer, the CPU core configures several test registers through the AMBA bus, thereby controlling the SPI communication module to work in normal mode or test mode; when the SPI communication module works in normal mode, the test module does not work, and the SPI functional module performs the communication function normally; when the SPI communication module works in test mode, the input signal and output signal of the SPI communication module can be monitored by reading and writing accesses to several test registers, thereby realizing the test of the SPI communication module.

[0010] Beneficial effects of the present invention:

[0011] The SPI communication module provided by the present invention embeds a test module in the SPI communication module at the beginning of chip design, and separates the test logic of the test module from the functional logic of the SPI functional module; the test module is mainly implemented by a plurality of test registers, and the SPI communication module is controlled to work in a normal mode or a test mode through the configuration of the CPU, and in the test mode, the input signal and the output signal of the SPI functional module are monitored by reading and writing access to these test registers, so as to realize the internal test of the SPI communication module. The design can help users quickly locate the source of errors, reduce the difficulty of testing, improve the test efficiency, save manpower and material resources, and also improve the test coverage.

[0012] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 It is an architecture diagram of an SPI communication module provided by an embodiment of the present invention;

[0014] Figure 2 It is a schematic diagram of a design scheme of a test input port of an SPI communication module provided in an embodiment of the present invention;

[0015] Figure 3 It is a schematic diagram of a design scheme for a test output port of an SPI communication module provided in an embodiment of the present invention;

[0016] Figure 4 It is an overall architecture diagram of the test module provided by an embodiment of the present invention;

[0017] Figure 5 It is a schematic diagram of a port design scheme for a loopback test mode of an SPI communication module provided in an embodiment of the present invention;

[0018] Figure 6 The present invention provides a CPU chip framework diagram including a test module in an SPI communication system. DETAILED DESCRIPTION

[0019] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0020] The first aspect of the present invention provides an SPI communication module. Figure 1 , Figure 1The present invention provides an architecture diagram of an SPI communication module provided by an embodiment of the present invention, wherein the SPI communication module includes an SPI function module and a test module (also referred to as an SPI test module), and the test logic of the test module is independent of the function logic of the SPI function module; wherein the test module includes a plurality of test registers, and the plurality of test registers are connected to the SPI function module;

[0021] Several test registers are based on the configuration of the CPU to control the SPI communication module to work in normal mode or test mode; when the SPI communication module works in normal mode, the test module does not work, and the SPI functional module performs the communication function normally; when the SPI communication module works in test mode, the input signal and output signal of the SPI functional module can be monitored by reading and writing accesses to several test registers, thereby realizing the test of the SPI communication module.

[0022] Generally speaking, the SPI communication module is a submodule of a chip, which is connected to the CPU via an AMBA bus and realizes normal functions based on the configuration of the CPU. The present invention embeds a test module in the SPI communication module, issues instructions to the CPU through C program programming, and performs normal function access and test access through the CPU and the SPI communication module.

[0023] Optionally, as an implementation method, the test module designed in this embodiment specifically includes four test registers, namely, a test control register, a test input register, a test output register and a test data register, and all four registers are readable and writable registers; at the same time, four test modes are also designed, namely, input test mode, output test mode, data test mode and loop test mode.

[0024] The relevant information of the four test registers is shown in Table 1 below.

[0025] Table 1 Test register list

[0026]

[0027]

[0028] Among them, the test control register is used to control the opening and closing of the test mode;

[0029] The test input register is used to read and write the input port of the SPI function module in the input test mode to implement the input path test of the signal from outside the chip to inside the chip;

[0030] The test output register is used to read and write the output port of the SPI function module in the output test mode to implement the output path test of the signal from inside the chip to outside the chip;

[0031] The test data register is used to read and write the transmit and receive FIFO of the SPI function module in the data test mode to implement the FIFO function test.

[0032] The internal design and function of each test register are introduced in detail below.

[0033] For the test control register SPITCR, this embodiment configures it as a readable and writable register with a bit width of 2; wherein,

[0034] The first bit is the test mode enable pin, which is configured by the CPU and connected to the test input register and the test output register;

[0035] The second bit is the test FIFO enable pin, which is configured by the CPU and connected to the test data register and FIFO.

[0036] The specific functional design of the test control register SPITCR can be reflected in detail in Table 2 below.

[0037] Table 2 Test control register function

[0038]

[0039] For the test input register SPITIR, this embodiment configures it as a readable and writable register with a bit width of 4; wherein,

[0040] The first bit is connected to the data input signal SPIRXD port of the SPI function module and is used to monitor the value of the SPIRXD port;

[0041] The second bit is connected to the chip select input signal SPISIN port of the SPI function module, which is used to monitor the value of the SPISIN port;

[0042] The third bit is connected to the clock synchronization input signal SPICLKIN port of the SPI function module, which is used to monitor the value of the SPICLKIN port;

[0043] The fourth bit is configured by the CPU to terminate the DMA transfer function.

[0044] The specific functional design of the test input register SPITIR can be detailed in Table 3 below.

[0045] Table 3 Test input register function

[0046]

[0047] For the test output register SPITOR, this embodiment configures it as a readable and writable register with a bit width of 7; wherein,

[0048] The first bit is configured by the CPU module to send out data output signals;

[0049] The second bit is configured by the CPU module to issue a chip select output signal;

[0050] The third bit is configured by the CPU module to issue a clock output signal;

[0051] The fourth bit is configured by the CPU module to issue a clock output enable signal;

[0052] The fifth bit is configured by the CPU module to issue an output enable signal;

[0053] The sixth bit is configured by the CPU and connected to the SPINTR port of the SPI function module to send an interrupt service request signal and monitor the value of the SPINTR port;

[0054] The seventh bit is configured by the CPU and connected to the SPIDMAREQ port of the SPI function module to output a DMA request signal and monitor the value of the SPIDMAREQ port.

[0055] The specific functional design of the test output register SPITOR can be shown in detail in Table 4 below.

[0056] Table 4 Test output register function

[0057]

[0058] For the test data register SPITDR, the test data register is configured as a readable and writable register with a bit width of 16; when the second bit of the test FIFO enable terminal of the test control register is configured as 1, the SPI communication module works in the data test mode, and the FIFO function is tested by writing data to the receive FIFO or reading data from the transmit FIFO.

[0059] The specific functional design of the test data register SPITDR can be detailed in Table 5 below.

[0060] Table 5. Test Data Registers

[0061]

[0062] The present invention aims at developing a test function for an SPI communication module in a chip. A test module mainly composed of test registers is embedded in the SPI communication module. The input signal and the output signal of the SPI communication module can be monitored by reading and writing accesses to the test registers.

[0063] It is understandable that after configuring the dedicated test registers for access, the input and output ports need to be designed to make the test independent from the normal function. The following is a detailed description of the port design of the SPI communication module in different test modes.

[0064] Specifically, the data input end of the test control register SPITCR is connected to the CPU through the AMBA bus, so that the CPU can configure its ITEN bit and TESTFIFO bit, thereby controlling the SPI communication module to work in normal mode or test mode. When ITEN is 1, the SPI communication module works in test mode; when ITEN is 0, the SPI communication module works in normal mode, and the ITEN bit of the test control register acts as a control end to control the test input register SPITIR and the test output register SPITOR. When TESTFIFO is 1, the FIFO can be read and written through the test register to perform data testing on the SPI communication module. When TESTFIFO is 0, the SPI communication module cannot be tested for data. The TESTFIFO bit of the test control register acts as a control end to control the test data register.

[0065] For the design of the SPI communication module test input port, the input signal generated by the test input register SPITIR is separated from the input signal in normal mode. When ITEN is 1, the SPI function module works in test mode, and the input signal is generated by the test input register; if ITEN is 0, the SPI function module works in normal mode, and the input signal is generated by the external module.

[0066] When the test mode is turned on, when the test input register SPITIR is working, the SPI communication module works in the input test mode. Figure 2 , Figure 2 1 is a schematic diagram of a design scheme for a test input port of an SPI communication module provided in an embodiment of the present invention. The data input end of the test input register is connected to the CPU via an AMBA bus; the fourth bit of the test input register (i.e., SPITIR[3]) is configured by the CPU and connected to the first multiplexer (i.e., Figure 2 The first input terminal of the multiplexer 1) in the test module; the second input terminal of the first multiplexer is connected to the Ex_DMACLR (clear interrupt) port of the test module; the control terminal of the first multiplexer is connected to the test mode enable terminal;

[0067] When the SPI communication module operates in the normal mode, the first multiplexer selects the DMA clear signal of the Ex_DMACLR port of the output test module to the input port of the SPI function module;

[0068] When the SPI communication module works in input test mode, the CPU sends a DMACLR (clear interrupt) signal to the SPI function module by writing the fourth bit of the test input register. At the same time, by reading the first to third bits of the test input register (i.e., SPITIR[2:0]), it monitors the value of the SPI function module input port to determine whether the signal input path from outside the chip to inside the chip is normal.

[0069] Specifically, when writing 1 to ITEN in the test control register, the port input signal is determined by the corresponding bit in the SPITIR register. Writing 1 and then 0 to SPITIR[3] can simulate the transfer clear signal sent by the external DMA controller, and reading this bit can tell what the clear value sent by the DMA controller to the SPI function module is.

[0070] In input test mode, by writing the SPITIR[3] bit, the DMA module in the chip sends the DMACLR signal to the SPI function module instead of the DMA module in the chip. By reading the value of the SPI input port monitored by SPITIR[2:0], it is determined whether the data path from the outside of the chip to the inside of the chip is normal.

[0071] Furthermore, for the design of the SPI functional module test output port, the output signal generated by the test is separated from the signal generated by the normal function. If ITEN is 1, the output signal is generated by the test register; if ITEN is 0, the output signal is generated by the internal functional module.

[0072] When the test mode is on, when the test output register SPITOR is working, the SPI communication module works in the output test mode. Figure 3 , Figure 3 1 is a schematic diagram of a design scheme for a test output port of an SPI communication module provided in an embodiment of the present invention. The data input end of the test output register is connected to the CPU via an AMBA bus; the sixth and seventh bits of the test output register (i.e., SPITOR[6:5]) are configured by the CPU and connected to the second multiplexer (i.e., Figure 3 The first input terminal of the multiplexer 2) in the multiplexer; the second input terminal of the second multiplexer is connected to the SPIDMAREQ port and the SPINTR port of the SPI function module; the control terminal of the second multiplexer is connected to the test mode enable terminal;

[0073] The first to fifth bits of the test output register (i.e., SPITOR[4:0]) are configured by the CPU module and connected to the third multiplexer (i.e., Figure 3The first input terminal of the multiplexer 3) in the third multiplexer; the second input terminal of the third multiplexer is connected to the normal function register of the SPI function module, and the control terminal of the third multiplexer is connected to the test mode enable terminal;

[0074] When the SPI communication module works in normal mode, the second multiplexer selects to output the data of the SPIDMAREQ port and the SPIINTR port of the SPI function module to the DMA controller and the interrupt controller; the third multiplexer selects to output the data of the normal function register of the SPI function module to the output port of the SPI function module;

[0075] When the SPI communication module operates in the output test mode, the second multiplexer selects the sixth and seventh bits of the output test output register to the DMA controller and the interrupt controller; the third multiplexer selects the first to fifth bits of the output test output register to the output port of the SPI functional module.

[0076] Specifically, when ITEN in the test control register is written as 1, the test mode is entered, and then SPITOR[6:5] is written as 1 and then as 0 to issue a DMA request signal and an interrupt request signal. When ITEN is written as 0, the signal value generated by the internal functional module can be known by reading this register to determine whether there is an internal error.

[0077] In the output test mode, by writing the SPITOR[6:5] bits, the normal function modules in the SPI send signals to the DMA and interrupt controller instead of sending signals. By writing the SPITOR[4:0] bits, data is sent to the SPI output port to determine whether the data path from the chip inside to the outside is normal.

[0078] Further, when the test mode is turned on, when the test data register SPIDR works, the SPI communication module specifically works in the data test mode.

[0079] In the data test mode, the data reading and writing of the test FIFO in the SPI function module is controlled by reading and writing the SPITDR register to determine whether the normal FIFO functions normally.

[0080] This embodiment reasonably designs the functions of the four test registers in the test module and the port design of each test register and the SPI communication module, and realizes the test of different ports of the SPI function module. The overall architecture of the test module is as follows: Figure 4 As shown, each test register in the figure is mainly implemented by a D flip-flop, and the signal description of each port in the figure is shown in Table 6 below.

[0081] Table 6 Test module port signal description

[0082]

[0083]

[0084] Among them, the port signals are divided into AMBA bus signals, SPI internal signals, and SPI communication signals. Among them, SPICR mainly generates the enable signal of the multiplexer inside the test module.

[0085] In the test mode, the test input register SPITIR can mainly read the clock, data and other signals received on the SPI channel for monitoring, and can also generate a DMA clear signal to transmit to the SPI control core.

[0086] In the test mode, the test output register SPITOR can mainly read the clock, data and other signals sent by the SPI controller for monitoring. It can also generate a DMA request signal to the DMA controller in the chip, and can also generate an interrupt request signal to the interrupt controller in the chip.

[0087] If you want to read the value of a test register, you can access the address of the corresponding test register through the CPU to read the data, and the data is sent to the APB bus through PRDATA.

[0088] Depend on Figure 4 It can be seen that when ITEN is 0, SPI works in normal mode, all test registers are turned off, and the test module input signal will bypass all test registers and be directly output without affecting normal functions.

[0089] It should be noted that when the test mode is turned on, the input port and output port of the SPI function module can also be connected to make the SPI communication module work in the loopback test mode. Figure 5 shown.

[0090] In the loopback test mode, the SPI function module can be used to send and receive signals autonomously to check whether the entire data path is normal.

[0091] The SPI communication module provided by the present invention has a test module embedded in the SPI communication module at the beginning of chip design, and the test logic of the test module is separated from the functional logic of the SPI functional module; the test module is mainly implemented by a number of test registers, and the SPI communication module is controlled to work in a normal mode or a test mode through the configuration of the CPU. In the test mode, the input signal and the output signal of the SPI functional module are monitored by reading and writing access to these test registers, so as to realize the internal test of the SPI communication module. Specifically, in the SPI communication module designed by the present invention, the signal is mainly divided into two parts, one part is the data for communication between SPIs, and the other part is the bus signal for communication between the internal module and the CPU core. The test module embedded in the SPI communication module is mainly used to monitor the communication data of the SPI functional module and a part of the bus signal. When the test function is not turned on, all data will bypass the test module and directly enter the SPI functional module. This design can help users quickly locate the source of the error, reduce the difficulty of testing, improve the efficiency of testing, save manpower and material resources, and also improve the test coverage.

[0092] The second aspect of the present invention also provides an SPI communication system, which includes a CPU chip, an SPI communication module integrated in the CPU chip, and the SPI communication module includes an SPI functional module and a test module, and the test logic of the test module is independent of the functional logic of the SPI functional module. Figure 6 , Figure 6 The present invention provides a CPU chip framework diagram including a test module in a SPI communication system. The test module includes a plurality of test registers, which are connected to the SPI function module and are also connected to the CPU core via an AMBA bus.

[0093] Based on the instructions issued by the host computer, the CPU core configures several test registers through the AMBA bus, thereby controlling the SPI communication module to work in normal mode or test mode; when the SPI communication module works in normal mode, the test module does not work, and the SPI functional module performs the communication function normally; when the SPI communication module works in test mode, the input signal and output signal of the SPI functional module can be monitored by reading and writing accesses to several test registers, thereby realizing the test of the SPI communication module.

[0094] For the specific structural design and testing principle of the SPI communication module, please refer to the relevant description in the first aspect above. It can be seen that the SPI communication module provided by the present invention can mainly realize the following functions:

[0095] 1. Capture the input signal of the SPI function module and enter it into the internal register for monitoring;

[0096] 2. Simulate the output signal of the SPI function module;

[0097] 3. Connect the input and output signals of the SPI function module to test whether the SPI communication module is connected to the system correctly.

[0098] The generation, transmission and reception of the test signal are all carried out through the AMBA bus.

[0099] Therefore, the SPI communication system provided by the present invention can also implement the test of the SPI functional module, so as to determine whether the chip works normally in the system, improve the reliability of the chip, reduce the test difficulty, and improve the test efficiency.

[0100] In the description of the present invention, it should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0101] Although the present application is described herein in conjunction with various embodiments, in the process of implementing the claimed application, those skilled in the art may understand and implement other changes to the disclosed embodiments by viewing the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other components or steps, and "one" or "an" does not exclude multiple situations. A single processor or other unit may implement several functions listed in the claims. Certain measures are recorded in different dependent claims, but this does not mean that these measures cannot be combined to produce good results.

[0102] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the protection scope of the present invention.

Claims

1. An SPI communication module, characterized in that: The SPI communication module includes an SPI functional module and a test module, and the test logic of the test module is independent of the functional logic of the SPI functional module; wherein the test module includes a plurality of test registers, and the plurality of test registers are connected to the SPI functional module; The several test registers control the SPI communication module to operate in normal mode or test mode based on the configuration of the CPU; when the SPI communication module operates in normal mode, the test module does not operate, and the SPI functional module performs the communication function normally; when the SPI communication module operates in test mode, the input signal and output signal of the SPI functional module can be monitored by performing read and write access to the several test registers, thereby realizing the test of the SPI communication module.

2. The SPI communication module according to claim 1, characterized in that: The test module specifically includes four test registers, namely a test control register, a test input register, a test output register and a test data register; the test mode includes an input test mode, an output test mode, a data test mode and a loopback test mode; wherein, The test control register is used to control the opening and closing of the test mode; The test input register is used to read and write the input port of the SPI functional module in the input test mode to implement the input path test of the signal from outside the chip to inside the chip; The test output register is used to read and write the output port of the SPI functional module in the output test mode to implement the output path test of the signal from inside the chip to outside the chip; The test data register is used to read and write the sending and receiving FIFO of the SPI functional module in the data test mode to implement the test of the FIFO function.

3. The SPI communication module according to claim 2, characterized in that: The test control register is configured as a register with a bit width of 2; wherein, The first bit is a test mode enable terminal, which is configured by the CPU and connected to the test input register and the test output register; The second bit is a test FIFO enable terminal, which is configured by the CPU and connected to the test data register and the FIFO.

4. The SPI communication module according to claim 3, characterized in that: The test input register is configured as a register with a bit width of 4; wherein, The first bit is connected to the data input signal SPIRXD port of the SPI function module and is used to monitor the value of the SPIRXD port; The second bit is connected to the chip select input signal SPISIN port of the SPI function module, and is used to monitor the value of the SPISIN port; The third bit is connected to the clock synchronization input signal SPICLKIN port of the SPI functional module, and is used to monitor the value of the SPICLKIN port; The fourth bit is configured by the CPU to terminate the DMA transfer function.

5. The SPI communication module according to claim 4, characterized in that: The data input end of the test input register is connected to the CPU via the AMBA bus; the fourth bit of the test input register is connected to the first input end of the first multiplexer after being configured by the CPU; the second input end of the first multiplexer is connected to the Ex_DMACLR port of the test module; the control end of the first multiplexer is connected to the test mode enable end; When the SPI communication module operates in normal mode, the first multiplexer selects to output the DMA clear signal of the Ex_DMACLR port of the test module to the input port of the SPI function module; When the SPI communication module operates in input test mode, the CPU sends a DMACLR signal to the SPI functional module by writing the fourth bit of the test input register, and monitors the value of the input port of the SPI functional module by reading the first to third bits of the test input register to determine whether the input path of the signal from outside the chip to inside the chip is normal.

6. The SPI communication module according to claim 3, characterized in that: The test output register is configured as a register with a bit width of 7; wherein, The first bit is configured by the CPU to send out data output signals; The second bit is configured by the CPU to issue a chip select output signal; The third bit is configured by the CPU to issue a clock output signal; The fourth bit is configured by the CPU to issue a clock output enable signal; The fifth bit is configured by the CPU to issue an output enable signal; The sixth bit is configured by the CPU and connected to the SPINTR port of the SPI function module, for sending an interrupt service request signal and monitoring the value of the SPINTR port; The seventh bit is configured by the CPU and connected to the SPIDMAREQ port of the SPI function module for outputting a DMA request signal and monitoring the value of the SPIDMAREQ port.

7. The SPI communication module according to claim 6, characterized in that: The data input end of the test output register is connected to the CPU via the AMBA bus; the sixth and seventh bits of the test output register are connected to the first input end of the second multiplexer after being configured by the CPU; the second input end of the second multiplexer is connected to the SPIDMAREQ port and the SPIINTR port of the SPI function module; the control end of the second multiplexer is connected to the test mode enable end; The first to fifth bits of the test output register are connected to the first input terminal of the third multiplexer after being configured by the CPU; the second input terminal of the third multiplexer is connected to the normal function register of the SPI function module, and the control terminal of the third multiplexer is connected to the test mode enable terminal; When the SPI communication module operates in normal mode, the second multiplexer selects to output data of the SPIDMAREQ port and the SPIINTR port of the SPI function module to the DMA controller and the interrupt controller; the third multiplexer selects to output data of the normal function register of the SPI function module to the output port of the SPI function module; When the SPI communication module operates in the output test mode, the second multiplexer selects to output the sixth and seventh bits of the test output register to the DMA controller and the interrupt controller; the third multiplexer selects to output the first to fifth bits of the test output register to the output port of the SPI functional module.

8. The SPI communication module according to claim 7, characterized in that: When the SPI communication module operates in a loopback test mode, the output port of the SPI functional module is connected to the input port to implement a test of the connection relationship between the SPI communication module and the off-chip system.

9. The SPI communication module according to claim 3, characterized in that: The test data register is configured as a register with a bit width of 16; when the second bit test FIFO enable terminal of the test control register is configured as 1, the SPI communication module operates in data test mode, and the FIFO function is tested by writing data into the receiving FIFO or reading data from the transmitting FIFO.

10. An SPI communication system, comprising a CPU chip, characterized in that: The CPU chip is integrated with an SPI communication module, the SPI communication module includes an SPI function module and a test module, and the test logic of the test module is independent of the function logic of the SPI function module; wherein the test module includes a plurality of test registers, the plurality of test registers are connected to the SPI function module, and are also connected to the CPU core through an AMBA bus; The CPU core configures the several test registers through the AMBA bus based on the instructions issued by the host computer, thereby controlling the SPI communication module to work in a normal mode or a test mode; when the SPI communication module works in the normal mode, the test module does not work, and the SPI functional module performs the communication function normally; when the SPI communication module works in the test mode, the input signal and the output signal of the SPI functional module can be monitored by reading and writing the several test registers, thereby realizing the test of the SPI communication module.

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