Test signal processing method, programmable logic device, computer equipment, readable storage medium and program product

Abstract

The invention relates to a test signal processing method, a programmable logic device, computer equipment, a computer readable storage medium and a computer program product. The method is applied to a programmable logic device and comprises the following steps: receiving a corresponding first test signal through at least one first interface; analyzing each first test signal to obtain target data, and sending the target data to an upper computer through a second interface; receiving protocol data in a target format sent by the upper computer through the second interface, wherein the protocol data comprises protocol configuration data and a second test signal; and determining a target first interface according to the protocol configuration data, and sending a second test signal through the target first interface. By adopting the method, on one hand, the accuracy of a protocol data test result is improved, on the other hand, the programmable logic device can perform protocol analysis and protocol test, and the flexibility of the programmable logic device is improved.

Description

Technical Field

[0001] The present application relates to the field of communication technology, and in particular to a test signal processing method, a programmable logic device, a computer device, a computer-readable storage medium, and a computer program product. Background Art

[0002] Chips, such as SOC (System on Chip), MCU (Micro Control Unit), etc., require a large number of communication peripheral protocols, such as SPI (Serial Peripheral Interface), UART (Universal Asynchronous Receiver / Transmitter), I2C (Inter-Integrated Circuit), etc.

[0003] A conventional protocol analysis system receives protocol data through a communication peripheral protocol interface and analyzes the protocol data. When the protocol analysis process is used as a test of the protocol data, the accuracy of the protocol data test result is not high. Summary of the invention

[0004] Based on this, it is necessary to provide a test signal processing method, a programmable logic device, a computer device, a computer-readable storage medium and a computer program product that can improve the accuracy of protocol testing in response to the above technical problems.

[0005] In a first aspect, the present application provides a test signal processing method, which is applied to a programmable logic device, and the method comprises:

[0006] receiving a corresponding first test signal through at least one first interface;

[0007] Analyze each of the first test signals to obtain target data, and send the target data to a host computer through a second interface;

[0008] Receiving protocol data in a target format sent by the host computer through the second interface, the protocol data including protocol configuration data and a second test signal;

[0009] A target first interface is determined according to the protocol configuration data, and the second test signal is sent through the target first interface.

[0010] In one embodiment, determining the target first interface according to the protocol configuration data includes:

[0011] Parsing the protocol configuration data, determining a target detection module, and a communication baud rate and a communication mode of the target detection module;

[0012] In the communication mode, the second test signal is sent to the corresponding enhanced capture module by the target detection module according to the communication baud rate;

[0013] According to the enhanced capture module, a target first interface is determined; wherein the enhanced capture module is used to send the second test signal to the target first interface.

[0014] In one embodiment, the second test signal includes at least one of a sending Tx signal, a clock line SCL signal, and a clock CLK signal; and sending the second test signal to the corresponding enhanced capture module according to the communication baud rate by the target detection module includes at least one of the following:

[0015] When the target detection module is a UART detection module, the Tx signal is sent to the corresponding first enhanced capture module according to the communication baud rate through the UART detection module;

[0016] When the target detection module is an I2C detection module, the clock line SCL signal is sent to the corresponding second enhanced capture module according to the communication baud rate through the I2C detection module;

[0017] When the target detection module is an SPI detection module, the clock CLK signal is sent to the corresponding third enhanced capture module through the SPI detection module according to the communication baud rate;

[0018] Accordingly, the target first interface includes at least one of a first interface configured as a UART protocol, a first interface configured as an I2C protocol, and a first interface configured as an SPI protocol; and the method further includes at least one of the following:

[0019] Sending the transmit Tx signal to a first interface configured as a UART protocol through the first enhanced capture module;

[0020] Sending the clock line SCL signal to a first interface configured as an I2C protocol through the second enhanced capture module;

[0021] The clock CLK signal is sent to a first interface configured as an SPI protocol through the third enhanced capture module.

[0022] In one embodiment, the receiving a corresponding first test signal through at least one first interface includes:

[0023] Receiving a corresponding first test signal through at least two first interfaces; each of the first interfaces corresponds to a protocol, and the protocol types are different;

[0024] After receiving the corresponding first test signal through at least one first interface, the method further includes:

[0025] Acquire clock information of the first test signal through the enhanced capture modules corresponding to the first interfaces;

[0026] A detection module corresponding to the enhanced capture module is determined according to the clock information, and the first test signal is received through the detection module.

[0027] In one embodiment, the first test signal includes at least one of a transmitted Tx signal, a clock line SCL signal, and a clock CLK signal; and the acquiring clock information of the first test signal through the enhanced capture module corresponding to each of the first interfaces includes at least one of the following:

[0028] When the communication protocol of the first interface is configured as the UART protocol, the clock information of the Tx signal is captured by the enhanced capture module corresponding to the first interface configured as the UART protocol;

[0029] When the communication protocol of the first interface is configured as the I2C protocol, the clock information of the clock line SCL signal is captured by the enhanced capture module corresponding to the first interface configured as the I2C protocol;

[0030] When the communication protocol of the first interface is configured as the SPI protocol, the clock information of the clock CLK signal is captured by the enhanced capture module corresponding to the first interface configured as the SPI protocol.

[0031] In one embodiment, the protocol for configuring the second interface includes a UART protocol and a USB protocol, and the second interface includes a UART module and a USB module, wherein the protocol for configuring the UART module includes the UART protocol; and the protocol for configuring the USB module includes the USB protocol.

[0032] In a second aspect, the present application further provides a programmable logic device, the programmable logic device comprising:

[0033] At least one first interface, configured to receive a first test signal;

[0034] A processing module, used for analyzing each of the first test signals to obtain target data;

[0035] The second interface is used to send the target data to the host computer; and is also used to receive the protocol data in the target format sent by the host computer, wherein the protocol data includes protocol configuration data and a second test signal;

[0036] The processing module is further used to determine a target first interface according to the protocol configuration data, and send the second test signal through the target first interface.

[0037] In a third aspect, the present application further provides a computer device, including a memory and a processor, wherein the memory stores a computer program, and the processor implements the steps of the above method when executing the computer program.

[0038] In a fourth aspect, the present application further provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program implements the steps of the above method when executed by a processor.

[0039] In a fifth aspect, the present application also provides a computer program product, including a computer program, which implements the steps of the above method when executed by a processor.

[0040] The above-mentioned test signal processing method, device, computer equipment, computer-readable storage medium and computer program product, first, receive the first test signal sent by the peripheral device through at least one first interface through the programmable logic device to implement the analysis of the first test signal, and then, the host computer sends the second test signal to the peripheral device through the second interface, that is, the programmable logic device can implement the transmission of protocol data while implementing the analysis of the protocol, and the programmable logic device can flexibly switch in both directions. Compared with the results of the one-way process of only relying on the analysis of the protocol in the related art, the present application can determine the final test result of the protocol data based on the test results of the first test signal and the test results of the second test signal, on the one hand, improve the accuracy of the test results of the protocol data, on the other hand, it also enables the programmable logic device to perform both protocol analysis and protocol testing, thereby improving the flexibility of the programmable logic device. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the drawings required for use in the embodiments of the present application or related technical descriptions will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0042] FIG1 is a diagram showing an application environment of a test signal processing method according to an embodiment;

[0043] FIG2 is a schematic diagram of a flow chart of a test signal processing method in one embodiment;

[0044] FIG3 is a schematic diagram of a process of determining a target first interface according to protocol configuration data in one embodiment;

[0045] FIG4 is a schematic diagram of a process in which a target detection module sends a test signal to an enhanced capture module in one embodiment;

[0046] FIG5 is a schematic diagram of a process of an enhanced capture module sending a test signal to a target first interface in one embodiment;

[0047] FIG6 is a schematic diagram of a processing flow of a first test signal in another embodiment;

[0048] FIG7 is a schematic diagram of a process of an enhanced capture module acquiring clock information of a first test signal in one embodiment;

[0049] FIG8 is a schematic diagram of a flow chart of analyzing and testing signals of a programmable logic device in another embodiment;

[0050] FIG9 is a block diagram of a programmable logic device in one embodiment;

[0051] FIG. 10 is a diagram showing the internal structure of a computer device in one embodiment. DETAILED DESCRIPTION

[0052] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0053] The test signal processing method provided in the embodiment of the present application can be applied to the application environment as shown in Figure 1. Among them, the external device 101 communicates with the host computer 103 through the programmable logic device 102. The programmable logic device 102 receives the first test signal sent by the corresponding external device 101 through at least one first interface; analyzes each first test signal to obtain target data, and sends the target data to the host computer 103 through the second interface; receives the protocol data of the target format sent by the host computer 103 through the second interface, and the protocol data includes protocol configuration data and a second test signal; according to the protocol configuration data, the target first interface is determined, and the second test signal is sent to the external device 101 through the target first interface. Among them, the external device 102 can be, but is not limited to, various input devices, output devices and external storage devices, such as keyboards, mice, pen input devices, scanners, printers, mobile storage devices, etc. The host computer 103 can be, but is not limited to, various personal computers, laptops, smart phones, tablet computers, etc.

[0054] In an exemplary embodiment, as shown in FIG2 , a test signal processing method is provided, which is described by taking the method applied to the programmable logic device in FIG1 as an example, and includes the following steps S202 to S208 . Among them:

[0055] Step S202: receiving a corresponding first test signal through at least one first interface.

[0056] The first interface is a peripheral device interface, which is used to receive a first test signal sent by a peripheral device.

[0057] Optionally, the programmable logic device receives the corresponding first test signal 1 through the peripheral interface 1; the programmable logic device simultaneously receives the corresponding first test signal 1 through the peripheral interface 1; and receives the corresponding first test signal 2 through the peripheral interface 2. As shown in FIG. 1 , the programmable logic device simultaneously receives the corresponding first test signal 1 through the peripheral interface 1; receives the corresponding first test signal 2 through the peripheral interface 2; and receives the corresponding first test signal 3 through the peripheral interface 3.

[0058] In practical applications, the number of peripheral interfaces in a programmable logic device can be adjusted according to actual conditions, and no limitation on the number is made here.

[0059] Step S204, analyzing each first test signal to obtain target data, and sending the target data to the host computer through the second interface.

[0060] Among them, the second interface can be a universal serial bus (USB) to asynchronous serial port module. That is, the protocol for configuring the universal serial interface includes the USB protocol; the protocol for configuring the serial port module includes the serial port protocol, and the asynchronous serial port module can be an interface configured as a UART (Universal Asynchronous Receiver / Transmitter) protocol. The second interface is connected to the USB of the host computer through a USB module to asynchronous serial port module (for example, a UART module), as shown in Figure 1, and is connected to the USB of the host computer on the one hand, and is connected to the communication UART module of the programmable logic device on the other hand.

[0061] Optionally, the programmable logic device analyzes and organizes each first test signal through a processing and analysis unit to obtain target data. For example, after analyzing and organizing each received first test signal, the target data obtained is "date: 1 2 3 4"; the target data "date: 1 2 3 4" is forwarded to the second interface through the communication UART module, and the second interface first receives the target data through an interface configured as a UART protocol, and then forwards the target data to a USB module; finally, the target data is sent from the USB module of the second interface to the USB module of the host computer, and the host computer now receives the target data sent through the second interface, and the host computer can also display the received target data.

[0062] Step S206: receiving protocol data in a target format sent by the host computer through the second interface, where the protocol data includes protocol configuration data and a second test signal.

[0063] The protocol data is a string of characters. The target format specifies the field information carried by the string, as shown in Table 1, such as test module, test mode, module channel, project and parameters, etc., where the project and parameters include the communication baud rate and communication mode of the protocol configuration.

[0064] Optionally, the host computer sends the protocol data in the target format to the programmable logic device. The protocol data in the target format can be sent to the USB module of the second interface through the USB module of the host computer, and the USB module of the second interface forwards the protocol data in the target format to the UART module of the second interface, so as to complete the conversion of the protocol data in the target format. Finally, the second interface forwards the protocol data in the target format that has completed the conversion to the communication URAT module through the UART module. For example, the target format is the protocol data carrying the test module, test mode, module channel, project and parameter fields. The protocol data includes protocol configuration data and transmission data content, that is, the second test signal. So that the programmable logic device can parse the protocol data in the communication URAT module. Among them, the protocol configuration data includes communication baud rate and communication mode. The second test signal can be "1 23" or "ABC". The content of the second test signal is not limited here. Among them, UART belongs to asynchronous communication.

[0065] Optionally, the programmable logic device receives protocol data in a target format through a communication UART module connected to the second interface, where the protocol data includes protocol configuration data and a second test signal.

[0066] Table 1 Fields that can be carried by protocol data

[0067]

[0068] Step S208: determine the target first interface according to the protocol configuration data, and send the second test signal through the target first interface.

[0069] Optionally, the programmable logic device receives protocol configuration data through the communication UART module, parses the protocol configuration data, obtains the detection module name, the communication mode of the detection module and the communication baud rate of the detection module, and determines the target first interface through the detection module name. At the same time, the programmable logic device receives the second test signal through the communication UART module, and determines the corresponding first interface of the detection module obtained by parsing the protocol configuration data as the target first interface.

[0070] It should be noted that the programmable logic device may first execute step S202 to step S204 and then execute step S206 to step S208; or may first execute step S206 to step S208 and then execute step S202 to step S204.

[0071] In the above-mentioned test signal processing method, a programmable logic device receives a first test signal sent by a peripheral device through at least one first interface to implement the analysis of the first test signal. The method also includes a host computer sending a second test signal to the peripheral device through a second interface, that is, the programmable logic device can implement the transmission of protocol data while implementing the analysis of the protocol, and the programmable logic device can flexibly switch in both directions. Compared with the results of the one-way process of only relying on the analysis of the protocol in the related art, the present application can determine the final test result of the protocol data based on the test results of the first test signal and the test results of the second test signal, which improves the accuracy of the test results of the protocol data on the one hand, and enables the programmable logic device to perform both protocol analysis and protocol testing on the other hand, thereby improving the flexibility of the programmable logic device.

[0072] In an exemplary embodiment, as shown in FIG3 , determining the target first interface according to the protocol configuration data includes steps S302 to S306 . In which:

[0073] Step S302, parsing the protocol configuration data, determining the target detection module, and the communication baud rate and communication mode of the target detection module.

[0074] Optionally, the programmable logic device reads the protocol configuration data from the communication UART module through the processing and analysis unit, parses the protocol configuration data, obtains the detection module name, the communication mode of the detection module and the communication baud rate of the detection module, thereby determining the target detection module, the communication mode and the communication bit rate. The communication mode is used to characterize the current state of the target detection module, and is used to receive data or send data. In an optional embodiment, the protocol configuration data, for example, "UART config 0 baudr:115200 mode:0" represents that the UART detection module is configured as standard mode 0, and the communication baud rate is 115200. At this time, the UART detection module is configured as standard mode 0, which can be a receiving mode; the communication baud rate is 115200.

[0075] Step S304: in the communication mode, the target detection module sends the second test signal to the corresponding enhanced capture module according to the communication baud rate.

[0076] Optionally, if the communication mode is to send data, when the communication mode is to send data, the programmable logic device sends the second test signal to the corresponding enhanced capture module through the target detection module according to the communication baud rate. Each target detection module corresponds to an enhanced capture module one by one. Detection module 1 corresponds to enhanced capture module 1; detection module 2 corresponds to enhanced capture module 2; detection module 3 corresponds to enhanced capture module 3.

[0077] Optionally, the programmable logic device parses "UART write 0 data0:1 data1:2 data2:3" to obtain three second test signals sent by UART, which are 1, 2, and 3. As shown in FIG1 , the target detection module is a UART detection module. In the standard mode, the UART detection module sends three second test signals, which are 1, 2, and 3, to the corresponding enhanced capture module eCAP1 according to the communication baud rate of 115200.

[0078] Step S306, determining the target first interface according to the enhanced capture module; wherein the enhanced capture module is used to send the second test signal to the target first interface.

[0079] The enhanced capture modules correspond to the first interfaces one by one. The enhanced capture module 1 corresponds to the first interface 1; the enhanced capture module 2 corresponds to the first interface 2; and the enhanced capture module 3 corresponds to the first interface 3.

[0080] Optionally, since the enhanced capture module corresponds to the first interface one by one, the programmable logic device determines the corresponding first interface as the target first interface according to the enhanced capture module. In the case of the enhanced capture module 2, the first interface 2 is used as the target first interface. For example, the programmable logic device sends the second test signal to the first interface 2 through the enhanced capture module 2. As shown in FIG1 , eCAP1 sends the second test signals 1, 2, and 3 to the target first interface UART interface.

[0081] In this embodiment, the information of the target detection module is determined by the protocol configuration data. After the programmable logic device sends the second test signal through the target detection module and the enhanced capture module, the second test signal is sent to the target first interface. This allows the programmable logic device to analyze the first test data and send the second test data in reverse. On the one hand, the versatility and flexibility of the programmable logic device are enhanced; on the other hand, the test result of the test signal can be jointly judged based on the analysis result and the sending result, thereby improving the accuracy of the test result.

[0082] In an exemplary embodiment, as shown in FIG4 , the second test signal includes at least one of a transmitted Tx signal, a clock line SCL signal, and a clock CLK signal; the second test signal is sent to the corresponding enhanced capture module according to the communication baud rate by the target detection module, including at least one of steps S402 to S406. Wherein:

[0083] Step S402: When the target detection module is a UART detection module, the UART detection module sends a Tx signal to the corresponding first enhanced capture module according to the communication baud rate.

[0084] Among them, UART is a serial communication protocol, and the UART detection module is used to detect data using the UART protocol. The Tx signal is the Transmit signal, that is, the sending signal.

[0085] Optionally, when the target detection module is a UART detection module, the programmable logic device can detect the Tx signal through the UART detection module, and the programmable logic device sends the Tx signal to the corresponding first enhanced capture module eCAP1 according to the communication baud rate, such as 115200, through the UART detection module.

[0086] Step S404: when the target detection module is an I2C detection module, the clock line SCL signal is sent to the corresponding second enhanced capture module according to the communication baud rate through the I2C detection module.

[0087] The I2C bus is a serial, half-duplex bus that is mainly used for short-distance, low-speed communication between chips. The SCL signal is the clock signal line on the I2C bus.

[0088] Optionally, when the target detection module is an I2C detection module, the programmable logic device can detect the SCL signal through the I2C detection module, and send the transmission clock line SCL signal to the corresponding second enhanced capture module eCAP2 according to the communication baud rate.

[0089] Step S406: when the target detection module is an SPI detection module, the clock CLK signal is sent to the corresponding third enhanced capture module through the SPI detection module according to the communication baud rate.

[0090] Among them, the Serial Peripheral Interface (SPI) is a high-speed, full-duplex, synchronous communication bus. The CLK signal is the clock signal.

[0091] Optionally, when the target detection module is an SPI detection module, the programmable logic device can detect the CLK signal through the SPI detection module, and send the transmission clock line CLK signal to the corresponding third enhanced capture module eCAP3 according to the communication baud rate.

[0092] Accordingly, as shown in FIG5 , the target first interface includes at least one of a first interface configured as a UART protocol, a first interface configured as an I2C protocol, and a first interface configured as an SPI protocol; and also includes at least one of steps S502 to S506. Wherein:

[0093] Step S502: Sending a Tx signal to a first interface configured as a UART protocol through a first enhanced capture module.

[0094] Optionally, the programmable logic device sends the transmit Tx signal to the first interface configured as the UART protocol through the first enhanced capture module eCAP1.

[0095] Step S504: Send the clock line SCL signal to the first interface configured as the I2C protocol through the second enhanced capture module.

[0096] Optionally, the programmable logic device sends the SCL signal to the first interface configured as the I2C protocol through the second enhanced capture module eCAP2.

[0097] Step S506: Send the clock CLK signal to the first interface configured as the SPI protocol through the third enhanced capture module.

[0098] Optionally, the programmable logic device sends the transmission clock CLK signal to the first interface configured as the SPI protocol through the third enhanced capture module eCAP3.

[0099] In this embodiment, the second detection signal is sent to the corresponding first interface through different detection modules, so that the programmable logic device can not only analyze the first test data, but also send the second test data in reverse. On the one hand, the versatility and flexibility of the programmable logic device are enhanced; on the other hand, the test result of the test signal can be jointly judged based on the analysis result and the sending result, thereby improving the accuracy of the test result.

[0100] In an exemplary embodiment, as shown in FIG6 , receiving a corresponding first test signal through at least one first interface includes step S602:

[0101] Step S602: receiving a corresponding first test signal through at least two first interfaces; each first interface corresponds to a protocol, and the protocol types are different.

[0102] Optionally, the programmable logic device is provided with at least two first interfaces. As shown in FIG1 , the programmable logic device is provided with three first interfaces, namely, a first interface for configuring a UART protocol, a first interface for configuring an I2C protocol, and a first interface for configuring an SPI protocol. Each first interface corresponds to a protocol, and the protocol types are different. The programmable logic device starts three threads, and receives the first test signals corresponding to each other through three peripheral interfaces. Each thread occupies an eCAP module, as shown in FIG1 , eCAP1 is connected to the UART Tx signal; eCAP2 is connected to the I2C SCL signal; and eCAP3 is connected to the SPI SCK signal.

[0103] After receiving the corresponding first test signal through at least one first interface, the method further includes steps S604 to S606.

[0104] Step S604: Acquire clock information of the first test signal through the enhanced capture modules corresponding to the first interfaces.

[0105] The clock information includes the clock frequency.

[0106] Optionally, the first interface of the UART protocol corresponds to enhanced capture module 1, eCAP1; the first interface of the I2C protocol corresponds to enhanced capture module 2, eCAP2; the first interface of the SPI protocol corresponds to enhanced capture module 3, eCAP3; the first interface of the USB protocol corresponds to enhanced capture module 4, eCAP4.

[0107] It should be noted that the protocol used to configure the first interface in this application includes but is not limited to the UART protocol, I2C protocol or SPI protocol, and may also be the USB protocol, CAN bus protocol, etc.

[0108] Step S606: determining a detection module corresponding to the enhanced capture module according to the clock information, and receiving a first test signal through the detection module.

[0109] Optionally, the programmable logic device determines the detection module corresponding to the enhanced capture module according to the clock frequency, so that the detection module works in the receiving mode and turns on the real-time receiving mode. After receiving the first test signal, the received first test signal is sorted, and then the sorted first test signal is forwarded through the communication UART module. The sorted first test signal can be sent to the host computer through the second interface, and the host computer displays the sorted first test signal. For example, if the UART detection module receives "1 2 3 4", the data sent after sorting is: "UART data: 1 2 3 4", and similarly, the data of I2C and SPI are also sorted accordingly; in this way, the programmable logic device can perform analysis functions on the three protocols.

[0110] In this embodiment, first test data of multiple protocols can be received through at least two first interfaces; the frequency can be intelligently identified through the enhanced capture module so that the first test signal of the programmable logic device can be analyzed, and the programmable logic device can realize the analysis of the first test signals of multiple protocols, thereby improving the flexibility of the programmable logic device.

[0111] In an exemplary embodiment, as shown in FIG7 , the first test signal includes at least one of a transmitted Tx signal, a clock line SCL signal, and a clock CLK signal; and acquiring clock information of the first test signal through the enhanced capture module corresponding to each first interface includes at least one of steps S702 to S706. Wherein:

[0112] Step S702: When the communication protocol of the first interface is configured as the UART protocol, the clock information of the transmitted Tx signal is captured by the enhanced capture module corresponding to the first interface configured as the UART protocol.

[0113] When the communication protocol of the first interface is configured as a UART protocol, the first interface may also be referred to as a UART interface. The clock information includes a clock frequency.

[0114] Optionally, when the communication protocol of the first interface is configured as a UART protocol, that is, the first interface is a UART interface, the clock frequency of sending the Tx signal is captured by the enhanced capture module 1 corresponding to the UART interface.

[0115] Step S704: when the communication protocol of the first interface is configured as the I2C protocol, the clock information of the clock line SCL signal is captured by the enhanced capture module corresponding to the first interface configured as the I2C protocol.

[0116] When the communication protocol of the first interface is configured as the I2C protocol, the first interface may also be referred to as an I2C interface.

[0117] Optionally, when the communication protocol of the first interface is configured as the I2C protocol, that is, the first interface is an I2C interface, the clock frequency of the SCL signal sent is captured by the enhanced capture module 2 corresponding to the I2C interface.

[0118] Step S706: when the communication protocol of the first interface is configured as the SPI protocol, the clock information of the clock CLK signal is captured by the enhanced capture module corresponding to the first interface configured as the SPI protocol.

[0119] When the communication protocol of the first interface is configured as the SPI protocol, the first interface may also be referred to as an SPI interface.

[0120] Optionally, when the communication protocol of the first interface is configured as the SPI protocol, that is, the first interface is an SPI interface, the clock frequency of the sent CLK signal is captured by the enhanced capture module 3 corresponding to the SPI interface.

[0121] Optionally, three eCAPs are initialized respectively, and the working modes of the three eCAPs are all to capture the rising edge and falling edge of the first test signal waveform. And eCAP1 captures the Tx signal of UART, eCAP2 captures the SCL signal of I2C, and eCAP3 captures the CLK signal of SPI. When different signals are captured, the eCAP module can calculate the clock frequency of the corresponding signal.

[0122] In this embodiment, the frequency of the first test signal is intelligently identified through the enhanced capture module without redundant settings, thereby reducing the chip area occupied.

[0123] In an exemplary embodiment, the protocol for configuring the second interface includes a UART protocol and a USB protocol, and the second interface includes a UART module and a USB module, wherein the protocol for configuring the UART module includes the UART protocol; and the protocol for configuring the USB module includes the USB protocol.

[0124] Optionally, the second interface is an interface for connecting the editable logic device to the host computer, which can be called a host computer interface. The second interface includes a USB module and a UART module, the USB module configures a USB protocol, the UART module configures a UART protocol, and the USB module and the UART module are connected so that the second interface can be used for USB to UART. The second interface can be connected to the USB module of the host computer for communication through the USB module, wherein the communication baud rate can be fixed to 115200bps. The second interface can be connected to the communication UART module through the UART module. On the one hand, the communication UART module can be used to analyze the first test signal after sorting and send it to the host computer through the second interface; on the other hand, the communication UART module can be used to receive the second test signal sent by the host computer.

[0125] In this embodiment, two-way communication between the programmable logic device and the host computer can be achieved through the second interface, so that the programmable logic device can not only analyze the first test data, but also send the second test data in reverse. On the one hand, the versatility and flexibility of the programmable logic device are enhanced; on the other hand, the test result of the test signal can be jointly judged based on the analysis result and the sending result, thereby improving the accuracy of the test result.

[0126] In an exemplary embodiment, a programmable logic device is used in the analysis phase: the programmable logic device is provided with three peripheral interfaces, including a UART interface, an I2C interface, and an SPI interface, which are connected to the first test signals to be tested. The programmable logic device starts three threads, and the three threads occupy one eCAP module respectively. Initialize three threads, and initialize three eCAPs respectively: the working mode of the three eCAPs is to capture the rising and falling edges of the waveform, eCAP1 captures the Tx signal of UART, eCAP2 captures the SCL signal of I2C, and eCAP3 captures the CLK signal of SPI. When different signals are captured, the eCAP module can calculate the clock frequency of the corresponding signal. That is, as shown in Figure 8, the acquisition of clocks for different protocol interfaces is completed. After the programmable logic device collects the clock frequency corresponding to each first test signal, it performs different initialization work on the test modules (including UART test module, I2C test module, SPI test module) corresponding to different first test signals according to the clock frequency, so that the test module works in the receiving mode and starts the real-time receiving mode, thereby receiving the first test signal connected from each peripheral interface, such as the UART test module receives the first test signal connected to the UART interface; the I2C test module receives the first test signal connected to the I2C interface; the SPI test module receives the first test signal connected to the SPI interface. The processing and analysis unit sorts the first test signal. For example, if the UART test module receives "1 23 4", the data sent after sorting is: "UART data: 1 2 3 4". Similarly, the data of I2C and SPI are also sorted accordingly. The analyzed and sorted first test signal is sent through the communication UART module, and the second interface, that is, the host computer interface, receives the analyzed and sorted first test signal sent by the communication UART module, and sends the analyzed and sorted first test signal to the host computer, which can display the analyzed and sorted first test signal.

[0127] The programmable logic device is used in the test phase: the USB module of the second interface receives the protocol data in the target format sent by the host computer, and the USB module sends it to the UART module; the second interface converts the protocol data in the target format into a specific instruction and sends it to the communication UART module, wherein the protocol data includes protocol configuration data and a second test signal;

[0128] The programmable logic device parses the protocol configuration data of the communication UART module through the processing and analysis unit, determines the target detection module, and the communication baud rate and communication mode of the target detection module.

[0129] If the protocol configuration data is parsed; it is determined that the target detection module is a UART detection module, then in the communication mode, the Tx signal is sent to the corresponding first enhanced capture module according to the communication baud rate through the UART detection module; accordingly, the Tx signal is sent to the first interface configured as the UART protocol through the first enhanced capture module.

[0130] If the protocol configuration data is parsed; it is determined that the target detection module is an I2C detection module, then in the communication mode, the clock line SCL signal is sent to the corresponding second enhanced capture module according to the communication baud rate through the I2C detection module; accordingly, the clock line SCL signal is sent to the first interface configured as the I2C protocol through the second enhanced capture module.

[0131] If the protocol configuration data is parsed; it is determined that the target detection module is an SPI detection module, then in the communication mode, the clock CLK signal is sent to the corresponding third enhanced capture module through the SPI detection module according to the communication baud rate; accordingly, the clock CLK signal is sent to the first interface configured as the SPI protocol through the third enhanced capture module.

[0132] The programmable logic device sends a Tx signal to the peripheral device through a first interface configured as a UART protocol; sends an SCL signal to the peripheral device through a first interface configured as an I2C protocol; and sends a CLK signal to the peripheral device through a first interface configured as an SPI protocol.

[0133] On the one hand, programmable logic devices can realize both signal analysis and signal testing functions, and can switch between sending and receiving in both directions, which enhances the flexibility and versatility of programmable logic devices. On the other hand, the signal test results can be jointly determined by the signal analysis results and the signal test results, which can improve the accuracy of the signal test.

[0134] It should be understood that, although the various steps in the flowcharts involved in the above-mentioned embodiments are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence according to the order indicated by the arrows. Unless there is a clear explanation in this article, the execution of these steps does not have a strict order restriction, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowcharts involved in the above-mentioned embodiments can include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily carried out in sequence, but can be executed in turn or alternately with other steps or at least a part of the steps or stages in other steps.

[0135] Based on the same inventive concept, the embodiment of the present application also provides a programmable logic device for implementing the test signal processing method involved above. The implementation scheme for solving the problem provided by the programmable logic device is similar to the implementation scheme recorded in the above method, so the specific limitations in one or more programmable logic device embodiments provided below can refer to the limitations of the test signal processing method above, and will not be repeated here.

[0136] In an exemplary embodiment, as shown in FIG9 , a programmable logic device is provided, including: a first interface 901 , a processing module 902 , and a second interface 903 , wherein:

[0137] At least one first interface 901 is used to receive a first test signal.

[0138] The processing module 902 is used to analyze each first test signal to obtain target data.

[0139] The second interface 903 is used to send target data to the host computer; it is also used to receive protocol data in a target format sent by the host computer, the protocol data including protocol configuration data and a second test signal.

[0140] The processing module 902 is further configured to determine the target first interface according to the protocol configuration data, and send the second test signal through the target first interface.

[0141] In an exemplary embodiment, the processing module 902 includes:

[0142] The processing and analysis unit is used to parse the protocol configuration data, determine the target detection module, and the communication baud rate and communication mode of the target detection module. It is also used to send the second test signal to the corresponding enhanced capture module according to the communication baud rate through the target detection module in the communication mode; it is also used to determine the target first interface according to the enhanced capture module; wherein the enhanced capture module is used to send the second test signal to the target first interface.

[0143] In an exemplary embodiment, the second test signal includes at least one of a sending Tx signal, a clock line SCL signal and a clock CLK signal; a processing and analysis unit is used to send the sending Tx signal to the corresponding first enhanced capture module through the UART detection module according to the communication baud rate when the target detection module is a UART detection module; when the target detection module is an I2C detection module, the clock line SCL signal is sent to the corresponding second enhanced capture module through the I2C detection module according to the communication baud rate; when the target detection module is an SPI detection module, the clock CLK signal is sent to the corresponding third enhanced capture module through the SPI detection module according to the communication baud rate.

[0144] Accordingly, the target first interface 901 includes at least one of a first interface configured as a UART protocol, a first interface configured as an I2C protocol, and a first interface configured as an SPI protocol; the processing and analysis unit is also used to send the Tx signal to the first interface configured as the UART protocol through the first enhanced capture module; send the clock line SCL signal to the first interface configured as the I2C protocol through the second enhanced capture module; and send the clock CLK signal to the first interface configured as the SPI protocol through the third enhanced capture module.

[0145] In an exemplary embodiment, at least two first interfaces 901 are used to receive corresponding first test signals; each first interface corresponds to a protocol, and the protocol types are different.

[0146] The enhanced capture module corresponding to each first interface 901 is used to obtain clock information of the first test signal.

[0147] A detection module corresponding to the enhanced capture module is determined according to the clock information, and the detection module is used to receive a first test signal.

[0148] In an exemplary embodiment, the enhanced capture module corresponding to each first interface 901 is used to capture the clock information of the sent Tx signal through the enhanced capture module corresponding to the first interface 901 configured as the UART protocol when the communication protocol of the first interface 901 is configured as the UART protocol; when the communication protocol of the first interface 901 is configured as the I2C protocol, the clock information of the clock line SCL signal is captured through the enhanced capture module corresponding to the first interface 901 configured as the I2C protocol; when the communication protocol of the first interface 901 is configured as the SPI protocol, the clock information of the clock CLK signal is captured through the enhanced capture module corresponding to the first interface 901 configured as the SPI protocol.

[0149] In an exemplary embodiment, the protocol for configuring the second interface 903 includes a UART protocol and a USB protocol, and the second interface 903 includes a UART module and a USB module, wherein the protocol for configuring the UART module includes the UART protocol; and the protocol for configuring the USB module includes the USB protocol.

[0150] Each module in the above-mentioned programmable logic device can be implemented in whole or in part by software, hardware or a combination thereof. Each of the above-mentioned modules can be embedded in or independent of a processor in a computer device in the form of hardware, or can be stored in a memory in a computer device in the form of software, so that the processor can call and execute operations corresponding to each of the above modules.

[0151] In an exemplary embodiment, a computer device is provided, which may be a server, and its internal structure diagram may be shown in FIG10. The computer device includes a processor, a memory, an input / output interface (Input / Output, referred to as I / O) and a second interface. The processor, the memory and the input / output interface are connected via a system bus, and the second interface is connected to the system bus via the input / output interface. The processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The database of the computer device is used to store test signal data. The input / output interface of the computer device is used to exchange information between the processor and an external device. The second interface of the computer device is used to communicate with an external terminal via a network connection. When the computer program is executed by the processor, a test signal processing method is implemented.

[0152] Those skilled in the art will understand that the structure shown in FIG. 10 is merely a block diagram of a partial structure related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than shown in the figure, or combine certain components, or have a different arrangement of components.

[0153] In one embodiment, a computer device is further provided, including a memory and a processor, wherein a computer program is stored in the memory, and the processor implements the steps in the above method embodiments when executing the computer program.

[0154] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the steps in the above-mentioned method embodiments are implemented.

[0155] In one embodiment, a computer program product is provided, including a computer program, which implements the steps in the above method embodiments when executed by a processor.

[0156] A person of ordinary skill in the art can understand that all or part of the processes in the above-mentioned embodiment method can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to the memory, database or other medium used in the embodiments provided in the present application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. As an illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM). The database involved in each embodiment provided in this application may include at least one of a relational database and a non-relational database. Non-relational databases may include distributed databases based on blockchains, etc., but are not limited to this. The processor involved in each embodiment provided in this application may be a general-purpose processor, a central processing unit, a graphics processor, a digital signal processor, a programmable logic device, a data processing logic device based on quantum computing, an artificial intelligence (AI) processor, etc., but are not limited to this.

[0157] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0158] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the present application. It should be noted that, for a person of ordinary skill in the art, several modifications and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.

Claims

1. A test signal processing method, characterized in that: Applied to a programmable logic device, the method comprises: receiving a corresponding first test signal through at least one first interface; Analyze each of the first test signals to obtain target data, and send the target data to a host computer through a second interface; Receiving protocol data in a target format sent by the host computer through the second interface, the protocol data including protocol configuration data and a second test signal; A target first interface is determined according to the protocol configuration data, and the second test signal is sent through the target first interface.

2. The method according to claim 1, characterized in that The step of determining the target first interface according to the protocol configuration data includes: Parsing the protocol configuration data, determining a target detection module, and a communication baud rate and a communication mode of the target detection module; In the communication mode, the second test signal is sent to the corresponding enhanced capture module by the target detection module according to the communication baud rate; According to the enhanced capture module, a target first interface is determined; wherein the enhanced capture module is used to send the second test signal to the target first interface.

3. The method according to claim 2, characterized in that The second test signal includes at least one of a sending Tx signal, a clock line SCL signal, and a clock CLK signal; the sending of the second test signal to the corresponding enhanced capture module according to the communication baud rate by the target detection module includes at least one of the following: When the target detection module is a UART detection module, the Tx signal is sent to the corresponding first enhanced capture module according to the communication baud rate through the UART detection module; When the target detection module is an I2C detection module, the clock line SCL signal is sent to the corresponding second enhanced capture module according to the communication baud rate through the I2C detection module; When the target detection module is an SPI detection module, the clock CLK signal is sent to the corresponding third enhanced capture module through the SPI detection module according to the communication baud rate; Accordingly, the target first interface includes at least one of a first interface configured as a UART protocol, a first interface configured as an I2C protocol, and a first interface configured as an SPI protocol; and the method further includes at least one of the following: Sending the transmit Tx signal to a first interface configured as a UART protocol through the first enhanced capture module; Sending the clock line SCL signal to a first interface configured as an I2C protocol through the second enhanced capture module; The clock CLK signal is sent to a first interface configured as an SPI protocol through the third enhanced capture module.

4. The method according to claim 1, characterized in that: The receiving a corresponding first test signal through at least one first interface includes: Receiving a corresponding first test signal through at least two first interfaces; each of the first interfaces corresponds to a protocol, and the protocol types are different; After receiving the corresponding first test signal through at least one first interface, the method further includes: Acquire clock information of the first test signal through the enhanced capture modules corresponding to the first interfaces; A detection module corresponding to the enhanced capture module is determined according to the clock information, and the first test signal is received through the detection module.

5. The method according to claim 4, characterized in that The first test signal includes at least one of a sending Tx signal, a clock line SCL signal, and a clock CLK signal; the clock information of the first test signal is obtained through the enhanced capture module corresponding to each of the first interfaces, including at least one of the following: When the communication protocol of the first interface is configured as the UART protocol, the clock information of the Tx signal is captured by the enhanced capture module corresponding to the first interface configured as the UART protocol; When the communication protocol of the first interface is configured as the I2C protocol, the clock information of the clock line SCL signal is captured by the enhanced capture module corresponding to the first interface configured as the I2C protocol; When the communication protocol of the first interface is configured as the SPI protocol, the clock information of the clock CLK signal is captured by the enhanced capture module corresponding to the first interface configured as the SPI protocol.

6. The method according to any one of claims 1 to 5, characterized in that: The protocol for configuring the second interface includes a UART protocol and a USB protocol, and the second interface includes a UART module and a USB module, wherein the protocol for configuring the UART module includes the UART protocol; and the protocol for configuring the USB module includes the USB protocol.

7. A programmable logic device, characterized in that: The programmable logic device comprises: At least one first interface, configured to receive a first test signal; A processing module, used for analyzing each of the first test signals to obtain target data; The second interface is used to send the target data to the host computer; and is also used to receive the protocol data in the target format sent by the host computer, wherein the protocol data includes protocol configuration data and a second test signal; The processing module is further used to determine a target first interface according to the protocol configuration data, and send the second test signal through the target first interface.

8. A computer device comprising a memory and a processor, wherein the memory stores a computer program, wherein: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 6 are implemented.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 6 are implemented.

10. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 6 are implemented.

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