Comparator threshold imbalance detection method and system based on code density

Abstract

The invention discloses a comparator threshold imbalance detection method and system based on code density. The method comprises the following steps: acquiring a result of converting a single-tone sinusoidal signal by an assembly line ADC (Analog to Digital Converter); carrying out code density statistics on the last-level output code of the assembly line ADC; comparing the code density statistical result with a code density statistical result obtained in a preset ideal state; if the comparison results are inconsistent, adjusting the threshold value of the corresponding j comparator in the last pipeline stage of the pipeline ADC according to the difference value, and performing calibration again; if the comparison results are consistent, calibrating the (j + 1) th comparator until the calibration of the Mth comparator is completed; m is greater than or equal to j + 1, M is the total number of all comparators in the last pipeline stage of the pipeline ADC, and j is greater than M and greater than or equal to 1. According to the statistical probability of the output signal, the offset condition of the comparator threshold value is detected one by one, and the accurate calibration of the offset of the comparator threshold value is realized in combination with the comparator threshold value adjusting circuit in the ADC chip.

Description

Technical Field

[0001] The present invention relates to the technical field of analog-to-digital conversion technology, and more particularly to a comparator threshold misalignment detection method and system based on code density. Background Art

[0002] Analog-to-digital converters (ADCs) are key components in modern electronic systems, responsible for converting continuous analog signals into discrete digital signals. This conversion process is widely used in wireless communications, high-end test equipment, image and voice processing, and many other fields. With the continuous advancement of technology and the diversification of application scenarios, the market demand for high-speed, high-precision ADCs is growing.

[0003] As an efficient ADC architecture, pipelined ADC is favored for its excellent conversion rate, low power consumption and chip area. This type of ADC is particularly suitable for demanding high-speed application scenarios, such as wireless communication systems, charge-coupled device (CCD) image data processing, and ultrasound imaging.

[0004] On the other hand, Flash ADC, also known as fully parallel ADC, is known for its unparalleled conversion speed, making it an ideal choice for implementing high-speed instruments with GHz bandwidth (such as digital oscilloscopes). Despite its high power consumption and cost, Flash ADC is still an indispensable choice in applications that pursue extreme speed.

[0005] In the design of pipeline ADC, in order to achieve high-speed conversion, each pipeline stage usually integrates a small Flash ADC as a sub-ADC. However, due to the limitations of the manufacturing process and other non-ideal factors, the comparators in these sub-ADCs may have threshold offset problems. This offset not only affects the overall performance of the ADC, but may also cause bit errors in the output signal, seriously affecting the reliability and accuracy of the system.

[0006] Therefore, providing a solution for detecting the threshold misalignment of comparators one by one and calibrating them sequentially is an issue that needs to be urgently addressed by those skilled in the art. Summary of the invention

[0007] In view of this, the present invention provides a comparator threshold offset detection method and system based on code density, which detects the comparator threshold offset degree one by one and calibrates them in sequence, effectively improving the overall linearity of the Pipelined ADC.

[0008] In order to achieve the above object, the present invention adopts the following technical solution:

[0009] In a first aspect, the present invention provides a comparator threshold misalignment detection method based on code density, comprising the following steps:

[0010] S1, collect the result of pipeline ADC converting single-tone sinusoidal signal;

[0011] S2, performing code density statistics on the last-stage output code of the pipeline ADC;

[0012] S3. Compare the code density statistical result with the code density statistical result obtained under a preset ideal state;

[0013] S4. If the comparison results are inconsistent, adjust the threshold of the corresponding j-th comparator in the last pipeline stage of the pipeline ADC according to the difference value, and recalibrate; if the comparison results are consistent, calibrate the j+1-th comparator, and repeat steps S1-S4 until the calibration of the M-th comparator is completed; M≥j+1, M is the total number of all comparators in the last pipeline stage of the pipeline ADC, M>j≥1.

[0014] Furthermore, the pipeline ADC in step S1 includes: K pipeline stages; a single-tone sinusoidal signal is input from the first stage, and the output of the i-1th stage is used as the input of the i-th stage; wherein K is the total number of pipeline stages, K≥i≥2.

[0015] Furthermore, the step S1 specifically includes:

[0016] S11, generate a sinusoidal signal with a known frequency, and ensure that the signal amplitude is within the input range of the ADC, between 0 and Vref;

[0017] S12, inputting the generated sinusoidal signal into the first stage of the calibrated Pipelined ADC;

[0018] S13. Use the sampling function of the ADC to continuously collect a preset number of ADC conversion results.

[0019] Furthermore, the step S2 specifically includes:

[0020] S21, extract the Flash ADC output code of the last stage;

[0021] S22, counting the number of times each output code appears in all collected data;

[0022] S23. Divide the number of occurrences of each output code by the total number of samples, calculate the occurrence probability of each output code, and form a probability distribution table of the output code.

[0023] Furthermore, the step S3 specifically includes:

[0024] S31, modeling and simulating the Pipelined ADC according to the ideal state, and generating corresponding ideal code density statistical results;

[0025] S32. Compare the statistical results of the probability distribution table of the actual output code with the statistical results of the code density under the ideal state one by one.

[0026] Furthermore, the step S4 specifically includes:

[0027] S41, if the comparison results are inconsistent, calculate the difference between the actual output code probability and the ideal output code probability, and adjust the threshold of the corresponding j-th comparator through the adjustment circuit inside the ADC to compensate for the previously detected offset;

[0028] S42. After completing the threshold adjustment, return to step S1, re-input the single-tone sinusoidal signal, and repeat the acquisition of new ADC conversion results; repeat steps S2 and S3 until the comparison results are consistent, then calibrate the j+1th comparator until all comparators in the last pipeline stage of the pipeline ADC are calibrated.

[0029] Furthermore, in step S41, the threshold of the j-th comparator is adjusted as follows:

[0030] There is a linear relationship between the threshold misadjustment degree of the j-th comparator and the probability of occurrence of the corresponding output code; the threshold of the j-th comparator is adjusted according to the linear relationship.

[0031] In a second aspect, the present invention provides a comparator threshold misalignment detection system based on code density, comprising:

[0032] Acquisition module: used to collect the results of pipeline ADC converting single-tone sine signals;

[0033] Statistics module: used for performing code density statistics on the last-stage output code of the pipeline ADC;

[0034] Comparison module: used for comparing the code density statistical result with the code density statistical result obtained under a preset ideal state;

[0035] An adjustment module: used for adjusting the threshold of the j-th comparator corresponding to the last pipeline stage of the pipeline ADC according to the difference value;

[0036] Iterative calibration module: used to calibrate the j+1th comparator until the calibration of the Mth comparator is completed; the M≥j+1, M is the total number of all comparators, M>j≥1.

[0037] It can be seen from the above technical solution that, compared with the prior art, the present invention discloses a comparator threshold offset detection method and system based on code density, which can realize accurate calibration of comparator threshold offset by checking the offset of comparator threshold one by one and combining the comparator threshold adjustment circuit inside the ADC chip. For Pipelined ADC, this method is not limited by the circuit structure and can effectively improve its overall linearity. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying creative work.

[0039] Figure 1 This is an overall structural block diagram of the pipeline analog-to-digital converter provided by the present invention.

[0040] Figure 2 The transmission curve of the comparator provided by the present invention when the threshold is misadjusted.

[0041] Figure 3 A flow chart of a comparator threshold misalignment detection method based on code density provided by the present invention.

[0042] Figure 4 This is the overall structure diagram of the 14-bit Pipelined ADC provided by the present invention.

[0043] Figure 5a The first-stage transfer curve of the ideal 14-bit Pipelined ADC provided by the present invention.

[0044] Figure 5b The second-stage transfer curve of the ideal 14-bit Pipelined ADC provided by the present invention.

[0045] Figure 5c The third-stage transfer curve of the ideal 14-bit Pipelined ADC provided by the present invention.

[0046] Figure 5d The fourth-stage transfer curve of the ideal 14-bit Pipelined ADC provided by the present invention.

[0047] Figure 5e The fifth-stage transfer curve of the ideal 14-bit Pipelined ADC provided by the present invention.

[0048] Figure 6This is a structural diagram of the comparator threshold misalignment detection system based on code density provided by the present invention. DETAILED DESCRIPTION

[0049] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0050] Before introducing the embodiments of the present invention, the following definitions are given for the relevant terms involved in the embodiments of the present invention:

[0051] Analog-to-digital converter (ADC) is a converter that converts analog quantity after comparison with standard quantity into discrete signal represented by binary value. It is referred to as ADC or A / D converter. The most important parameter of analog-to-digital converter is the conversion accuracy, which is usually expressed by the number of bits of the output digital signal. The more bits of digital signal that the converter can accurately output, the stronger the ability of the converter to distinguish the input signal, and the better the performance of the converter. A / D conversion generally goes through four processes: sampling, holding, quantization and encoding. In actual circuits, some processes are combined, such as sampling and holding, quantization and encoding are implemented simultaneously during the conversion process.

[0052] Pipelined ADC, see Figure 1 The overall structural block diagram of the disclosed pipeline analog-to-digital converter includes at least two stages (first stage and second stage) of pipeline stages, and may include more stages (such as the kth stage). The basic principle is to distribute the pressure of high-resolution analog-to-digital conversion to each pipeline stage. Each pipeline stage successively analyzes a small number of bits, and multiple pipeline stages work continuously to achieve high-resolution analog-to-digital conversion, wherein the most significant bit is analyzed by the first stage in the pipeline, and the least significant bit is analyzed by the last stage in the pipeline.

[0053] Reference Figure 1 As shown, each pipeline stage contains the following key components:

[0054] Sample / Hold Circuit (S / H): At the beginning of each clock cycle, the sample / hold circuit samples the analog input signal and holds it at a stable level for the subsequent analog-to-digital conversion process.

[0055] Analog-to-digital converter (ADC): The sampled analog signal is fed into the analog-to-digital converter, which converts it into a digital signal. In a pipeline ADC, the ADC at each stage may have different resolutions and speeds to suit the performance requirements of the overall converter.

[0056] Digital-to-Analog Converter (DAC): In some pipeline ADC designs, each stage also includes a DAC to convert the converted digital signal back to an analog signal for comparison and correction with the input signal of the next stage. However, please note that not all pipeline ADCs include a DAC component, depending on the specific implementation.

[0057] Adders and comparators: These components are used to compare and correct signals between various stages of the pipeline ADC to ensure the accuracy of the final output digital signal.

[0058] Its working process is:

[0059] Sampling phase: At the beginning of each clock cycle, the sample / hold circuit samples the analog input signal V in The sample is taken and maintained at a stable level.

[0060] Conversion stage: The sampled analog signal is sent to the first-stage ADC for analog-to-digital conversion. The converted digital signal is temporarily stored and prepared for further processing in the next clock cycle.

[0061] Pipeline operation: After the first stage completes the conversion, the next clock cycle begins and the sample / hold circuit samples the analog input signal again, while the digital output of the first stage is fed into the second stage for further processing. This pipelining allows each stage to process data in parallel within consecutive clock cycles, thereby increasing the overall conversion speed.

[0062] Correction and output: At each stage of the pipeline, it may be necessary to use multiple adders and multiple comparators to correct the digital signal to ensure the accuracy of the final output digital signal. Ultimately, after processing at all stages, the digital output Vout will contain a digital value corresponding to the analog input signal Vin.

[0063] The present invention also mentions Flash ADC, also known as parallel ADC, which converts the sampled signal into binary numbers in one step; the conversion rate is the highest, usually used in low resolution (8^10 bits), 20-50MSPS application scenarios, generally used in video and communication fields. Flash ADC converters generally have 2N-1 comparators.

[0064] The Microsoft database access component with a 0.5-bit redundant structure proposed in the prior art can tolerate a certain comparator threshold misalignment of the sub-ADC. It is a commonly used Pipelined ADC architecture. Its principle is as follows:

[0065] First, to reduce the possibility of missing codes due to gain errors or comparator threshold offsets, the interstage gain is increased from 2 n Reduce to 2 n-1 At the same time, one comparator is reduced, and all the remaining comparator thresholds are shifted to avoid the phenomenon that the starting value of the ADC digital output is not 0 and there is a fixed offset.

[0066] In this case, as long as the comparator threshold offset is within a certain range, it can be corrected. At this time, the transfer curve refers to Figure 2 As shown; where Vin is the input signal of the analog-to-digital converter, it is a continuous analog voltage value. The task of the analog-to-digital converter is to convert this analog voltage value into digital form so that it can be processed and analyzed in a digital system. Vref stands for the reference voltage, which is an important parameter used in ADC and related circuits to define the maximum value of the input signal. Vref provides a known voltage reference for the ADC, which uses this reference to convert the analog input voltage Vin into a digital output. Vres represents the threshold voltage or offset voltage of the comparator. In the case of a comparator threshold offset, the output voltage Vout may change due to the influence of the input signal Vin and the threshold voltage Vres.

[0067] The last pipeline stage of the Pipelined ADC is usually implemented by a Flash ADC. Since this pipeline stage is the last stage, there is no redundant bit structure to tolerate comparator threshold offset within a certain range. At this time, the comparator threshold offset of the Flash ADC will seriously affect the overall linearity of the ADC.

[0068] Based on this, the embodiment of the present invention discloses a comparator threshold misalignment detection method based on code density, referring to Figure 3 As shown, the following steps are included:

[0069] S1, collect the result of pipeline ADC converting single-tone sinusoidal signal;

[0070] S2, performing code density statistics on the last-stage output code of the pipeline ADC;

[0071] S3. Compare the actual code density statistical result with the code density statistical result obtained under a preset ideal state;

[0072] S4. If the comparison results are inconsistent, adjust the threshold of the j-th comparator corresponding to the last pipeline stage of the pipeline ADC according to the difference value, and recalibrate; if the comparison results are consistent, calibrate the j+1-th comparator, and repeat steps S1-S4 until the calibration of the M-th comparator is completed; M≥j+1, M is the total number of all comparators, M>j≥1.

[0073] This method detects comparator threshold offset by testing and calibrating all comparators one by one, and can accurately calibrate comparator threshold offset by combining the comparator threshold adjustment circuit inside the ADC chip. This method can effectively improve the overall linearity of the Pipelined ADC.

[0074] By implementing the modeling of Pipelined ADC and analyzing the ADC output waveform, the code density statistics of the Flash ADC output code without comparator threshold offset are summarized. Then, by fitting the actual test data to the model, the degree of actual comparator threshold offset can be estimated, thereby realizing the detection of comparator threshold offset and further calibrating the comparators one by one.

[0075] Refer to the following Figure 4 The overall structure diagram of the 14-bit Pipelined ADC provided is used to introduce the present invention in detail. In this embodiment, the Pipelined ADC is composed of 5 2.5-bit pipeline stages and the last 4-bit Flash ADC. A single-tone sinusoidal signal is input from the first stage, and the output of the first stage is used as the input of the second stage; the output of the second stage is used as the input of the third stage, and so on; until the output of the fifth stage is used as the input of the sixth stage, the sixth stage is composed of a 4-bit Flash ADC, including 0-15 comparators, and finally outputs the probability of occurrence of the output code of 0-15.

[0076] Step S1, performing matlab modeling on the pipelined ADC, and collecting the result of the pipelined ADC converting a single-tone sinusoidal signal.

[0077] S11, generate a sinusoidal signal with a known frequency, and ensure that the signal amplitude is within the input range of the Pipelined ADC, between 0 and Vref;

[0078] The maximum peak value of the generated sinusoidal signal should not exceed Vref to avoid signal distortion or ADC damage. A digital signal processor (DSP) or a dedicated waveform generator can be used to generate the required sinusoidal waveform and adjust the amplitude of the signal through an appropriate attenuation circuit.

[0079] S12, inputting the generated sinusoidal signal to the first stage of the Pipelined ADC;

[0080] Correctly input the sinusoidal signal into the Pipelined ADC. Since the Pipelined ADC has a multi-stage pipeline structure, each stage is responsible for a part of the signal conversion process, so we need to ensure that the signal is correctly directed to the first stage of the ADC. This usually involves connecting the signal to the input pin of the ADC and ensuring impedance matching and signal integrity on the signal path. In addition, it is also necessary to pay attention to possible signal interference and noise issues, and take appropriate shielding and filtering measures to reduce the impact of these interferences on ADC performance.

[0081] S13. Use the sampling function of the ADC to continuously collect a preset number of ADC conversion results.

[0082] And get the transmission curve of each level of pipeline, refer to Figure 5a-Figure 5e The transfer curves of the first to fifth stages of an ideal 14-bit Pipelined ADC are provided.

[0083] It can be seen that for the first to fifth pipeline stages, the residual signals outputted therefrom are substantially evenly distributed between -0.5Vref and +0.5Vref.

[0084] Step S2, performing code density statistics on the sixth-stage output code of the Pipelined ADC.

[0085] In this embodiment, the sixth stage of the pipelined ADC is the last stage, and the input signal of the sixth stage comes from the output of the fifth stage. The output of the fifth stage is sampled and quantized, and then passed to the input of the sixth stage. The sixth stage is composed of a 4-bit Flash ADC, including 0-15 comparators, each of which corresponds to a different threshold voltage. The output code, that is, the output result of the comparator is combined into a 4-bit binary code ranging from 0 to 15.

[0086] S21, extracting the Flash ADC output code of the sixth stage;

[0087] This embodiment extracts all output codes from the Flash ADC part of the sixth stage, i.e., the last stage, of the Pipelined ADC. These output codes are the direct result of the ADC converting the analog signal into a digital signal, and they are represented in the form of binary or Gray code. In order to extract these output codes, the converted digital signal can be read out and stored in a suitable storage device, such as a memory or a hard disk, by using the data output port or internal register of the ADC.

[0088] S22, counting the number of times each output code appears in all collected data;

[0089] In this embodiment, it is achieved by writing appropriate programs or using ready-made statistical tools. In the statistical process, it is necessary to ensure the accuracy and completeness of the data to avoid statistical result deviations caused by data loss or errors.

[0090] S23. Divide the number of occurrences of each output code by the total number of samples, calculate the occurrence probability of each output code, and form a probability distribution table of the output code.

[0091] After obtaining the probability of each output code by dividing the number of occurrences of each output code by the total number of samples, these probability values ​​are arranged in the order of the output codes to form an output code probability distribution table. This table can intuitively show the distribution of ADC output codes, which helps to evaluate the performance of the ADC and detect potential problems.

[0092] Step S3, comparing the actual code density statistical result with the code density statistical result obtained under a preset ideal state;

[0093] For each output code (0-15), the difference value between the actual occurrence probability and the ideal occurrence probability is calculated, and the difference value is calculated using the following formula: Difference value = |actual probability-ideal probability|.

[0094] S31, modeling and simulating the Pipelined ADC according to the ideal state, and generating corresponding ideal code density statistical results;

[0095] The pipeline ADC to be calibrated is simulated and modeled. In specific implementation, a statistical model with comparator threshold error can be established, or an ideal model without error can be directly established.

[0096] S32. Compare the statistical results of the probability distribution table of the actual output code with the statistical results of the code density under the ideal state one by one.

[0097] In one embodiment, the Flash ADC output code of the last stage is counted and its statistical distribution is obtained as follows:

[0098]

[0099]

[0100] Table 1

[0101] It can be seen that, ideally, the probability of the output code of the last-stage Flash ADC appearing in 0-3 and 12-15 is 0, and the probability of appearing in 4-11 digital code is basically the same, which is about 12.5%.

[0102] If the comparator threshold of the last-stage Flash ADC is misaligned, for example, the threshold of the fourth comparator is 10% larger, the statistical distribution of the output code of the last-stage Flash ADC is:

[0103]

[0104]

[0105] Table 2

[0106] The statistical results show that the statistical probability of digital code 4 dropped from 12.88% to 11.59%, a decrease of about 10%, due to the 10% larger threshold of the fourth comparator; while the statistical probability of digital code 3 increased from 0.00% to 1.28%. It can be seen that for the last-stage Flash ADC, there is a linear relationship between the comparator threshold offset and the probability of occurrence of the two digital codes corresponding to the comparator.

[0107] This shows that we can reversely infer the degree of misadjustment of the comparator threshold corresponding to the digital code based on the statistical probability of the output signal. When calibrating the jth comparator, the rate of decrease (increase) of the probability of the jth digital code is the rate of increase (decrease) of the adjustment of the jth comparator threshold.

[0108] Next, step S4 is performed, which specifically includes:

[0109] S41, if the comparison results are inconsistent, calculating the difference between the actual output code probability and the ideal output code probability, and adjusting the threshold of the j-th comparator through the adjustment circuit inside the ADC to compensate for the previously detected offset;

[0110] After S42, the threshold value of the j-th comparator is adjusted, return to step S1, re-input the single-tone sinusoidal signal, and repeat the collection of new ADC conversion results. Then, perform steps S2 and S3 again, that is, perform consistency check of code density statistics and comparison results.

[0111] If the comparison result is still inconsistent, then we need to continue adjusting the threshold of the jth comparator until the comparison result is consistent. Once the threshold of the jth comparator is successfully calibrated, we can start calibrating the next comparator, which is the j+1th comparator.

[0112] This process will be repeated until all comparators are calibrated. In this process, M represents the total number of all comparators, and j represents the serial number of the comparator currently being calibrated. Therefore, M≥j+1 always holds true, and the value range of j is from 1 to M-1.

[0113] It should be noted that after each threshold adjustment, we need to re-collect the ADC conversion results and perform code density statistics to ensure the accuracy of the adjustment. In addition, since each stage of the pipeline ADC may have offsets, we need to calibrate the comparator of each stage to ensure the accuracy and stability of the entire ADC.

[0114] Through the above calibration process, we can effectively reduce the offset of the comparator in the pipeline ADC and improve the conversion accuracy and stability of the ADC. This is very important for applications that require high-precision analog-to-digital conversion.

[0115] This method is applicable to any Pipelined ADC and is not limited by its circuit structure. The ideal and actual models are modeled and simulated, and the code density and probability statistics are combined to extract the comparator threshold offset information of the last-stage Flash ADC by comparing the difference between the actual test results and the ideal model.

[0116] Based on the same idea, the embodiment of this specification also provides a comparator threshold misalignment detection system based on code density. Figure 6 As shown, including:

[0117] Acquisition module: used to collect the results of pipeline ADC converting single-tone sine signals;

[0118] Statistics module: used for performing code density statistics on the last-stage output code of the pipeline ADC;

[0119] Comparison module: used for comparing the code density statistical result with the code density statistical result obtained under a preset ideal state;

[0120] An adjustment module: used for adjusting the threshold of the j-th comparator corresponding to the last pipeline stage of the pipeline ADC according to the difference value;

[0121] Iterative calibration module: used to calibrate the j+1th comparator until the calibration of the Mth comparator is completed; the M≥j+1, M is the total number of all comparators, M>j≥1.

[0122] Its working process is:

[0123] When a single-tone sinusoidal signal with known frequency and amplitude is input, the acquisition module captures the digital output after ADC conversion. These output data will be used for subsequent analysis and calibration.

[0124] The statistics module receives data from the acquisition module and calculates the frequency of each output code. Ideally, for an ADC without comparator threshold offset, the distribution of output codes should be uniform. The statistics module will record the actual code density distribution to provide a basis for subsequent comparisons.

[0125] The comparison module receives the actual code density distribution provided by the statistics module and compares it with the preset ideal code density distribution. By calculating the difference between the two, the deviation degree of the current ADC output is determined. These difference values ​​will be used to guide subsequent adjustment operations.

[0126] The adjustment module receives the difference values ​​output by the comparison module and fine-tunes the threshold of the jth comparator based on these values. The specific adjustment method is to increase or decrease the threshold so that the actual code density distribution is closer to the ideal state. After the adjustment, the system will re-collect and count data to verify the effect of the adjustment.

[0127] The iterative calibration module is responsible for managing the entire calibration process cycle. Starting from the jth comparator, it calibrates backwards in sequence until all comparators that need to be calibrated (from the jth to the Mth) reach the optimal state. After each adjustment of a comparator, the system will re-collect data, statistics and comparisons to ensure that the threshold of each comparator is accurately calibrated.

[0128] This system is not limited to single-stage ADCs, but is specifically designed for multi-stage pipeline ADCs, and can effectively handle comparator threshold offset problems in multi-stage structures. By using a single-tone sinusoidal signal as a test signal, the test process is simplified, and through code density statistics and comparison, an intuitive and effective method is provided to evaluate and calibrate the comparator threshold. An automated process is provided to detect and calibrate the comparator threshold, reducing the need for manual intervention, allowing the ADC to maintain high performance under a wider range of conditions. By detecting and correcting the comparator threshold offset, the conversion error caused by comparator threshold deviation can be significantly reduced, thereby improving the overall conversion accuracy of the ADC.

[0129] This system can significantly reduce the nonlinear error caused by threshold offset by detecting and calibrating the comparator threshold offset, thereby improving the conversion accuracy of the ADC; and the calibrated ADC can better maintain linear characteristics and reduce DNL (differential nonlinearity) and INL (integral nonlinearity) errors. Through calibration, the noise caused by threshold offset can be reduced, thereby improving the signal-to-noise ratio (SNR) of the ADC and extending its dynamic range; and the calibrated ADC can process the input signal more accurately, especially when processing weak signals or high dynamic range signals.

[0130] In this specification, each embodiment is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part.

[0131] The above description of the disclosed embodiments enables one skilled in the art to implement or use the present invention. Various modifications to these embodiments will be apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A comparator threshold misalignment detection method based on code density, characterized in that: The following steps are involved: S1, collect the result of pipeline ADC converting single-tone sinusoidal signal; S2, performing code density statistics on the last-stage output code of the pipeline ADC; S3. Compare the code density statistical result with the code density statistical result obtained under a preset ideal state; S4, if the comparison results are inconsistent, adjust the threshold of the jth comparator corresponding to the last pipeline stage of the pipeline ADC according to the difference value, and recalibrate; if the comparison results are consistent, calibrate the j+1th comparator, and repeat steps S1-S4 until the calibration of the Mth comparator is completed; The M≥j+1, M is the total number of all comparators in the last pipeline stage of the pipeline ADC, and M>j≥1.

2. A comparator threshold misalignment detection method based on code density as claimed in claim 1, characterized in that: The pipeline ADC in step S1 comprises: K pipeline stages; a single-tone sinusoidal signal is input from the first stage, and the output of the i-1th stage is used as the input of the ith stage; wherein K is the total number of pipeline stages, K≥i≥2.

3. A comparator threshold misalignment detection method based on code density as claimed in claim 2, characterized in that: The step S1 specifically includes: S11, generate a sinusoidal signal with a known frequency, and ensure that the signal amplitude is within the input range of the ADC, between 0 and Vref; S12, inputting the generated sinusoidal signal to the first stage of the pipeline ADC; S13. Use the sampling function of the ADC to continuously collect a preset number of ADC conversion results.

4. A comparator threshold misalignment detection method based on code density as claimed in claim 3, characterized in that: The step S2 specifically includes: S21, extract the Flash ADC output code of the last stage; S22, counting the number of times each output code appears in all collected data; S23. Divide the number of occurrences of each output code by the total number of samples, calculate the occurrence probability of each output code, and form a probability distribution table of the output code.

5. A comparator threshold misalignment detection method based on code density as claimed in claim 4, characterized in that: The step S3 specifically includes: S31, modeling and simulating the Pipelined ADC according to the ideal state, and generating corresponding ideal code density statistical results; S32. Compare the statistical results of the probability distribution table of the actual output code with the statistical results of the code density under the ideal state one by one.

6. A comparator threshold misalignment detection method based on code density as claimed in claim 5, characterized in that: The step S4 specifically includes: S41, if the comparison results are inconsistent, calculate the difference between the actual output code probability and the ideal output code probability, and adjust the threshold of the corresponding j-th comparator through the adjustment circuit inside the ADC to compensate for the previously detected offset; S42. After completing the threshold adjustment, return to step S1, re-input the single-tone sinusoidal signal, and repeat the acquisition of new ADC conversion results; repeat steps S2 and S3 until the comparison results are consistent, then calibrate the j+1th comparator until all comparators in the last pipeline stage of the pipeline ADC are calibrated.

7. A comparator threshold misalignment detection method based on code density as claimed in claim 6, characterized in that: In step S41, the threshold of the j-th comparator is adjusted as follows: There is a linear relationship between the threshold misadjustment degree of the j-th comparator and the probability of occurrence of the corresponding output code; the threshold of the j-th comparator is adjusted according to the linear relationship.

8. A comparator threshold misalignment detection system based on code density, characterized in that: include: Acquisition module: used to collect the results of pipeline ADC converting single-tone sine signals; Statistics module: used for performing code density statistics on the last-stage output code of the pipeline ADC; Comparison module: used for comparing the code density statistical result with the code density statistical result obtained under a preset ideal state; An adjustment module: used for adjusting the threshold of the j-th comparator corresponding to the last pipeline stage of the pipeline ADC according to the difference value; Iterative calibration module: used to calibrate the j+1th comparator until the Mth comparator is calibrated; The M≥j+1, M is the total number of all comparators, and M>j≥1.

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