Field effect transistor and preparation method thereof

Abstract

The embodiment of the invention relates to the technical field of semiconductor devices, and discloses a field effect transistor and a preparation method thereof. According to the field effect transistor, the structure of which the doping concentration is gradually reduced in the direction far away from the substrate is arranged in the field effect transistor, so that electric field distribution in the field effect transistor can be gently changed, the conditions of local strong electric field and large current are avoided, and the phenomenon that the local temperature is too high is prevented; the voltage endurance capability of the field effect transistor during single particle injection can be improved, and the reliability of the field effect transistor is improved.

Description

Technical Field

[0001] The embodiments of the present invention relate to the technical field of semiconductor devices, and in particular to a field effect transistor and a method for manufacturing the same. Background Art

[0002] Power MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) is a semiconductor discrete device. It has the advantages of high input impedance, low loss, fast switching speed, and good frequency characteristics. Power devices usually require higher breakdown voltage and lower conduction resistance, but power MOSFET has Ron,sp∝VB 2.5 Therefore, as the breakdown voltage of the device increases, the conduction loss increases accordingly. The emergence of super junction structure breaks the traditional "silicon limit". Super junction MOSFET has excellent electrical characteristics and is an ideal power switching device in high-power systems.

[0003] In recent years, due to the presence of various heavy ions and rays in space, the space radiation environment is complex and the device life is seriously affected, which puts higher requirements on the reliability of power devices in special environments. In the space radiation environment, a variety of heavy particles and cosmic rays have a serious impact on the working life of the device, such as the single event effect (SEE), which is one of the permanent failure mechanisms of MOSFET devices, mainly single event gate penetration (SEGR) and single event burnout (SEB).

[0004] Single event burnout (SEB) is triggered by heavy ions striking a device in the blocking state. Electron-hole pairs are generated along the incident path of the heavy ions in a parasitic bipolar transistor formed by the n-source, p-body, and n-drift regions inherent to the MOSFET power transistor. If the generated carrier current causes a voltage drop and turns on the parasitic bipolar junction transistor (BJT), carrier multiplication occurs, resulting in excessive current and thermal burnout.

[0005] Single event gate breakdown (SEGR) is the breakdown of the gate oxide layer due to heavy ion impact. When the n-channel device is in the off state, that is, when VGS≤0V and heavy ions pass through the gate oxide layer, the generated holes accumulate at the silicon-oxide interface, which causes an increase in the transient electric field on the gate oxide layer. The gate oxide layer has an intrinsic breakdown electric field proportional to its thickness. When the transient field increases above the intrinsic breakdown field, a conduction path through the damaged gate oxide layer is formed between the silicon neck region of the device and the gate contact, resulting in an increase in gate current. Summary of the invention

[0006] The object of the present invention is to provide a field effect transistor and a method for preparing the same, which can improve the single particle effect resistance performance of the field effect transistor.

[0007] In order to solve the above technical problems, the first aspect of the present invention provides a field effect transistor, comprising:

[0008] substrate;

[0009] An epitaxial layer is stacked on the substrate;

[0010] A conductive layer, stacked on the epitaxial layer and located on a side of the epitaxial layer away from the substrate;

[0011] A channel layer is provided on a side of the conductive layer away from the substrate;

[0012] The epitaxial layer includes a plurality of sub-epitaxial layers formed of a semiconductor matrix, the plurality of sub-epitaxial layers are doped with impurity elements, and the concentration of the impurity elements in the plurality of sub-epitaxial layers decreases in a direction from the substrate toward the channel layer.

[0013] The present invention also provides a method for preparing the above field effect transistor, comprising:

[0014] Providing a substrate, forming a plurality of sub-epitaxial layers sequentially on the substrate, wherein the plurality of sub-epitaxial layers are composed of a semiconductor matrix and doped with impurity elements, and the concentration of the impurity elements in the plurality of sub-epitaxial layers decreases in a direction away from the substrate;

[0015] forming a conductive layer on the sub-epitaxial layer away from the substrate;

[0016] A channel layer is formed on the conductive layer.

[0017] The second aspect of the present invention also provides another field effect transistor, comprising:

[0018] substrate;

[0019] A conductive layer, stacked on the substrate;

[0020] A channel layer is provided on a side of the conductive layer away from the substrate;

[0021] The conductive layer includes a first conductive column region, which is composed of a semiconductor matrix doped with a first type of impurity element. In a direction from the substrate to the channel layer, the doping concentration of the first type of impurity element decreases.

[0022] The present invention also provides a method for preparing the above field effect transistor, comprising:

[0023] Providing a substrate, sequentially forming a plurality of first conductive type layers on the substrate, each of the first conductive type layers being doped with a first type of impurity element, and the doping concentration of the first type of impurity element decreasing in a direction away from the substrate, and the plurality of first conductive type layers forming a first conductive type column region;

[0024] A channel layer is formed on a side of the first conductive type column region away from the substrate.

[0025] Compared with the prior art, the present invention sets a structure with decreasing doping concentration in the direction away from the substrate inside the field effect transistor, which can make the electric field distribution inside the field effect transistor change smoothly, avoid the occurrence of local strong electric field and large current, prevent the occurrence of local excessive temperature, improve the voltage resistance of the field effect transistor during single particle injection, and increase the reliability of the field effect transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] One or more embodiments are exemplarily described by pictures in the corresponding drawings, and these exemplified descriptions do not constitute limitations on the embodiments. Elements with the same reference numerals in the drawings represent similar elements, and unless otherwise stated, the figures in the drawings do not constitute proportional limitations.

[0027] Figure 1 is a schematic structural diagram of an epitaxial layer of a field effect transistor according to a first embodiment of the present invention;

[0028] Figure 2 is a schematic structural diagram of a gate layer of a field effect transistor according to a first embodiment of the present invention;

[0029] Figure 3 is a schematic structural diagram of a field effect transistor according to a first embodiment of the present invention;

[0030] Figure 4 is a schematic structural diagram of a field effect transistor according to a second embodiment of the present invention;

[0031] Figure 5 is a schematic structural diagram of another field effect transistor according to the second embodiment of the present invention;

[0032] Figure 6 is a flow chart of a method for manufacturing a field effect transistor according to a third embodiment of the present invention;

[0033] Figure 7 is a flow chart of a method for manufacturing a field effect transistor according to a fourth embodiment of the present invention;

[0034] Figure 8 is a flow chart of a method for manufacturing a field effect transistor according to a fifth embodiment of the present invention;

[0035] Fig. 9is a flow chart of a method for manufacturing a first conductive type column region and a second conductive type column region according to a fifth embodiment of the present invention;

[0036] Fig.10 is a schematic structural diagram of a field effect transistor manufactured by the manufacturing method of the fifth embodiment of the present invention;

[0037] Fig.11 is a schematic diagram of changing the irradiation angle of the photolithography light in the fifth embodiment of the present invention;

[0038] Fig.12 It is a flow chart of a method for manufacturing a field effect transistor according to the sixth embodiment of the present invention. DETAILED DESCRIPTION

[0039] In order to make the purpose, technical scheme and advantages of the embodiments of the present invention clearer, the following will be described in detail with reference to the accompanying drawings. However, it will be appreciated by those skilled in the art that in the various embodiments of the present invention, many technical details are provided in order to enable the reader to better understand the present application. However, even without these technical details and various changes and modifications based on the following embodiments, the technical scheme claimed in the present application can be implemented.

[0040] In the embodiments of the present invention, the terms "upper", "lower", "left", "right", "front", "back", "top", "bottom", "inner", "outer", "middle", "vertical", "horizontal", "lateral", "longitudinal" and the like indicating directions or positional relationships are based on the directions or positional relationships shown in the accompanying drawings. These terms are mainly used to better describe the present invention and its embodiments, and are not used to limit the indicated devices, elements or components to have a specific direction, or to be constructed and operated in a specific direction.

[0041] In addition, some of the above terms may be used to express other meanings in addition to indicating orientation or positional relationship. For example, the term "on" may also be used to express a certain dependency or connection relationship in some cases. For those skilled in the art, the specific meanings of these terms in the present invention can be understood according to specific circumstances.

[0042] In addition, the terms "installed", "set", "provided with", "opened", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral structure; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate medium, or it can be an internal connection between two devices, elements, or components. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0043] In addition, the terms "first", "second", etc. are mainly used to distinguish different devices, elements or components (the specific types and structures may be the same or different), and are not used to indicate or imply the relative importance and quantity of the indicated devices, elements or components. Unless otherwise specified, "plurality" means two or more.

[0044] There is a positive correlation between the on-resistance R and the breakdown voltage VB of the traditional planar MOSFET. When the planar MOSFET meets the performance requirements of high breakdown voltage, it has a higher on-resistance, which increases power loss and limits the use of planar MOSFET in high-power application scenarios. The increased power consumption will also cause serious heating of the device. The above problems can be solved by setting a superjunction structure in the MOSFET. Specifically, by setting alternating P-type and N-type regions in the vertical direction inside the MOSFET, each P-type region and the N-type region next to it together constitute a superjunction unit. In the superjunction structure, when the MOSFET is in the on state, the current can flow through a lower resistance path, while still being able to withstand high voltage in the off state. However, the existing superjunction MOSFET is still weak in its ability to resist single particle effects, and is prone to permanent failure due to the influence of single particle effects in many scenarios.

[0045] In order to solve the above technical problems, the present invention provides a field effect transistor on one hand, comprising: a substrate; an epitaxial layer, stacked on the substrate; a conductive layer, stacked on the epitaxial layer, and located on the side of the epitaxial layer away from the substrate; a channel layer, arranged on the side of the conductive layer away from the substrate; wherein the epitaxial layer comprises a plurality of sub-epitaxial layers composed of a semiconductor matrix, and the plurality of sub-epitaxial layers are doped with impurity elements, and the concentration of the impurity elements of the plurality of sub-epitaxial layers decreases in the direction from the substrate to the channel layer. The key point of the scheme is that the epitaxial layer is divided into a plurality of sub-epitaxial layers composed of a semiconductor matrix, and the concentration of the doped elements of these sub-epitaxial layers gradually decreases in the direction from the substrate to the channel layer, which can reduce the local ionization rate at the position where the concentration of the epitaxial layer changes, and will not produce drastic changes, thereby forming an electric field with a relatively gentle intensity change inside the field effect transistor, avoiding the occurrence of local strong electric fields and large currents, and improving the withstand voltage capability of the field effect transistor.

[0046] On the other hand, the present invention also provides a field effect transistor, comprising: a substrate; a conductive layer, stacked on the substrate; a channel layer, arranged on the side of the conductive layer away from the substrate; wherein the conductive layer includes a first conductive column region, the first conductive column region is composed of a semiconductor matrix doped with a first type of impurity element, and the doping concentration of the first type of impurity element decreases in the direction from the substrate to the channel layer. The key point of this scheme is that the first conductive column region in the conductive layer of the field effect transistor is composed of a semiconductor matrix doped with a first type of impurity element, and the doping concentration of the first type of impurity element decreases in the direction from the substrate to the channel layer. In this way, the concentrated change of the local high electric field in the conductive layer can be avoided, which effectively reduces the device burning caused by the local excessive temperature caused by the electric field change in the single particle state, and increases the reliability of the device.

[0047] The present invention also provides a corresponding preparation method of the above field effect transistor.

[0048] The implementation details of the field effect transistor of the embodiment of the present invention are specifically described below. The following content is only provided for easy understanding of the implementation details and is not necessary for implementing the present solution.

[0049] Embodiment 1

[0050] See also Figure 1 The field effect transistor 100 of this embodiment includes a substrate 101, an epitaxial layer 102, a conductive layer 103 and a channel layer 104. The epitaxial layer 102 is stacked on the substrate 101, the conductive layer 103 is stacked on the epitaxial layer 102 and is located on a side of the epitaxial layer 102 away from the substrate 101, and the channel layer 104 is located on a side of the conductive layer 103 away from the substrate 101.

[0051] The epitaxial layer 102 includes a plurality of sub-epitaxial layers 1021 formed of a semiconductor matrix. The plurality of sub-epitaxial layers 1021 are doped with impurity elements, and the concentration of the impurity elements in the plurality of sub-epitaxial layers 1021 decreases gradually in a direction from the substrate 101 to the channel layer 104 .

[0052] It can be understood that the semiconductor matrix is ​​the basic material that constitutes the semiconductor, such as silicon, germanium, gallium arsenide and silicon carbide, etc., and the impurity elements are doped into the semiconductor matrix, so that the semiconductor matrix forms a semiconductor material with a certain conductivity under the influence of these impurity elements, which is generally divided into P-type semiconductors and N-type semiconductors. For example, by doping the semiconductor matrix with donor elements, electrons can be provided to the semiconductor matrix, thereby increasing the number of electrons in the conduction band, so that the doped semiconductor material has conductivity. Common donor elements include phosphorus (P) and arsenic (As). In their atomic structures, the outermost electrons are five, and this type of semiconductor material is an N-type semiconductor; in addition, by doping the semiconductor matrix with acceptor elements, the valence band electrons of the semiconductor matrix material can be accepted and holes can be generated, so that the doped semiconductor material has conductivity. Common acceptor elements include boron (B) and gallium (Ga), etc., in their atomic structures, the outermost electrons are three, and this type of semiconductor material is a P-type semiconductor.

[0053] In the present invention, the semiconductor matrix material of each sub-epitaxial layer 1021 can be any one of the above-mentioned semiconductor matrix materials, and the impurity elements used can be selected from any one of the above-mentioned materials according to actual needs. The following description takes silicon as the semiconductor matrix material, and explains that it forms an N-type semiconductor by doping with phosphorus elements and forms a P-type semiconductor by doping with boron elements, but is not limited to this.

[0054] For example, each sub-epitaxial layer 1021 is made of an N-type semiconductor material formed by silicon doped with phosphorus, and the concentration of phosphorus doped in each sub-epitaxial layer 1021 gradually decreases in a direction away from the substrate 101 .

[0055] In an operative solution, the concentration of phosphorus doped in each sub-epitaxial layer 1021 is one tenth to one fifth of the concentration of phosphorus doped in the previous sub-epitaxial layer 1021. For example, except for the first sub-epitaxial layer 1021, the concentration of phosphorus in each sub-epitaxial layer 1021 is one tenth of the concentration of phosphorus in the previous sub-epitaxial layer 1021, that is, the molar amount of phosphorus in the first sub-epitaxial layer 1021 is 10 20 , then the molar amount of phosphorus in the second layer is 10 19 , the third layer is 10 18 , in descending order.

[0056] It should be noted that, in this embodiment, each sub-epitaxial layer 1021 may be an independent layer structure, or may be a different region divided according to the concentration change distribution of the impurity elements in the epitaxial layer 102. In addition, the specific number of sub-epitaxial layers 1021 is not specifically limited, and may be specifically set or divided according to actual needs.

[0057] With such a configuration, the electric field inside the epitaxial layer 102 will be affected by the change in the concentration of the impurity elements, and the strength distribution of the electric field will change smoothly layer by layer. During the single-particle test, a large number of electron-hole pairs will not be generated locally due to the influence of the single particle, which can prevent the occurrence of local strong electric fields and large currents, avoid local overheating, and thus improve the voltage resistance of the field effect transistor 100.

[0058] See also Figure 2 The field effect transistor 100 further includes a first metal layer 105 disposed on a side of the substrate 101 away from the epitaxial layer 102 . The first metal layer 105 can be used as an electrode layer of the field effect transistor 100 , for example, as a drain electrode layer.

[0059] See again Figure 1 In this embodiment, the conductive layer 103 includes a first conductive column region 1031 and second conductive column regions 1032 located on opposite sides of the first conductive column region 1031. The first conductive column region 1031 is composed of an N-type semiconductor and the second conductive column region 1032 is composed of a P-type semiconductor. For example, in the orthographic projection direction of the substrate 101, the conductive layer 103 is divided into a middle region and edge regions located on both sides of the middle region. The first conductive column region 1031 is arranged in the middle region, and two second conductive column regions 1032 are respectively arranged in the two edge regions. The first conductive column region 1031 protrudes relative to the two second conductive column regions 1032 in a direction away from the substrate 101. There are two channel layers 104, which are respectively arranged on the two edge regions. The two channel layers 104 can respectively form the collector and emitter of the field effect transistor 100.

[0060] It can be understood that the first conductive column region 1031 and the second conductive column region 1032 are respectively formed of semiconductor matrices doped with different types of impurity elements. For example, the first conductive column region 1031 can be doped with donor elements, while the second conductive column region 1032 is doped with acceptor elements.

[0061] The two channel layers 104 are symmetrically arranged on opposite sides of the first conductive column region 1031, and one of the channel layers 104 is used for illustration. The channel layer 104 includes a P-type semiconductor layer 1041 and an N-type semiconductor layer 1042. The P-type semiconductor layer 1041 is stacked on the second conductive column region 1032, and its portion close to the first conductive column region 1031 is bent in a direction away from the substrate 101 and protrudes from the remaining portion to be flush with the surface of the first conductive column region 1031 away from the substrate 101. The N-type semiconductor layer 1042 is arranged on a side of the P-type semiconductor layer 1041 away from the second conductive column region 1032, and is flush with the protruding portion of the P-type semiconductor layer 1041 and the surface of the first conductive column region 1031 away from the substrate 101. A PN junction is formed at the interface between the N-type semiconductor layer 1042 and the P-type semiconductor layer 1041 , and a PN junction is also formed at the interface between the P-type semiconductor layer 1041 and the first conductive column region 1031 as a part of the conductive path.

[0062] The P-type semiconductor layer 1041 is divided into two parts. The end portion away from the first conductive column region 1031 forms a P-well region by doping donor elements, while the portion close to the first conductive column region 1031 serves as a P+ region.

[0063] See again Figure 2 , the field effect transistor 100 also includes a gate layer 106 disposed on the surface of the first conductive column region 1031, the P-type semiconductor layer 1041 and the N-type semiconductor layer 1042 away from the substrate 101. The gate layer 106 includes a gate oxide layer 1061 and a polycrystalline gate layer 1062 disposed in sequence in a direction away from the substrate 101, and the thickness of the gate oxide layer 1061 in the region facing the first conductive column region 1031 is set to be greater than the thickness of other regions. In this way, the withstand voltage of the field effect transistor 100 in the region with a larger thickness of the gate oxide layer 1061 can be improved, and it is not easy to be broken down under the action of the superimposed strong electric field when a single particle bombards. In this embodiment, by configuring the impurity element concentration of the P-well region and combining the thickness of the N-type semiconductor layer 1042 and the gate oxide layer 1061, the turn-on threshold voltage of the field effect transistor 100 can be regulated.

[0064] See also Figure 3 In this embodiment, the field effect transistor 100 is further provided with an isolation oxide layer 107 on the side of the polycrystalline gate layer 1062 facing away from the substrate 101, so as to protect the polycrystalline gate layer 1062 and prevent the polycrystalline gate layer 1062 from being corroded. The isolation oxide layer 107 may be silicon dioxide or other oxide layers that meet the requirements.

[0065] See again Figure 3In this embodiment, the field effect transistor 100 further includes a conductive metal layer 108 disposed on the surface of the isolation oxide layer 107 and the P-type semiconductor layer 1041 away from the substrate 101. The conductive metal layer 108 includes a second metal layer 1081 and a third metal layer 1082 disposed on the isolation oxide layer 107 and the P-type semiconductor layer 1041 in sequence. The second metal layer 1081 and the third metal layer 1082 are different types of metals, and the second metal layer 1081 is used to prevent the third metal layer 1082 and the silicon material inside the field effect transistor 100 from mutually diffusing. For example, the second metal layer 1081 uses titanium metal (Ti or TiN), and the third metal layer 1082 uses aluminum metal (AlSi or AlSiCu), silver or copper. In this way, the titanium metal can form a good ohmic contact with silicon, while avoiding the mutual diffusion of aluminum elements and silicon elements, and can maintain the long-term reliability of the device. In addition, different metals have different blocking effects on single particles, which can enhance the single particle resistance of the field effect transistor 100 to different particles.

[0066] See again Figure 3 In this embodiment, the field effect transistor 100 further includes a protective layer 109 and a passivation layer 110 sequentially disposed on the surface of the third metal layer 1082 facing away from the substrate, for protecting the internal structure of the field effect transistor 100. The protective layer 109 may be made of silicon dioxide, and the passivation layer 110 may be made of silicon nitride or polyimide.

[0067] Embodiment 2

[0068] See also Figure 4 and Figure 5 The field effect transistor 100 of this embodiment is substantially the same as the field effect transistor 100 in the first embodiment, and the main difference is that the epitaxial layer 102 of this embodiment does not have a multi-layer configuration with decreasing impurity concentration, the epitaxial layer 102 does not have a concentration change, or the field effect transistor 100 does not have an epitaxial layer 102. Moreover, in the direction from the substrate 101 to the channel layer 104, the concentration of the element doped in the first conductive column region 1031 gradually decreases. In this way, the concentrated change of the electric field inside the first conductive column region 1031 can be avoided, and the local temperature caused by the change of the electric field in the single particle state is effectively reduced, so as to avoid the burning of the field effect transistor 100 and increase the reliability of the field effect transistor 100.

[0069] In order to improve the withstand voltage capability of the field effect transistor 100, the variation trend of the doping concentration of the impurity elements in the two second conductive type column regions 1032 is the same as the variation trend of the impurity elements in the first conductive type column region 1031. In this way, the charge balance inside the field effect transistor 100 can be achieved, the electric field distribution inside the field effect transistor 100 can be better balanced, and the single event effect resistance capability of the field effect transistor 100 can be improved.

[0070] Similarly, the first conductive column region 1031 and the second conductive column region 1032 both include a multi-layer structure, and in the direction away from the substrate 101, except for the first layer, the concentration of impurity elements in each layer is one tenth to one fifth of the concentration of impurity elements in the previous layer. In addition, the layer structures in the first conductive column region 1031 and the second conductive column region 1032 can be independent layer structures, or layer regions divided according to the change of the concentration of impurity elements in the first conductive column region 1031 and the second conductive column region 1032.

[0071] In some feasible solutions, the width of the first conductive column region 1031 gradually decreases in the direction from the substrate 101 to the channel layer 104, which is consistent with the change trend of the internal voltage of the field effect transistor 100 when it is turned off, and can increase the withstand voltage performance of the field effect transistor 100. For example, the first conductive column region 1031 can be a trapezoidal structure.

[0072] The widths of the two second conductive type column regions 1032 gradually increase in a direction from the substrate 101 to the channel layer 104. Specifically, the shapes of the two second conductive type column regions 1032 may be inverted trapezoids, which are complementary to the first conductive type column regions 1031.

[0073] Embodiment 3

[0074] See also Figure 6 The field effect transistor 100 of this embodiment is a combination of the field effect transistor 100 in the first embodiment and the field effect transistor 100 in the second embodiment, that is, the field effect transistor 100 simultaneously has a sub-epitaxial layer 1021 having a plurality of impurity element doping concentrations decreasing in a direction away from the substrate 101, and a first conductive column region 1031 having a plurality of impurity element doping concentrations decreasing in a direction away from the substrate 101.

[0075] See again Figure 6 Similarly, in order to achieve charge balance and evenly distribute the electric field inside the field effect transistor 100, the two second conductive column regions 1032 also have a multilayer structure in which the doping concentration of the impurity element decreases in the direction away from the substrate 101. It can be understood that by simultaneously providing the above structures in a field effect transistor 100, the withstand voltage capability and the single event effect resistance capability of the field effect transistor 100 can be effectively improved.

[0076] Embodiment 4

[0077] See also Figure 7 The present invention further provides a method for manufacturing the field effect transistor 100 of the first embodiment, comprising:

[0078] S100. Provide a substrate, and sequentially form a plurality of sub-epitaxial layers on the substrate, wherein the plurality of sub-epitaxial layers are composed of a semiconductor matrix and are doped with impurity elements, and the concentration of the impurity elements in the plurality of sub-epitaxial layers decreases in a direction away from the substrate.

[0079] S200. Form a conductive layer on the sub-epitaxial layer away from the substrate.

[0080] S300. Form a channel layer on the conductive layer.

[0081] For step S100, a first semiconductor matrix layer may be coated, solidified or deposited on the substrate 101, and then the target concentration of impurity ions may be doped into the semiconductor matrix layer by ion implantation or the like to form a first sub-epitaxial layer 1021. Afterwards, the target concentration of doping may be changed, or the energy during ion implantation may be reduced layer by layer to change the implanted impurity concentration, and then a plurality of different sub-epitaxial layers 1021 may be formed by the same method, and these sub-epitaxial layers 1021 together constitute the epitaxial layer of the field effect transistor 100.

[0082] For step S200 , the conductive layer may be formed by coating, curing or deposition. Specifically, the first conductive column region 1031 may be formed in the middle region of the substrate 101 , and then the second conductive column regions 1032 may be formed on the edge regions on both sides of the middle region.

[0083] Alternatively, the first conductive column region 1031 may be formed on the entire substrate 101 first, and then the first conductive column region 1031 on the edge region may be removed by photolithography or the like, and then the second conductive column region 1032 may be formed on the edge region.

[0084] For S300 , specifically, a P-type semiconductor layer 1041 may be first formed on the conductive layer 103 , and then a donor element of a certain concentration may be doped in a specific region to form a P-well region, and then an N-type semiconductor layer 1042 may be formed on the P-type semiconductor layer 1041 .

[0085] Embodiment 5

[0086] See also Figure 8 The present invention further provides a method for manufacturing the field effect transistor 100 of the second embodiment, comprising:

[0087] S400. Provide a substrate 101, and sequentially form a plurality of first conductive type layers 1031a on the substrate 101, wherein each first conductive type layer 1031a is doped with a first type of impurity element, and the doping concentration of the first type of impurity element decreases in a direction away from the substrate 101, and the plurality of first conductive type layers 1031a form a first conductive type column region 1031.

[0088] S500. Form a channel layer on a side of the first conductive type column region away from the substrate.

[0089] For step S400, specifically, a semiconductor matrix layer of a first first conductive layer 1031a can be formed on the substrate 101 by coating, curing or deposition, and then a first type of impurity element, such as a donor element, can be doped into the semiconductor base layer by high-energy ion implantation. In another field effect transistor 100, a second type of impurity element, such as an acceptor element, can also be doped. Then, multiple layers of the first conductive layer 1031a are formed in sequence according to the above content. It should be noted that since the doping concentration of each first conductive layer 1031a is different, the concentration of the target doping ion needs to be changed when performing ion implantation.

[0090] See also Fig. 9 In this embodiment, there is a step S401. Each time a first conductive layer 1031a is formed, the first conductive layer 1031a is etched. In this way, the first first conductive layer 1031a is located in the middle area of ​​the substrate 101, and each subsequent first conductive layer 1031a is located in the middle area of ​​the previous first conductive layer 1031a. Specifically, for ease of operation, the first first conductive layer 1031a formed on the substrate 101 can completely cover the substrate 101, and then the first first conductive layer 1031a is photoetched to remove the first conductive layer 1031a on the two edge areas of the substrate 101. Afterwards, a second first conductive layer 1031a is formed on the first first conductive layer 1031a to completely cover the first first conductive layer 1031a, and then the areas on both sides of the second first conductive layer 1031a are etched, and so on, to gradually form multiple layers of first conductive layers 1031a to constitute the first conductive column region 1031.

[0091] See also Fig.10 Since the orthographic projection area of ​​each first conductive layer 1031a on the substrate 101 is smaller than the orthographic projection area of ​​the previous first conductive layer 1031a on the substrate 101, the first conductive column region 1031 is generally trapezoidal, and the left and right sides of the trapezoid are stepped curves.

[0092] In other feasible solutions, when performing photolithography on the first conductive layer 1031a, the photolithography angle can be adjusted to form a more accurate trapezoidal structure of the first conductive column region 1031. Specifically, the irradiation angle of the photolithography light is set to form an angle with the thickness direction of the substrate 101. For details, see Fig.11 In the figure, the dotted arrow indicates the irradiation direction of the etching light. In this way, the change trend of the structure and ion doping concentration of the first conductive column region 1031 can be smoother, thereby improving the withstand voltage capability of the field effect transistor 100.

[0093] Then, the process further includes S402. Forming a second conductive type layer 1032a on the exposed substrate 101 and the exposed area of ​​each first conductive type layer 1031a. Specifically, the first second conductive type layer 1032a covers the edge areas on both sides of the substrate 101. The second second conductive type layer 1032a covers the first second conductive type layer 1032a and the exposed areas on both sides of the first conductive type layer 1031a, and so on, gradually forming multiple layers of second conductive type layers 1032a to form two second conductive type column regions 1032.

[0094] For step S500 , specifically, a channel layer 104 is formed on one side of the first conductive column region 1031 away from the substrate 101 , specifically on two opposite sides of the first conductive column region 1031 away from one end of the substrate 101 , that is, on one side of the two second conductive column regions 1032 away from the substrate 101 .

[0095] A P-type semiconductor layer 1041 may be first formed on the conductive layer 103 , and then a donor element is doped at a certain concentration in a specific region to form a P-well region, and then an N-type semiconductor layer 1042 may be formed on the P-type semiconductor layer 1041 .

[0096] Embodiment 6

[0097] See also Fig.12 The present invention also provides a method for manufacturing the field effect transistor 100 of the third embodiment, which is specifically a combination of the fourth embodiment and the fifth embodiment. In this way, a sub-epitaxial layer having multiple impurity elements with a doping concentration decreasing in a direction away from the substrate 101 and a first conductive column region 1031 having multiple impurity elements with a doping concentration decreasing in a direction away from the substrate 101 can be simultaneously formed in a field effect transistor 100. Specifically, it includes:

[0098] S600. Provide a substrate, and sequentially form a plurality of sub-epitaxial layers 1021 on the substrate 101. The plurality of sub-epitaxial layers 1021 are composed of a semiconductor matrix and are doped with impurity elements. In a direction away from the substrate 101, the concentration of the impurity elements in the plurality of sub-epitaxial layers 1021 decreases.

[0099] S700. A plurality of first conductive type layers 1031a are sequentially formed on the sub-epitaxial layer 1021 away from the substrate 101, each first conductive type layer 1031a is doped with a first type of impurity element, and the doping concentration of the first type of impurity element decreases in a direction away from the substrate 101, and the plurality of first conductive type layers 1031a form a first conductive type column region 1031.

[0100] S800. Form a channel layer on a side of the first conductive type column region away from the substrate.

[0101] For steps S600, S700 and S800, please refer to the fourth embodiment and the fifth embodiment for details, and make adaptive adjustments according to actual conditions, which will not be described in detail in this embodiment.

[0102] By using the preparation method provided in Example 6, a sub-epitaxial layer having multiple layers of impurity elements whose doping concentration decreases in a direction away from the substrate 101 and a first conductive column region 1031 having multiple layers of impurity elements whose doping concentration decreases in a direction away from the substrate 101 can be simultaneously formed in a field effect transistor 100, which can effectively improve the voltage resistance and single particle effect resistance of the field effect transistor 100.

[0103] As described above, the present invention provides a layered structure in which the doping concentration decreases layer by layer from the substrate 101 toward the channel layer 104 in the field effect transistor 100, so that the internal electric field of the field effect transistor 100 can change gradually, avoiding excessive changes in the local electric field / current, thereby preventing the field effect transistor 100 from being burned and improving the single particle resistance of the field effect transistor 100. Optionally, these layered structures can be multiple sub-epitaxial layers 1021 or multiple first conductive type layers 1031a.

[0104] The field effect transistor and its preparation method provided by the embodiment of the present invention are introduced in detail above. Specific examples are used in this article to illustrate the principle and implementation of the present invention. The description of the above implementation is only used to help understand the idea of ​​the present invention. There may be changes in the specific implementation and application scope. In summary, the content of this specification should not be understood as a limitation on the present invention.

Claims

1. A field effect transistor, characterized in that: include: substrate; An epitaxial layer is stacked on the substrate; A conductive layer, stacked on the epitaxial layer; A channel layer is provided on a side of the conductive layer away from the substrate; The epitaxial layer includes a plurality of sub-epitaxial layers formed of a semiconductor matrix, the plurality of sub-epitaxial layers are doped with impurity elements, and the concentration of the impurity elements in the plurality of sub-epitaxial layers decreases in a direction from the substrate toward the channel layer.

2. The field effect transistor according to claim 1, characterized in that The conductive layer includes a first conductive column region, which is composed of a semiconductor matrix doped with a first type of impurity element. In a direction from the substrate to the channel layer, the doping concentration of the first type of impurity element decreases.

3. The field effect transistor according to claim 2, characterized in that: In a direction from the substrate toward the channel layer, a width of the first conductive column region gradually decreases.

4. The field effect transistor according to claim 2, characterized in that: The conductive layer also includes two second conductive type column regions, the first conductive type column region is sandwiched between two second conductive type column regions, the second conductive type column region is composed of a semiconductor matrix doped with second type impurity elements, and the doping concentration of the second type impurity elements decreases in the direction from the substrate toward the channel layer.

5. The field effect transistor according to claim 4, characterized in that: In a direction from the substrate toward the channel layer, the widths of the two second conductive pillar regions gradually increase.

6. The field effect transistor according to claim 2, characterized in that: It also includes a gate oxide layer stacked on the first conductive column region and the channel layer on a side away from the substrate, and a region of the gate oxide layer facing the first conductive column region is set as a thick oxygen region.

7. The field effect transistor according to claim 6, characterized in that: It also includes an isolation oxide layer, a second metal layer and a third metal layer stacked in sequence on the side of the gate oxide layer facing away from the substrate, the isolation oxide layer is used to protect the internal structure of the field effect transistor, the second metal layer is used to electrically connect the third metal layer and the channel layer and prevent the third metal layer and the channel layer from diffusing each other, and the third metal layer is used for an external circuit.

8. The field effect transistor according to any one of claims 1 to 7, characterized in that: In a direction from the substrate toward the channel layer, the doping concentration of the impurity element in each of the sub-epitaxial layers is one tenth to one fifth of the doping concentration of the impurity element in the previous sub-epitaxial layer.

9. A method for preparing a field effect transistor as claimed in claim 1, characterized in that: Providing a substrate, forming a plurality of sub-epitaxial layers sequentially on the substrate, wherein the plurality of sub-epitaxial layers are composed of a semiconductor matrix and doped with impurity elements, and the concentration of the impurity elements in the plurality of sub-epitaxial layers decreases in a direction away from the substrate; forming a conductive layer on the sub-epitaxial layer away from the substrate; A channel layer is formed on the conductive layer.

10. The preparation method according to claim 9, characterized in that: The step of forming a conductive layer on the sub-epitaxial layer away from the substrate comprises: Multiple layers of first conductive type layers are sequentially formed on the sub-epitaxial layer, each of which is doped with a first type of impurity element, and the doping concentration of the first type of impurity element decreases in a direction from the substrate toward the channel layer, and the multiple layers of the first conductive type layers form a first conductive type column region.

11. The preparation method according to claim 10, characterized in that: The step of sequentially forming a plurality of first conductive type layers on the sub-epitaxial layer further comprises: Each time a first conductive layer is formed, the first conductive layer is etched so that the first first conductive layer is located in the middle area of ​​the sub-epitaxial layer and each subsequent first conductive layer is located in the middle area of ​​the previous first conductive layer.

12. The preparation method according to claim 11, characterized in that: The step of etching the first conductive type layer each time the first conductive type layer is formed further comprises: A plurality of second conductive type layers are sequentially formed on the sub-epitaxial layer exposed by the first conductive type layer and the first conductive type layer before each first conductive type layer is exposed, each second conductive type layer is doped with a second type of impurity element, and the doping concentration of the second type of impurity element decreases in the direction from the substrate to the channel layer, and the plurality of second conductive type layers form a second conductive type column region; there are two second conductive type column regions, which are respectively located on opposite sides of the first conductive type column region.

13. A field effect transistor, characterized in that: include: substrate; A conductive layer, stacked on the substrate; A channel layer is provided on a side of the conductive layer away from the substrate; The conductive layer includes a first conductive column region, which is composed of a semiconductor matrix doped with a first type of impurity element. In a direction from the substrate to the channel layer, the doping concentration of the first type of impurity element decreases.

14. The field effect transistor according to claim 13, characterized in that: The conductive layer also includes two second conductive type column regions, the first conductive type column region is sandwiched between two second conductive type column regions, the second conductive type column region is composed of a semiconductor matrix doped with second type impurity elements, and the doping concentration of the second type impurity elements decreases in the direction from the substrate toward the channel layer.

15. The field effect transistor according to claim 14, characterized in that: In a direction from the substrate toward the channel layer, the widths of the two second conductive pillar regions gradually increase.

16. The field effect transistor according to claim 13, characterized in that: It also includes a gate oxide layer stacked on the first conductive column region and the channel layer on a side away from the substrate, and a region of the gate oxide layer facing the first conductive column region is set as a thick oxygen region.

17. The field effect transistor according to claim 16, characterized in that: It also includes an isolation oxide layer, an inert metal layer and a second metal layer stacked in sequence on the side of the gate oxide layer facing away from the substrate, the isolation oxide layer is used to protect the internal structure of the field effect transistor, the inert metal layer is used to electrically connect the second metal layer and the channel layer and prevent the second metal layer and the channel layer from diffusing each other, and the second metal layer is used for an external circuit.

18. The field effect transistor according to any one of claims 13 to 17, characterized in that: In a direction from the substrate toward the channel layer, a width of the first conductive column region gradually decreases.

19. A method for preparing a field effect transistor as claimed in claim 13, characterized in that: Providing a substrate, sequentially forming a plurality of first conductive type layers on the substrate, each of the first conductive type layers being doped with a first type of impurity element, and the doping concentration of the first type of impurity element decreasing in a direction away from the substrate, and the plurality of first conductive type layers forming a first conductive type column region; A channel layer is formed on a side of the first conductive type column region away from the substrate.

20. The preparation method according to claim 19, characterized in that: The step of sequentially forming a plurality of first conductive type layers on the substrate further comprises: Each time a first conductive layer is formed, the first conductive layer is etched so that the first first conductive layer is located in the middle area of ​​the substrate and each subsequent first conductive layer is located in the middle area of ​​the previous first conductive layer.

21. The preparation method according to claim 20, characterized in that: The step of etching the first conductive type layer each time the first conductive type layer is formed further comprises: A plurality of second conductive type layers are sequentially formed on the substrate where the first conductive type layer is exposed and on each first conductive type layer before the first conductive type layer is exposed, each second conductive type layer is doped with a second type of impurity element, and the doping concentration of the second type of impurity element decreases in a direction from the substrate toward the channel layer, and the plurality of second conductive type layers form a second conductive type column region; there are two second conductive type column regions, and the second conductive type column regions are respectively located on opposite sides of the first conductive type column region.

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