Buffer circuit

Abstract

The invention relates to a snubber circuit. The present disclosure provides a buffer amplifier arrangement seeking to find a solution to address varying load configurations, output modes, modulator modes, etc. on the buffer output, as well as corresponding varying current or voltage occurring at transistor devices throughout the circuit. To solve this problem, the current source that provides the buffer output is divided into a fixed current source that provides current for a buffer transistor and a variable current source that provides current for a variable load. The variable current source is a programmable current source that can be adjusted according to the associated modulator mode bus. Therefore, the current source is not optimized only for one load configuration, output mode, modulator mode and the like, but adapts to a variety of different loads, outputs, modulator modes and the like. In addition, this reduces power efficiency in the buffer, as less power is wasted during the "suboptimal" modulator mode. Furthermore, since the adaptive current source can match the modulator mode, there is substantially no difference between transistor gate voltages, glitch effects will be greatly reduced, resulting in a more stable output voltage, where stability in this case is related to limiting offset drift due to power supply changes or changes over time.

Description

Technical Field

[0001] The present invention generally relates to stable operation of current mirror output circuits, particularly in the presence of load current or supply voltage variations, which may be used in conjunction with amplifier circuits and associated reference buffers. More specifically, the present invention relates to power supply rejection of current mirrors and using load information to control variable current mirrors.

[0002] The present disclosure seeks to improve the power supply rejection of a current source or current source circuit. For example, the present disclosure discusses measuring and correcting first-order AC interference current from a power supply that will be used as part of a reference circuit driving an ADC reference, a DAC reference, or driving a precision analog circuit load, etc. Background Art

[0003] Figure 1 A known buffer amplifier architecture for amplifying a voltage reference used in an analog-to-digital conversion process is shown. As shown, the buffer amplifier architecture includes a first stage 12, a second stage 14, and a third stage 16. While there are a variety of different buffer amplifier arrangements, the first stage typically includes some type of input transistor, such as a junction field effect transistor (JFET), to provide gain and high input impedance. It is known that the second stage can provide additional gain and can include some type of chopper circuit, such as a preamplifier circuit, before the chopper amplifier stage [1], and if desired, the third stage will include an output amplifier or driver, which can provide further gain and can reduce the output impedance. The circuit will also include an input node 10 and a corresponding output node 18. Reducing and limiting waste and inaccuracy throughout the buffer amplifier architecture is critical to ensuring the accuracy of other devices downstream of the buffer amplifier, such as an analog-to-digital converter (ADC). The third stage can be a Miller stage including a Miller capacitor in parallel with the output amplifier, or other compensation schemes and related variations, including right hand pole (RHP) cancellation using a series resistor, etc.

[0004] Figure 2The circuit schematic for the second and third stages of the buffer amplifier architecture is shown. The output of this circuit is intended to drive a corresponding ADC device; however, the output can drive a DAC device, a precision load, etc. In the circuit, the reference buffer contains a modulator mode bus that indicates different operating modes, which indicate the number of downstream ADCs that are operating and whether the ADC is single-ended, differential, etc. Therefore, the variable DC load presented to Vout is related to the operating mode indicated on the modulator mode bus. Since there are multiple different operating modes, there are different DC loads, so the current source I2 is sized for the maximum output load current. Therefore, this arrangement works best when the system digital control or control input (which may be the modulator mode bus) indicates that the system is operating in the mode corresponding to the maximum output load current. However, in all other modes, the current source I2 is not optimally selected, so the circuit operation is wasteful - highlighting the first weakness of the traditional reference buffer circuit. In another arrangement, the variable load current is provided by a PMOS device with its source coupled to AVDD3p3 and its drain coupled to Vout. This arrangement is more efficient because the PMOS device only needs to provide the required load current, but those skilled in the art know that when a Miller cap (such as C1) is present between the drain and source of such a device, high-frequency power supply noise can couple strongly to Vout.

[0005] Furthermore, in a chopper buffer amplifier circuit, the gates of the corresponding transistor devices can be considered to be at substantially the same voltage level because the devices operate at substantially the same current density. Therefore, when chopping, the gate voltage does not change substantially. However, in Figure 2 In the case of a load change, the current also changes. Therefore, the gate voltage of the varying transistor device will change, for example, the gate voltage of MN6 will be different from the gate voltage of MN4 during the suboptimal modulator mode where the full output current provided by the current source I2 is not required. This is problematic because in this case, each time the chopping operation is performed, a step will appear on the drains of MN1 and MN2 due to the undesirable voltage difference between the gate voltages of the varying transistor devices. This will cause glitches and instabilities in the output voltage of the circuit, where the instability in this case is related to offset drift caused by power supply variations, changes over time, or changes with temperature. The output of the circuit is used as a reference, so the output needs to be as controlled and stable as possible, or essentially constant. Therefore, the second weakness of the conventional reference buffer circuit is the voltage output glitches that occur due to the variable gate voltage on the transistor device. Output glitches will eventually lead to buffer offsets and offset drifts. Reducing transient glitches is also desirable.

[0006] therefore, Figure 2The conventional arrangement shown suffers from two problems - inefficiencies due to the large current source I2 having to drive a variety of possible loads depending on the state of the downstream ADC being driven, which in turn results in glitches in voltage on the transistor terminals. The present disclosure provides an alternative buffer amplifier arrangement to limit and reduce power inefficiencies and prevent glitches on the voltage output. The present disclosure therefore seeks to provide a buffer amplifier having improved power efficiency and improved voltage output instability performance.

[0007] DACs may have code current dependence, for example ladder DACs such as voltage mode R / 2R have significant code dependence, so that the equivalent load presented by the DAC at the reference terminals varies significantly with respect to code. This code dependence can be measured or simulated. Information from the DAC architecture and microarchitectural details can be used to study and understand the nominal code dependence. Summary of the invention

[0008] The present invention provides a buffer amplifier device, such as Figure 3 As shown, the above problems are solved by introducing a variable current source (I3). The amplifier output stage may include a fixed current source I2. Fundamentally, the buffer amplifier circuit attempts to find a solution to the load current variations caused by load configuration, output mode, modulator mode, etc., and the corresponding varying currents or voltages appearing across transistor devices throughout the circuit. In this example, the variable current source (I3) is a programmable current source. Therefore, further current supply can be varied based on the associated modulator mode bus, for example, to match the load presented to the buffer. Therefore, the current source is not optimized for only one load configuration, output mode, modulator mode, etc., but is adapted to a variety of different loads, outputs, modulator modes, etc. The current source does not necessarily have to be optimized for all load configurations, modulator modes, etc., but for enough load configurations / modulation modes that the current source is considered to be the best solution considering the development effort, the final cost of adding additional modes, and the performance impact. In addition, this reduces the power inefficiency in the prior art because less power is wasted in the "suboptimal" modulator mode. Furthermore, since the adaptive current source can match the ADC modulator pattern, there is essentially no difference between the transistor gate voltages, so the glitch effect will be greatly reduced, resulting in a more stable output voltage.

[0009] The above programmable current source makes the buffer efficient in all load configurations, output modes, modulator modes, etc. Figure 2 MN4-6 in the example operate at essentially the same current density under all load conditions (the same is true for MN1,2,3). This therefore minimizes the amplitude of the chopped square wave at the drains of MN1 and MN2. As a result, the amplifier only removes the error in the programmable current source.

[0010] In an embodiment of the present invention, the buffer amplifier circuit is arranged so that the programmable current source I3 can be used to map to the modulator mode. This is achieved through data from the system digital control or control input, which in some cases can be a modulator mode bus, which provides data or information related to the load configuration, output mode, modulator mode, etc. to the programmable current source. The programmable current source can be changed from providing no current to providing a maximum current value, so the programmable current source powers a variable load.

[0011] In other embodiments of the invention, the buffer amplifier circuit is arranged so that control of the programmable current source I3 uses the DAC current requirement code dependency information. It can also be used to drive a substitute analog load while using the load current information.

[0012] A first aspect of the present disclosure provides a buffer amplifier circuit, comprising at least one or more of the following: a driver, which provides current to a load depending on a voltage across a variable load; at least one variable current source, which is arranged in use to supply current to the variable load; and a control input, which receives control information related to the current demand of the load; the arrangement is such that, depending on the received control information, the variable current source is controlled to change its output current so that the current from the driver and the variable current source meets the current requirement of the load, wherein at least most of the current requirement of the load is provided by the variable current source.

[0013] A second aspect of the present disclosure provides a shunt current source circuit, comprising at least one or more of the following: a first operational amplifier, a first transistor device, a first impedance, and a second impedance, arranged to generate a first current through a first current source; a second operational amplifier and a second transistor device, arranged to generate a second current through a second current source; the second operational amplifier, the second transistor device, the first impedance, and the second impedance are arranged to generate the second current through the second current source; and wherein the first current is a multiple of the second current, the multiple depending on the relative values ​​of the first and second impedances.

[0014] A third aspect of the present disclosure provides a current source circuit comprising at least one or more of the following: a first component subsystem coupled between a power supply and a critical node, generating a first AC current flowing into the critical node as a result of an unwanted AC signal on the power supply; a replica component subsystem coupled to the power supply to generate a second AC current, the second AC current being a ratiometric replica of the first AC current; a replica bias circuit subsystem arranged to set bias conditions of components within the replica component subsystem to be equal to or equivalent to bias conditions of components in the first component subsystem; and a current-to-voltage converter subsystem arranged to generate, in use: i) a first signal via a first signal path that reduces the second AC current, wherein the first signal path couples the current-to-voltage converter subsystem to the replica component subsystem; and ii) a second signal via a second signal path that reduces the first AC current, wherein the second signal couples the current-to-voltage converter subsystem to the first component subsystem.

[0015] Further features and advantages will be apparent from the dependent claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Other features and advantages of the present disclosure will become apparent from the following description of embodiments of the present disclosure, given by way of example only, with reference to the accompanying drawings, in which like reference numerals represent like parts, and in which:

[0017] Figure 1 shows a top-level system diagram of a buffer amplifier according to the prior art;

[0018] Figure 2 The second stage of a buffer amplifier according to the prior art is shown (eg Figure 1 Schematic diagram of ;

[0019] Figure 3 shows a schematic diagram of a second stage of a buffer amplifier according to an embodiment of the present disclosure;

[0020] Figure 4a A programmable current source (such as Figure 3 Schematic diagram of ;

[0021] Figure 4b A programmable current source (such as Figure 4a ) as shown;

[0022] Figure 4c A programmable current source (eg, Figure 4a Schematic diagram of ;

[0023] Figure 4d A programmable current source (such as Figure 3 A more complete schematic diagram of

[0024] Figure 5 An example frequency response graph is shown showing the effect of the circuit of the present disclosure compared to a prior art circuit;

[0025] Figure 6 The embodiment according to the present disclosure is shown Figure 3 A simplified circuit diagram of the schematic shown;

[0026] Figure 7 An example according to an embodiment of the present disclosure is shown. Figure 3 the schematic diagram shown, but in which it is arranged to provide a clean current source to the secondary circuit;

[0027] Figure 8 A schematic diagram of a shunt current source arrangement according to another embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0028] The present disclosure provides a buffer amplifier device that attempts to find a solution to the load impedance changes caused by the modulator mode changes on the buffer output and the corresponding changing current or voltage appearing at the transistor devices in the entire circuit. To solve this problem, the current of the load is provided by a variable current source and a buffer amplifier, the variable current source provides current to the variable load, and the buffer amplifier provides a compensation current to correct any errors in the variable current source. The variable current source can be a programmable current source that can be changed based on the associated modulator mode bus. Therefore, the current source is not only optimized for one modulator mode, but also suitable for multiple modulator modes. In addition, this reduces the power inefficiency in the buffer because less power is wasted in the "suboptimal" modulator mode. In addition, since the adaptive current source can match the modulator mode, the buffer amplifier only needs to provide a correction current. Then, the difference between the transistor gate voltages in the corresponding chopper devices is small, and the glitch effect will be greatly reduced, resulting in a more stable output voltage.

[0029] More specifically, the present disclosure relates to a current source PSRR (Power Supply Rejection Ratio) improvement circuit by which a buffer amplifier output is stabilized or maintained at a more constant level using a variable current source in the presence of power supply variations.

[0030] More specifically, in one embodiment, the present invention relates to a programmable current source circuit that can be used as a variable current source in conjunction with a buffer amplifier to map a load drive current to a variable downstream modulation pattern.

[0031] As a brief non-limiting overview, the present disclosure is a buffer amplifier arrangement in which the circuit includes a variable current source, referred to as a programmable current source, adapted to change to different modulator modes. Thus, the programmable current source improves the buffer power efficiency in multiple modulator operating modes. Figure 3 As shown, the programmable current source works by ensuring that the buffer transistors (MN4-6) operate at substantially the same current density in a variety of modulator modes or load conditions. This therefore minimizes the amplitude of the truncated square wave on the MN1 / 2 drain. In other words, this prevents voltage glitches after each chopping operation to improve output voltage stability.

[0032] refer to Figure 4a , the programmable current source is arranged to significantly reduce the disturbance to the power supply AVDD coupled to the output node Vout. This is achieved in part by creating the same output voltage copy Vout_copy via a diode connected device MP15 and a source follower MP14. The MP1 AC drain current caused by the disturbance in the power supply AVDD flows primarily through MP14 to the high impedance node at the drain of MP14. Therefore, the high impedance node is coupled to the gate of MP1 via MP10, so that the loop serves MP1 AC to substantially zero. Since the gates of MP1, 3, 5, and 8 are all connected and arranged to have substantially the same terminal voltage, if the MP1 AC drain current is substantially zero, then by matching, the drain currents of MP3, 5, and 8 are also substantially zero because they have the same terminal voltage as MP1. It should be noted that MP12 and MP13 act as switches with finite impedance under the control of the modulator mode bus. MP6 and MP7 are shown as having grounded gates and are used to ensure that MP1, MP3, MP5, and MP8 all have the same drain-source voltage. The MP6 and MP7 gates can also be coupled to a non-zero DC or quasi-DC level. Devices MP6 and MP7 replicate the "on" condition of devices MP12 and MP13, which act as switches operating in their linear operating region in the "on" state. Using MP12 and MP13 in the linear operating mode allows the circuit to operate with low output compliance, which is useful for low supply operation and power efficiency.

[0033] If output compliance permits, these MP6, MP7, MP12, MP13 devices can be changed to use the saturated operating region. In this case, if Figure 4bAs shown, the bias voltage can be ideally set to keep the device in saturation, but in some use cases, the device may also at least partially transition from saturation to the linear operating region, similar to the cascode design used in known current mirror or current replica circuits. The gate of the variable current source cascode can be switched between an "off" voltage and an "on" cascode voltage. This should be achieved by a break-before-make drive circuit so that during the transition, the cascode voltage is not shorted to the off voltage source through the switching circuit, such as Figure 4c As shown, mcc <1> and mccb <1> The control signals use abbreviations in the naming to denote the control of the gates of the modulator mode control 1 and modulator mode control bar, where bar is the convention of an inverted or complementary version. These signals can be driven directly by synthesized digital signals, which are usually automatically routed, or the switches can use a hand-crafted digital switch driver design that can be optimized for low power and timing optimized for synchronization of switching activity in multiple switched current source cascode devices.

[0034] The programmable current source consists of four key subsystems, such as Figure 4a As shown, specifically Figure 4b As shown, they are basically a first component subsystem 40, a replica component subsystem 42, a replica bias circuit subsystem 44, and a current-to-voltage converter 46. The first component subsystem 40 is coupled between a power supply and a critical node (such as Vout), which provides a first AC path flowing into the critical node due to an unwanted AC signal on the power supply. The replica component subsystem 42 is coupled to a power supply that produces a second AC output, which is a ratiometric replica of the first AC. The replica bias circuit subsystem 44 sets the bias on the replica component to be equal to or equal to the bias on the first component (even when the power supply varies). Finally, the current-to-voltage converter subsystem 46 receives a portion of the second AC and provides a first signal path and a corresponding first signal from the current-to-voltage converter subsystem 46 to the replica component 42, and the replica component 42 reduces the second AC in response to the first signal. The current-to-voltage converter subsystem 46 also provides a second signal path and a corresponding second signal from the current-to-voltage converter 46 to the first component subsystem 40, and the first component subsystem 40 reduces the first AC in response to the second signal.

[0035] Now we will combine the relevant Figure 3-7 The present disclosure is discussed in more detail. Figure 3 FIG. 1 shows a circuit diagram of the second and third stages of a buffer amplifier 3 including a programmable current source I3 according to an embodiment of the present disclosure. Figure 2The prior art circuit shown is the same. Therefore, it includes a chopping device including a plurality of PMOS and NMOS devices, an input voltage, a fixed current source and a variable load, wherein the variable load represents a downstream circuit load configuration, an output mode, a modulator mode, etc. However, Figure 3 A variable programmable current source I3 is also included, which varies according to feedforward data from the system digital control or control input or modulator mode bus, which feedforward data indicates the operating mode of the modulator, that is, which ADCs are currently running, which parts of the ADCs are currently running, whether the ADCs are single-ended or differential, etc. The operating mode of the modulator can also indicate the number of DACs currently operating and their corresponding characteristics, or more generally can indicate the current demand of the analog load. It is worth noting that although DACs are generally considered to provide relatively stable load conditions, some DACs may have highly variable load conditions. The circuit described herein is capable of providing the necessary current to drive a variety of load conditions, including highly variable DAC loads for reference buffers. There may be other indicators in the system, such as measured values ​​or calibration values, which can indicate manufacturing variations and can also be used as inputs to the amplifier output stage control. The programmable current source changes its output current based on feedforward data via the modulator mode bus, which indicates the modulator mode. Therefore, the programmable current source changes its output current so that the connected devices MN4, MN5, and MN6 all operate at the same current density regardless of the load conditions or modulator mode. This helps keep the voltage on the drains of MN1 and MN2 nominally constant over the chopping cycle and prevents the generation of a chopped square wave as in the prior art. As in the prior art, current source I2 may still be present in this circuit, but it is much smaller and is now sized to provide a nominal reference bias current level for the devices in the amplifier rather than being sized for the modulator mode associated with the maximum output load current. If further calibration or fine tuning of current source I2 is required, it can be done outside of this block before providing the nominal reference bias current. Also, it is worth noting that current source I2 is optional (as in Figure 3 If it does not exist, the same function can be achieved by only using the variable current source I3. Figure 3 The only difference in this case is that the operating range of the variable current source will have a minimum value of 360uA instead of 0uA.

[0036] In other words, it can be said that Figure 2 The fixed current source in has been divided into a smaller fixed current source and a variable current source (programmable current source). This can be Figure 2 As can be seen in Figure 1, I2 provides 1.8 mA. However, Figure 3In the example above, I2 now only provides 360uA to bias the NMOS / PMOS devices, and I3 provides a variable current between 0 and 1260uA to drive the variable load associated with the different modulator modes. Therefore, when the modulator is in no-load mode, i.e. when nothing is being used in the output stage, only 360uA is provided, so there is greater potential power savings.

[0037] To describe the second stage buffer amplifier 3 in more detail, the circuit consists of four PMOS devices (MP1-MP4), six NMOS devices (MN1-MN6), three current sources (I1-I3), resistor capacitor devices (R1 and C1), and a variable load (R LOAD). The circuit also includes a voltage high node AVDD3p3 and a ground node AGND. The circuit also includes a modulator mode bus for transmitting the current operating mode of the modulator, including information indicating the number of downstream ADCs being operated, whether the ADC is single-ended or differential, etc. It can be said that the NMOS and PMOS devices are arranged to create a network of transistor devices.

[0038] In addition, the circuit includes three voltage inputs, Vin, Vip, and Vcasc. Vin and Vip are coupled to the gates of PMOS devices MP1 and MP2, respectively. The drains of MP1 and MP2 are coupled to the sources of MP3 and MP4, respectively. The gates of MP3 and MP4 are both tied to ground. The sources of MP1 and MP2 are coupled to the voltage high node AVDD3p3 via a current source I1. Vcasc is coupled to the gates of NMOS devices MN1, MN2, and MN3. The drains of MN1 and MN2 are then coupled to the drains of PMOS devices MP3 and MP4, respectively. The sources of MN1, MN2, and MN3 are coupled to the drains of MN4, MN5, and MN6, respectively, and the sources of MN4, MN5, and MN6 are connected to the ground node AGND. The output of the reference buffer is connected to a series network of R1 and C1, where R1 and C1 exist to create a dominant pole in the Miller amplifier device, thereby producing a stable output. Its output drives the downstream ADC, so stability is critical.

[0039] Figure 4a A schematic circuit diagram of a programmable current source is shown. Figure 3 The programmable current source 4 consists of four different subsystems: a first component 40, a replica component 42 arranged to have the same or equivalent voltage at its terminals as the first component, a replica bias circuit 44 that sets the bias on the replica component by creating a replica voltage Vout (referred to as Vout_copy), and a current-to-voltage converter 46.

[0040] To further decompose the subsystems, the first component subsystem 40 includes two example modulator mode inputs and a plurality of PMOS devices associated with the operating modes of the modulator. <1> and modulator_mod <0> ) are coupled to the gates of PMOS devices MP12 and MP13, respectively. The sources of MP12 and MP13 are connected to the drains of MP5 and MP8, respectively. In turn, the sources of MP5 and MP8 are coupled to the source AVDD, while the gates of MP5 and MP8 are coupled to the gates of MP3 (also in the first component subsystem 40), MP2, and MP1 (part of the replica component subsystem 42). The drains of MP12 and MP13 are connected to Vout. In addition, the source of PMOS device MP7 is coupled to the drain of MP3, and the gates of MP7 and MP6 (part of the replica component subsystem 42) are coupled to AGND. Finally, the drain of MP7 is connected to Vout.

[0041] The replica component subsystem 42 includes two PMOS devices MP1 and MP6. The source of MP1 is coupled to the source AVDD, and the drain is coupled to the source of MP6. As previously described, the gate of MP1 is coupled to the gates of MP2, MP3, MP5, and MP8. The drain of MP6 is connected to the source of resistors R1 and MP14 (part of the replica bias subsystem 44). The node coupling MP6, MP14, and R1 is considered to be the Vout_copy node. In addition, the first component subsystem 40 includes a first control terminal, and the replica component subsystem 42 includes a second control terminal, and the first control terminal and the second control terminal can have substantially the same terminal voltage. In addition, the first and second control terminals are coupled to the gates of MP1 and MP3 / 5 / 8, respectively.

[0042] The replica bias circuit subsystem 44 includes two PMOS devices MP14 and MP15. As previously described, the source of MP14 is coupled to the Vout_copy node and, by association, to the drains of R1 and MP6. The drain of MP14 is coupled to the drain of NMOS device MN1 (part of the current-to-voltage converter subsystem 46), as well as to the gate of MP10. Finally, the gate of MP14 is connected to the gate of MP15 and to AC ground through C2. The source of MP15 is coupled to the Vout node. The drain of MP15 is connected to its gate and also to the drain of NMOS device MN2. It can be seen that when MP14 and MP15 have the same gate length and operate at the same current density, the Vout_copy node will be at substantially the same voltage as Vout.

[0043] Finally, in the exemplary embodiment, the current-to-voltage converter subsystem 46 includes a PMOS device MP14 (also forming part of the replica bias circuit subsystem) and two NMOS devices MN1 and MN4. As previously described, the source of MP14 is coupled to the Vout_copy node and, by association, to the drains of R1 and MP6. The drain of MP14 is coupled to the drain of NMOS device MN1 and to the gate of MP10. Finally, the gate of MP14 is connected to the gate of MP15 and to AC ground through C2. The source of MN1 is coupled to the drain of MN4. The gate of MN1 is coupled to the gate of MN2, and this node is considered to be the Vcasc node. The gate of MN4 is coupled to the gate of MN5, and this node is considered to be the Vbias node. The sources of MN4 and MN5 are coupled to the ground node AGND.

[0044] Other components fall outside the designated subsystem, such as PMOS devices MP2 and MP10. MP2 and MP10 are essential to the first and second signal paths to be described. The source of MP2 is coupled to the source AVDD, the gate of MP2 is coupled to the gates of MP1, MP3, MP5, and MP8, and the drain of MP2 is coupled to the source of MP10 and its own gate. The gate of MP10 is coupled to the drain of MP14 and MN1. The drain of MP10 is grounded.

[0045] The first component subsystem 40 is coupled between the power supply AVDD and a critical node at Vout, which generates a first AC current flowing into the critical node due to an unwanted AC signal on the power supply. The replica component subsystem 42 is also coupled to the power supply AVDD and generates a second AC current output, which is a ratiometric replica of the first AC current. The replica bias circuit subsystem 44 works in conjunction with the replica component subsystem 42 when the replica bias circuit subsystem 44 sets the bias on the replica component subsystem 42 to be equal to or equal to the bias on the first component (even when the power supply changes). In addition, the replica bias circuit subsystem 44 can be coupled to an impedance, a current source, a current sink to set a DC bias, etc. The impedance can be composed of a resistor device, a network of resistor devices, or devices of the same type, such as using a "unit" device. In addition, it can also use different types of impedances to achieve specific desired characteristics. Active devices can also be used to provide variable or adjustable impedance. The current-to-voltage converter subsystem 46 is the starting point of the first signal path, and the corresponding first signal is transmitted from the current-to-voltage converter subsystem 46 to the replica component 42, and the replica component 42 reduces the second AC current in response to the first signal. The first signal path passes through MP10 from the current-to-voltage converter and toward MP1. There is another second signal path and a corresponding second signal transmitted from the current-to-voltage converter 46 to the first component 40, and the first component 40 reduces the first AC current in response to the second signal. The second signal path couples the current-to-voltage converter through MP10 and MP2, and is further coupled to MP3, MP5 and MP8 within the first component subsystem. However, the first signal path and the second signal path can be different, the same (as shown here), or partially shared. It can be seen that the bias of device MP1 is substantially the same as that of output devices MP5 and MP8. To simplify the explanation, we can consider that all NMOS devices are the same size, and all PMOS devices are also the same size, except for MP1 and MP6, which will effectively double the aspect ratio of all other PMOS devices. Therefore, the following equation is true:

[0046]

[0047] During operation, a DC current flows from the drain of MP1 through MP6 to the high impedance node at the drain of MP14. The same DC current will also flow from the drain of MP1 through MP6 and R1 to ground. The high impedance node at the drain of MP14 is coupled to the gate of MP1 via MP10 to form a loop. From a DC perspective, if Vout_copy drops below Vout, the current flowing into MP14 decreases and the voltage at the high impedance node MP14 drain drops. This in turn causes the voltage at the MP10 source and MP1 gate to decrease. MP1 (and MP6) will respond with an increase in drain current, which then causes the voltage at Vout_copy to rise toward the ideal voltage Vout. From an AC perspective, operation is similar: any unwanted AC flowing from the supply AVDD through MP8 and MP13 to Vout will cause a corresponding amount of AC to flow through MP1 and MP6 to Vout_copy. This current (as it increases) will flow primarily through the low impedance source of MP14 to the high impedance node at the drain of MP14, causing the voltage at the high impedance node to increase. The rise in voltage will be passed through MP10 to the gate of MP1, which then responds to reduce the rise in current so that the loop serves to AC-servo MP1 to nominal zero. Due to the arrangement of MP1 and MP8, if the MP1 drain AC current is zero, the MP8 drain current is also zero. A resistor (such as R1) or a current source / sink can be coupled to the replica component to set the DC bias. Furthermore, the current flowing to Vout is a ratiometric measure of the current in R1.

[0048] MP10 is arranged as a source follower and level shifts the voltage on the high impedance node on the drain of MP15 to the gate of MP1 to prevent MP14 from coming out of saturation. In addition, MP10 acts as a buffer to isolate the high impedance node from any AC flowing out of the gates of MP1, MP2, MP3, MP5, and MP8. For this circuit to work properly, the only AC that can flow into the high impedance node is the current from the drain of MP6. In some cases, the AC gate currents flowing out of MP1, MP2, MP3, MP5, and MP8 may be small enough that a buffer is not needed, and in some arrangements, a level shifter is not needed.

[0049] As a modification to this embodiment, MP12-13 can be configured as switchable cascodes instead of being used as switches. The MP12-13 gates can then be independently connected to a new cascode bias voltage or a shutdown voltage such as AVDD, while MP6-7 are connected to this new cascode bias.

[0050] Figure 4b Shows the Figure 4a A simplified block diagram of the above schematic diagram related to the above. Figure 4bA simplified relationship is shown between the first component subsystem 40, the replica component subsystem 42, the replica bias circuit subsystem 44, and the current-to-voltage transformer subsystem 46. It should be noted that some components involve multiple subsystems and therefore may function in multiple sub-blocks, such as MP14 performing functions in both the replica bias circuit subsystem 42 and the current-to-voltage converter subsystem 46. In other words, there is overlap between the replica bias circuit subsystem and the current-to-voltage converter subsystem.

[0051] Figure 4c Another schematic diagram showing a programmable current source (e.g. Figure 3 As shown in Figure 2, it can be seen that the figure illustrates the Figure 4a Another embodiment of a programmable current source is shown in FIG. Figure 4a The arrangements of are basically corresponding, but differ only in the arrangement of the control input or modulator mode input. Figure 4a The control inputs coupled to the gates of MP12 and MP13 are Figure 4c The dual cascade 48a-b arrangement 48a-b is replaced by the control input mmc <1> 、mmcb <1> 、mmp <0> and mmcb <0> The drains of the cascodes are then coupled to MP12 and MP13, respectively. One cascode source pin in each dual cascode arrangement is coupled to the AVDD node, and the other cascode power supply pin in each dual cascode arrangement is coupled to the Vcascp pin.

[0052] Figure 4d A more complete schematic is shown, which includes Figure 4a All devices shown in . In this embodiment, the voltages Vbias and Vcasc are generated internally by the additional devices MP9, MP11, MP3, and MP6, and resistor R3. In addition, to more accurately generate the Vout_copy node, cascodes MP14b and MP15b and bias resistor r2 are added to better match the drain voltages of MP14a and MP15a. Also note that MN7, biased by gate voltage Vbias2, is added to provide a current path. This may be appropriate when a constant current is required, independent of the voltage on Vout. MN7 is in addition to R1, but can also replace R1. Vbias can be a fixed voltage or a variable voltage, in which case MN7 can be considered a variable current source. In another example, the MN7 gate voltage can be dynamically operated, for example, it can be turned on for a limited time while the current in the programmable current source is established. This may be necessary because when the circuit is biased by resistor R1 alone, it can have a stable state in which no current flows in any device. Alternatively, for low power circuits, the dynamic switching of the MN7 can speed up the circuit's turn-on time.

[0053] Figure 5 shows a simulated frequency response Figure 5 , shows a performance model comparison of the example embodiment with the power supply rejection (PSR) loop disabled versus enabled. It can be seen that the PSR loop has a significant positive impact on the performance of the circuit, indicating that the PSR loop significantly reduces the coupling from the power supply to Vout. To emphasize this more clearly, Figure 5 It is shown that at a frequency of 1MHz, the PSR loop reduces the power supply variation coupled to Vout by 34dB. Therefore, the AC interference current is significantly reduced.

[0054] Simplified general circuit of programmable current source Figure 6 like Figure 6 As shown in Figure 1. It can still be seen that the replica component subsystem exists in the form of MP1 and the first component subsystem exists in the form of MP8. Similarly, the current-to-voltage converter is shown as I_to_V. Level_shifter and Buffer2 are implemented by MP10, as shown in Figure 1. Figure 4a As shown. Level_shifter and Buffer2 are both optional components and can also be interchanged in the arrangement, i.e. the buffer can be arranged before the level shifter. Level shifting can also be achieved by means of a battery cover (as described in US 10931122 B2), where the battery capacitor is often referred to as a supercapacitor or ultracapacitor, i.e. a capacitor that substantially maintains its relative charge level when loaded for a short period of time.

[0055] Furthermore, it is worth noting that the output stage variation of the present disclosure can use degradation to balance the current distribution within the output stage. The output stage can use scaling and / or segmentation [2].

[0056] Figure 7 FIG. 1 shows a schematic diagram of a clean current source circuit 7 for a secondary circuit according to another embodiment of the present disclosure. It can be seen that the circuit is Figure 4a The circuit in is very similar, but provides a fixed current to a secondary circuit that is largely immune to unwanted disturbances on the power supply AVDD.

[0057] like Figure 4a As shown, the clean current source circuit 7 includes four main subsystems: a first component subsystem 70 , a replica component subsystem 72 , a replica bias subsystem 74 and a current-to-voltage converter subsystem 76 .

[0058] To further decompose the subsystems, the first component subsystem 70 includes a plurality of PMOS devices MP5-MP6 and MP11-MP12. The sources of MP5 and MP6 are connected to the high voltage node AVDD. The drains of MP5, MP6 are connected to the sources of MP11 and MP12, respectively. The gates of MP5 and MP6 are tied together and tied to the gates of MP1, MP2 and MP3 (MP1 and MP2 form part of the replica component subsystem 72). The gates of MP11 and MP12 are connected together with the gate of MP9 present in the replica bias subsystem 74 and the current-to-voltage converter subsystem 76. The drains of MP11 and MP12 provide current outputs to the circuit blocks. It is worth noting that, as Figure 7 As shown, this embodiment and Figure 3 The arrangement is similar in that it uses the same PSR technique, but instead of driving a single load at Vout, it provides one or more clean current sources to circuits that normally require multiple current sources, such as op amps.

[0059] The replica component subsystem 42 includes two PMOS devices MP1 and MP2. The sources of MP1 and MP2 are coupled to the source AVDD, while the drains of MP1 and MP2 are coupled to the source of MP9. As previously described, the gates of MP1 and MP2 are coupled to the gates of MP2, MP3, MP4, MP5, and MP6. The drain of MP2 is coupled to the source of resistor R1 and MP9 (part of the replica bias subsystem 74 and current-to-voltage converter 76). The node between MP1, MP2, MP9, and R1 is considered the MP11 / 12_source_copy node.

[0060] The replica bias circuit subsystem 74 includes three PMOS devices MP9, MP11, and MP12. As previously described, the source of MP9 is coupled to the MP11 / 12_source_copy node and, by association, to R1 and the drains of MP1 and MP2. The drain of MP9 is coupled to the drain of the NMOS device MN1 (part of the current-to-voltage converter subsystem 76).

[0061] The current-to-voltage converter subsystem 76 includes a PMOS device MP9 (also forming part of the replica bias circuit subsystem 74) and an NMOS device MN1. As previously described, the source of MP9 is coupled to the MP11 / 12_source_copy node and, by association, to the drains of R1 and MP1 / MP2. The drain of MP9 is coupled to the drain of the NMOS device MN1 and also to the gate of MP8. The source of MN1 is coupled to the ground pin AGND.

[0062] The first and second signals and the first and third signal paths are connected to Figure 4a , however, they are Figure 7 MP8 and MP3 instead of Figure 4a MP10 and MP2 appear in. Figure 4a The circuit and Figure 7 The main difference between the circuits in is that the clean current source 7 does not have any control input or modulation mode bus and therefore does not receive feed-forward data indicating downstream operation, modulation mode or load conditions. Figure 4a The gates of the appropriate PMOS devices (MP12 and MP13) in the Figure 7 The gates of the appropriate PMOS devices (MP11 and MP12) in the replica bias subsystem 74 are connected to the gate of the PMOS device (MPa9) in the replica bias subsystem 74. Therefore, MP9 has the same source-gate voltage as MP11 and MP12, thereby replicating the voltage on the source of the new key nodes MP11 and MP12 on the node "MP11 / 12_source_copy". V1 is a voltage source that sets the gate voltage of MP9, MP11 and MP12. This voltage source does not need to be a fixed voltage, it can depend on node voltages within the circuit or elsewhere. Alternatively, it may depend on temperature, such as to maximize the headroom of MP11 / 12 over the operating temperature range.

[0063] Figure 8 A simplified schematic diagram of a shunt current source device 8 according to another embodiment of the present disclosure is shown. The circuit includes a network including two resistors or impedances (R_ff (first impedance) and R_ff / 64 (second impedance)), two operational amplifier devices 80 (first operational amplifier), 82 (second operational amplifier), a first current sink iReq, a first transistor device or NMOS device 84, a second transistor device or NMOS device 86, and a capacitor (CBypass) and a second current sink iLoad. The shunt current source device 8 also includes a high voltage node VDDH and a ground node 88. It is worth noting that although embodiments related to current sources are discussed, the solution can also be reversed to provide a current source of negative polarity, commonly referred to as a current sink.

[0064] In addition, the high voltage node or voltage source VDDH is directly coupled to the drain of NMOS device 86 and is coupled to the drain of NMOS device 84 through resistor R_ff / 64. The two gates of NMOS device 84 and NMOS device 86 are coupled to the outputs of operational amplifier 80 and operational amplifier 82, respectively. The drain of NMOS device 84 is coupled to the positive input of operational amplifier 80, and the source of NMOS device 86 is coupled to the negative input of operational amplifier 82. The positive input of operational amplifier 82 is connected to a 1.8V reference (1.8V_ref). The negative terminal of operational amplifier 80 is coupled to a node intersecting VDDH via R_ff and is coupled to GND 88 via a current sink iReq. The current sink iReq is the feed-forward current information from the circuit. The sources of NMOS device 84 and NMOS device 86 are coupled together, the source connection branch of NMOS device 84 is coupled to GND 88 via capacitor CBypass, and the source connection branch of NMOS device 86 is coupled to GND 88 via load iLoad.

[0065] According to another embodiment of the present disclosure, Figure 8 The circuit provides Figure 3 Similar operations. In this embodiment, Figure 8 Feedback devices are used instead of Figure 3 A feed forward device is provided which utilizes a modulation mode bus to feed forward information indicative of load conditions and downstream circuit operation. This is accomplished by the circuit observing the load currently being driven and then providing this small current, which is a measure of iLoad, through a resistor R_ff to produce a voltage which is replicated by the operational amplifier 80. In this arrangement, the iReq current may be equal to 1 / 65 of the total current. The load represented by the current sink iLoad may be a transistor circuit such as an operational amplifier. In almost all such circuits, current sinks are required to bias the various stages within the amplifier. Typically these current sinks in CMOS circuits are made from ratio or replica NMOS devices that share a common gate and have their sources grounded. The gate voltage may be generated by a diode connected device. When iLoad is represented by such a circuit, an additional NMOS current sink is provided, forming a current mirror with the diode connected device, sized so that the current of this current sink is 1 / 65 of the total amplifier current (e.g. Figure 8The generation of iReq can be considered as an indirect measurement of the load current. R_ff, amplifier 80, R_ff / 64 and NMOS device 84 multiply this current by a factor of 64, so that the current provided by NMOS device 84 is equal to a fraction 64 / 65 of the iLoad current. Therefore, NMOS device 86 only needs a source of 1 / 65 of the load current. It is worth noting that the values ​​of R_ff and R_ff / 64 provided here are for example purposes only. The values ​​of R_ff and R_ff / 64 can vary depending on the current ratio between NMOS device 84 and NMOS device 86 and the source that the designer desires.

[0066] In another embodiment, iReq may be Figure 4d The current in the drain of MN7 is calculated by removing R1, where MN7 is the output device of the current mirror and Vbias2 is connected to a diode connected device within the circuit. In this arrangement, MP5 and MP8 will be sized to provide the current generated by Figure 8 The current is provided by NMOS device 84 in MN7. In this feedback arrangement, node Vout_copy is the control input and the current in MN7 is the control information (rather than the modulator mode bus, which is simply grounded to turn on MP12 and MP13).

[0067] The motivation for this arrangement is that during load switching, the circuit can operate and react faster to replicate the current conditions under load, because amplifier 82 only needs to make a small change in the current provided by NMOS device 86 to make a large change in the iLoad current. Therefore, the voltage glitch effect is again reduced. Therefore, the circuit provides a more stable output voltage under variable load conditions.

[0068] Although the current source implementation has nominal values, using a variable current source in conjunction with a driver can justify output current limiting within the driver. The programmable current source short-circuit current can be largely self-limiting.

[0069] As described herein, the preferred embodiment uses static encoding, which is often required to reduce design complexity, verification, and validation. Many variations of dynamic element matching (DEM) can also be used to change the selected devices to randomize or noise the effects of mismatches at the cost of additional design complexity, as known to those skilled in the art [3].

[0070] Unless the context clearly requires otherwise, throughout the specification and claims, the words "includes," "comprising," "including," and "containing" should be interpreted as being inclusive and not exclusive or exhaustive; that is, in the sense of "including but not limited to."

[0071] The term "coupled" or "connected" or "bound" as generally used herein refers to two or more elements or nodes that may be directly connected or connected through one or more intermediate elements. In addition, the terms "herein," "above," "below," and words of similar meaning as used in this application shall refer to the entire application and not to any particular part of this application. Where the context permits, words used in the singular or plural in the detailed description may also include the plural or singular, respectively. When referring to a list of two or more items, the word "or" is intended to cover all of the following interpretations of the word: any item in the list, all items in the list, and any combination of the items in the list.

[0072] It should be understood that the above list is not exhaustive and that the methods and systems described herein are applicable to many technical problem areas to which machine learning models may be applied.

[0073] It is worth noting that although example embodiments have been presented with respect to NMOS and PMOS transistor devices, the present disclosure may be implemented using different transistor devices such as CMOS, BiCMOS, BJT, JFET, etc.

[0074] Various modifications, whether by addition, substitution, or deletion, will become apparent to the intended reader to provide further embodiments of the present disclosure, any and all modifications being intended to be covered by the appended claims.

[0075] Below is a series of numbered clauses, each of which defines an example of the present disclosure. If a numbered clause refers to an earlier numbered clause, the features of those clauses should be considered in conjunction.

[0076] [Clause 1] A buffer amplifier circuit comprising:

[0077] A driver, which supplies current to a load depending on the voltage across the variable load;

[0078] at least one variable current source arranged, in use, to supply current to the variable load; and

[0079] A control input for receiving control information related to the current demand of the load;

[0080] The arrangement enables the variable current source to be controlled to vary its output current depending on received control information so that the current from the driver and the variable current source meets the current requirement of the load, wherein at least most of the current requirement of the load is provided by the variable current source.

[0081] [Clause 2] The circuit of clause 1, wherein the driver is an output stage of an operational amplifier.

[0082] [Clause 3] The circuit of clause 1, wherein the driver is separate from the at least one variable current source.

[0083] [Clause 4] The circuit of clause 1, wherein all current requirements of the variable load are provided by the variable current source.

[0084] [Clause 5] The circuit of clause 1, wherein the control input receives digital information related to the current demand of the load.

[0085] [Clause 6] The circuit of clause 1, wherein the control input receives control information related to the magnitude of the load voltage from a direct or indirect measurement of the load current.

[0086] [Clause 7] The circuit of clause 6, wherein the control information is generated using a current mirror.

[0087] [Clause 8] The circuit of clause 7, wherein the control information is current and sets a bias in the variable current source.

[0088] [Clause 9] The circuit of clause 1, wherein the at least one variable current source comprises the following subsystems:

[0089] a first component subsystem, wherein the first component subsystem is coupled between a power source and a critical node to generate a first AC current that flows into the critical node as a result of an unwanted AC signal on the power source;

[0090] a replicating component subsystem, wherein the replicating component subsystem is coupled to the power source to generate a second AC current that is a ratio replica of the first AC current;

[0091] A replica bias circuit subsystem, wherein the replica bias circuit is arranged to:

[0092] Setting bias conditions of components within the replicated component subsystem to be equal or identical to bias conditions of components in the first component subsystem and further arranged to be coupled to an impedance, current source or current sink to set a DC bias; and

[0093] a current-to-voltage converter subsystem, wherein the current-to-voltage converter subsystem generates:

[0094] (i) a first signal via a first signal path that reduces the second AC current, wherein the first signal path couples the current-to-voltage converter subsystem to the replica component subsystem; and

[0095] (ii) a second signal via a second signal path that reduces the first AC current, wherein the second signal couples the current-to-voltage converter subsystem to the first component subsystem.

[0096] [Clause 10] The circuit of clause 9, wherein one or more of the first and second signal paths include a buffer.

[0097] [Clause 11] The circuit of clause 9, wherein one or more of the first and second signal paths include a level shifter, wherein the level shift is provided by a threshold in a transistor device or a battery cover.

[0098] [Clause 12] A shunt current source circuit comprising at least:

[0099] a first operational amplifier, a first transistor device, a first impedance, and a second impedance, arranged to generate a first current via a first current source;

[0100] a second operational amplifier and a second transistor device arranged to generate a second current via a second current source;

[0101] The second operational amplifier, the second transistor device, the first impedance and the second impedance are arranged to generate the second current through the second current source; and

[0102] The first current is a multiple of the second current, and the multiple depends on the relative values ​​of the first and second impedances.

[0103] [Clause 13] A current source circuit comprising:

[0104] a first component subsystem coupled between the power source and the critical node, generating a first AC current flowing into the critical node as a result of an unwanted AC signal on the power source;

[0105] a replica component subsystem coupled to the power source to generate a second AC current that is a ratiometric replica of the first AC current;

[0106] a replica bias circuit subsystem arranged to set bias conditions of components within the replica component subsystem to be equal to or identical to bias conditions of components in the first component subsystem; and

[0107] A current-to-voltage converter subsystem arranged, in use, to produce:

[0108] i) a first signal via a first signal path that reduces the second AC current, wherein the first signal path couples the current-to-voltage converter subsystem to the replica component subsystem; and

[0109] ii) a second signal via a second signal path that reduces the first AC current, wherein the second signal couples the current-to-voltage converter subsystem to the first component subsystem.

[0110] [Clause 14] The circuit of clause 13, wherein a control terminal voltage of the first component subsystem is the same as a control terminal voltage of the replica component subsystem.

[0111] [Clause 15] The circuit of clause 13, wherein the first signal path and the second signal path may be different, the same, or partially shared.

[0112] [Clause 16] The circuit of clause 13, wherein the circuit further comprises a level shifter within the first and / or second signal path.

[0113] [Clause 17] The circuit of clause 13, wherein the circuit further comprises a buffer within the first and / or second signal path.

[0114] [Clause 18] The circuit of clause 13, wherein the first component subsystem includes a first control terminal and the replica component subsystem includes a second control terminal, the first control terminal and the second control terminal having substantially the same terminal voltage.

[0115] [Clause 19] The circuit of claim 13, wherein the source of a transistor device arranged as a voltage follower is coupled to the replica component subsystem, the drain of the transistor device is directly or indirectly coupled to the output of the current-to-voltage converter subsystem, and the gate of the source follower is biased to set the bias conditions of the components within the replica component subsystem to be equal to or identical to the components in the first component subsystem.

[0116] [Clause 20] The circuit of clause 13, wherein the critical node is a source terminal of one or more transistor devices biased as a cascode, wherein the drain terminal of the cascode provides current to a component within the circuit, such as an operational amplifier.

[0117] References

[0118] [1] C. C. Enz and G. C. Temes, "Circuit techniques for reducing theeffects of op-amp imperfections: autozeroing, correlated double sampling, andchopper stabilization," in Proceedings of the IEEE, vol. 84, no. 11, pp.1584-1614, Nov. 1996, doi: 10.1109 / 5.542410.

[0119] [2] Manganaro, Gabriele. Advanced data converters. CambridgeUniversity Press, 2011.

[0120] [3] Schreier, Richard, and Gabor C. Temes. Understanding delta-sigmadata converters. Vol. 74. Piscataway, NJ: IEEE press, 2005。

Claims

1. A buffer amplifier circuit, comprising: A driver, which supplies current to a load depending on the voltage across the variable load; at least one variable current source arranged, in use, to supply current to the variable load; and a control input for receiving control information related to a current demand of the load; The arrangement enables the variable current source to be controlled to vary its output current depending on received control information so that the current from the driver and the variable current source meets the current requirement of the load, wherein at least most of the current requirement of the load is provided by the variable current source.

2. The circuit of claim 1, wherein the driver is an output stage of an operational amplifier.

3. The circuit of claim 1, wherein the driver is separate from the at least one variable current source.

4. The circuit of claim 1, wherein all current requirements of the variable load are provided by the variable current source.

5. The circuit of claim 1, wherein the control input receives digital information related to the current demand of the load.

6. The circuit of claim 1, wherein the control input receives control information related to the magnitude of the load voltage from a direct or indirect measurement of the load current.

7. The circuit of claim 6, wherein the control information is generated using a current mirror.

8. The circuit of claim 7, wherein the control information is a current and sets a bias in the variable current source.

9. The circuit of claim 1 , wherein the at least one variable current source comprises the following subsystems: a first component subsystem, wherein the first component subsystem is coupled between a power source and a critical node to generate a first AC current that flows into the critical node as a result of an unwanted AC signal on the power source; a replicating component subsystem, wherein the replicating component subsystem is coupled to the power source to generate a second AC current that is a ratio replica of the first AC current; A replica bias circuit subsystem, wherein the replica bias circuit is arranged as: setting bias conditions of components within the replicated component subsystem to be equal or identical to bias conditions of components in the first component subsystem and further arranged to couple to an impedance, current source or current sink to set a DC bias; and A current-to-voltage converter subsystem, wherein the current-to-voltage converter subsystem generates: (i) a first signal via a first signal path that reduces the second AC current, wherein the first signal path couples the current-to-voltage converter subsystem to the replica component subsystem; and (ii) a second signal via a second signal path that reduces the first AC current, wherein the second signal couples the current-to-voltage converter subsystem to the first component subsystem.

10. The circuit of claim 9, wherein one or more of the first and second signal paths include a buffer.

11. The circuit of claim 9, wherein one or more of the first and second signal paths include a level shifter, wherein the level shift is provided by a threshold in a transistor device or a battery cap.

12. A shunt current source circuit, comprising at least: a first operational amplifier, a first transistor device, a first impedance, and a second impedance, arranged to generate a first current via a first current source; a second operational amplifier and a second transistor device arranged to generate a second current via a second current source; the second operational amplifier, the second transistor device, the first impedance and the second impedance being arranged to generate the second current via the second current source; and The first current is a multiple of the second current, and the multiple depends on the relative values ​​of the first and second impedances.

13. A current source circuit, comprising: a first component subsystem coupled between a power source and a critical node, generating a first AC current flowing into the critical node as a result of an unwanted AC signal on the power source; a replicating component subsystem coupled to the power source to generate a second AC current that is a ratiometric replica of the first AC current; a replica bias circuit subsystem arranged to set bias conditions of components within the replica component subsystem to be equal or identical to bias conditions of components in the first component subsystem; and A current-to-voltage converter subsystem arranged to produce, in use: i) a first signal via a first signal path that reduces the second AC current, wherein the first signal path couples the current-to-voltage converter subsystem to the replica component subsystem; and ii) a second signal via a second signal path that reduces the first AC current, wherein the second signal couples the current-to-voltage converter subsystem to the first component subsystem.

14. The circuit of claim 13, wherein a control terminal voltage of the first component subsystem is the same as a control terminal voltage of the replica component subsystem.

15. The circuit of claim 13, wherein the first signal path and the second signal path may be different, the same, or partially shared.

16. The circuit of claim 13, wherein the circuit further comprises a level shifter within the first and / or second signal path.

17. The circuit of claim 13, wherein the circuit further comprises a buffer within the first and / or second signal path.

18. The circuit of claim 13, wherein the first component subsystem includes a first control terminal and the replica component subsystem includes a second control terminal, the first control terminal and the second control terminal having substantially the same terminal voltage.

19. A circuit according to claim 13, wherein the source of a transistor device arranged as a voltage follower is coupled to the replica component subsystem, the drain of the transistor device is directly or indirectly coupled to the output of the current-to-voltage converter subsystem, and the gate of the source follower is biased to set the bias conditions of the components within the replica component subsystem to be equal to or identical to the components in the first component subsystem.

20. The circuit of claim 13, wherein the critical node is a source terminal of one or more transistor devices biased as cascodes, wherein the drain terminals of the cascodes provide current to a component within the circuit, such as an operational amplifier.

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