Data transmission system and chip
By adopting a combination solution of fork configuration module and data path module in the data transmission chip, the architecture of the traditional data transmission solution is optimized, and the problem of excessive area and difficulty of timing reset during chip integration is solved, thereby reducing chip manufacturing costs and simplifying timing Reset effect.
Patent Information
- Application Number
- CN202411561428.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-04
- Publication Date
- 2025-02-14
AI Technical Summary
When existing data transmission chips implement multiple fork modes, they lead to increased chip integration difficulty and increased timing reset difficulty, and the chip area is too large, which increases manufacturing cost.
By providing a data transmission system and chip, using a combination scheme of fork configuration modules and data path modules, each channel controls submodule corresponding to a different number of data paths. By optimizing the architecture of the traditional data transmission scheme, the top-level design complexity is saved. Simplify the timing reset step.
It solves the problem of excessive area during chip integration, reduces chip manufacturing costs, simplifies the timing reset steps, and reduces the difficulty of data reset.
Smart Images
Figure CN119442996A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of chip technology, and in particular to a data transmission system and a chip. Background Art
[0002] When a high-speed electronic system needs to run at a higher or lower clock frequency, a data transmission chip, such as a Retimer chip, is usually used to receive and buffer the original clock signal, and then synchronize the clock by adjusting the delay time or multiplication / division to adapt it to different bus rate requirements, thereby solving the problem of clock speed mismatch in the above-mentioned high-speed electronic system.
[0003] In the prior art, taking the Retimer chip as an example, the data transmission chip can support at least 33 bifurcation modes according to the protocol requirements, for example, it can support any one or more of a device with 16 data channels (i.e., X16 device), two devices with 8 data channels (i.e., X8 device), four devices with 4 data channels (i.e., X4 device), and eight devices with 2 data channels (i.e., X2 device). In order to support the above bifurcation modes, the Retimer chip is often equipped with 8 controllers, and the above controllers include a data path module and a control module to achieve data channel conduction, and the area of the data path module under each controller accounts for a large proportion of the controller area. Based on this, when conventional data transmission chips implement multiple bifurcation modes, it will increase the difficulty of chip integration and the difficulty of timing reset in high-speed electronic systems.
[0004] There is an urgent need for a chip architecture that can solve the problem of excessive chip integration area while maintaining the gating solution, thereby reducing chip manufacturing costs. Summary of the invention
[0005] The object of the present invention is to provide a data transmission system and a chip, which can solve the problem of excessive area during chip integration and achieve the effect of reducing chip manufacturing costs.
[0006] The embodiments of the present invention can be implemented as follows:
[0007] In a first aspect, the present invention provides a data transmission system, the data transmission system comprising a bifurcation configuration module and a data path module; the data path module comprises a plurality of data paths, the bifurcation configuration module comprises a plurality of path control submodules; each path control submodule corresponds to a different number of data paths; an output end of each data path is connected to an external device for transmitting a data signal to the external device;
[0008] A fork configuration module, used for receiving configuration information, and sending a first control signal to a corresponding path control submodule according to the total number of data paths to be connected in the configuration information, so as to connect a corresponding number of data paths to obtain a data transmission channel;
[0009] After a first preset time delay, the data path module is used to align the data sending / receiving order of each data path under the data transmission channel to obtain a first data channel; and use the first data channel to process the transmitted data signal to obtain a processed data signal.
[0010] In a possible implementation, the data path module further includes a data processing unit and a channel adjustment unit; the data processing unit is connected to the output end of each data path, and the channel adjustment unit is connected to the control end of each data path;
[0011] Wherein, the data processing unit is used to obtain and process the data signal transmitted by the first data channel;
[0012] The channel adjustment unit is used to send a second control signal to each data channel under the data transmission channel when the fork configuration module sends a first control signal to the corresponding channel control submodule, so as to align the data sending / receiving order of each data channel under the data transmission channel to obtain the first data channel.
[0013] In a second aspect, the present invention further provides a data transmission chip, comprising the data transmission system described in any one of the above-mentioned first aspects.
[0014] The beneficial effects of the present invention include, for example:
[0015] The present invention provides a data transmission system and chip, the data transmission system includes a bifurcation configuration module and a data path module; the data path module includes multiple data paths, the bifurcation configuration module includes multiple path control submodules; each path control submodule corresponds to a different number of data paths. The present invention saves the complexity of top-level design by optimizing the architecture of traditional data transmission solutions, solves the problem of excessive area during chip integration, and achieves the effect of reducing chip manufacturing costs. At the same time, the bifurcation configuration module receives configuration information, and sends a first control signal to the corresponding path control submodule according to the total number of data paths to be turned on in the configuration information, so as to turn on the corresponding number of data paths and obtain a data transmission channel. After a first preset time delay, the data path module aligns the data sending / receiving order of each data path under the data transmission channel to obtain a first data channel; and uses the first data channel to process the transmitted data signal to obtain a processed data signal, so as to simplify the step of timing reset by aligning the data sending / receiving order and reduce the difficulty of data reset. BRIEF DESCRIPTION OF THE DRAWINGS
[0016] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments are briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.
[0017] Figure 1 One of the structural schematic diagrams of a data transmission system provided by the present invention;
[0018] Figure 2 A second structural diagram of a data transmission system provided by the present invention;
[0019] Figure 3 A third structural diagram of a data transmission system provided by the present invention;
[0020] Figure 4 It is one of the structural schematic diagrams of the data path module in the present invention;
[0021] Figure 5 This is one of the structural schematic diagrams of the data processing unit in the present invention;
[0022] Figure 6 This is the second structural diagram of the data processing unit in the present invention;
[0023] Figure 7 The third structural diagram of the data processing unit in the present invention;
[0024] Figure 8 This is the second structural diagram of the data path module in the present invention;
[0025] Fig. 9 This is one of the structural schematic diagrams of the fork configuration module in the present invention;
[0026] Fig.10 is a schematic diagram of the structure of the second data path sequence in the present invention;
[0027] Fig.11 It is a control timing diagram of the data transmission system in the present invention.
[0028] Icons: 100-data transmission system; 101-fork configuration module; 102-data path module; 201-path control submodule; 202-data processing unit; 203-channel adjustment unit; 301-character delimitation subunit; 302-decoding subunit; 303-descrambling subunit; 401-configuration unit; 402-judgment unit. DETAILED DESCRIPTION
[0029] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings here can be arranged and designed in various different configurations.
[0030] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention claimed for protection, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.
[0031] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.
[0032] In the description of the present invention, it should be noted that the terms “first”, “second”, etc., if used, are only used to distinguish the descriptions and cannot be understood as indicating or implying relative importance.
[0033] It should be noted that, in the absence of conflict, the features in the embodiments of the present invention may be combined with each other.
[0034] As described in the background technology, taking the Retimer chip as an example, the existing data transmission chip needs to support multiple modes in actual scenarios. For example, in any mode, the Retimer chip supports up to 16 data channels in working state at the same time, so the existing data transmission chip can realize up to 16 data channels in each mode. Among them, different modes in the existing data transmission chip correspond to different controllers, and then the corresponding number of data channels are turned on separately through the corresponding controller. Multiple controllers will greatly increase the difficulty of chip integration. At the same time, when conventional data transmission chips realize multiple bifurcated modes, there will be nearly 10,000 interactive lines between any controller and other controllers to realize information interaction. At the same time, due to the back-end wiring, the controllers will cross each other, thereby increasing the workload of layout and wiring, and also increasing the difficulty of timing reset in high-speed electronic systems.
[0035] Based on this, the present invention provides a data transmission solution to improve the chip architecture, which can solve the problem of excessive chip integration area while maintaining the gating solution, thereby achieving the effect of reducing chip manufacturing costs.
[0036] Please refer to Figure 1 , Figure 1The schematic diagram of the structure of a data transmission system provided by the present invention is shown. In this embodiment, the data transmission system 100 includes a bifurcation configuration module 101 and a data path module 102. The data path module 102 includes multiple data paths, and the bifurcation configuration module 101 includes multiple path control submodules 201; each path control submodule 201 corresponds to a different number of data paths; the output end of each data path is connected to an external device for transmitting data signals.
[0037] This embodiment does not limit the configuration of the data path, which can be selected arbitrarily and / or determined in sequence. In one possible implementation, assuming that a certain path control submodule among multiple path control submodules corresponds to four data paths, the path control submodule currently corresponding to the four data paths is the X4 path control submodule, and the X4 path control submodule corresponds to four data paths. The above four data paths can be composed of any four data paths in the data path module, and / or three data paths adjacent to a certain data path according to the arrangement order of the data paths. Please refer to Figure 2 , Figure 2 The schematic diagram of the structure of the data transmission system in the present invention is shown. Assuming that the above four data paths are formed according to the arrangement order of the data paths, the data path numbered i=2 and the three data paths adjacent to the data path numbered i=2 are selected to form the four data paths corresponding to the X4 path control submodule. The above data paths include the data path numbered i=1, the data path numbered i=2, the data path numbered i=3 and the data path numbered i=4. Data paths other than the above corresponding numbered data paths, such as the data path numbered i=n (n is an integer), do not participate in the control and adjustment of the X4 path control submodule. In this embodiment, the X4 path control submodule can conduct the corresponding numbered data paths after being enabled.
[0038] In this embodiment, the fork configuration module is used to receive configuration information and send a first control signal to the corresponding path control submodule according to the total number of data paths to be connected in the configuration information, so as to connect the corresponding number of data paths to obtain a data transmission channel.
[0039] After a first preset time delay, the data path module is used to align the data sending / receiving order of each data path under the data transmission channel to obtain a first data channel; and use the first data channel to process the transmitted data signal to obtain a processed data signal.
[0040] Based on this, the present invention saves the complexity of top-level design by optimizing the architecture of traditional data transmission solutions, solves the problem of excessive area during chip integration, and achieves the effect of reducing chip manufacturing costs. At the same time, the fork configuration module and the data path module are used to cooperate to process data signals, that is, the fork configuration module receives configuration information, and sends a first control signal to the corresponding path control submodule according to the total number of data paths to be turned on in the configuration information, so as to turn on the corresponding number of data paths and obtain a data transmission channel. After a first preset time delay, the data path module is used to align the data sending / receiving order of each data path under the data transmission channel, so as to simplify the step of timing reset by aligning the data sending / receiving order and reduce the difficulty of data reset.
[0041] In this embodiment, taking the X4 path control submodule as an example, after the fork configuration module receives the configuration information, if the configuration information shows that the total number of data paths to be turned on is 4, the fork configuration module sends a first control signal to the corresponding path control submodule, i.e., the X4 path control submodule, to turn on the corresponding number of data paths to obtain a data transmission channel, wherein the data transmission channel includes four data paths, and the composition of the above four data paths is not limited and will not be repeated here.
[0042] It should be noted that in this embodiment, each path control submodule under the fork configuration module reuses the data path, that is, the data path numbered i=1 can be called by the X4 path control submodule or the X12 path control submodule (path control submodules corresponding to twelve data paths).
[0043] Please refer to Figure 3 , Figure 3 A structural diagram showing another possible implementation of the data transmission system in this embodiment is shown. Specifically, if 12 data paths need to be turned on at the same time, that is, after the fork configuration module receives the configuration information, the corresponding configuration information shows that the total number of data paths to be turned on is 12, then the fork configuration module sends a first control signal to the corresponding path control submodule, that is, the X12 path control submodule, to turn on the corresponding number of data paths to obtain data transmission channels, wherein the data transmission channels include twelve data paths including a data path numbered i=1, ..., a data path numbered i=11 and a data path numbered i=12.
[0044] It should be noted that whether the corresponding channel under the X4 channel control submodule participates at this time depends on whether the X4 channel control submodule responds to the corresponding control signal, such as a high-level enable signal. If the data transmission system needs to output multiple processed data signals, in one possible implementation, the bifurcation configuration module can send enable signals to different channel control submodules at the same time. At the same time, in order to avoid interference between the processed data signals of each channel, the current data transmission system can set multiple output ports accordingly.
[0045] In this embodiment, in order to optimize the integration of the data transmission system, the fork configuration module can be integrated with a slot, so as to read the slot information (configuration signal) from the outside and directly send an enable signal to the corresponding path control submodule.
[0046] After obtaining the data transmission channel matching the configuration information, after a first preset time delay, the data path module aligns the data sending / receiving order of each data path under the data transmission channel to obtain a first data channel; and uses the first data channel to process the transmitted data signal to obtain a processed data signal.
[0047] In this embodiment, the input end of each data channel under the data path module is connected to the physical layer chip (Port Physical Layer, PHY) so that after receiving the scrambled and encoded data signal transmitted by the PHY chip, the above data signal is processed. In this embodiment, the data processing may include serial-to-parallel conversion, decoding, alignment, and encoding scrambling of the data signal. Among them, since the data transmission system includes multiple data transmission modes, and the data path is reused in each data transmission mode, the data skew of each data path under the data transmission channel can be automatically adjusted by aligning the data transmission / reception order of each data path under the data transmission channel to meet the corresponding protocol requirements, and at the same time, the accuracy of the data transmission system in the process of calling the data channel is guaranteed, and the data is stably transmitted. Taking the Retimer chip as an example, in this embodiment, the data skew is used to characterize the phenomenon that the accuracy of data transmission is reduced due to the inconsistent data transmission / reception order under each data path. The above data skew is usually caused by the following two situations: first, the hardware circuit routing between the root complex (RC) and the channels of the Retimer chip is inconsistent, or the hardware circuit routing between the Retimer chip and the channels of the endpoint (EP) is inconsistent; second, the Retimer chip, the root endpoint, and the endpoints perform serial-to-parallel conversion and parallel-to-serial conversion.
[0048] This embodiment does not limit the way in which the data path module processes the data signal. The data processing method may be any arrangement of serial-to-parallel conversion, decoding, alignment, encoding, scrambling and other processing methods.
[0049] In one possible implementation, please refer to Figure 4 , Figure 4A structural diagram of an implementation of the data path module in this embodiment is shown. The data path module 102 includes a data processing unit 202 and a channel adjustment unit 203. When the data processing unit 202 is connected to the output end of each data path and the channel adjustment unit 203 is connected to the control end of each data path, the data processing unit 202 is used to obtain and process the data signal transmitted by the first data path; the channel adjustment unit 203 is used to send a second control signal to each data path under the data transmission channel when the fork configuration module sends a first control signal to the corresponding channel control submodule, so as to align the data sending / receiving order of each data path under the data transmission channel to obtain the first data channel.
[0050] In this embodiment, the alignment process may be preferentially performed, that is, when the bifurcation configuration module sends the first control signal to the corresponding path control submodule, the channel adjustment unit simultaneously sends the second control signal to each data path under the data transmission channel to align the data transmission / reception order of each data path under the data transmission channel. If this embodiment includes a total of sixteen data paths, the channel adjustment unit will send the second control signal to the sixteen data paths at the same time as the bifurcation configuration module sends the first control signal to the corresponding path control submodule to align the data transmission / reception order of the sixteen data paths. In a possible implementation, the channel adjustment unit aligns each data path by removing the data skew between each data path under the data transmission channel.
[0051] After calibrating the data transmission / reception order of each data channel, the acquired data signal can be processed by the data processing unit such as serial-to-parallel conversion, decoding, encoding and scrambling.
[0052] In one possible implementation, please refer to Figure 5 , Figure 5 A structural diagram of an implementation of the data processing unit in this embodiment is shown. The data processing unit 202 includes a character delimiter subunit 301 and a decoding subunit 302. The input end of the character delimiter subunit 301 is connected to the output end of each data path; the output end of the character delimiter subunit 301 is connected to the input end of the decoding subunit 302.
[0053] The character delimiting subunit 301 is used for parallel processing of data signals output by each data path under the first data channel to convert the data signals into parallel data. The decoding subunit 302 is used for decoding the parallel data to obtain valid data.
[0054] In this embodiment, the data transmitted by the PHY chip is usually serial data. To adapt to different transmission modes, the serial data needs to be preprocessed first, for example, the serial data is converted into parallel data, so that the data path module can perform data descrambling and decoding operations. After obtaining the corresponding parallel data, the decoding subunit decodes the parallel data to obtain valid data.
[0055] In another possible implementation, please refer to Figure 6 , Figure 6 A structural diagram of an implementation of the data processing unit in this embodiment is shown. The data processing unit 202 includes a character delimiter subunit 301 and multiple decoding subunits 302. The character delimiter subunit includes multiple data input ports and multiple data output ports. Each data input port is connected to the output end of a data path, and each data output port is connected to the input end of a decoding subunit, so as to process the serial data output by each data path, ensure the data isolation between the data paths, and avoid interference between the data paths.
[0056] In this embodiment, to further identify valid data, please refer to Figure 7 , Figure 7 Another implementation structure diagram of the data processing unit in this embodiment is shown, the data processing unit 202 further includes a descrambling subunit 303, and the descrambling subunit 303 is connected to the output end of the decoding subunit 302. The descrambling subunit 303 is used to descramble the valid data to convert the valid data into a recognizable data code stream.
[0057] exist Figure 7 Based on Figure 8 , Figure 8 Another implementation structure diagram of the data path module in this embodiment is shown. Different from the previous embodiment, if the alignment process is not performed preferentially, in order to ensure that each data transmission channel receives a data-aligned and identifiable data code stream, the channel adjustment unit 203 can be set at the output end of the descrambling sub-unit 303. At this time, the channel adjustment unit 203 can be used to directly adjust the skew time of the data code stream, so that the data transmission system can meet the protocol requirements when transmitting the code stream to the subsequent device or module, and at the same time improve the accuracy of the judgment unit in the following fork configuration module in determining the path condition.
[0058] In this embodiment, the bifurcation configuration module can also be used to determine the path conditions, and when it is determined that the path conditions are not met, timely adjust the corresponding data path to improve the efficiency and stability of data transmission. In this embodiment, the manner in which the bifurcation configuration module improves the efficiency and stability of data transmission is not limited.
[0059] In one possible implementation, please refer to Fig. 9 , Fig. 9A structural diagram of an implementation of the fork configuration module in this embodiment is shown, and the fork configuration module 101 also includes a configuration unit 401 and a judgment unit 402; the configuration unit 401 is connected to the control end of each data path; the decoding subunit 302 is connected to the judgment unit 402; when the valid data includes a first data set, the first data set is used to represent the set of parameters of each data path under the first data channel, that is, the data channel currently actually participating in the transmission.
[0060] Among them, the configuration unit 401 is used to configure the own parameters of each data path; and when the fork configuration module sends a first control signal to the corresponding path control submodule and obtains the data transmission channel, it sends a second data set to the judgment unit, and the second data set is used to characterize the set of the own parameters of each data path under the data transmission channel, that is, the data channel that theoretically needs to participate in the transmission configured by the fork configuration module.
[0061] The decoding subunit 302 is configured to send the first data set to the determination unit.
[0062] The judgment unit 402 is used to determine whether there are unconnected data channels according to the arrangement relationship between the parameters in the first data set and the second data set; if there are, a third control signal is sent to the path control submodules other than the corresponding path control submodules to connect the corresponding number of data channels; wherein the number of data channels corresponding to the path control submodules other than the corresponding path control submodule is consistent with the total number of data channels to be connected.
[0063] According to the previous embodiment, when the own parameter includes the data path number, the determination unit 402 is further used to determine the first data path number sequence and / or number according to the first data set; and determine the second data path number sequence and / or number according to the second data set.
[0064] The judging unit 402 is further configured to judge whether the arrangement sequence of the first data path number and the second data path number is consistent, and if not, to send a third control signal to the path control submodules except the corresponding path control submodule.
[0065] And / or the judging unit 402 is further configured to judge whether the number of the first data path number is consistent with the number of the second data path number, and if not, send a third control signal to the path control submodules other than the corresponding path control submodule.
[0066] In this embodiment, if the number of data channels currently actually participating in the transmission is different from the number of data channels theoretically required to participate in the transmission, the following situations may be included: First, the number between the first data path number and the second data path number is different; for example, theoretically 4 data channels are required to participate in the transmission, but in fact only 2 data channels participate in the transmission. Second, the order between the first data path number and the second data path number is different; for example, theoretically 4 data channels are required to participate in the transmission, and the order is from the data path number i=1 to the data path number i=4, and in fact there are 4 data channels participating in the transmission, but the monitored data path numbers are: data path number i=1, data path number i=4, data path number i=5, and data path number i=7. The above situations all belong to the situation where there are data channels that are not conducting, and it is necessary to send a third control signal to readjust the corresponding number of data channels to achieve accurate data transmission.
[0067] At this time, if the data path numbers between the data transmission channels are arranged in sequence, and the first control signal sequentially turns on a corresponding number of data transmission channels in the arrangement order to form a first data path sequence, if the arrangement order and / or the number of numbers between the first data path numbers and the second data path numbers are inconsistent, the fork configuration module is further used to use the third control signal to sequentially turn on a corresponding number of data paths according to the arrangement order with the data number adjacent to the end data number in the first data path sequence as the starting number to form a second data path sequence.
[0068] exist Figure 2 Based on Fig.10 , Fig.10 A possible combination of a second data path sequence in this embodiment is shown. Taking the X4 path control submodule as an example, it is assumed that the four data paths corresponding to the X4 path control submodule are a data path numbered i=1, a data path numbered i=2, a data path numbered i=3, and a data path numbered i=4; if the determination unit determines that the number of the first data path number and the second data path number are inconsistent and / or the arrangement order of the first data path number and the second data path number are inconsistent, the fork configuration module uses the third control signal according to the arrangement order, with the data path numbered i=5 adjacent to the data path numbered i=4 as the starting number, and sequentially turns on the corresponding number of data paths, that is, turns on the data path numbered i=5, the data path numbered i=6, the data path numbered i=7, and the data path numbered i=8, to form a second data path sequence.
[0069] In this embodiment, after determining that the corresponding data channel is turned on according to the control signal, the data channel module can also implement data interaction with the corresponding channel control submodule according to a preset time node to ensure the integrity of data transmission.
[0070] In a possible implementation, after the second preset time delay, the data path module is further used to send a first instruction to the corresponding path control submodule to instruct the data transmission channel to complete data processing; wherein the end time of the first preset time delay is less than the start time of the second preset time delay. After receiving the first instruction, the corresponding path control submodule sends a second instruction to the data path module to instruct the data path module to output the processed data signal to the external device through the first data channel.
[0071] It should be noted that, in this embodiment, the specific ranges of the first preset time delay and the second preset time delay are not limited, and it is sufficient that the end time of the first preset time delay is less than the start time of the second preset time delay.
[0072] Please refer to Fig.11 , Fig.11 The interactive timing diagram corresponding to the data transmission system in this embodiment is shown. Assuming that two data channels need to be turned on at present, that is, a first control signal x2_en (high level - enable signal) is sent to the corresponding X2 channel control submodule, after a first preset time delay t1, the data channel module starts to work, and uses the data channel numbered i=1 and the data channel numbered i=2 to process the input data signal data_in[n*2-1:0] (n is the number of valid bits processed by a single channel in each clock cycle), after a second preset time delay t2, the data channel module sends a first instruction state_en_2 (1 bit) (high level - enable signal) to the corresponding X2 channel control submodule to indicate that the data transmission channel completes data processing, and then after a third preset time delay t3, the X2 channel control submodule outputs a signal data_control_2 (1 bit) (high level - enable signal) to instruct the data channel module to output the processed data signal to the external device through the first data channel.
[0073] In this embodiment, after a fourth preset time delay t4, the data path module starts to output the processed data signal to the external device through the first data channel.
[0074] In summary, the present invention provides a data transmission system including a forked configuration module and a data path module; the data path module includes multiple data paths, and the forked configuration module includes multiple path control submodules; each path control submodule corresponds to a different number of data paths. The present invention saves the complexity of the top-level design by optimizing the architecture of the traditional data transmission scheme, solves the problem of excessive area during chip integration, and achieves the effect of reducing chip manufacturing costs. At the same time, the forked configuration module receives configuration information, and sends a first control signal to the corresponding path control submodule according to the total number of data paths to be turned on in the configuration information, so as to turn on the corresponding number of data paths and obtain a data transmission channel. After a first preset time delay, the data path module aligns the data sending / receiving order of each data path under the data transmission channel to obtain a first data channel; and uses the first data channel to process the transmitted data signal to obtain a processed data signal, so as to simplify the step of timing reset by aligning the data sending / receiving order and reduce the difficulty of data reset.
[0075] With the same concept as the previous embodiment, the present invention also provides a data transmission chip, which includes all the technical means and technical effects of the data transmission system in the above embodiment. That is, by optimizing the architecture of the traditional data transmission solution, the complexity of the top-level design is saved, the problem of excessive area during chip integration is solved, and the effect of reducing chip manufacturing costs is achieved. At the same time, the use of bifurcated configuration and data path module simplifies the steps of timing reset and reduces the difficulty of data reset.
[0076] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.
Claims
1. A data transmission system, characterized in that: The data transmission system includes a bifurcation configuration module and a data path module; the data path module includes multiple data paths, and the bifurcation configuration module includes multiple path control submodules; Each of the channel control submodules corresponds to a different number of data channels; an output end of each of the data channels is connected to an external device for transmitting data signals; The fork configuration module is used to receive configuration information, and send a first control signal to the corresponding path control submodule according to the total number of data paths to be connected in the configuration information, so as to connect the corresponding number of data paths to obtain a data transmission channel; After a first preset time delay, the data path module is used to align the data sending / receiving order of each data path under the data transmission channel to obtain a first data channel; and use the first data channel to process the transmitted data signal to obtain a processed data signal.
2. The data transmission system according to claim 1, characterized in that: After the second preset time delay, the data path module is further used to send a first instruction to the corresponding path control submodule to instruct the data transmission channel to complete data processing; wherein the end time of the first preset time delay is less than the start time of the second preset time delay; The corresponding path control submodule is further used to send a second instruction to the data path module to instruct the data path module to output the processed data signal to the external device through each data path under the first data channel.
3. The data transmission system according to claim 1, characterized in that: The data path module further comprises a data processing unit and a channel adjustment unit; the data processing unit is connected to the output end of each data path, and the channel adjustment unit is connected to the control end of each data path; Wherein, the data processing unit is used to obtain and process the data signals transmitted by each data path under the first data channel; The channel adjustment unit is used to send a second control signal to each data channel under the data transmission channel when the fork configuration module sends a first control signal to the corresponding channel control submodule, so as to align the data sending / receiving order of each data channel under the data transmission channel to obtain the first data channel.
4. The data transmission system according to claim 3, characterized in that: The data processing unit comprises a character delimiting subunit and a decoding subunit; the input end of the character delimiting subunit is connected to the output end of each of the data paths; the output end of the character delimiting subunit is connected to the input end of the decoding subunit; The character delimiting subunit is used for processing in parallel the data signals output by each data path under the first data channel to convert the data signals into parallel data; The decoding subunit is used to decode the parallel data to obtain valid data.
5. The data transmission system according to claim 4, characterized in that: The data processing unit further comprises a descrambling subunit, wherein the descrambling subunit is connected to an output end of the decoding subunit; The descrambling subunit is used to perform data descrambling on the valid data to convert the valid data into a recognizable data code stream.
6. The data transmission system according to claim 5, characterized in that: The bifurcation configuration module further includes a configuration unit and a judgment unit; the configuration unit is connected to the control end of each data path; the decoding subunit is connected to the judgment unit; the valid data includes a first data set, and the first data set is used to represent the set of parameters of each data path under the first data channel; The configuration unit is used to configure the parameters of each data path; and when the fork configuration module sends a first control signal to the corresponding path control submodule to obtain the first data path, the second data set is sent to the judgment unit, and the second data set is used to represent the set of parameters of each data path under the data transmission channel; The decoding subunit is further configured to send the first data set to the determination unit; The determination unit is further configured to determine whether there is a disconnected data channel according to an arrangement relationship between the parameters in the first data set and the second data set; If so, a third control signal is sent to the path control submodules other than the corresponding path control submodule to turn on the corresponding number of data paths; wherein the number of data paths corresponding to the path control submodules other than the corresponding path control submodule is consistent with the total number of data paths to be turned on.
7. The data transmission system according to claim 6, characterized in that: When the self parameter includes a data path number, the determination unit is further configured to determine a sequence and / or number of first data path numbers according to the first data set; The determination unit is further used to determine the sequence and / or number of second data path numbers for the second data set; The judging unit is further configured to judge whether the arrangement order of the first data path number and the second data path number is consistent, and if not, to send a third control signal to the path control submodule other than the corresponding path control submodule; And / or the judging unit is further configured to judge whether the number of the first data path number is consistent with the number of the second data path number, and if not, send a third control signal to the path control submodule other than the corresponding path control submodule.
8. The data transmission system according to claim 7, characterized in that: When the data path numbers between the data transmission channels are arranged in sequence, and the first control signal sequentially turns on the corresponding number of data transmission channels according to the arrangement order to form a first data path sequence, If the arrangement order and / or the number of the first data path numbers and the second data path numbers are inconsistent, the fork configuration module is further used to use the third control signal to sequentially turn on a corresponding number of data paths according to the arrangement order, taking the data number adjacent to the end data number in the first data path sequence as the starting number, to form a second data path sequence.
9. The data transmission system according to claim 3, characterized in that: The channel adjustment unit is used to remove the skew between the data paths under the data transmission channel to keep the data sending / receiving order between the data paths consistent.
10. A data transmission chip, characterized in that: A data transmission system comprising any one of claims 1 to 9.