Method, device and equipment for adjusting design layout, medium and product

Abstract

The invention discloses a method, device and equipment for adjusting a design layout, a medium and a product, and is applied to the technical field of photoetching. The method comprises the following steps: firstly, performing clustering operation according to the distribution density of each dead pixel in an overall dead pixel information database on an original design layout, and dividing each dead pixel into a plurality of local design layouts; and then, adjusting the local design layout to obtain a target local design layout, and obtaining a final target design layout. According to the scheme provided by the embodiment of the invention, the clustering operation is carried out through the distribution density of each dead pixel on the original design layout, the local design layout where the dead pixels are located can be quickly determined, then the graph at the corresponding position is modified, and the consumed time is less. And only the local design layout needs to be adjusted, so that compared with the overall adjustment of the whole design layout, the scheme consumes less computing resources and computing time, and the actual production requirements can be met.

Description

Technical Field

[0001] The present application belongs to the field of photolithography technology, and in particular, relates to a method, device, equipment, medium and product for adjusting a design layout. Background Art

[0002] With the further reduction in the size of advanced semiconductor nodes and the increasing complexity of processes, the concept of circuit design and process co-optimization (design technology co-optimization, DTCO) came into being. The core idea is to connect the two relatively separated technical sectors of design and manufacturing, and feed back the bad pixel information on the manufacturing side to the design side for collaborative optimization. On the manufacturing side, the mask layout output by the optical proximity effect correction may not give the expected imaging results, resulting in bad pixels and affecting the final chip yield. At this time, the problem may not be solved on the manufacturing side, and the design layout needs to be adjusted on the design side to eliminate the bad pixels.

[0003] In the traditional solution, the design side adjusts the entire design layout based on the bad pixel information fed back by the manufacturing side. However, this method requires processing too much information, consumes a lot of computing resources and time, and cannot meet actual production needs. Summary of the invention

[0004] The embodiments of the present application provide a method, device, equipment, medium and product for adjusting a design layout, which can quickly and accurately adjust the design layout to eliminate bad pixels, thereby saving computing resources and time.

[0005] On the one hand, an embodiment of the present application provides a method for adjusting a design layout, comprising:

[0006] Perform photolithography simulation based on the original design layout to determine the corresponding overall bad pixel information database;

[0007] Performing a clustering operation according to the distribution density of each bad pixel in the overall bad pixel information database on the original design layout, and dividing each bad pixel into a plurality of local design layouts;

[0008] Determine a local bad pixel information database corresponding to the local design layout;

[0009] Based on the local bad pixel information database, adjusting the local design layout to eliminate each bad pixel in the local bad pixel information database to obtain a target local design layout;

[0010] The target partial design layout is merged with an unprocessed area of ​​the original design layout except the partial design layout to obtain a target design layout.

[0011] On the other hand, the lithography simulation is performed based on the original design layout to determine the corresponding overall bad pixel information database, including:

[0012] Perform photolithography simulation based on the original design layout to determine the initial overall bad pixel information database;

[0013] Selecting a target bad pixel from the initial overall bad pixel information database; the target bad pixel is a bad pixel that can be eliminated by modifying the line width;

[0014] Each of the target bad pixels is determined as the overall bad pixel information database.

[0015] On the other hand, the lithography simulation is performed based on the original design layout to determine the initial overall bad pixel information database, including:

[0016] Based on a photolithography simulation tool, the original design layout is simulated to obtain overall photoresist development profile information;

[0017] A photolithography rule check is performed on the overall photoresist development profile information to obtain the initial overall bad pixel information database.

[0018] On the other hand, the determining of the local bad pixel information database corresponding to the local design layout includes:

[0019] Based on a photolithography simulation tool, the local design layout is simulated to obtain local photoresist development profile information;

[0020] A photolithography rule check is performed on the local photoresist development profile information to obtain the local bad pixel information database.

[0021] On the other hand, adjusting the local design layout based on the local bad pixel information database to eliminate each bad pixel in the local bad pixel information database to obtain a target local design layout includes:

[0022] Determine the target edge line of the bad point to be eliminated in the local design layout;

[0023] Determine the bad pixel category of the bad pixel to be eliminated;

[0024] Based on the bad pixel category of the bad pixel to be eliminated, the target edge line is moved to obtain the target local design layout.

[0025] On the other hand, the step of moving the target edge line based on the bad pixel category of the bad pixel to be eliminated to obtain the target local design layout includes:

[0026] Obtaining a bad pixel size value and an expected value of the bad pixel to be eliminated; the bad pixel size value is the distance between two side lines that cause the bad pixel, and when the distance between the two side lines that cause the bad pixel is the expected value, the bad pixel to be eliminated is eliminated;

[0027] Determine the difference between the bad pixel size value and the expected value;

[0028] Based on the bad point category of the bad point to be eliminated, the target edge line is moved by the difference to obtain a first revised layout;

[0029] Determining whether the first revised layout satisfies an iteration stop condition;

[0030] When the first revised layout does not meet the iteration stop condition, the target edge is moved by a preset step length to obtain a second revised layout;

[0031] The second revised layout is determined as a new first revised layout, and the step of determining whether the first revised layout satisfies the iteration stop condition is returned until the first revised layout satisfies the iteration stop condition; the iteration stop condition includes that the bad point to be eliminated is eliminated or the layout design rule restricts the continued movement of the target edge line.

[0032] On the other hand, after merging the target partial design layout with the unprocessed area of ​​the original design layout except the partial design layout to obtain the target design layout, the method further includes:

[0033] Determine the moving direction and moving distance of the target edge line;

[0034] The target design layout is adjusted based on the overall bad pixel information database, the moving direction and the moving distance of the target edge line.

[0035] In another aspect, an embodiment of the present application provides a device for adjusting a design layout, comprising: a processor and a memory storing computer program instructions;

[0036] When the processor executes the computer program instructions, the method for adjusting the design layout as described above is implemented.

[0037] On the other hand, an embodiment of the present application provides a computer-readable storage medium, on which computer program instructions are stored. When the computer program instructions are executed by a processor, the method for adjusting the design layout as described above is implemented.

[0038] On the other hand, an embodiment of the present application provides a computer program product. When instructions in the computer program product are executed by a processor of an electronic device, the electronic device executes the method for adjusting the design layout as described above.

[0039] A method for adjusting a design layout provided in an embodiment of the present application first performs a clustering operation based on the distribution density of each bad point in the overall bad point information database on the original design layout, and divides each bad point into multiple local design layouts. Then, the local design layout is adjusted to obtain a target local design layout, and a final target design layout is obtained. The scheme proposed in the embodiment of the present application performs a clustering operation based on the distribution density of each bad point on the original design layout, and can quickly determine the local design layout where the bad point is located, and then modify the graphics at the corresponding position, which is less time-consuming. And because only the local design layout needs to be adjusted, compared with the overall adjustment of the entire design layout, this scheme consumes less computing resources and computing time, thereby being able to meet actual production needs. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the technical solution of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0041] Figure 1 A schematic diagram of a flow chart of a method for adjusting a design layout provided by an embodiment of the present application is shown;

[0042] Figure 2 A schematic diagram of a process of graphics merging provided by an embodiment of the present application is shown;

[0043] Figure 3 A complete schematic diagram of the process of adjusting the design layout provided by an embodiment of the present application is shown;

[0044] Figure 4(a) shows the graph corresponding to the bad pixels of the pinch category;

[0045] Figure 4(b) shows the graph corresponding to the bad pixel of the bridge category;

[0046] Figure 5 A schematic diagram of a process for adjusting the line width of a graphic provided by an embodiment of the present application is shown;

[0047] Figure 6 A schematic diagram of the structure of a device for adjusting a design layout provided in an embodiment of the present application is shown;

[0048] Figure 7 A schematic diagram of the hardware structure of a device for adjusting a design layout provided in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0049] The features and exemplary embodiments of various aspects of the present application will be described in detail below. In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain the present application, rather than to limit the present application. For those skilled in the art, the present application can be implemented without the need for some of these specific details. The following description of the embodiments is only to provide a better understanding of the present application by illustrating the examples of the present application.

[0050] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the statement "include..." does not exclude the presence of other identical elements in the process, method, article or device including the element.

[0051] In order to solve the problems of the traditional solution, the embodiment of the present application provides a method, device, equipment, medium and product for adjusting the design layout. The method for adjusting the design layout provided by the embodiment of the present application is first introduced below. Figure 1 FIG. 1 is a flow chart showing a method for adjusting a design layout provided by an embodiment of the present application. Figure 1 As shown, the method includes the following steps: S101 to S105.

[0052] S101: Performing lithography simulation based on the original design layout to determine a corresponding overall bad pixel information database.

[0053] First, we need to obtain the initial overall bad pixel information database (N0) of the original design layout. We clearly define a layer of design layout that has been signed off as the processing object, and use the lithography simulation tool to simulate the design layout to obtain the photoresist development contour information. Then, we use the Litho Rule Check (LRC) tool to set the bad pixel detection category and bad pixel definition range to detect the simulated photoresist development contour, and obtain the initial overall bad pixel information database (N0), including the x / y coordinates of the bad pixel, the category to which the bad pixel belongs, the size of the bad pixel (unit: nm), etc. The categories to which the bad pixel belongs are mainly pinch, bridge, contact size, etc., which can be expanded according to needs.

[0054] After obtaining the initial overall bad pixel information database (N0), the design tool is then used to filter the initial overall bad pixel information database (N0) according to the design rules check (DRC) tool, and the bad pixel positions that cannot be optimized by modifying the line width to avoid invalid optimization are screened out, and a new overall bad pixel information database (N1) is obtained. Only the target bad pixels are retained in the overall bad pixel information database (N1), and the target bad pixels are bad pixels that can be eliminated by modifying the line width.

[0055] S102: performing a clustering operation according to the distribution density of each bad pixel in the overall bad pixel information database on the original design layout, and dividing each bad pixel into a plurality of local design layouts.

[0056] In the embodiment of the present application, based on the bad pixel density corresponding to each bad pixel in the overall bad pixel information database on the original design layout, a clustering operation is performed on each bad pixel in the overall bad pixel information database to determine multiple local design layouts. By optimizing multiple local design layouts separately, the optimization of the entire design layout can be quickly completed.

[0057] The bad pixels in the overall bad pixel information database (N1) are clustered using a clustering algorithm. The clustering algorithm divides the bad pixel density reflected by the location of the bad pixels on the entire design layout, and uses boxes to frame these bad pixels, so that multiple boxes (i.e., local design layouts) can be obtained. Here, the corresponding clustering algorithm can be used according to actual needs to obtain the local design layout.

[0058] S103: Determine a local bad pixel information database corresponding to the local design layout.

[0059] In order to adjust the local design layout, it is necessary to first determine the local bad pixel information database corresponding to the local design layout. It should be noted that the information of the overall bad pixel information database (N1) in the previous step can be directly reused here, or the local design layout in the box can be re-simulated to obtain the contour and perform LRC inspection to obtain the local bad pixel information database, because there may be errors in the overall and local bad pixel calculations, and recalculation can eliminate this error.

[0060] In the above overall and local calculations, a suitable simulation lithography tool can be selected according to the needs to obtain the lithography development contour, such as the traditional optical proximity correction (OPC) method or the artificial intelligence-based lithography feedback tool method.

[0061] S104: Based on the local bad pixel information database, the local design layout is adjusted to eliminate each bad pixel in the local bad pixel information database to obtain a target local design layout.

[0062] Each bad pixel has two corresponding values, namely the bad pixel size value defect size (that is, the distance between the two edges that cause the bad pixel) and the expected value spec of the bad pixel definition range (if the distance between the two edges that cause the bad pixel exceeds this value, it is not a bad pixel).

[0063] This step optimizes the predicted bad pixels as a whole. Subtract the defect size corresponding to the bad pixel to be eliminated from the expected value spec to get the difference, and then move the edge corresponding to the bad pixel's location according to the bad pixel's category, and the moving distance is the difference. Because the distance of the edge movement of the graphic and the corresponding contour movement are not necessarily equal, some bad pixels need to set a step size (step), and check once for each step, and repeat the iteration until the bad pixel is resolved or cannot be moved due to the influence of design rules.

[0064] It should be noted that the adjustment methods corresponding to different categories of bad pixels are different, because the bad pixels targeted by this application are bad pixels that can optimize the design layout by modifying the line width. The bad pixel categories include pinch and bridge, etc. The two sides that cause the bad pixels are the target side lines. The target side lines can be moved according to the corresponding category (that is, the corresponding line width is changed).

[0065] S105: merging the target partial design layout with the unprocessed area of ​​the original design layout except the partial design layout to obtain the target design layout.

[0066] Finally, the target local design layout (i.e., the optimized graphics within the box) is obtained, and the optimized graphics within the box and the unoptimized graphics outside the box are merged to obtain the required target design layout.

[0067] Figure 2 FIG. 1 shows a schematic diagram of a process of merging graphics provided by an embodiment of the present application; Figure 2 As shown, it includes an original design layout 201, a local design layout 202, a target local design layout 203, an unprocessed area 204, and a target design layout 205. The bad pixels in the overall bad pixel information database are clustered to determine the local design layout 202 and the unprocessed area 204 in the original design layout 201. Then, based on the local bad pixel information database, the local design layout 202 is adjusted to obtain the target local design layout 203. Finally, the target local design layout 203 is merged with the unprocessed area 204 in the original design layout except the local design layout to obtain the target design layout 205.

[0068] Figure 3 FIG. 1 shows a complete schematic diagram of the process of adjusting the design layout provided by an embodiment of the present application; Figure 3 As shown, the following steps are included: S301 to S309.

[0069] S301: Obtain the original design layout D0.

[0070] S302: Perform simulation based on the original design layout D0 to obtain photoresist development profile information, and obtain an initial overall bad pixel information database N0 based on photolithography rule detection.

[0071] S303: Filtering by design tools to obtain an overall bad pixel information database N1.

[0072] S304: performing clustering processing on the entire bad pixel information database N1 to obtain multiple boxes.

[0073] S305: Optimize the graphics in each box respectively.

[0074] S306: Merge the optimized graphics within the box with the unprocessed graphics outside the box to obtain a target design layout.

[0075] S307: Compare the original design layout D0 and the target design layout D1 to obtain optimization information, and save the target design layout D1 as a text file.

[0076] S308: Further optimize the design layout based on the optimization information and the text file.

[0077] S309: Output the final design layout.

[0078] Because the above optimization is only for the graphic line width, the effect is limited. Therefore, the entire optimization processing information can also be summarized and transmitted to the design optimization tool for the final optimization of the design layout. First, the original design layout is compared with the optimized target design layout obtained in the above steps, and the optimized graphic processing information is saved as a guide text file, including the information in the initial overall bad pixel information database N0, that is, the x / y coordinates of the bad pixel, the category of the bad pixel, the size of the bad pixel, etc., as well as the optimization information, that is, the direction and distance of the optimized target edge line movement. Then the obtained guide file is transferred to the design optimization tool. Since the optimization of the above steps mainly considers the line width and graphic spacing in the DRC, the effect is limited, so the design layout still needs the design optimization tool on the design side to further complete the modification and optimization, and optimize the design layout according to the more comprehensive DRC and other physical design constraints combined with the guide file information, and finally obtain the final design layout.

[0079] It can be seen that the scheme proposed in the embodiment of the present application first needs to clarify a layer of the original design layout after signoff, use the lithography simulation model to simulate the original design layout, and use the LRC tool to predict the bad points of the simulated photoresist development profile of the full design layout after obtaining the simulated photoresist development profile, and use the design tool to filter out the bad points in the unchangeable area according to the DRC. Then, for the bad points of the full layout, the local graphics are iteratively optimized according to their location and the category to which they belong. Finally, the entire optimized design layout is compared with the initial design layout to obtain information such as the optimized processing position and processing method, and it is converted into guide information and saved in a text file format, and then transmitted to the design tool. The design tool then judges the information in the guide file according to the DRC rules, and finally the design tool completes the optimization of the design layout, thereby achieving an overall decrease in the number of predicted bad points in the full design layout and improving the manufacturing yield.

[0080] This solution extends the local mask repair in the traditional way to the local design layout fine-tuning, and uses a progressive strategy to feed back the bad pixel information and repair method to the design end, so that the design end can further solve the lithography bad pixels and improve the yield while ensuring the DRC rules. The clustering algorithm generates a box, iteratively modifies and optimizes the graphics within the local box, and only processes the line width and graphic distance of the local graphics, which can save a lot of computing resources and time.

[0081] The design side and the manufacturing side are two relatively separate technical divisions, usually completed by two companies with different divisions of labor. In addition, the chip industry has high information confidentiality, and the information exchange between the two is limited and inefficient. With the evolution of technology nodes, the process itself has become more and more complex, and the information barriers between the design side and the manufacturing side have become higher and higher. Currently, there is no product that combines information feedback from the process manufacturing side with local design optimization tools, resulting in new products being repeatedly iterated during the process end tape-out. The semiconductor industry takes a long time for new products to be introduced into the tape-out and finally pass the yield. Therefore, if the design side can obtain more and more comprehensive process information, and through the technical architecture to automatically feedback information to each other for collaborative optimization, this process can be greatly simplified and accelerated, thereby improving the yield and reducing costs.

[0082] In the embodiment of the present application, a comprehensive tool is provided that combines an integrated process information feedback tool with a design optimization tool. The process feedback information can be combined with the design optimization tool to perform targeted local optimization of the layout design, so that the technologies of the two partitions can automatically complete collaborative optimization. By combining process information and design information, the two relatively separated technical partitions of the design end and the process manufacturing end are connected. And through technology, both sides can automatically complete the optimization through the program, which greatly reduces the labor cost and the barriers to the use of technology.

[0083] This method provides a new exploration direction for DTCO in the field of computational lithography, accelerating the interaction of process information and design information throughout the entire chain from design to manufacturing, forming a synchronous optimization mode with mutual feedback, overcoming the bottleneck of the lithography process, and ultimately achieving the goal of improving yield and reliability.

[0084] A method for adjusting a design layout provided in an embodiment of the present application first performs a clustering operation based on the distribution density of each bad point in the overall bad point information database on the original design layout, and divides each bad point into multiple local design layouts. Then, the local design layout is adjusted to obtain a target local design layout, and a final target design layout is obtained. The scheme proposed in the embodiment of the present application performs a clustering operation based on the distribution density of each bad point on the original design layout, and can quickly determine the local design layout where the bad point is located, and then modify the graphics at the corresponding position, which is less time-consuming. And because only the local design layout needs to be adjusted, compared with the overall adjustment of the entire design layout, this scheme consumes less computing resources and computing time, thereby being able to meet actual production needs.

[0085] In the above embodiments, it is mentioned that it is necessary to perform lithography simulation based on the original design layout to determine the corresponding overall bad pixel information database. However, in actual applications, in the initial overall bad pixel information database determined by performing lithography simulation based on the original design layout, there are some bad pixels that can be eliminated by modifying the line width wirelessly, so it is necessary to filter out such bad pixels and only retain the target bad pixels. That is, select the target bad pixels in the initial overall bad pixel information database, and the target bad pixels are the bad pixels that can be eliminated by modifying the line width. Then determine each target bad pixel as the overall bad pixel information database.

[0086] The embodiment of the present application only processes the distance between the edge lines of a local graphic, and meets the optimization requirements of the design end by modifying the graphic line width, thereby avoiding invalid optimization adjustments to the remaining bad points, saving computing resources and time.

[0087] In practical applications, a corresponding solution can be selected according to actual needs to determine the initial overall bad pixel information database. The embodiment of the present application provides a specific implementation solution, which performs lithography simulation based on the original design layout to determine the initial overall bad pixel information database, including:

[0088] Based on the photolithography simulation tool, the original design layout is simulated to obtain the overall photoresist development profile information; the overall photoresist development profile information is checked for photolithography rules to obtain an initial overall bad pixel information database.

[0089] The embodiment of the present application obtains the resist development profile information through simulation, and then performs a lithography rule check, so as to efficiently determine the bad pixel information database.

[0090] In the above embodiment, it is mentioned that when determining the local bad pixel information database, if the information of the overall bad pixel information database (N1) in the above step is directly reused, errors may occur. Therefore, in the embodiment of the present application, the reuse method is not adopted, but the local bad pixel information database corresponding to the local design layout is re-determined. Specifically, the local design layout is simulated based on the lithography simulation tool to obtain the local photoresist development profile information; then the local photoresist development profile information is subjected to the lithography rule check to obtain the local bad pixel information database.

[0091] After determining a local design layout with bad pixels, this embodiment redefines the local bad pixel information database for the local design layout instead of reusing information in the overall bad pixel information database, thereby avoiding errors caused by using information in the overall bad pixel information database.

[0092] In the above embodiments, it is mentioned that different types of bad pixels correspond to different adjustment methods. This embodiment provides a specific solution, which adjusts the local design layout based on the local bad pixel information database to eliminate the bad pixels in the local bad pixel information database and obtain the target local design layout, including:

[0093] First, a target edge line of the bad point to be eliminated in the local design layout is determined, then the bad point category of the bad point to be eliminated is determined, and finally, based on the bad point category of the bad point to be eliminated, the target edge line is moved to obtain a target local design layout.

[0094] Figure 4(a) shows the graphics corresponding to the bad pixels of the pinch category; as shown in Figure 4(a), for pinch, there is a risk of disconnection due to necking, and the line width needs to be increased and moved to the space on both sides of the graphic (i.e., the distance between the graphics). Figure 4(b) shows the graphics corresponding to the bad pixels of the bridge category; as shown in Figure 4(b), bridge is caused by insufficient space, and there is a risk of adhesion between the two graphics, so the space needs to be increased, that is, the line width needs to be reduced and the two target edges need to be moved inside the graphic.

[0095] The embodiment of the present application adopts a corresponding moving method to move the target edge line based on the corresponding bad pixel category, which can improve the optimization efficiency.

[0096] In practical applications, because the distance moved by the edge of a graphic and the corresponding distance moved by the contour are not necessarily equal, when adjusting the line width of a graphic, a combination of one-step movement (the moving distance is the difference between the bad pixel value and the expected value) and setting the step size to iterate and optimize the movement can be used. Figure 5 FIG. 1 shows a schematic diagram of a process for adjusting the line width of a graphic provided by an embodiment of the present application; Figure 5 As shown, the following steps are included: S501 to S505.

[0097] S501: Obtain the bad pixel size value and expected value of the bad pixel to be eliminated.

[0098] The bad pixel size value is the distance between two side lines that cause the bad pixel. When the distance between the two side lines that cause the bad pixel is an expected value, the bad pixel to be eliminated is eliminated.

[0099] S502: Determine the difference between the bad pixel size value and the expected value.

[0100] S503: Based on the bad pixel category of the bad pixel to be eliminated, the target edge line is moved by a difference value to obtain a first revised layout.

[0101] S504: Determine whether the first revised layout meets the iteration stop condition; if the first revised layout does not meet the iteration stop condition, proceed to S505; if the first revised layout meets the iteration stop condition, proceed to S507.

[0102] S505: moving the target edge by a preset step length to obtain a second revised layout;

[0103] S506: Determine the second revised layout as the new first revised layout, and return to S504.

[0104] S507: The iteration stops and the target local design layout is obtained.

[0105] The above iteration stopping conditions include that the bad points to be eliminated are eliminated or the layout design rules restrict the continued movement of the target edge line.

[0106] Since the distance of the edge of the figure and the distance of the corresponding contour are not necessarily equal, and the distance of the movement is limited due to the influence of design rules, when moving the target edge line, the present embodiment first moves the distance corresponding to the difference between the bad pixel size value and the expected value, and then repeatedly iterates to move, thereby efficiently and accurately completing the optimization of the figure.

[0107] The scheme in the above embodiment only moves the target edge line to optimize the line width, and the optimization effect on the design layout is limited. Therefore, in practical applications, after obtaining the target design layout, the moving direction and moving distance of the target edge line can also be determined, and based on the initial overall bad pixel information database (specifically, the initial overall bad pixel information database can be used), the moving direction and moving distance of the target edge line, the target design layout can be further adjusted.

[0108] Since the main consideration for graphic optimization in the above solution is the line width in the design rules, this optimization is limited. Therefore, the design optimization tool on the design side is required to further optimize the design layout based on more comprehensive DRC rules and other physical design constraints.

[0109] In order to solve the above technical problems, the embodiment of the present application also provides a device for adjusting the design layout. Figure 6 FIG. 1 is a schematic diagram showing the structure of a device for adjusting a design layout provided in an embodiment of the present application. Figure 6 As shown, the device includes the following modules:

[0110] The first determination module 601 is used to perform lithography simulation based on the original design layout to determine the corresponding overall bad pixel information database;

[0111] A clustering module 602 is used to perform a clustering operation according to the distribution density of each bad pixel in the overall bad pixel information database on the original design layout, and divide each bad pixel into multiple local design layouts;

[0112] The second determination module 603 is used to determine the local bad pixel information database corresponding to the local design layout;

[0113] An adjustment module 604 is used to adjust the local design layout based on the local bad pixel information database to eliminate each bad pixel in the local bad pixel information database to obtain a target local design layout;

[0114] The merging module 605 is used to merge the target partial design layout with the unprocessed area of ​​the original design layout except the partial design layout to obtain the target design layout.

[0115] In some embodiments, the first determining module is specifically configured to:

[0116] Perform photolithography simulation based on the original design layout to determine the initial overall bad pixel information database;

[0117] Select a target bad pixel in the initial overall bad pixel information database; the target bad pixel is a bad pixel that can be eliminated by modifying the line width;

[0118] Each target bad pixel is determined as an overall bad pixel information database.

[0119] In some embodiments, the first determination module is specifically used to: simulate the original design layout based on a photolithography simulation tool to obtain overall photoresist development profile information;

[0120] Perform photolithography rule check on the overall photoresist development profile information to obtain an initial overall bad pixel information database.

[0121] In some embodiments, the second determining module is specifically configured to:

[0122] Based on the photolithography simulation tool, the local design layout is simulated to obtain the local photoresist development profile information;

[0123] Perform photolithography rule check on local photoresist development profile information to obtain a local bad pixel information database.

[0124] In some embodiments, the adjustment module is specifically configured to:

[0125] Determine the target edge line of the bad points to be eliminated in the local design layout;

[0126] Determine the bad pixel category to be eliminated;

[0127] Based on the bad pixel category to be eliminated, the target edge line is moved to obtain the target local design layout.

[0128] In some embodiments, the adjustment module is specifically configured to:

[0129] Obtain the bad pixel size value and expected value of the bad pixel to be eliminated; the bad pixel size value is the distance between the two side lines that cause the bad pixel, and when the distance between the two side lines that cause the bad pixel is the expected value, the bad pixel to be eliminated is eliminated;

[0130] Determine the difference between the bad pixel size value and the expected value;

[0131] Based on the bad pixel category of the bad pixel to be eliminated, the target edge line is moved by the difference value to obtain a first corrected layout;

[0132] Determine whether the first revised layout meets the iteration stop condition;

[0133] When the first revised layout does not meet the iteration stop condition, the target edge is moved by a preset step length to obtain a second revised layout;

[0134] The second revised layout is determined as the new first revised layout, and the step of determining whether the first revised layout satisfies the iteration stop condition is returned until the first revised layout satisfies the iteration stop condition; the iteration stop condition includes that the bad points to be eliminated are eliminated or the layout design rules restrict the continued movement of the target edge line.

[0135] In some embodiments, the device for adjusting the design layout further includes: a third determination module, configured to determine the moving direction and moving distance of the target edge line after merging the target partial design layout with the unprocessed area of ​​the original design layout except the partial design layout to obtain the target design layout;

[0136] The adjustment module is also used to adjust the target design layout based on the initial overall bad pixel information database, the moving direction and moving distance of the target edge line.

[0137] The device provided in the embodiment of the present application is the same as the method in the above embodiment, so both have the same embodiments and beneficial effects, which will not be repeated here.

[0138] Figure 7 FIG. 1 is a schematic diagram showing the hardware structure of a device for adjusting a design layout provided in an embodiment of the present application. Figure 7 As shown, the device for adjusting the design layout may include a processor 701 and a memory 702 storing computer program instructions.

[0139] Specifically, the processor 701 may include a central processing unit (CPU), or an application specific integrated circuit (ASIC), or may be configured to implement one or more integrated circuits of the embodiments of the present application.

[0140] The memory 702 may include a large capacity memory for data or instructions. By way of example and not limitation, the memory 702 may include a hard disk drive (HDD), a floppy disk drive, a flash memory, an optical disk, a magneto-optical disk, a magnetic tape, or a universal serial bus (USB) drive or a combination of two or more of these. In appropriate cases, the memory 702 may include a removable or non-removable (or fixed) medium. In appropriate cases, the memory 702 may be inside or outside the integrated gateway disaster recovery device. In a specific embodiment, the memory 702 is a non-volatile solid-state memory.

[0141] The memory 702 may include a read-only memory (ROM), a random access memory (RAM), a magnetic disk storage medium device, an optical storage medium device, a flash memory device, an electrical, optical or other physical / tangible memory storage device. Therefore, generally, the memory includes one or more tangible (non-transitory) computer-readable storage media (e.g., a memory device) encoded with software including computer-executable instructions, and when the software is executed (e.g., by one or more processors), it is operable to perform the operations described with reference to the method according to one aspect of the present disclosure.

[0142] The processor 701 reads and executes computer program instructions stored in the memory 702 to implement any one of the methods for adjusting the design layout in the above embodiments.

[0143] In one example, the device for adjusting the design layout may further include a communication interface 703 and a bus 704. The processor 701, the memory 702, and the communication interface 703 are connected via the bus 704 and communicate with each other.

[0144] The communication interface 703 is mainly used to implement communication between various modules, devices, units and / or equipment in the embodiments of the present application.

[0145] The bus 704 includes hardware, software, or both, coupling the components of the device for adjusting the design layout to each other. By way of example and not limitation, the bus may include an Accelerate Graphical Port (AGP) or other graphics bus, an Enhanced Industry Standard Architecture (EISA) bus, a Front Side Bus (FSB), a Hyper Transport (HT) interconnect, an Industry Standard Architecture (ISA) bus, an InfiniBand interconnect, a Low Pin Count (LPC) bus, a Memory bus, a Micro Channel Architecture (MCA) bus, a Peripheral Component Interconnect (PCI) bus, a PCI-Express (PCI-X) bus, a Serial Advanced Technology Attachment (SATA) bus, a Video Electronics Standards Association Local Bus (VLB) bus, or other suitable buses or a combination of two or more of these. Where appropriate, the bus 704 may include one or more buses. Although embodiments of the present application describe and illustrate a particular bus, the present application contemplates any suitable bus or interconnect.

[0146] In addition, in combination with the method for adjusting the design layout in the above embodiment, the embodiment of the present application can provide a computer storage medium for implementation. The computer storage medium stores computer program instructions; when the computer program instructions are executed by the processor, any one of the methods for adjusting the design layout in the above embodiment is implemented.

[0147] An embodiment of the present application also provides a computer program product, including a computer program, which, when executed, implements any one of the methods for adjusting the design layout in the above embodiments.

[0148] It should be clear that the present application is not limited to the specific configuration and processing described above and shown in the figures. For the sake of simplicity, a detailed description of the known method is omitted here. In the above embodiments, several specific steps are described and shown as examples. However, the method process of the present application is not limited to the specific steps described and shown, and those skilled in the art can make various changes, modifications and additions, or change the order between the steps after understanding the spirit of the present application.

[0149] The functional blocks shown in the block diagram above can be implemented as hardware, software, firmware or a combination thereof. When implemented in hardware, it can be, for example, an electronic circuit, an ASIC, appropriate firmware, a plug-in, a function card, etc. When implemented in software, the elements of the present application are programs or code segments used to perform the required tasks. The program or code segment can be stored in a machine-readable medium, or transmitted on a transmission medium or a communication link by a data signal carried in a carrier wave. "Machine-readable medium" can include any medium capable of storing or transmitting information. Examples of machine-readable media include electronic circuits, semiconductor memory devices, ROM, flash memory, erasable ROM (Erasable ROM, EROM), floppy disks, compact disc read-only memory (Compact Disc Read-Only Memory, CD-ROM), optical discs, hard disks, optical fiber media, radio frequency (Radio Frequency, RF) links, etc. Code segments can be downloaded via computer networks such as the Internet, intranets, etc.

[0150] It should also be noted that the exemplary embodiments mentioned in this application describe some methods or systems based on a series of steps or devices. However, this application is not limited to the order of the above steps, that is, the steps can be performed in the order mentioned in the embodiment, or in a different order from the embodiment, or several steps can be performed simultaneously.

[0151] Aspects of the present disclosure are described above with reference to a method, device, equipment, medium and product for adjusting a design layout according to an embodiment of the present disclosure. It should be understood that each box in the flowchart and / or block diagram and the combination of each box in the flowchart and / or block diagram can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device to produce a machine so that these instructions executed by the processor of the computer or other programmable data processing device enable the implementation of the function / action specified in one or more boxes of the flowchart and / or block diagram. Such a processor can be, but is not limited to, a general-purpose processor, a special-purpose processor, a special application processor or a field programmable logic circuit. It can also be understood that each box in the block diagram and / or flowchart and the combination of boxes in the block diagram and / or flowchart can also be implemented by dedicated hardware that performs a specified function or action, or can be implemented by a combination of dedicated hardware and computer instructions.

[0152] The above contents are only specific implementation methods of the present application. Those skilled in the art can clearly understand that for the convenience and simplicity of description, the specific working processes of the systems, modules and units described above can refer to the corresponding processes in the aforementioned method embodiments, and will not be repeated here. It should be understood that the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of various equivalent modifications or replacements within the technical scope disclosed in the present application, and these modifications or replacements should be included in the protection scope of the present application.

Claims

1. A method for adjusting a design layout, characterized in that: include: Perform photolithography simulation based on the original design layout to determine the corresponding overall bad pixel information database; Performing a clustering operation according to the distribution density of each bad pixel in the overall bad pixel information database on the original design layout, and dividing each bad pixel into a plurality of local design layouts; Determine a local bad pixel information database corresponding to the local design layout; Based on the local bad pixel information database, adjusting the local design layout to eliminate each bad pixel in the local bad pixel information database to obtain a target local design layout; The target partial design layout is merged with an unprocessed area of ​​the original design layout except the partial design layout to obtain a target design layout.

2. The method for adjusting the design layout according to claim 1, characterized in that: The performing of lithography simulation based on the original design layout to determine the corresponding overall bad pixel information database includes: Perform photolithography simulation based on the original design layout to determine the initial overall bad pixel information database; Selecting a target bad pixel from the initial overall bad pixel information database; the target bad pixel is a bad pixel that can be eliminated by modifying the line width; Each of the target bad pixels is determined as the overall bad pixel information database.

3. The method for adjusting the design layout according to claim 2, characterized in that: The method of performing lithography simulation based on the original design layout to determine the initial overall bad pixel information database includes: Based on a photolithography simulation tool, the original design layout is simulated to obtain overall photoresist development profile information; A photolithography rule check is performed on the overall photoresist development profile information to obtain the initial overall bad pixel information database.

4. The method for adjusting the design layout according to claim 1, characterized in that: The determining of the local bad pixel information database corresponding to the local design layout includes: Based on a photolithography simulation tool, the local design layout is simulated to obtain local photoresist development profile information; A photolithography rule check is performed on the local photoresist development profile information to obtain the local bad pixel information database.

5. The method for adjusting the design layout according to claim 1, characterized in that: The adjusting the local design layout based on the local bad pixel information database to eliminate each bad pixel in the local bad pixel information database to obtain a target local design layout includes: Determine the target edge line of the bad point to be eliminated in the local design layout; Determine the bad pixel category of the bad pixel to be eliminated; Based on the bad pixel category of the bad pixel to be eliminated, the target edge line is moved to obtain the target local design layout.

6. The method for adjusting the design layout according to claim 5, characterized in that: The step of moving the target edge line based on the bad point category of the bad point to be eliminated to obtain the target local design layout includes: Obtaining a bad pixel size value and an expected value of the bad pixel to be eliminated; the bad pixel size value is the distance between two side lines that cause the bad pixel, and when the distance between the two side lines that cause the bad pixel is the expected value, the bad pixel to be eliminated is eliminated; Determine the difference between the bad pixel size value and the expected value; Based on the bad point category of the bad point to be eliminated, the target edge line is moved by the difference to obtain a first revised layout; Determining whether the first revised layout satisfies an iteration stop condition; When the first revised layout does not meet the iteration stop condition, the target edge is moved by a preset step length to obtain a second revised layout; The second revised layout is determined as a new first revised layout, and the step of determining whether the first revised layout satisfies the iteration stop condition is returned until the first revised layout satisfies the iteration stop condition; the iteration stop condition includes that the bad point to be eliminated is eliminated or the layout design rule restricts the continued movement of the target edge line.

7. The method for adjusting the design layout according to claim 5 or 6, characterized in that: After merging the target partial design layout with the unprocessed area of ​​the original design layout except the partial design layout to obtain the target design layout, the method further includes: Determining the moving direction and moving distance of the target edge line; The target design layout is adjusted based on the overall bad pixel information database, the moving direction and the moving distance of the target edge line.

8. A device for adjusting a design layout, characterized in that: include: a processor and a memory storing computer program instructions; When the processor executes the computer program instructions, the method for adjusting the design layout as described in any one of claims 1 to 7 is implemented.

9. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer program instructions, and when the computer program instructions are executed by a processor, the method for adjusting the design layout according to any one of claims 1 to 7 is implemented.

10. A computer program product, characterized in that When the instructions in the computer program product are executed by a processor of an electronic device, the electronic device executes the method for adjusting the design layout as described in any one of claims 1 to 7.

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