Transistor manufacturing method and semiconductor process equipment

Abstract

The invention discloses a transistor manufacturing method and semiconductor process equipment, and the method comprises the steps: carrying out the etching of a target device with a graphical mask layer, so as to form a groove, and enabling the target device to be used for manufacturing a transistor; performing surface etching on the mask layer, wherein the surface etching is used for removing a charge accumulation layer formed on the surface of the mask layer in the etching process; and performing ion implantation on the target device to form a channel region at the groove of the target device. After the charge accumulation layer on the surface of the mask layer is removed, the scattering effect of the charges accumulated on the surface of the mask layer on the implanted ions can be reduced, so that the uniformity of ion implantation can be improved, the doping concentration of the channel region can be more accurately controlled, and the threshold voltage of the transistor can be more accurately controlled.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor processing, and in particular to a method for manufacturing a transistor and semiconductor process equipment. Background Art

[0002] Threshold voltage is one of the important parameters that affect transistor performance, and the ion implantation process is one of the important factors that affect the threshold voltage of transistors. Although the threshold voltage of transistors can be adjusted by adjusting the ion implantation concentration and angle during the ion implantation process, the threshold voltage of transistors cannot be accurately controlled. Summary of the invention

[0003] The invention discloses a method for manufacturing a transistor and semiconductor process equipment, so as to more accurately control the threshold voltage of the transistor.

[0004] In a first aspect, the present invention discloses a method for manufacturing a transistor, comprising: etching a target device having a patterned mask layer to form a groove; the target device is used to make a transistor; surface etching the mask layer, the surface etching is used to remove a charge accumulation layer formed on the surface of the mask layer during the etching process; using the mask layer as a mask, ion implanting the target device to form a channel region in the groove of the target device.

[0005] In some embodiments of the present invention, the target device includes a substrate and a polysilicon layer located on the surface of the substrate; the etching of the target device having a patterned mask layer includes: etching the polysilicon layer on the surface of the substrate to form a groove penetrating the polysilicon layer; the ion implantation of the target device includes: ion implantation of the substrate at the bottom of the groove of the target device to form a channel region in the substrate at the bottom of the groove of the target device.

[0006] In some embodiments of the present invention, the etching of the polysilicon layer on the surface of the substrate includes: etching the natural oxide layer on the surface of the polysilicon layer using a first etching gas; etching the polysilicon layer for a first time using a second etching gas; and etching the polysilicon layer for a second time using a third etching gas; wherein the first etching gas includes at least a fluorine-containing gas, the second etching gas includes at least a chlorine-containing gas, and the third etching gas includes at least a bromine-containing gas.

[0007] In some embodiments of the present invention, the mask layer includes a photoresist layer.

[0008] In some embodiments of the present invention, the surface etching of the mask layer includes: etching the photoresist layer using a fourth etching gas, and the fourth etching gas includes an oxygen-containing gas.

[0009] In some embodiments of the present invention, when the mask layer is surface-etched, the etching amount of the charge accumulation layer on the surface of the mask layer is controlled by controlling any one or any combination of the gas flow rate of the etching gas, the etching time, the upper RF power and the chamber pressure.

[0010] In some embodiments of the present invention, the gas flow rate range of the etching gas is 10sccm-200sccm; and / or the etching time range is 4s-40s; and / or the upper RF power range is 100W-1000W; and / or the chamber pressure range is 50mTorr-100mTorr.

[0011] In some embodiments of the present invention, when the mask layer is surface-etched, the lower RF power output by the lower RF power supply is controlled to be 0.

[0012] In some embodiments of the present invention, during the process of etching a target device having a patterned mask layer and surface etching the mask layer, the process chamber where the etching is performed is in a continuous ignition state.

[0013] In a second aspect, the present invention discloses a semiconductor process equipment, including a process chamber, an air intake assembly, an upper RF power supply, a lower RF power supply and a controller, wherein the controller is used to control the gas flow rate and chamber pressure of the process chamber and the upper RF power output by the upper RF power supply and the lower RF power output by the lower RF power supply, and the controller includes a processor and a memory, wherein a computer program is stored in the memory, and when the computer program is executed by the processor, a method for manufacturing a transistor as described in any of the above items is implemented.

[0014] The manufacturing method and semiconductor process equipment of the transistor disclosed in the present invention, after etching a target device having a patterned mask layer used to make a transistor to form a groove, firstly perform surface etching on the mask layer to remove the charge accumulation layer formed on the surface of the mask layer during the etching process, and then perform ion implantation on the target device using the mask layer as a mask to form a channel region at the groove of the target device. Because after removing the charge accumulation layer on the surface of the mask layer, the scattering effect of the charge accumulated on the surface of the mask layer on the implanted ions can be reduced, so the uniformity of the ion implantation can be improved, and then the doping concentration of the channel region can be more accurately controlled, and then the threshold voltage of the transistor can be more accurately controlled. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the background technology, the drawings required for use in the embodiments of the present invention or the background technology will be described below.

[0016] Figure 1A schematic diagram of the effect of ion implantation on an etched device.

[0017] Figure 2 The present invention is a flowchart of a method for manufacturing a transistor disclosed in an embodiment of the present invention.

[0018] Figure 3 A schematic diagram of the cross-sectional structure of a target device disclosed in an embodiment of the present invention.

[0019] Figure 4 The cross-sectional structure diagram of a target device with a patterned mask layer disclosed in an embodiment of the present invention.

[0020] Figure 5 It is a schematic diagram of the cross-sectional structure of a target device with a groove disclosed in an embodiment of the present invention.

[0021] Figure 6 The cross-sectional structure schematic diagram of a target device after surface etching of a mask layer disclosed in an embodiment of the present invention is shown.

[0022] Figure 7 A schematic diagram of the movement direction of plasma in a groove of a target device under low chamber pressure disclosed in an embodiment of the present invention.

[0023] Figure 8 A schematic diagram of the movement direction of plasma in a groove of a target device under high chamber pressure disclosed in an embodiment of the present invention.

[0024] Fig. 9 A schematic diagram of the structure of a semiconductor process equipment disclosed in an embodiment of the present invention. DETAILED DESCRIPTION

[0025] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0026] In integrated circuit manufacturing, precise control and quality assessment of wafer products run through the entire manufacturing process. Among them, the wafer products need to be subjected to WAT (Wafer Acceptance Test) electrical testing before shipment to ensure that the electrical parameters of the key components of the integrated circuit meet the electrical design principles. The threshold voltage is one of the important WAT test parameters of transistors in integrated circuits. Among them, the factors affecting the threshold voltage of transistors mainly include the following aspects: 1. Abnormal well ion implantation; 2. Ion implantation damage is not activated during annealing; 3. Abnormal size of polysilicon gate after etching; 4. Abnormal thickness of gate oxide layer.

[0027] In general, the threshold voltage of the transistor can be effectively adjusted by adjusting the concentration and angle of ion implantation. However, it cannot accurately control the threshold voltage of the transistor. This is because ion implantation is relatively complex. For example, the energy of the implanted ions will also affect the threshold voltage of the transistor. If the energy of the implanted ions is too high, it will damage the structure of the transistor and affect the threshold voltage of the transistor; if the energy of the implanted ions is too low, it will not be possible to accurately control the depth of the PN junction formed, nor will it be possible to accurately control the diffusion path of the ions, and thus it will not be possible to accurately control the threshold voltage of the transistor.

[0028] In addition, the charge accumulation layer on the surface of the mask layer used in the ion implantation process will also affect the threshold voltage of the transistor. Figure 1 As shown, after the polysilicon layer 10 is etched to form the groove 101, a charge accumulation layer 102 will exist on the surface of the mask layer 11. The charge accumulation layer 102 is formed by the accumulation of charges in the plasma generated during the etching process. The charges in the charge accumulation layer 102 will scatter the injected ions, resulting in poor uniformity of ion injection, making it impossible to accurately control the ion doping concentration at the groove 101, and further, unable to accurately control the threshold voltage of the transistor.

[0029] Based on this, the present invention discloses a transistor manufacturing scheme. After etching a target device used to make the transistor and before ion implantation into the target device, the mask layer on the surface of the target device is surface etched to remove the charge accumulation layer on the surface of the mask layer so as to more accurately control the threshold voltage of the transistor.

[0030] As an optional implementation of the disclosure of the present invention, an embodiment of the present invention discloses a method for manufacturing a transistor, such as Figure 2 As shown, the method includes:

[0031] S101: etching a target device having a patterned mask layer to form a groove, wherein the target device is used to manufacture a transistor.

[0032] In some embodiments of the present invention, the target device is a device in which a channel region is to be formed, such as Figure 3 As shown, the target device includes a substrate 20 and a polysilicon layer 10 located on the surface of the substrate 20 , wherein the substrate 20 may include a silicon substrate, and a silicon oxide layer 21 is further included between the substrate 20 and the polysilicon layer 10 .

[0033] Based on this, etching the target device having a patterned mask layer includes: Figure 4 The polysilicon layer 10 on the surface of the substrate 20 with the patterned mask layer 11 is etched to form a Figure 5 A groove 101 is shown penetrating the polysilicon layer 10 .

[0034] Of course, the present invention is not limited to this. In other embodiments, the target device may also be a device with a source region or a drain region to be formed, which will not be described in detail here.

[0035] S102: performing surface etching on the mask layer, wherein the surface etching is used to remove a charge accumulation layer formed on the surface of the mask layer during the etching process.

[0036] In the process of using plasma to etch the target device to form the groove 101, the charges in the plasma will accumulate on the surface of the target device, specifically on the surface of the mask layer 11 on the surface of the target device, forming Figure 5 The charge accumulation layer 102 is shown. Since the mask layer 11 on the surface of the target device is not removed during the ion implantation process, the charge accumulation layer 102 on the surface of the mask layer 11 will affect the uniformity of the ion implantation.

[0037] Based on this, in the embodiment of the present invention, after etching the target device and before ion implantation, the mask layer 11 is surface etched to remove the charge accumulation layer 102 formed by the mask layer 11 in the aforementioned etching process, thereby forming Figure 6 The structure shown.

[0038] It should be noted that, because the charge accumulation layer 102 on the surface of the mask layer 11 at the side wall of the groove 101 has a greater impact on the uniformity of ion implantation, in the embodiment of the present invention, the charge accumulation layer 102 on the surface of the mask layer 11 at the side wall of the groove 101 is mainly etched.

[0039] S103: using the mask layer as a mask, ion implantation is performed on the target device to form a channel region in the groove of the target device.

[0040] Because the charge accumulation layer 102 on the surface of the mask layer 11 has been removed, when ion implantation is performed on the target device and a channel region is formed at the groove 101 of the target device, the uniformity of ion implantation in the channel region can be improved, and the ion doping concentration in the channel region can be more accurately controlled to more accurately control the threshold voltage of the transistor. It should be noted that the threshold voltage is very sensitive to the ion doping concentration in the channel region. In order to accurately control the threshold voltage of the transistor, it is necessary to accurately control the ion doping concentration in the channel region.

[0041] In some embodiments of the present invention, performing ion implantation on the target device includes: performing ion implantation on the substrate 20 at the bottom of the groove 101 of the target device to form a channel region in the substrate 20 at the bottom of the groove 101 of the target device. Of course, the present invention is not limited thereto, and in other embodiments, performing ion implantation on the target device may also include: performing ion implantation on the substrate 20 at the bottom of the groove 101 of the target device to form a source region or a drain region in the substrate 20 at the bottom of the groove 101 of the target device.

[0042] In some embodiments of the present invention, etching the polysilicon layer 10 on the surface of the substrate 20 includes: etching the natural oxide layer on the surface of the polysilicon layer 10 using a first etching gas; performing a first etching on the polysilicon layer 10 using a second etching gas; and performing a second etching on the polysilicon layer 10 using a third etching gas. The first etching will etch away a portion of the polysilicon layer 10, and the second etching will etch away the remaining polysilicon layer 10, and may even etch away a portion of the silicon oxide layer 21.

[0043] Wherein, the natural oxide layer includes a silicon oxide layer. The first etching gas includes at least a fluorine-containing gas, such as CF4, etc. The second etching gas includes at least a chlorine-containing gas, such as Cl2, etc., and of course, the second etching gas may also include HBr and HeO2, etc. The third etching gas includes at least a bromine-containing gas, such as HBr, etc., and of course, the third etching gas may also include HeO2 and He, etc.

[0044] It should be noted that, in some embodiments of the present invention, during etching of a target device having a patterned mask layer 11 and surface etching of the mask layer 11, the process chamber where the etching is performed is in a continuous ignition state to reduce the risk of ignition failure.

[0045] In some embodiments of the present invention, the mask layer 11 includes a photoresist layer. Based on this, in some embodiments of the present invention, surface etching the mask layer 11 includes: etching the photoresist layer using a fourth etching gas, wherein the fourth etching gas includes an oxygen-containing gas, such as O2.

[0046] In some embodiments of the present invention, when the mask layer 11 is surface etched, the etching amount of the charge accumulation layer 102 on the surface of the mask layer 11 can be precisely controlled by controlling any one or any combination of the gas flow rate of the fourth etching gas, the etching time, the upper RF power and the chamber pressure, thereby precisely controlling the uniformity of ion implantation in the channel region and the ion doping concentration in the channel region to precisely control the threshold voltage of the transistor.

[0047] In some embodiments of the present invention, when the mask layer 11 is surface etched, the gas flow rate of the fourth etching gas is in the range of 10sccm-200sccm. It should be noted that by making the gas flow rate of the fourth etching gas any value in the range of 10sccm-200sccm, for example, 50sccm, the gas flow rate of the fourth etching gas can be relatively increased, and then the concentration of the plasma in the process chamber where the etching is performed can be increased, thereby intensifying the collision and bombardment of the plasma on the charge accumulation layer 102 on the surface of the mask layer 11, and accelerating the etching speed of the charge accumulation layer 102.

[0048] In some embodiments of the present invention, when the mask layer 11 is surface etched, the upper RF power ranges from 100W to 1000W. It should be noted that by setting the upper RF power to any value between 100W and 1000W, such as 960W, the upper RF power can be relatively increased to excite the etching gas to generate more plasma, thereby accelerating the etching speed of the charge accumulation layer 102. It is understandable that if the upper RF power is too low, the etching gas cannot be excited to generate plasma, and the charge accumulation layer 102 cannot be etched.

[0049] In some embodiments of the present invention, when the mask layer 11 is surface etched, the etching time ranges from 4s to 40s. It should be noted that by setting the etching time to any value between 4s and 40s, such as 20s, the etching time can be relatively increased, and the purpose of completely removing the charge accumulation layer 102 on the surface of the mask layer 11 can be achieved by allowing the plasma to continuously react and bombard the mask layer 11.

[0050] In some embodiments of the present invention, when the mask layer 11 is etched, the chamber pressure ranges from 50mTorr to 100mTorr. It should be noted that if the chamber pressure is lower than 50mTorr, Figure 7 As shown, the plasma will maintain a consistent direction of movement in the process chamber, which is not conducive to etching the charge accumulation layer 102 at the side wall of the groove 101; if the chamber pressure is any value between 50mTorr and 100mTorr, for example, 80mTorr, the relatively high chamber pressure value shortens the average molecular free path of the same amount of plasma in the process chamber, increasing the probability of collision between the plasmas, such as Figure 8As shown, the plasma can be made to move in all directions, so that it is difficult for the plasma to enter the bottom of the groove 101 , and only the charge accumulation layer 102 at the side wall of the top of the groove 101 is etched.

[0051] In some embodiments of the present invention, when the mask layer 11 is surface etched, the lower RF power output by the lower RF power supply is controlled to be 0. It should be noted that by setting the lower RF power to 0, the plasma can be prevented from bombarding the substrate 20, the silicon oxide layer 21 and the polysilicon layer 10 at the groove 101, so that the plasma is evenly distributed on the surface of the target device, and the plasma reacts and bombards the charge accumulation layer 102 on the surface of the mask layer 11 with high selectivity, so as to achieve the purpose of etching the charge accumulation layer 102 on the surface of the mask layer 11.

[0052] In some embodiments of the present invention, when the mask layer 11 is surface etched, the temperature in the process chamber is in the range of 30° C. to 90° C. Of course, in other embodiments of the present invention, other parameters in the etching process of the charge accumulation layer 102 may also be limited, which will not be described in detail here.

[0053] It should be noted that after the channel region is formed at the groove 101 of the target device, steps such as forming a source and a drain are further performed, which will not be described in detail here.

[0054] As an optional implementation of the disclosure of the present invention, an embodiment of the present invention discloses a semiconductor process equipment, such as Fig. 9 As shown, the semiconductor process equipment includes a process chamber 6, an air inlet assembly 7, an upper RF power supply (Source Radio Frequency, abbreviated as SRF), a lower RF power supply (Bias Radio Frequency, abbreviated as BRF) and a controller (not shown in the figure), and the controller is used to control the gas flow and chamber pressure of the process chamber 6, as well as the upper RF power output by the upper RF power supply SRF and the lower RF power output by the lower RF power supply BRF.

[0055] Among them, the gas inlet assembly 7 is used to introduce etching gas, etc. into the process chamber 6. The upper RF power supply SRF is electrically connected to the upper electrode 1 in the process chamber 6 through an adapter. The upper electrode 1 includes an outer coil and an inner coil of an inductive coupling coil, which are used to load RF power to the outer coil and the inner coil. The outer coil and the inner coil are coupled to the process chamber 6 through a dielectric window 2 to ionize the gas in the process chamber 6 into plasma 3. The lower RF power supply BRF is electrically connected to the base 4 through an adapter to apply bias power to the base 4. The base 4 is used to carry the device 5 to be prepared, and the device 5 to be prepared includes a target device, etc.

[0056] Wherein, the controller includes a processor and a memory, and a computer program is stored in the memory. When the computer program is executed by the processor, the method for manufacturing a transistor disclosed in any of the above embodiments is implemented. The semiconductor process equipment includes but is not limited to inductively coupled plasma etching equipment. Specifically, the controller is electrically connected to the intake valve in the intake assembly 7 to control the gas flow rate and chamber pressure by controlling the opening degree of the intake valve. The controller is also electrically connected to the upper RF power supply SRF and the lower RF power supply BRF to control the upper RF power output by the upper RF power supply SRF and the lower RF power output by the lower RF power supply BRF.

[0057] The technical features of the above embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0058] The above embodiments only express several implementation methods of this specification, and the descriptions are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that for ordinary technicians in this field, several modifications and improvements can be made without departing from the concept of this specification, which all belong to the protection scope of this specification. Therefore, the protection scope of the patent of this specification shall be based on the attached claims.

Claims

1. A method for manufacturing a transistor, characterized in that: include: etching a target device having a patterned mask layer to form a groove; The target device is used to make a transistor; Performing surface etching on the mask layer, wherein the surface etching is used to remove a charge accumulation layer formed on the surface of the mask layer during the etching process; Using the mask layer as a mask, ion implantation is performed on the target device to form a channel region at the groove of the target device.

2. The method according to claim 1, characterized in that: The target device includes a substrate and a polysilicon layer located on a surface of the substrate; The etching of the target device having the patterned mask layer comprises: etching the polysilicon layer on the surface of the substrate to form a groove penetrating the polysilicon layer; The performing ion implantation on the target device includes: performing ion implantation on the substrate at the bottom of the groove of the target device to form a channel region in the substrate at the bottom of the groove of the target device.

3. The method according to claim 2, characterized in that The etching of the polysilicon layer on the surface of the substrate comprises: Etching the natural oxide layer on the surface of the polysilicon layer using a first etching gas; Performing a first etching on the polysilicon layer using a second etching gas; Performing a second etching on the polysilicon layer using a third etching gas; The first etching gas at least includes a fluorine-containing gas, the second etching gas at least includes a chlorine-containing gas, and the third etching gas at least includes a bromine-containing gas.

4. The method according to claim 1, characterized in that: The mask layer includes a photoresist layer.

5. The method according to claim 4, characterized in that The surface etching of the mask layer comprises: The photoresist layer is etched using a fourth etching gas, wherein the fourth etching gas comprises an oxygen-containing gas.

6. The method according to claim 5, characterized in that When the mask layer is surface-etched, the etching amount of the charge accumulation layer on the surface of the mask layer is controlled by controlling any one or any combination of the gas flow rate, etching time, upper RF power and chamber pressure of the fourth etching gas.

7. The method according to claim 6, characterized in that The gas flow rate of the etching gas is in the range of 10 sccm-200 sccm; and / or, The etching time ranges from 4s to 40s; and / or, The upper radio frequency power ranges from 100W to 1000W; and / or, The chamber pressure ranges from 50mTorr to 100mTorr.

8. The method according to claim 1, characterized in that When the mask layer is surface-etched, the lower RF power output by the lower RF power supply is controlled to be 0.

9. The method according to claim 1, characterized in that: During the process of etching the target device having the patterned mask layer and surface etching the mask layer, the process chamber where the etching is performed is in a continuous ignition state.

10. A semiconductor process equipment, comprising a process chamber, an air inlet assembly, an upper RF power supply, a lower RF power supply and a controller, wherein the controller is used to control the gas flow and chamber pressure of the process chamber, the upper RF power output by the upper RF power supply and the lower RF power output by the lower RF power supply, characterized in that: The controller includes a processor and a memory, wherein a computer program is stored in the memory, and when the computer program is executed by the processor, the method for manufacturing a transistor according to any one of claims 1 to 9 is implemented.

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