Manufacturing method of semiconductor device and semiconductor device

Abstract

The embodiment of the invention provides a manufacturing method of a semiconductor device and the semiconductor device, and the method comprises the steps: providing a substrate, forming a copper-containing metal structure prepared based on a Damascus technology on the substrate, and enabling the copper-containing metal structure to be ground through a chemical mechanical polishing technology; performing reduction treatment on the surface of the ground copper-containing metal structure by using first plasma; second plasma is introduced into the surface of the reduced copper-containing metal structure, and a compound layer is formed on the surface of the copper-containing metal structure; third plasma is introduced into the surface of the compound layer, and the compound layer is converted into a mixed compound layer; and sequentially depositing and forming a passivation layer and an oxide isolation layer on the mixed compound layer. The electromigration resistance of the copper metal layer is effectively improved.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of semiconductor technology, and in particular, to a method for manufacturing a semiconductor device and a semiconductor device. Background Art

[0002] At present, integrated circuit manufacturing is usually divided into front-end process and back-end process. As the feature size of the device continues to decrease, the current density of the metal connection continues to increase, resulting in the resistance-capacitance delay of the back-end process becoming the main factor limiting the circuit performance. Since the resistivity of copper is smaller than that of aluminum, and the anti-electromigration rate of copper is better than that of aluminum, the reliability of copper electromigration becomes a key factor in the circuit performance of the device, so that in the 65nm and below process, the back-end process uses copper metal connections and low dielectric constant films to a certain extent to effectively improve the resistance-capacitance delay. Among them, electromigration refers to the fact that when the device is working, a certain current passes through the metal connection, and the metal ions form mass transport along the conductor, which will cause voids in certain positions of the conductor. Electromigration can easily cause the device to short-circuit or open circuit, etc., thereby causing device failure. Compared with the aluminum process, the electromigration of the copper process is due to diffusion at the interface or surface. In the Damascus process of copper, the metal substrate has good adhesion to the conductor, thereby inhibiting the diffusion of the conductor through the dielectric in the layer.

[0003] However, after the electroplating growth of the metal substrate is completed, chemical mechanical polishing is required to remove the excess copper on the surface, so that a thin layer of copper oxide is formed on the surface of the copper metal layer. This layer of copper oxide reduces the adhesion between the copper metal layer and the subsequent dielectric layer, and is a channel for metal ions to diffuse at the interface, causing electromigration of the device, which may cause device failure. In the related art, electromigration is weakened by depositing cobalt tungsten phosphide, cobalt tin phosphide or palladium on the surface of the copper metal layer, which has the problems of high cost and complex process. Summary of the invention

[0004] The embodiment of the present application provides a method for manufacturing a semiconductor device and a semiconductor device, which solves the problem of high cost and complex process in the related art of reducing electromigration by depositing cobalt tungsten phosphide, cobalt tin phosphide or palladium on the surface of the copper metal layer. The surface of the copper-containing metal structure after grinding is reduced by using a first plasma, effectively reducing copper oxide to copper, and by converting the compound layer into a mixed compound layer, the adhesion of the mixed compound layer to the copper-containing metal structure and the adhesion of the mixed compound layer to the passivation layer are enhanced compared to the compound layer, which can effectively improve the anti-electromigration ability of the copper metal layer.

[0005] In a first aspect, an embodiment of the present application provides a manufacturing method, comprising:

[0006] Providing a substrate, on which a copper-containing metal structure prepared based on a Damascus process is formed, wherein the copper-containing metal structure has been polished using a chemical mechanical polishing process;

[0007] Using a first plasma to perform a reduction treatment on the surface of the copper-containing metal structure after the grinding treatment;

[0008] Passing a second plasma onto the surface of the copper-containing metal structure after the reduction treatment to form a compound layer on the surface of the copper-containing metal structure;

[0009] Passing a third plasma into the surface of the compound layer to convert the compound layer into a mixed compound layer;

[0010] A passivation layer and an oxide isolation layer are sequentially deposited on the mixed compound layer.

[0011] The flow rate of the first plasma is 500 sccm to 2000 sccm, and the first plasma is hydrogen or ammonia.

[0012] Optionally, when the first plasma is used to perform reduction treatment on the surface of the copper-containing metal structure after the grinding treatment, the corresponding process temperature is set to 300° C. to 400° C.

[0013] Optionally, the flow rate of the second plasma is 50 sccm to 300 sccm, the second plasma is silicon hydride gas, and the compound layer includes copper silicon compound.

[0014] Optionally, when the second plasma is introduced into the surface of the copper-containing metal structure after the reduction treatment, the corresponding process temperature is set to 200° C. to 350° C.

[0015] Optionally, the flow rate of the third plasma is 500 sccm to 2000 sccm, the third plasma is ammonia, and the mixed compound layer includes copper-silicon compound, copper-nitrogen compound and silicon-nitrogen compound.

[0016] Optionally, when the third plasma is introduced into the surface of the compound layer, the corresponding process temperature is set to 300° C. to 400° C.

[0017] Optionally, when a passivation layer and an oxide isolation layer are sequentially deposited on the mixed compound layer, a corresponding process temperature is set to 350° C. to 400° C.

[0018] Optionally, the passivation layer is a carbon-doped silicon nitride layer, and the oxide isolation layer is a silicon carbon oxyhydride layer.

[0019] In a second aspect, an embodiment of the present application further provides a semiconductor device, which uses the manufacturing method described in any embodiment of the present application to prepare a copper-containing semiconductor structure.

[0020] In an embodiment of the present application, a substrate is provided, and a copper-containing metal structure prepared based on a Damascus process is formed on the substrate, wherein the copper-containing metal structure has been ground using a chemical mechanical polishing process; a first plasma is used to reduce the surface of the copper-containing metal structure after the grinding process; a second plasma is introduced into the surface of the copper-containing metal structure after the reduction process to form a compound layer on the surface of the copper-containing metal structure; a third plasma is introduced into the surface of the compound layer to convert the compound layer into a mixed compound layer; a passivation layer and an oxide isolation layer are sequentially deposited on the mixed compound layer. In the above scheme, the surface of the copper-containing metal structure after the grinding process is reduced by using the first plasma, so that copper oxide is effectively reduced to copper, and by converting the compound layer into a mixed compound layer, compared with the compound layer, the adhesion of the mixed compound layer to the copper-containing metal structure and the adhesion of the mixed compound layer to the passivation layer are enhanced, which can effectively improve the anti-electromigration ability of the copper metal layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 A schematic diagram of copper oxide formed on the surface of an exemplary copper-containing metal structure after chemical mechanical polishing;

[0022] Figure 2 A schematic diagram of holes generated between a copper metal layer and a metal connection layer or a passivation layer due to electromigration is shown as an example;

[0023] Figure 3 A flowchart of a method for manufacturing a semiconductor device provided in an embodiment of the present application;

[0024] Figure 4 A schematic diagram of a cross-sectional structure of a semiconductor structure provided in step S101 of the manufacturing method provided in an embodiment of the present application;

[0025] Figure 5 A schematic diagram of a cross-sectional structure of a semiconductor structure provided in step S102 of the manufacturing method provided in an embodiment of the present application;

[0026] Figure 6 A schematic diagram of the cross-sectional structure of a semiconductor structure provided in step S103 of the manufacturing method provided in an embodiment of the present application;

[0027] Figure 7 A schematic diagram of a cross-sectional structure of a semiconductor structure provided in step S104 of the manufacturing method provided in an embodiment of the present application;

[0028] Figure 8A schematic diagram of a cross-sectional structure of a semiconductor structure provided in step S105 of the manufacturing method provided in an embodiment of the present application;

[0029] Fig. 9 A graph showing the relationship between the relative resistance degradation over time of a control sample to which the manufacturing method provided in the embodiment of the present application is not applied;

[0030] Fig.10 A transmission electron microscope slice image of a control sample to which the manufacturing method provided in the embodiment of the present application is not applied;

[0031] Fig.11 A graph showing the relationship between the relative resistance degradation over time of an experimental sample using the manufacturing method provided in an embodiment of the present application;

[0032] Fig.12 A transmission electron microscope slice image of an experimental sample using the manufacturing method provided in an embodiment of the present application. DETAILED DESCRIPTION

[0033] The embodiments of the present application are further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the embodiments of the present application, rather than to limit the embodiments of the present application. It should also be noted that, for ease of description, only parts related to the embodiments of the present application are shown in the accompanying drawings, rather than all structures.

[0034] The terms "first", "second", etc. in the specification and claims of the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described here, and the objects distinguished by "first", "second", etc. are generally of one type, and the number of objects is not limited. For example, the first object can be one or more. In addition, "and / or" in the specification and claims represents at least one of the connected objects, and the character " / " generally indicates that the objects associated with each other are in an "or" relationship.

[0035] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers. Spatial relationship terms such as "under ...", "under ...", "below ...", "under ...", "above ...", "above", etc., can be used here to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientation shown in the figure, spatial relationship terms also include different orientations of devices in use and operation. For example, if the device in the accompanying drawings is turned over, the element or feature described as "under other elements" or "under it" or "under it" will be oriented as "on" other elements or features. Therefore, the exemplary terms "under ..." and "under ..." can include both upper and lower orientations. Furthermore, the devices may be included in alternative orientations (eg, rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.

[0036] When used herein, the singular forms "a", "an" and " / the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "consisting of" and / or "comprising" are used in this specification, the presence of features, integers, steps, operations, elements and / or components can be determined, but the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups is not excluded. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0037] Integrated circuit manufacturing is usually divided into front-end process and back-end process. As the feature size of devices continues to decrease, the current density of metal wiring continues to increase, resulting in the resistance-capacitance delay of the back-end process becoming the main factor limiting circuit performance. Since the resistivity of copper is smaller than that of aluminum, and copper has better resistance to electromigration than aluminum, the reliability of copper electromigration is a key factor in the performance of device circuits. Therefore, in the 65nm and below processes, the back-end process uses copper metal wiring and low dielectric constant films to a certain extent to effectively improve the resistance-capacitance delay. Among them, electromigration refers to the fact that when the device is working, a certain current passes through the metal wiring, and metal ions form mass transport along the conductor, which will cause voids in certain locations of the conductor. Electromigration can easily cause device short circuits or open circuits, etc., causing device failure. Compared with the aluminum process, the electromigration of the copper process is due to diffusion at the interface or surface. In the Damascus process of copper, the metal substrate has good adhesion to the conductor, thereby inhibiting the diffusion of the conductor through the dielectric within the layer. However, as Figure 1 As shown, after the copper-containing metal structure is grown by electroplating on the metal substrate, chemical mechanical polishing is required to remove excess copper on the surface, so that a thin layer of copper oxide (CuO) 101 is formed on the surface of the metal copper, wherein the copper metal structure also includes a copper metal layer 102, a barrier metal layer 103, an undoped silicate glass (USG) layer 104, a silicon carbon oxyhydride (SiCOH) layer 105 and a carbon-doped silicon nitride layer (NDC) 106, and the barrier metal layer 103 is composed of tantalum (Ta) or tantalum nitride (TaN).

[0038] Since the copper oxide layer 101 reduces the adhesion between the copper metal layer and the subsequent metal connection layer or passivation layer, and the copper oxide layer 101 is a channel for metal ions to diffuse at the interface, the device will undergo electromigration, which may cause device failure. According to the principle of electromigration, there are two electromigration modes in the copper process, such as Figure 2 As shown, including electrons from the copper metal layer M x-1 Flow into the metal connection layer 201 to the copper metal layer M x , and electrons from the copper metal layer M x Flow into the metal connection layer 201 to the copper metal layer M x-1 . When electrons from the copper metal layer M x-1 Flow into the metal connection layer 201 to the copper metal layer M x In the case of copper metal layer M x-1 A thin layer of copper oxide forms on the surface, then the copper metal layer M x-1 A hole 202 may be formed between the copper metal layer M and the metal connection layer 201. x The adhesion of the copper metal layer M to the passivation layer 203 is poor. x A hole 204 may be formed between the passivation layer 203 and the copper metal layer M. x Flow into the metal connection layer 201 to the copper metal layer M x-1 In the case of copper metal layer M x-1 A thin layer of copper oxide forms on the surface, then the copper metal layer M x-1Holes 205 may be formed between the metal connection layer 201. Among them, the passivation layer can be a carbon-doped silicon nitride layer (NDC). It should be noted that the electromigration occurring in the above situation causes holes in the product, resulting in a decrease in the anti-electromigration ability of the copper metal layer. In the related art, electromigration is weakened by depositing cobalt tungsten phosphide (CoWP), cobalt tin phosphide (CoSnP) or palladium (Pd) on the surface of the copper metal layer, but there are problems of high cost and complex process. Based on this, the present application provides a method for manufacturing a semiconductor device and a semiconductor device, which effectively removes copper oxide on the surface of the copper metal layer, and improves the adhesion between the copper metal layer and the passivation layer, so that the density of the passivation layer is improved, and the anti-electromigration ability of the copper metal layer is significantly improved.

[0039] Figure 3 A flowchart of a method for manufacturing a semiconductor device provided in an embodiment of the present application is shown in FIG. Figure 3 As shown, the manufacturing method comprises the following steps:

[0040] S101, providing a substrate, on which a copper-containing metal structure prepared based on a Damascus process is formed, wherein the copper-containing metal structure has been polished using a chemical mechanical polishing process.

[0041] The substrate may be a P-type substrate or an N-type substrate, and the specific substrate material may be silicon (Si), germanium (Ge), silicon germanium (SiGe), carbon silicon (SiC), carbon germanium silicon (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP), gallium nitride (GaN) or other III-V compounds, and a multilayer structure composed of the aforementioned semiconductor materials. In addition, it may also be silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI) and germanium on insulator (GeOI), or double-side polished silicon wafers (Double Side Polished Wafers, DSP), etc., and the present application embodiment is not limited here. The Damascus process is a process for realizing multi-layer metal interconnection on a dielectric layer through specific steps. In the embodiment of the present application, the Damascus process is used to prepare a copper metal interconnection layer. The copper-containing metal structure is a semiconductor structure obtained by electrochemical copper plating in the Damascus process and grinding by a chemical mechanical polishing process. It should be noted that since the chemical mechanical polishing process uses a chemical grinding liquid, after the grinding process is completed, some residual chemical grinding liquid will exist on the surface of the copper metal layer. At the same time, a thin layer of copper oxide is formed on the surface of the copper metal layer. In one embodiment, the semiconductor structure provided in step S101 can refer to Figure 4The semiconductor structure includes a copper oxide layer 301, a copper metal layer 302, a barrier metal layer 303, an undoped silicate glass layer 304, a silicon carbon oxyhydride layer 305, and a carbon-doped silicon nitride layer 306, wherein the barrier metal layer 303 is composed of tantalum or tantalum nitride. Of course, in order to facilitate the understanding of the present invention, Figure 4 This is an example of a schematic diagram of the cross-sectional structure of the semiconductor structure provided in step S101 of the manufacturing method provided in an embodiment of the present application. There may be other suitable examples, and the present invention is not limited thereto.

[0042] S102, using a first plasma to perform a reduction treatment on the surface of the copper-containing metal structure after the grinding treatment.

[0043] Wherein, step S102 is to process the copper oxide layer on the surface of the copper-containing metal structure by chemical vapor deposition using plasma. In one embodiment, the flow rate of the first plasma can be 500 sccm to 2000 sccm, and the first plasma can be hydrogen (H 2 ) or ammonia (NH 3 ), which is used to reduce the copper oxide layer on the surface of the copper metal layer to metallic copper. In one embodiment, the first plasma can be used to reduce the surface of the copper-containing metal structure after the grinding treatment, and the corresponding process temperature can be set to 300°C to 400°C. In addition, the chemical grinding liquid remaining on the surface of the copper metal layer can also be sucked away by the process machine along with the reaction gas after the first plasma completes the surface treatment for a preset time, so as to avoid the residual chemical grinding liquid affecting the subsequent process. In one embodiment, the semiconductor structure provided in step S102 can refer to Figure 5 The semiconductor structure includes a copper metal layer 302, a barrier metal layer 303, an undoped silicate glass layer 304, a silicon carbon oxyhydride layer 305, and a carbon-doped silicon nitride layer 306. The barrier metal layer 303 is composed of tantalum or tantalum nitride. Of course, in order to facilitate the understanding of the present invention, Figure 5 This is an example of a schematic diagram of the cross-sectional structure of the semiconductor structure provided in step S102 of the manufacturing method provided in an embodiment of the present application. There may be other suitable examples, and the present invention is not limited thereto.

[0044] S103 , introducing a second plasma into the surface of the copper-containing metal structure after the reduction treatment to form a compound layer on the surface of the copper-containing metal structure.

[0045] In one embodiment, the flow rate of the second plasma may be 50 sccm to 300 sccm, and the second plasma may be silicon tetrahydride gas (SiH 4 ), correspondingly, the compound layer formed on the surface of the copper-containing metal structure may include a copper-silicon compound (CuSi x). In one embodiment, when the second plasma is introduced into the surface of the copper-containing metal structure after the reduction treatment, the corresponding process temperature can be 200°C to 350°C. It should be noted that according to thermodynamic research, the bonding enthalpy of the copper-silicon (Cu-Si) bond is about -220 kJ / mol. Combined with the copper-silicon binary phase diagram, at a suitable process temperature, silicon tetrahydride gas can react with copper to form a copper-silicon compound. In one embodiment, the semiconductor structure provided in step S103 can refer to Figure 6 The semiconductor structure includes a copper metal layer 302, a barrier metal layer 303, an undoped silicate glass layer 304, a silicon carbon oxyhydride layer 305, a carbon-doped silicon nitride layer 306, and a compound layer 307. The barrier metal layer 303 is composed of tantalum or tantalum nitride, and the compound layer 307 can be a copper silicon compound layer. Of course, in order to facilitate the understanding of the present invention, Figure 6 This is an example of a schematic diagram of the cross-sectional structure of the semiconductor structure provided in step S103 of the manufacturing method provided in an embodiment of the present application. There may be other suitable examples, and the present invention is not limited thereto.

[0046] S104 , introducing a third plasma into the surface of the compound layer to transform the compound layer into a mixed compound layer.

[0047] Among them, since the compound layer formed on the surface of the copper-containing metal structure may cause the resistance of the final product to increase and affect the product performance, the compound layer can be converted into a mixed compound layer by passing a third plasma into the surface of the compound layer, thereby maintaining the resistance of the product at the original level and ensuring the product performance. At the same time, converting the compound layer into a mixed compound layer can enhance the adhesion with the passivation layer. In one embodiment, the flow rate of the third plasma is 500sccm to 2000sccm, and the third plasma can be ammonia (NH 3 ), correspondingly, the mixed compound layer includes a copper silicon compound (CuSi x ), copper nitride (CuN x ) and silicon nitride (SiN x In one embodiment, when the third plasma is introduced into the surface of the compound layer, the corresponding process temperature may be 300° C. to 400° C. It should be noted that the N -The ions can combine with the copper and silicon atoms in the copper silicon compound to form copper-nitrogen (Cu-N) bonds and silicon-nitrogen (Si-N) bonds. Therefore, the copper silicon compound layer can be converted into a structure in which copper silicon compound, copper nitrogen compound and silicon nitrogen compound coexist. Part of the copper silicon compound in the original copper silicon compound layer is replaced by copper nitrogen compound and silicon nitrogen compound, which can effectively suppress the increase of resistance. In addition, silicon nitrogen compound can compensate for the dangling bonds in the copper silicon compound, making the mixed compound layer more compact. In one embodiment, the semiconductor structure provided in step S104 can refer to Figure 7 The semiconductor structure includes a copper metal layer 302, a barrier metal layer 303, an undoped silicate glass layer 304, a silicon carbon oxyhydride layer 305, a carbon-doped silicon nitride layer 306, and a mixed compound layer 308. The barrier metal layer 303 is composed of tantalum or tantalum nitride, and the mixed compound layer 308 may include copper silicon compound, copper nitrogen compound, and silicon nitrogen compound. Of course, in order to facilitate the understanding of the present invention, Figure 7 This is an example of a schematic diagram of the cross-sectional structure of the semiconductor structure provided in step S104 of the manufacturing method provided in an embodiment of the present application. There may be other suitable examples, and the present invention is not limited thereto.

[0048] S105 , depositing a passivation layer and an oxide isolation layer in sequence on the mixed compound layer.

[0049] In one embodiment, when the passivation layer and the oxide isolation layer are sequentially deposited on the mixed compound layer, the corresponding process temperature may be 350°C to 400°C. In one embodiment, the passivation layer may be a carbon-doped silicon nitride layer, and the oxide isolation layer may be a silicon carbon oxyhydride layer with a low dielectric constant. After the passivation layer and the oxide isolation layer are deposited, the subsequent related process steps may be continued to obtain the final semiconductor device. In one embodiment, the semiconductor structure provided in step S105 may refer to Figure 8 The semiconductor structure includes a copper metal layer 302, a barrier metal layer 303, an undoped silicate glass layer 304, a silicon carbon oxyhydride layer 305, a carbon-doped silicon nitride layer 306, a mixed compound layer 308, a passivation layer 309 and an oxide isolation layer 310. The barrier metal layer 303 is composed of tantalum or tantalum nitride, and the mixed compound layer 308 may include copper silicon compound, copper nitrogen compound and silicon nitrogen compound. Of course, in order to facilitate the understanding of the present invention, Figure 8 This is an example of a schematic diagram of the cross-sectional structure of the semiconductor structure provided in step S105 of the manufacturing method provided in an embodiment of the present application. There may be other suitable examples, and the present invention is not limited thereto.

[0050] In the above, by providing a substrate, a copper-containing metal structure prepared based on the Damascus process is formed on the substrate, wherein the copper-containing metal structure has been ground using a chemical mechanical polishing process; the surface of the copper-containing metal structure after the grinding process is reduced using a first plasma; a second plasma is introduced into the surface of the copper-containing metal structure after the reduction process to form a compound layer on the surface of the copper-containing metal structure; a third plasma is introduced into the surface of the compound layer to convert the compound layer into a mixed compound layer; a passivation layer and an oxide isolation layer are sequentially deposited on the mixed compound layer. In the above scheme, the surface of the copper-containing metal structure after the grinding process is reduced using the first plasma to effectively reduce copper oxide to copper, and by converting the compound layer into a mixed compound layer, compared with the compound layer, the adhesion of the mixed compound layer to the copper-containing metal structure and the adhesion of the mixed compound layer to the passivation layer are enhanced, which can effectively improve the anti-electromigration ability of the copper metal layer.

[0051] The present application also provides a semiconductor device, which adopts any of the above-mentioned manufacturing methods to prepare a copper-containing semiconductor structure. The semiconductor device can also achieve the technical effects that can be achieved by the manufacturing method in the above-mentioned embodiment, which will not be described in detail here.

[0052] In one embodiment, a control experiment can be set up to perform an electromigration test on a packaged semiconductor device, wherein the experimental sample is a copper-containing semiconductor structure prepared by applying the manufacturing method of a semiconductor device provided in the embodiment of the present application, and the control sample is a copper-containing metal structure that has been polished using a chemical mechanical polishing process, and a passivation layer is directly deposited on the surface of the copper metal layer. Fig. 9 As shown in Figure 1, the relative resistance degradation of 15 control samples at 325°C over time was tested. In the case of a total test time of 106 hours, a total of 3 control samples failed. Since the control samples deposited the passivation layer directly on the surface of the copper metal layer, the adhesion between the copper metal surface and the passivation layer was reduced due to the influence of the copper oxide layer, as shown in Figure 1. Fig.10 As shown in the figure, transmission electron microscopy can be used to find that holes are generated at the connection between the copper metal layer and the metal connection layer. The reason for this phenomenon is that electromigration occurs, which greatly increases the failure rate of the control sample. Fig.11 As shown in the figure, the relative resistance degradation of 15 experimental samples at 325°C over time was tested. In the case of a total test time of 450 hours, only one experimental sample failed. Fig.12 As shown, through a transmission electron microscope, it can be found that no holes are generated between the copper metal layer and the metal connection layer, no holes are generated between the copper metal layer and the passivation layer, and no electromigration occurs.

[0053] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0054] Note that the above are only preferred embodiments of the present invention and the technical principles used. Those skilled in the art will understand that the present invention is not limited to the specific embodiments herein, and that various obvious changes, readjustments and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in more detail through the above embodiments, the present invention is not limited to the above embodiments, and may include more other equivalent embodiments without departing from the concept of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: include: Providing a substrate, on which a copper-containing metal structure prepared based on a Damascus process is formed, wherein the copper-containing metal structure has been polished using a chemical mechanical polishing process; Using a first plasma to perform a reduction treatment on the surface of the copper-containing metal structure after the grinding treatment; Passing a second plasma onto the surface of the copper-containing metal structure after the reduction treatment to form a compound layer on the surface of the copper-containing metal structure; Passing a third plasma into the surface of the compound layer to convert the compound layer into a mixed compound layer; A passivation layer and an oxide isolation layer are sequentially deposited on the mixed compound layer.

2. The manufacturing method according to claim 1, characterized in that: The flow rate of the first plasma is 500 sccm to 2000 sccm, and the first plasma is hydrogen or ammonia.

3. The manufacturing method according to claim 1, characterized in that: When the first plasma is used to perform reduction treatment on the surface of the copper-containing metal structure after the grinding treatment, the corresponding process temperature is set to 300° C. to 400° C.

4. The manufacturing method according to claim 1, characterized in that: The flow rate of the second plasma is 50 sccm to 300 sccm, the second plasma is silicon hydride gas, and the compound layer includes copper silicon compound.

5. The manufacturing method according to claim 1, characterized in that: When the second plasma is introduced into the surface of the copper-containing metal structure after the reduction treatment, the corresponding process temperature is set to 200° C. to 350° C.

6. The manufacturing method according to claim 1, characterized in that: The flow rate of the third plasma is 500 sccm-2000 sccm, the third plasma is ammonia gas, and the mixed compound layer includes copper silicon compound, copper nitrogen compound and silicon nitrogen compound.

7. The manufacturing method according to claim 1, characterized in that: When the third plasma is introduced into the surface of the compound layer, the corresponding process temperature is set to 300° C. to 400° C.

8. The manufacturing method according to claim 1, characterized in that: While the passivation layer and the oxide isolation layer are sequentially deposited on the mixed compound layer, the corresponding process temperature is set to 350° C. to 400° C.

9. The manufacturing method according to claim 1, characterized in that: The passivation layer is a carbon-doped silicon nitride layer, and the oxide isolation layer is a silicon carbon oxyhydride layer.

10. A semiconductor device, characterized in that: The copper-containing semiconductor structure is prepared by the manufacturing method described in any one of claims 1 to 9.

Images