Semiconductor package structure and integrated circuit package

Abstract

The invention relates to the field of semiconductors, and discloses a semiconductor packaging structure and an integrated circuit packaging piece, and the semiconductor packaging structure comprises a first packaging seat which comprises a first heat exchange channel and is used for carrying out the heat exchange of a first semiconductor device; the second packaging seat is arranged opposite to the first packaging seat, and the second packaging seat comprises a second heat exchange channel and exchanges heat for the second semiconductor device; the wall part is arranged between the first packaging seat and the second packaging seat, and an airtight containing cavity is defined by the wall part. The semiconductor packaging structure and the integrated circuit packaging piece are used for solving the problem that the heat dissipation effect of the packaging structure is poor, according to the semiconductor packaging structure and the integrated circuit packaging piece, the first packaging base and the second packaging base which are oppositely arranged are provided with the first heat exchange channel and the second heat exchange channel respectively, heat exchange is conducted on semiconductor devices installed on the first packaging base and the second packaging base respectively, and the heat dissipation efficiency is improved. The heat exchange effect of the airtight semiconductor packaging structure is improved, a stable working environment is provided for the semiconductor device, and the service life of the semiconductor device is prolonged.

Description

Technical Field

[0001] The present application belongs to the field of semiconductors, and in particular to a semiconductor packaging structure and an integrated circuit package. Background Art

[0002] Semiconductor packaging structure is a structural form that encapsulates microelectronic components or chips in a protective shell. It not only provides physical support and protection for the chip, but also provides support for the connection, heat dissipation and other functions of the semiconductor chip. Semiconductor packaging structure types include dual in-line package (DIP package), quad flat package (QFP package), plastic leaded chip carrier (PLCC package), ball grid array package (BGA package) and chip scale package (CSP package).

[0003] However, the existing semiconductor device packaging mostly uses single-side heat dissipation, which has poor heat dissipation effect and affects the service life of the semiconductor device. Summary of the invention

[0004] The embodiments of the present application provide a semiconductor packaging structure and an integrated circuit package, which can improve the heat dissipation effect of the semiconductor device and increase the service life of the semiconductor device.

[0005] In a first aspect, an embodiment of the present application provides a semiconductor packaging structure, comprising: a first packaging seat for mounting a first semiconductor device, the first packaging seat comprising a first heat exchange channel for exchanging heat for the first semiconductor device; a second packaging seat, arranged opposite to the first packaging seat, for mounting a second semiconductor device, the second packaging seat comprising a second heat exchange channel for exchanging heat for the second semiconductor device; a wall portion, arranged between the first packaging seat and the second packaging seat, enclosing to form an airtight accommodating cavity, the accommodating cavity being used to accommodate the first semiconductor device and the second semiconductor device.

[0006] According to the semiconductor packaging structure provided by the embodiment of the present application, the wall portion includes a first side wall and a second side wall that are oppositely arranged, the first side wall is arranged around the circumference of the first packaging seat, and the second side wall is arranged around the circumference of the second packaging seat.

[0007] According to the semiconductor packaging structure provided by the embodiment of the present application, the first side wall includes a first body wall and a first metal strip, the first metal strip is arranged on the side of the first body wall facing away from the first packaging seat, and is annularly closed along the first body wall, and the first metal strip is welded to the second side wall.

[0008] According to the semiconductor packaging structure provided by the embodiment of the present application, the second side wall includes a second main body wall and a second metal strip, the second metal strip is arranged on the side of the second main body wall facing away from the second packaging seat, and is annularly closed along the second main body wall, and the second metal strip is staggered, inserted and welded with the first metal strip.

[0009] The semiconductor packaging structure provided according to an embodiment of the present application further includes an insulating tape, which is placed between the first body wall and the second body wall and on the side of the first metal tape facing away from the accommodating cavity; wherein the first packaging seat, the second packaging seat, and the wall portion are all made of insulating materials.

[0010] According to the semiconductor packaging structure provided in an embodiment of the present application, the first packaging seat includes a multi-layer heat exchange layer and a substrate stacked along the thickness direction, the substrate is placed between the multi-layer heat exchange layer and the accommodating cavity, and is used to install the first semiconductor device, and the first heat exchange channel is arranged in the heat exchange layer.

[0011] According to the semiconductor packaging structure provided by the embodiment of the present application, the heat exchange layer includes a spoiler structure, which points from the substrate to a direction away from the accommodating cavity, and the density of the spoiler structure of the multi-layer heat exchange layer shows a decreasing trend.

[0012] According to the semiconductor packaging structure provided in the embodiment of the present application, the multi-layer heat exchange layer includes a centralized heat exchange layer and a diffusion heat exchange layer, the centralized heat exchange layer is placed between the substrate and the diffusion heat exchange layer, the centralized heat exchange layer is used to perform local heat exchange on the area where the first semiconductor device is located, and the diffusion heat exchange layer is used to perform comprehensive heat exchange on the substrate.

[0013] According to the semiconductor packaging structure provided in the embodiment of the present application, the concentrated heat exchange layer includes a heat exchange area and an isolation area arranged along the layer extension direction, the isolation area is protruding relative to the heat exchange area, and is surrounded to form the heat exchange area, the heat exchange area is used to be arranged opposite to the area where the first semiconductor device is located, the spoiler structure is arranged in the heat exchange area, and the spoiler structures are arranged at intervals to form the first heat exchange channel along the flow direction of the heat exchange medium.

[0014] According to the semiconductor packaging structure provided by the embodiment of the present application, the diffusion heat exchange layer includes a first heat exchange layer and a second heat exchange layer stacked along the thickness direction, the first heat exchange layer and the second heat exchange layer both include the spoiler structure spaced apart along the layer span direction, and the spacing of the spoiler structure of the first heat exchange layer is smaller than the spacing of the spoiler structure of the second heat exchange layer.

[0015] In the second aspect, an embodiment of the present application also provides an integrated circuit package, comprising: a first semiconductor device, a second semiconductor device, a terminal assembly and the above-mentioned semiconductor packaging structure, the first semiconductor device is installed on the first packaging seat, the second semiconductor device is installed on the second packaging seat, and the terminals of the terminal assembly are electrically connected to the first semiconductor device and the second semiconductor device, respectively, and extend through the semiconductor packaging structure.

[0016] According to the integrated circuit package provided in the embodiment of the present application, the first semiconductor device constitutes a first half-bridge circuit, the second semiconductor device constitutes a second half-bridge circuit, and the first semiconductor device and the second semiconductor device constitute a full-bridge circuit through the electrical connection of the terminal assembly.

[0017] According to the integrated circuit package provided in the embodiment of the present application, the terminal assembly includes an input terminal group and an output terminal group along two opposite sides of the semiconductor package structure and extending in opposite directions, the output terminal group includes a first output terminal and a second output terminal, the first output terminal is connected to the first semiconductor device, the second output terminal is connected to the second semiconductor device, and the first output terminal and the second output terminal are staggered.

[0018] According to the integrated circuit package provided by the embodiment of the present application, the input terminal group includes a pair of first input terminals and a pair of second input terminals arranged at intervals, the pair of first input terminals are respectively connected to the first semiconductor device and the second semiconductor device and are arranged opposite to each other, and the pair of second input terminals are respectively connected to the first semiconductor device and the second semiconductor device and are arranged opposite to each other.

[0019] The semiconductor packaging structure and integrated circuit package of the embodiments of the present application respectively provide a first heat exchange channel and a second heat exchange channel on the relatively arranged first packaging seat and the second packaging seat, thereby achieving separate heat exchange for the semiconductor devices mounted thereon, improving the heat exchange effect of the airtight semiconductor packaging structure, providing a stable working environment for the semiconductor devices, and increasing the service life of the semiconductor devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solution of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0021] Figure 1 A schematic diagram of a semiconductor packaging structure provided by some embodiments of the present application is shown;

[0022] Figure 2An example is shown Figure 1 A top view of

[0023] Figure 3 Show Figure 2 The cross-section along the AA direction;

[0024] Figure 4 A schematic structural diagram of a first side wall provided in some embodiments of the present application is shown;

[0025] Figure 5 An exploded schematic diagram of a semiconductor package structure provided by some embodiments of the present application is shown;

[0026] Figure 6 An example is shown Figure 4 Explosion diagram of

[0027] Figure 7 A schematic diagram of the structure of a concentrated heat exchange layer provided in some embodiments of the present application is shown;

[0028] Figure 8 A distribution diagram of the turbulence structure of the first heat exchange layer provided in some embodiments of the present application is shown;

[0029] Fig. 9 A distribution diagram of the turbulence structure of the second heat exchange layer provided in some embodiments of the present application is shown;

[0030] Fig.10 An example is shown Figure 1 main view.

[0031] Reference numerals:

[0032] 100: first packaging seat; 101: isolation area; 102: heat exchange area; 103: spoiler structure; 110: diffusion heat exchange layer; 111: substrate; 112: concentrated heat exchange layer; 113: first heat exchange layer; 114: second heat exchange layer; 200: second packaging seat;

[0033] 300: wall; 301: airtight accommodating chamber; 302: insulating tape; 310: first side wall; 311: first body wall; 312: first metal tape; 320: second side wall; 321: second body wall; 322: second metal tape;

[0034] 401: first input terminal; 402: second input terminal; 403: first output terminal; 404: second output terminal; 405: driving terminal; 410: first semiconductor device; 420: second semiconductor device; 430: terminal assembly; 431: input terminal group; 432: output terminal group. DETAILED DESCRIPTION

[0035] The features and exemplary embodiments of various aspects of the present application will be described in detail below. In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain the present application, rather than to limit the present application. For those skilled in the art, the present application can be implemented without the need for some of these specific details. The following description of the embodiments is only to provide a better understanding of the present application by illustrating the examples of the present application.

[0036] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the statement "include..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0037] Taking chips as an example, semiconductor devices generate a lot of heat when performing high-speed calculations and data processing. This heat mainly comes from the switching operation of transistors inside the chip and the resistance heat generated when current passes through the conductor. Chips are composed of many tiny electronic components, which are very sensitive to temperature. As the temperature rises, the performance of electronic components will decline, and may even reach their physical limits, causing the chip to fail or be damaged. Long-term high-temperature operation will also accelerate the aging process of the chip and shorten its service life. Therefore, it is necessary to dissipate heat from the chip to take away the heat generated by the chip in time to prevent heat from accumulating inside the chip. Through heat dissipation, it is possible to ensure that the chip operates within a safe temperature range, thereby maintaining its optimal performance and stability. Effective heat dissipation can also improve the reliability and durability of the chip and extend its service life.

[0038] Existing chip packaging structures include airtight packaging and non-airtight packaging. Non-airtight packaging includes an open frame, which can protect the chip from damage by foreign substances while ensuring proper heat dissipation to maintain the stable performance of the chip. Common non-airtight packaging methods include SOIC packaging, QFN packaging, and BGA packaging. However, for some special chips or special application scenarios, the chip requires higher airtightness to prevent moisture, dust and corrosion. Therefore, airtight packaging is used to ensure the stable electrical performance of the chip, reduce noise interference and extend service life. Better adapt to harsh environments such as high temperature, high pressure, low temperature, vibration and impact.

[0039] At present, the heat dissipation effect of existing airtight packaged chips is limited, which seriously restricts the development of chips towards high power density.

[0040] In order to solve the problems in the prior art, the embodiments of the present application provide a semiconductor packaging structure and an integrated circuit package. The semiconductor packaging structure provided by the embodiments of the present application is first introduced below.

[0041] Figure 1 shows a schematic structural diagram of a semiconductor packaging structure provided by some embodiments of the present application, Figure 2 An example is shown Figure 1 A top view of Figure 3 Show Figure 2 Cross-section along AA direction.

[0042] like Figures 1 to 3 As shown, an embodiment of the present application provides a semiconductor packaging structure, including: a first packaging seat 100, used to install a first semiconductor device 410, the first packaging seat 100 includes a first heat exchange channel, used to exchange heat for the first semiconductor device 410; a second packaging seat 200, arranged opposite to the first packaging seat 100, used to install a second semiconductor device 420, the second packaging seat 200 includes a second heat exchange channel 120, and exchanges heat for the second semiconductor device 420; a wall portion 300, arranged between the first packaging seat 100 and the second packaging seat 200, enclosing to form an airtight accommodating cavity 301, the accommodating cavity is used to accommodate the first semiconductor device 410 and the second semiconductor device 420.

[0043] The first package seat 100 and the second package seat 200 can be a simple structure such as a separate cuboid or cylinder, or a complex structure composed of simple structures such as a cuboid or cylinder, which is not limited in the embodiments of the present application. In some embodiments, the first package seat 100 can be connected to the wall portion 300 to form a hollow structure with one end open, and the second package seat 200 is a plate-like structure. After the first semiconductor device 410 and the second semiconductor device 420 are installed, the wall portion 300 is covered and connected with the second package seat 200, and the first package seat 100, the wall portion 300, and the second package seat 200 jointly define an airtight accommodating cavity for accommodating the first semiconductor device 410 and the second semiconductor device 420. Alternatively, the first package seat 100 and the second package seat 200 are both plate-like structures. After the first semiconductor device 410 and the second semiconductor device 420 are installed, the wall portion 300 is respectively connected to the first package seat 100 and the second package seat 200 to form an airtight accommodating cavity. The shape of the accommodating cavity can be square, rectangular, trapezoidal, circular or triangular, etc. The accommodating cavity may be evacuated or filled with an inert gas, and the inert gas may include one or more of nitrogen, helium, argon, etc. The first semiconductor device 410 and the second semiconductor device 420 together form a complete circuit structure, such as a full-bridge circuit structure.

[0044] The first packaging seat 100 exchanges heat with the first semiconductor device 410 by passing a heat exchange medium into the first heat exchange channel, and the second packaging seat 200 exchanges heat with the second semiconductor device 420 by passing a heat exchange medium into the second heat exchange channel. In the application embodiment, the inlet of the first heat exchange channel and the second heat exchange channel can be connected, and the outlet of the first heat exchange channel and the second heat exchange channel can be connected. The first heat exchange channel and the second heat exchange channel are passed with heat exchange mediums of the same temperature and the same material to achieve synchronous heat exchange, thereby ensuring uniform heat exchange of the first semiconductor device 410 and the second semiconductor device 420.

[0045] In other embodiments of the present application, the inlet and outlet of the first heat exchange channel and the second heat exchange channel are independently set, and heat exchange media with different temperatures and / or different materials can be introduced into the first heat exchange channel and the second heat exchange channel to achieve targeted heat exchange for the first semiconductor device 410 and the second semiconductor device 420, improve heat exchange efficiency, and improve adaptability, so that different first semiconductor devices 410 and second semiconductor devices 420 can maintain various suitable operating temperatures. The heat exchange medium can be selected as a gas heat exchange medium or a liquid heat exchange medium. The liquid heat exchange medium can be selected as water, oil, organic solvent, etc. The gas heat exchange medium can be selected as air, steam, etc.

[0046] The first heat exchange channel and the second heat exchange channel may be pipes or channels provided through partitions or other heat exchange structures, which are not limited in the present embodiment.

[0047] The embodiment of the present application achieves separate heat dissipation by respectively disposing a complete circuit structure on the first packaging seat 100 and the second packaging seat 200 of the packaging structure, thereby improving the heat dissipation effect of the airtight packaging structure and extending the service life of the semiconductor device.

[0048] like Figure 1 and Figure 3 As shown, in one embodiment of the present application, the wall portion 300 includes a first side wall 310 and a second side wall 320 that are oppositely disposed, the first side wall 310 is disposed around the circumference of the first packaging seat 100 , and the second side wall 320 is disposed around the circumference of the second packaging seat 200 .

[0049] The first side wall 310 and the first package seat 100 are connected as an integral structure for accommodating and installing the first semiconductor device 410. The first side wall 310 is in a closed ring shape, protruding from the first package seat 100, and the first side wall 310 is connected to the first package seat 100 to form a structure with an opening at one end. The second side wall 320 and the second package seat 200 are connected as an integral structure for accommodating and installing the second semiconductor device 420. The second side wall 320 is in a closed ring shape, protruding from the second package seat 200, and the second side wall 320 is connected to the second package seat 200 to form a structure with an opening at one end. The first side wall 310 and the second side wall 320 are arranged opposite to each other. After the semiconductor device is installed, they are further connected to make the first package seat 100 and the second package seat 200 become a whole. The first side wall 310 and the second side wall 320 can be fixedly connected or detachably connected. The first side wall 310 can protect the first semiconductor device 410 after the first semiconductor device 410 is installed, and the second side wall 320 can protect the second semiconductor device 420 after the second semiconductor device 420 is installed to prevent the semiconductor device from being damaged during the installation of the semiconductor device or the assembly of the package seat.

[0050] In order to improve the sealing performance between the first side wall 310 and the second side wall 320 , a sealing ring or a sealing structure may be provided between the first side wall 310 and the second side wall 320 .

[0051] Of course, the wall portion 300 may also be disposed in the inner space of at least one of the first side wall 310 and the second side wall 320 , as long as the requirements for accommodating the semiconductor device and heat exchange can be guaranteed.

[0052] Figure 4 A schematic structural diagram of a first side wall 310 provided in some embodiments of the present application is shown.

[0053] like Figure 3 and Figure 4In a specific embodiment of the present application, the first side wall 310 includes a first body wall 311 and a first metal strip 312. The first metal strip 312 is arranged on the side of the first body wall 311 facing away from the first packaging seat 100, and is annularly closed along the first body wall 311. The first metal strip 312 is welded to the second side wall 320.

[0054] The second side wall 320 is connected to the first metal belt 312 which is annularly closed by welding, which improves the sealing effect of the accommodating cavity. The second side wall 320 can be made of metal, so as to be directly welded to the first metal belt 312. Alternatively, the second side wall 320 is provided with a metal groove, and the first metal belt 312 is inserted into the metal groove to achieve welding between the metal groove and the first metal belt 312. The first metal belt 312 can be narrower than the wall thickness of the first body wall 311 along the wall thickness direction of the first body wall 311, so as to facilitate insertion into the second side wall 320.

[0055] The first metal strip 312 may also be as wide as the first body wall 311 and laid flat on the end surface of the first body wall 311 to increase welding firmness. The first metal strip 312 may be made of kovar, silver, copper or other weldable metals.

[0056] Furthermore, in some embodiments of the present application, the second side wall 320 includes a second main body wall 321 and a second metal strip 322. The second metal strip 322 is arranged on the side of the second main body wall 321 facing away from the second packaging seat 200, and is annularly closed along the second main body wall 321. The second metal strip 322 and the first metal strip 312 are staggered, inserted and welded.

[0057] In order to ensure insulation, the first side wall 310 and the second side wall 320 are usually made of insulating materials, and the insulating materials can be glass fiber, ceramics, plastics, etc. Therefore, the connection between the first side wall 310 and the second side wall 320 is achieved by welding the first metal strip 312 and the second metal strip 322. The material of the second metal strip 322 can be other weldable metals such as kovar, silver, copper, etc.

[0058] In order to improve the sealing effect, the first metal strip 312 and the second metal strip 322 are staggered and plugged in the thickness direction of the side wall, and they are in contact with each other after plugging, which is convenient for welding. For example, the height of the first metal strip 312 and the second metal strip 322 along the height direction of the side wall is consistent. When the first metal strip 312 contacts the second body wall 321, the second metal strip 322 also contacts the first body wall 311. Solder paste can be applied to the opposite side of the first metal strip 312 and the second metal strip 322, and welding and fixing can be achieved through reflow soldering. Alternatively, there is a height difference between the first metal strip 312 and the second metal strip 322, and the shorter one is placed on the outside of the back of the accommodating cavity, which is convenient for welding.

[0059] Figure 5 An exploded schematic diagram of a semiconductor packaging structure provided by some embodiments of the present application is shown.

[0060] like Figure 3 and Figure 5 In other optional embodiments of the present application, the semiconductor packaging structure also includes an insulating tape 302, which is placed between the first body wall 311 and the second body wall 321, and is placed on the side of the first metal tape 312 facing away from the accommodating cavity; wherein the first packaging seat 100, the second packaging seat 200, and the wall portion 300 are all made of insulating materials.

[0061] The material of the insulating tape 302 can be glass fiber, ceramic, plastic, etc. The insulating tape 302 is used to seal the welding point between the first metal tape 312 and the second side wall 320 or the first metal tape 312 and the second metal tape 322 to improve the sealing effect. In addition, the insulating tape 302 insulates the first metal tape 312 and / or the second metal tape 322 from the outside air, and at the same time forms a completely insulated semiconductor packaging structure with the first packaging seat 100, the second packaging seat 200, and the wall portion 300 of the insulating material, insulates the inside and outside of the receiving cavity, reduces or avoids stray inductance, and ensures the electrical stability of the semiconductor device in the receiving cavity.

[0062] Figure 6 An example is shown Figure 4 Schematic diagram of the explosion.

[0063] like Figure 3 and Figure 6 As shown, in some embodiments of the present application, the first packaging seat 100 includes a plurality of heat exchange layers and a substrate 111 stacked along the thickness direction. The substrate 111 is placed between the plurality of heat exchange layers and the accommodating cavity for installing the first semiconductor device 410. A first heat exchange channel is arranged in the heat exchange layer.

[0064] The multi-layer heat exchange layer dissipates heat for the first semiconductor device 410 mounted on the substrate 111. The substrate 111 includes a ceramic substrate 111, a metal substrate 111, a glass substrate 111, etc., such as a direct copper-clad ceramic substrate 111 (DBC board). The substrate 111 is used to electrically connect semiconductor devices, terminals and other structures. The first semiconductor device 410 can be connected to the substrate 111 through a sintered layer.

[0065] The multiple layers of heat exchange layers are stacked in the thickness direction, and the multiple layers of heat exchange layers can be separated by partitions. There is an independent first heat exchange channel between each layer of heat exchange layer. In an embodiment of the present application, the inlets of the multiple layers of heat exchange layers can be connected, and the outlets of the multiple layers of heat exchange layers can be connected, and heat exchange media with the same temperature are passed into the multiple layers of heat exchange layers. Alternatively, in some embodiments of the present application, the inlets and outlets of the multiple layers of heat exchange layers are connected end to end in sequence to improve the energy utilization rate of the heat exchange medium. Alternatively, the multiple layers of heat exchange layers have multiple inlets and one or more outlets. Multiple inlets correspond to one or more layers of heat exchange layers, and each inlet can pass heat exchange media with different temperatures or different flow rates. For example, the closer the heat exchange layer is to the substrate 111, the lower the temperature is, which improves the heat exchange efficiency. The inlet and outlet directions of the multiple heat exchange layers can be the same or different.

[0066] Continue to refer Figure 6 In other embodiments of the present application, the heat exchange layer includes a spoiler structure 103, which points from the substrate 111 to a direction away from the accommodating cavity, and the density of the spoiler structure 103 of the multi-layer heat exchange layer shows a decreasing trend.

[0067] The spoiler structure 103 causes the fluid to continuously change direction and speed during the flow process, increasing the contact time and area between the fluid and the surface of the heat exchange layer, which is beneficial to the transfer of heat. The density of the spoiler structure 103 of the multi-layer heat exchange layer is distributed in a gradient. The density of the spoiler structure 103 of the heat exchange layer closer to the substrate 111 is greater. The greater the density of the spoiler structure 103, the larger the heat exchange area, so that the heat exchange efficiency of the layer is higher. Then, the farther away from the substrate 111, the lower the heat exchange effect of the heat exchange medium. In order to reduce energy loss and reduce the inlet and outlet pressure drop, the density of the spoiler structure 103 of the heat exchange layer away from the substrate 111 is smaller. Among them, the spoiler structure 103 can be set in the first heat exchange channel, or the spoiler structure 103 forms multiple first heat exchange channels.

[0068] The spoiler structures 103 of the multiple heat exchange layers can be the same or different. For example, the spoiler structure 103 can be a simple structure such as a plate, cylinder, or needle, or a complex structure that is a combination or deformation of a plate, cylinder, or needle. This embodiment does not limit this.

[0069] Figure 7 A schematic structural diagram of the concentrated heat exchange layer 112 provided in some embodiments of the present application is shown.

[0070] like Figure 3 and Figure 7 As shown, in other embodiments of the present application, the multi-layer heat exchange layer includes a concentrated heat exchange layer 112 and a diffusion heat exchange layer 110. The concentrated heat exchange layer 112 is placed between the substrate 111 and the diffusion heat exchange layer 110. The concentrated heat exchange layer 112 is used to perform local heat exchange on the area where the first semiconductor device 410 is located, and the diffusion heat exchange layer 110 is used to perform comprehensive heat exchange on the substrate 111.

[0071] The first heat exchange channel of the concentrated heat exchange layer 112 is placed in a local area of ​​the concentrated heat exchange layer 112 to exchange heat with a local area of ​​the substrate 111. When the first heat exchange channel of the concentrated heat exchange layer 112 is opposite to the first semiconductor device 410, the first heat exchange channel exchanges heat with the first semiconductor device 410. Targeted heat exchange can improve heat exchange efficiency. In the embodiment of the present application, the concentrated heat exchange layer 112 can be provided with multiple local heat exchange areas 102, and the first heat exchange channel is placed in the local heat exchange area 102 to achieve local heat exchange at multiple high heat generation locations.

[0072] In order to ensure the working temperature of the entire substrate 111 , the first heat exchange channel of the diffusion heat exchange layer 110 facing away from the substrate 111 is evenly laid to the layer, so as to achieve uniform heat exchange for the entire substrate 111 .

[0073] Continue to refer Figure 6 In another embodiment of the present application, the concentrated heat exchange layer 112 includes a heat exchange area 102 and an isolation area 101 arranged along the layer extension direction. The isolation area 101 is protruded relative to the heat exchange area 102 and is surrounded to form the heat exchange area 102. The heat exchange area 102 is used to be arranged opposite to the area where the first semiconductor device 410 is located. The spoiler structure 103 is arranged in the heat exchange area 102, and the spoiler structure 103 is arranged at intervals to form a first heat exchange channel along the flow direction of the heat exchange medium.

[0074] The concentrated heat exchange layer 112 can be a box structure or a plate splicing structure. For example, the concentrated heat exchange layer 112 includes an upper plate, a lower plate and an end sealing plate. The end sealing plate is connected between the upper plate and the lower plate and is placed on two opposite sides or around. There is a gap between the upper plate and the lower plate. The upper plate and the lower plate are arranged with concave and convex to form a heat exchange area 102 and an isolation area 101. The heat exchange medium flows in the heat exchange area 102, and the first heat exchange channel is formed in the heat exchange area 102 through the spoiler structure 103 to improve the heat exchange efficiency. The concentrated heat exchange layer 112 can include multiple heat exchange areas 102, and the multiple heat exchange areas 102 are connected to each other.

[0075] Alternatively, in other embodiments, the concentrated heat exchange layer 112 also includes an intermediate plate, which is stacked between the upper plate and the lower plate and is fitted with the upper plate and the lower plate. The intermediate plate is hollowed out to form a heat exchange area 102, and the plate body of the intermediate plate is the isolation area 101.

[0076] The spoiler structure 103 may include a strip plate, which is extended along the flow direction of the heat exchange medium to form a plurality of first heat exchange channels. For example, the spoiler structure 103 may be continuously or segmentally arranged along the flow direction of the heat exchange medium.

[0077] Figure 8The distribution diagram of the spoiler structure 103 of the first heat exchange layer 113 provided in some embodiments of the present application is shown. Fig. 9 A distribution diagram of the spoiler structure 103 of the second heat exchange layer 114 provided in some embodiments of the present application is shown.

[0078] like Figure 6 , 8 As shown in Figures 9 and 9, in a specific embodiment of the present application, the diffusion heat exchange layer 110 includes a first heat exchange layer 113 and a second heat exchange layer 114 stacked in the thickness direction, and the first heat exchange layer 113 and the second heat exchange layer 114 both include spoiler structures 103 spaced apart in the layer span direction, and the spacing between the spoiler structures 103 of the first heat exchange layer 113 is smaller than the spacing between the spoiler structures 103 of the second heat exchange layer 114.

[0079] Among them, the first heat exchange layer 113 may include one or more layers of stacked structures, and the second heat exchange layer 114 may also include one or more layers of stacked structures. The spacing between the flow disturbance structures 103 of the first heat exchange layer 113 is small, which can strongly disturb the fluid at the beginning of entering the first heat exchange layer 113, so that the fluid quickly reaches a higher degree of turbulence, thereby improving the heat exchange efficiency. The spacing between the flow disturbance structures 103 of the second heat exchange layer 114 is relatively large. After the fluid passes through the strong disturbance of the first heat exchange layer 113, the fluid continues to be moderately disturbed to avoid excessive pressure loss caused by excessive turbulence of the fluid, while also ensuring a certain heat exchange effect. The first heat exchange layer 113 and the second heat exchange layer 114 stacked in the thickness direction can make the fluid experience different degrees of disturbance and heat exchange processes in different heat exchange layers, thereby realizing graded control of fluid flow and heat exchange.

[0080] The first heat exchange layer 113 and the second heat exchange layer 114 are separated by a partition, and a spoiler structure 103 is arranged between adjacent partitions. For example, the spoiler structure 103 may be a plate-shaped, cylindrical structure, etc. The radial dimension of the spoiler structure 103 of the first heat exchange layer 113 is smaller than the radial dimension of the second heat exchange layer 114, and the thickness of the first heat exchange layer 113 may be greater than the thickness of the second heat exchange layer 114.

[0081] like Figures 1 to 3 As shown, an embodiment of the present application also provides an integrated circuit package, including: a first semiconductor device 410, a second semiconductor device 420, a terminal assembly 430 and the semiconductor packaging structure of the above embodiment, the first semiconductor device 410 is installed on the first packaging seat 100, the second semiconductor device 420 is installed on the second packaging seat 200, and the terminals of the terminal assembly 430 are electrically connected to the first semiconductor device 410 and the second semiconductor device 420, respectively, and extend through the semiconductor packaging structure.

[0082] The connection method of the first semiconductor device 410 and the second semiconductor device 420 can be the same. Taking the first semiconductor device 410 as an example, the bottom (for example, the drain) of the first semiconductor device 410 is connected to the copper layer of the substrate 111 of the first package seat 100 through a sintering layer, and the top (for example, the source, the gate) of the first semiconductor device 410 is connected to the copper layer of the substrate 111 through a bonding wire or a clip.

[0083] The first semiconductor device 410 is heat exchanged through the first package seat 100, and the second semiconductor device 420 is heat exchanged through the second package seat 200, thereby improving the heat exchange efficiency of the integrated circuit package and extending the service life of the first semiconductor device 410 and the second semiconductor device 420. The first semiconductor device 410 and the second semiconductor device 420 are electrically connected through the terminal assembly 430 to form a circuit, such as a topological circuit structure.

[0084] Furthermore, in some embodiments of the present application, the first semiconductor device 410 constitutes a first half-bridge circuit, the second semiconductor device 420 constitutes a second half-bridge circuit, and the first semiconductor device 410 and the second semiconductor device 420 constitute a full-bridge circuit through the electrical connection of the terminal assembly 430.

[0085] The first half-bridge circuit and the second half-bridge circuit are respectively arranged on the first package seat 100 and the second package seat 200 in mirror symmetry. For example, the orthographic projection areas of the two bridge arms of the first half-bridge circuit on the first package seat 100 are equal, so that the electrical performance consistency between the bridge arms is better.

[0086] The heat exchange of multiple half-bridge circuits of the full-bridge circuit is realized through a packaging structure, thereby improving the heat exchange effect. Compared with multiple packaging structures of multiple half-bridge circuits, the integrated circuit package of the present application is smaller in size.

[0087] like Figure 2 As shown, in a specific embodiment of the present application, the terminal assembly 430 includes an input terminal group 431 and an output terminal group 432 on opposite sides of the packaging structure and extending in opposite directions, the output terminal group 432 includes a first output terminal 403 and a second output terminal 404, the first output terminal 403 is connected to the first semiconductor device 410, the second output terminal 404 is connected to the second semiconductor device 420, and the first output terminal 403 and the second output terminal 404 are staggered.

[0088] Fig.10 An example is shown Figure 1 main view.

[0089] like Figure 2 and Fig.10As shown, in the orthographic projection of the first output terminal 403 and the second output terminal 404 onto the extension plane where the substrate 111 of the second package holder 200 is located, the first output terminal 403 and the second output terminal 404 are spaced apart. In the orthographic projection of the first output terminal 403 and the second output terminal 404 onto the wall portion 300, the first output terminal 403 and the second output terminal 404 are spaced apart along the thickness direction, thereby forming a staggered arrangement of the first output terminal 403 and the second output terminal 404.

[0090] The input terminal group 431 and the output terminal group 432 are located on opposite sides, which reduces the possibility of line crossing and interference, and improves the stability and reliability of the circuit. The opposite extension direction helps to better plan the line direction during wiring, avoid line confusion, and make the layout of the entire circuit system neater and more reasonable.

[0091] The first output terminal 403 is connected to the first semiconductor device 410, and the second output terminal 404 is connected to the second semiconductor device 420, and the two are staggered, so that the risk of short circuit between the two output terminals when connected to the external circuit can be avoided. The staggered setting increases the electrical clearance and creepage distance between the terminals, improving safety. It is helpful to improve the electromagnetic compatibility of the system. Through the position and direction of the staggered setting, the generation of electromagnetic interference can be reduced and the anti-interference ability of the system can be improved.

[0092] For example, in a full bridge circuit, the input terminal group 431 includes a DC+ terminal and a DC- terminal. The first output terminal 403 of the output terminal group 432 may be a U terminal, and the second output terminal 404 may be a V terminal.

[0093] In addition, in an embodiment of the present application, the input terminal group 431 includes a pair of first input terminals 401 and a pair of second input terminals 402 that are spaced apart, the pair of first input terminals 401 are respectively connected to the first semiconductor device 410 and the second semiconductor device 420, and are arranged opposite to each other, and the pair of second input terminals 402 are respectively connected to the first semiconductor device 410 and the second semiconductor device 420, and are arranged opposite to each other.

[0094] One of the pair of first input terminals 401 passes through the first side wall 310, and the other first input terminal 401 passes through the second side wall 320. One of the pair of second input terminals 402 passes through the first side wall 310, and the other second input terminal 402 passes through the second side wall 320. The first conductive screw passes through the pair of first input terminals 401, and the second conductive screw passes through the pair of second input terminals 402, so that the two half-bridge circuits are connected to a full-bridge circuit and connected to the positive and negative poles of the power supply. The structure is reasonably arranged and easy to connect.

[0095] In addition, in the embodiment of the present application, the integrated circuit package further includes a driving terminal 405, which is connected to the copper layer of the substrate 111 to achieve electrical connection with the first semiconductor device 410 and the second semiconductor device 420, and the driving terminal 405 and the output terminal group 432 are placed on the same side of the semiconductor package structure. The driving terminal 405 receives a signal from the control circuit to accurately control the on and off time of each switch tube in the full-bridge circuit.

[0096] The above is only a specific implementation of the present application. Those skilled in the art can clearly understand that for the convenience and simplicity of description, the specific working processes of the systems, modules and units described above can refer to the corresponding processes in the aforementioned method embodiments, and will not be repeated here. It should be understood that the protection scope of the present application is not limited to this. Any technician familiar with the technical field can easily think of various equivalent modifications or replacements within the technical scope disclosed in this application, and these modifications or replacements should be included in the protection scope of this application.

Claims

1. A semiconductor packaging structure, characterized in that: include: A first packaging seat, used for mounting a first semiconductor device, wherein the first packaging seat comprises a first heat exchange channel, used for exchanging heat for the first semiconductor device; A second packaging seat, arranged opposite to the first packaging seat, for mounting a second semiconductor device, wherein the second packaging seat comprises a second heat exchange channel and exchanges heat for the second semiconductor device; The wall portion is disposed between the first packaging seat and the second packaging seat to enclose and form an airtight accommodating cavity, and the accommodating cavity is used to accommodate the first semiconductor device and the second semiconductor device.

2. The semiconductor package structure according to claim 1, wherein: The wall portion includes a first side wall and a second side wall that are oppositely disposed. The first side wall is disposed around a circumference connected to the first packaging seat, and the second side wall is disposed around a circumference connected to the second packaging seat.

3. The semiconductor package structure according to claim 2, characterized in that: The first side wall includes a first body wall and a first metal belt. The first metal belt is arranged on a side of the first body wall facing away from the first packaging seat and is annularly closed along the first body wall. The first metal belt is welded to the second side wall.

4. The semiconductor package structure according to claim 3, characterized in that: The second side wall includes a second body wall and a second metal belt, the second metal belt is arranged on a side of the second body wall facing away from the second packaging seat and is annularly closed along the second body wall, and the second metal belt is staggered, inserted and welded with the first metal belt.

5. The semiconductor package structure according to claim 4, characterized in that: Also included is an insulating tape, which is disposed between the first body wall and the second body wall and disposed on a side of the first metal tape facing away from the accommodating cavity; Wherein, the first packaging seat, the second packaging seat and the wall portion are all made of insulating materials.

6. The semiconductor package structure according to claim 1, wherein: The first packaging seat includes a plurality of heat exchange layers and a substrate stacked in a thickness direction. The substrate is placed between the plurality of heat exchange layers and the accommodating cavity for mounting the first semiconductor device. The first heat exchange channel is arranged in the heat exchange layer.

7. The semiconductor package structure according to claim 6, characterized in that: The heat exchange layer comprises a spoiler structure, which points from the substrate to a direction away from the accommodating cavity, and the density of the spoiler structure of the multi-layer heat exchange layer shows a decreasing trend.

8. The semiconductor package structure according to claim 7, characterized in that: The multi-layer heat exchange layer includes a concentrated heat exchange layer and a diffuse heat exchange layer. The concentrated heat exchange layer is placed between the substrate and the diffuse heat exchange layer. The concentrated heat exchange layer is used to perform local heat exchange on the area where the first semiconductor device is located, and the diffuse heat exchange layer is used to perform comprehensive heat exchange on the substrate.

9. The semiconductor package structure according to claim 8, characterized in that: The concentrated heat exchange layer includes a heat exchange area and an isolation area arranged along the layer span direction. The isolation area is protruding relative to the heat exchange area and is surrounded to form the heat exchange area. The heat exchange area is used to be arranged opposite to the area where the first semiconductor device is located. The spoiler structure is arranged in the heat exchange area, and the spoiler structure is arranged at intervals to form the first heat exchange channel along the flow direction of the heat exchange medium.

10. The semiconductor package structure according to claim 8, wherein: The diffusion heat exchange layer includes a first heat exchange layer and a second heat exchange layer stacked in the thickness direction. The first heat exchange layer and the second heat exchange layer both include the spoiler structure spaced apart in the layer span direction. The spacing of the spoiler structure of the first heat exchange layer is smaller than the spacing of the spoiler structure of the second heat exchange layer.

11. An integrated circuit package, characterized in that: include: A first semiconductor device, a second semiconductor device, a terminal assembly, and a semiconductor packaging structure as described in any one of claims 1 to 10, wherein the first semiconductor device is mounted on the first packaging seat, the second semiconductor device is mounted on the second packaging seat, and the terminals of the terminal assembly are electrically connected to the first semiconductor device and the second semiconductor device, respectively, and extend through the semiconductor packaging structure.

12. The integrated circuit package according to claim 11, wherein: The first semiconductor device forms a first half-bridge circuit, the second semiconductor device forms a second half-bridge circuit, and the first semiconductor device and the second semiconductor device form a full-bridge circuit through the electrical connection of the terminal assembly.

13. The integrated circuit package according to claim 11, wherein: The terminal assembly includes an input terminal group and an output terminal group along two opposite sides of the semiconductor package structure and extending in opposite directions. The output terminal group includes a first output terminal and a second output terminal. The first output terminal is connected to the first semiconductor device, and the second output terminal is connected to the second semiconductor device. The first output terminal and the second output terminal are staggered.

14. The integrated circuit package according to claim 13, wherein: The input terminal group includes a pair of first input terminals and a pair of second input terminals arranged at intervals, the pair of first input terminals are respectively connected to the first semiconductor device and the second semiconductor device and are arranged opposite to each other, and the pair of second input terminals are respectively connected to the first semiconductor device and the second semiconductor device and are arranged opposite to each other.

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