Display panel and display device

Abstract

The invention relates to a display panel and a display device. The display panel may include: a plurality of sub-pixels disposed on a substrate; an insulating layer disposed on the substrate, the insulating layer including at least one recessed portion in at least one sub-pixel among the plurality of sub-pixels; an anode electrode disposed on the insulating layer, the anode electrode not overlapping the recessed portion; a bank disposed on the anode electrode and a portion of an upper surface of the insulating layer, the bank having an opening in each of the plurality of sub-pixels; a light emitting layer disposed in the opening; and a cathode electrode disposed on the light emitting layer. Further, each of the light emitting layer and the cathode electrode overlaps the recessed portions of the anode electrode and the insulating layer in the opening, and the cathode electrode has at least one step portion in the opening of the bank.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a display panel and a display device. Background Art

[0002] A display device that displays various information on a screen is a key technology in the information and communication technology era, and is used to display various information in a display area.

[0003] In a display device, excellent display quality and luminous efficiency are desired. In particular, since display devices are tasked with using limited power according to the development of technology, the importance of luminous efficiency is increasing.

[0004] The light efficiency of a display device can be determined by the light-emitting element included in the display device. A display device including a light-emitting element having excellent light efficiency can also have excellent light efficiency. Therefore, as a method for improving the light efficiency of a display device, it can be considered to improve the light efficiency of the light-emitting element.

[0005] However, there are difficulties in improving the light efficiency of the light emitting element and reducing the power consumption of the display device. Therefore, there is a need for a display device having a sub-pixel configuration that can improve brightness and prevent light leakage while also reducing power consumption. Summary of the invention

[0006] Embodiments of the present disclosure are directed to a display panel and a display device having a structure capable of improving light extraction efficiency and simultaneously reducing or preventing a light leakage phenomenon.

[0007] Embodiments of the present disclosure are directed to a display panel and a display device in which one sub-pixel includes a plurality of light emitting regions emitting light of the same color, thereby enabling low-power driving through high brightness characteristics.

[0008] An embodiment of the present disclosure may provide a display panel, comprising: a substrate comprising a plurality of sub-pixels; an insulating layer, which is disposed on the substrate and comprises at least one recessed portion in at least one sub-pixel; an anode electrode, which is disposed on the insulating layer and does not overlap the recessed portion; a bank, which is disposed on a portion of an upper surface of the anode electrode and the insulating layer and has an opening in each of the plurality of sub-pixels; a light-emitting layer, which is disposed in the opening; and a cathode electrode, which is disposed on the light-emitting layer, wherein each of the light-emitting layer and the cathode electrode overlaps the anode electrode in the opening and the recessed portion of the insulating layer and has a step in the opening.

[0009] An embodiment of the present disclosure may provide a display panel, comprising: a substrate comprising a plurality of sub-pixels; an insulating layer, which is disposed on the substrate and comprises at least one recessed portion in at least one sub-pixel; an anode electrode, which is disposed on the insulating layer and does not overlap the recessed portion; a dam, which is disposed on a portion of an upper surface of the anode electrode and the insulating layer and has an opening in each of the plurality of sub-pixels; a light-emitting layer, which is disposed in the opening; and a cathode electrode, which is disposed on the light-emitting layer, wherein each of the light-emitting layer and the cathode electrode overlaps the anode electrode in the opening and the recessed portion of the insulating layer and has a circular recess in the opening.

[0010] An embodiment of the present disclosure may provide a display device comprising: a plurality of first non-luminous areas; a plurality of first luminous areas, the plurality of first luminous areas surrounding the first non-luminous areas; a second luminous area, the second luminous area surrounding the first luminous areas; and a second non-luminous area surrounding the second luminous area, wherein the plurality of first non-luminous areas, the plurality of first luminous areas, the second luminous areas and the second non-luminous areas are arranged in one sub-pixel, and wherein the plurality of first non-luminous areas, the plurality of first luminous areas and the second luminous areas are arranged in at least one of the opening of the embankment or the boundary of the opening.

[0011] According to the embodiments of the present disclosure, since the area corresponding to the opening of the bank includes a recessed portion and the recessed portion and the anode electrode do not overlap each other, a display panel and a display device capable of improving light extraction efficiency and reducing light leakage can be provided.

[0012] According to an embodiment of the present disclosure, since one sub-pixel has a structure including a plurality of light-emitting regions and a plurality of non-light-emitting regions, light efficiency can be improved, and thus a display panel and a display device capable of low-power driving and improved brightness can be provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The above and other objects, features and advantages of the present disclosure will become more apparent to those skilled in the art by describing in detail example embodiments of the present disclosure with reference to the accompanying drawings briefly described below.

[0014] Figure 1 is a schematic system configuration diagram of a display device according to an embodiment of the present disclosure.

[0015] Figure 2 is a plan view illustrating a partial region of a sub-pixel provided in a display region of a display panel according to an embodiment of the present disclosure.

[0016] FIG. 3A to FIG. 3C is a diagram illustrating a light emitting area of ​​a display device according to an embodiment of the present disclosure.

[0017] Figure 4A and Figure 4B According to the embodiment of the present disclosure, Figure 2 A cross-sectional view taken along line AB.

[0018] Figure 5A and Figure 5B According to the embodiment of the present disclosure, Figure 2 A cross-sectional view taken along line CD.

[0019] Fig. 6A According to the embodiment of the present disclosure, Figure 3B and Figure 3C A cross-sectional view taken along line a-a'.

[0020] Figure 6B According to the embodiment of the present disclosure, Figure 3B and Figure 3C A cross-sectional view taken along line b-b'.

[0021] Figure 7 is a diagram illustrating a planar structure of four sub-pixels of a display device according to an embodiment of the present disclosure.

[0022] Figure 8 1 is a diagram illustrating a cross-sectional structure of opening regions of banks of four sub-pixels, a plurality of light-emitting regions, and one non-light-emitting region in a display device according to an embodiment of the present disclosure.

[0023] Fig.9A and Fig. 9B According to the embodiment of the present disclosure, Figure 7 A cross-sectional view taken along line EF.

[0024] Figures 10 to 12 are diagrams each illustrating a planar structure of a region corresponding to an opening of a bank provided in at least one sub-pixel in a display region of a display panel according to an embodiment of the present disclosure.

[0025] Fig.13 is a plan view illustrating the shape of a mask used to manufacture a planar structure of a region corresponding to an opening of a bank provided in at least one sub-pixel in a display region of a display panel according to an embodiment of the present disclosure.

[0026] Fig.14 and Fig.15 is a graph comparing characteristics of light emitted from one sub-pixel of a display panel according to an embodiment of the present disclosure with characteristics of light emitted from one sub-pixel of a display panel according to a comparative example.

[0027] Figures 16 to 20 is a diagram schematically showing a manufacturing process of a display panel according to an embodiment of the present disclosure.

[0028] Fig.21 and Fig. 22 are diagrams each showing a cross-sectional structure of a display panel according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0029] In the following description of examples or embodiments of the present disclosure, drawings in which specific examples or embodiments that can be implemented are shown by way of example are described, and wherein the same reference numerals and symbols, even if shown in drawings that are different from each other, can also be used to specify the same or similar components. In addition, in the following description of examples or embodiments of the present disclosure, when it is determined that the detailed description of the known functions and components incorporated herein may make the subject matter in some embodiments of the present disclosure less clear, the description will be omitted or briefly provided. Terms such as "including", "having", "comprising", "consisting of", "consisting of", and "formed of" used herein are generally intended to allow the addition of other components unless the term is used together with the term "only". As used herein, unless the context clearly indicates otherwise, the singular form is intended to include the plural form.

[0030] Terms such as "first", "second", "A", "B", "(A)" or "(B)" may be used herein to describe elements of the present disclosure. Each of these terms is not used to define the nature, order, sequence or quantity of the elements, etc., but is only used to distinguish the corresponding element from other elements.

[0031] When it is mentioned that a first element is “connected or coupled to”, “contacts or overlaps”, etc. a second element, it is generally interpreted that not only the first element may be “directly connected or coupled to” or “directly contact or overlaps” the second element, but also a third element may be “interposed” between the first and second elements, or the first and second elements may be “connected or coupled to”, “contacts or overlaps”, etc. each other via a fourth element. Here, the second element may be included in at least one element of two or more elements that are “connected or coupled to”, “contacts or overlaps”, etc. each other.

[0032] When time-related terms such as "after", "subsequently", "immediately following", "before", etc. are used to describe a process or operation of an element or configuration, or a flow or step in an operation, process, or manufacturing method, these terms may be used to describe non-continuous or non-sequential processes or operations, unless the term "immediately" or "immediately" is used together.

[0033] In addition, when any dimension, relative size, etc. is mentioned, even if no relevant description is specified, it can be considered that the numerical value or corresponding information (e.g., level, range, etc.) of the element or feature includes a tolerance or error range that may be caused by various factors (e.g., process factors, internal impact or external impact, noise, etc.). In addition, the term "may" fully encompasses all meanings of the term "can".

[0034] The features of the various embodiments of the present disclosure may be coupled or combined with each other in part or in whole, and may be interlocked and operated in technically various ways, and these embodiments may be performed independently or in association with each other.

[0035] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0036] Figure 1 is a schematic system configuration diagram of a display device according to an embodiment of the present disclosure.

[0037] The display device according to the embodiment of the present disclosure may include: a display device 100 , a lighting device, a light-emitting device, and the like.

[0038] Hereinafter, for convenience of explanation, the display device 100 will be mainly described. However, in addition to the display device 100, the display device may be identically or substantially identically applied to various other display devices such as a lighting device and a light emitting device as long as the various other display devices include transistors.

[0039] The display device 100 according to an embodiment of the present disclosure may include a display panel PLN that displays an image or outputs light and a driving circuit for driving the display panel PLN.

[0040] The display device 100 according to an embodiment of the present disclosure may be a bottom emission type display device in which light is emitted in a direction of a substrate on which a light emitting element is disposed, but the present disclosure is not limited thereto.

[0041] In addition, the display device 100 according to an embodiment of the present disclosure may be a top-emitting type in which light is emitted toward a surface opposite to a substrate on which a light-emitting element is disposed, or may be a dual-emitting type in which light generated by the light-emitting element is emitted in the direction of the substrate and toward a surface opposite to the substrate.

[0042] In the display panel PLN, a plurality of data lines DL and a plurality of gate lines GL may be provided.

[0043] A plurality of sub-pixels SP defined by a plurality of data lines DL and a plurality of gate lines GL may be arranged in a matrix type in the display panel PLN.

[0044] In the display panel PLN, a plurality of data lines DL and a plurality of gate lines GL may be disposed to intersect each other.

[0045] For example, a plurality of gate lines GL may be arranged in rows or columns, and a plurality of data lines DL may be arranged in columns or rows.

[0046] Hereinafter, for convenience of explanation, it is assumed that a plurality of gate lines GL are arranged in rows, and a plurality of data lines DL are arranged in columns.

[0047] In the display panel PLN, in addition to the plurality of data lines DL and the plurality of gate lines GL, other types of signal wirings may be provided according to the sub-pixel structure, etc. In the display panel PLN, a driving power line, a reference power line, or a common power line may also be provided.

[0048] The type of signal wiring provided in the display panel PLN may be changed depending on a sub-pixel structure and the like.

[0049] In the present disclosure, the signal wiring may be a concept including an electrode to which a signal is applied.

[0050] The display panel PLN may include a display area A / A in which an image (video) is displayed, and a non-display area N / A which is an area outside the display area A / A and in which no image is displayed.

[0051] The non-display area N / A is also called a bezel area.

[0052] A plurality of sub-pixels SP for displaying an image are disposed in the display area A / A.

[0053] A pad area to which the data driver DDR is to be electrically connected may be disposed in the non-display area N / A. In addition, a plurality of data link lines for connection between the pad area and the plurality of data lines DL may be disposed in the non-display area N / A.

[0054] The plurality of data link lines may be portions of the plurality of data lines DL extending to the non-display area N / A, or may be separate patterns electrically connected to the plurality of data lines DL.

[0055] In the non-display area N / A, a gate driving related wiring may be disposed to transmit a voltage (eg, a signal) required for gate driving to the gate driver GDR through a pad portion electrically connected to the data driver DDR.

[0056] For example, the gate drive related wiring may include: clock wiring for transmitting clock signals, gate power lines for transmitting gate voltages (VGH and VGL), gate drive control signal wiring for transmitting various control signals required to generate scan signals, etc.

[0057] Unlike the gate lines GL disposed in the display area A / A, these gate driving related wirings are disposed in the non-display area N / A.

[0058] The driving circuit may include a data driver DDR driving a plurality of data lines DL, a gate driver GDR driving a plurality of gate lines GL, and a controller CTR controlling the data driver DDR and the gate driver GDR.

[0059] The data driver DDR may drive the plurality of data lines DL by outputting data voltages to the plurality of data lines DL.

[0060] The gate driver GDR may drive the plurality of gate lines GL by outputting scan signals to the plurality of gate lines GL.

[0061] The controller CTR may control driving operations of the data driver DDR and the gate driver GDR by supplying various control signals DCS and GCS required for driving operations of the data driver DDR and the gate driver GDR.

[0062] The controller CTR may supply the image data DATA to the data driver DDR.

[0063] The controller CTR starts scanning according to the timing achieved in each frame.

[0064] The controller CTR converts input image data DATA input from the outside into a data signal format suitable for use in the data driver DDR, outputs the converted image data, and controls data driving at an appropriate time corresponding to scanning.

[0065] In order to control the data driver DDR and the gate driver GDR, the controller CTR can receive timing signals such as a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), an input data enable (DE: dataenable) signal and a clock signal (CLK) from the outside (e.g., a host system), and can generate various control signals.

[0066] The controller CTR outputs the generated various control signals to the data driver DDR and the gate driver GDR.

[0067] For example, in order to control the gate driver GDR, the controller CTR outputs various gate control signals GCS including a gate start pulse (GSP), a gate shift clock (GSC), and a gate output enable signal (GOE).

[0068] In order to control the data driver DDR, the controller CTR outputs various data control signals DCS including a source start pulse (SSP), a source sampling clock (SSC), and a source output enable signal (SOE).

[0069] The controller CTR may be a timing controller used in general display technology.

[0070] Alternatively, the controller CTR may be a control device including a timing controller, which can further perform other control functions.

[0071] The controller CTR may be implemented as a separate component from the data driver DDR.

[0072] Alternatively, the controller CTR may be implemented as an integrated circuit by being integrated with the data driver DDR.

[0073] The data driver DDR receives the image data DATA from the controller CTR and supplies data voltages to the plurality of data lines DL, thereby driving the plurality of data lines DL.

[0074] The data driver DDR is also called a source driver.

[0075] The data driver DDR may exchange various signals with the controller CTR through various interfaces.

[0076] The gate driver GDR sequentially supplies scan signals to the plurality of gate lines GL, thereby sequentially driving the plurality of gate lines GL.

[0077] The gate driver GDR is also called a scan driver.

[0078] The gate driver GDR sequentially supplies a scan signal of a turn-on voltage or a turn-off voltage to the plurality of gate lines GL under the control of the controller CTR.

[0079] When a specific gate line GL is turned on by the gate driver GDR, the data driver DDR converts the image data DATA received from the controller CTR into an analog type data voltage and supplies the data voltage to the plurality of data lines DL.

[0080] The data driver DDR may be located at one side (eg, an upper side or a lower side) of the display panel PLN, but is not limited thereto.

[0081] For example, the data driver DDR may be located at both sides (eg, upper and lower sides) of the display panel PLN according to a driving method, a display panel design method, etc.

[0082] The gate driver GDR may be located at one side (eg, left or right) of the display panel PLN, but is not limited thereto.

[0083] For example, depending on a driving method, a display panel design method, etc., the gate driver GDR may be located on both sides (eg, left and right sides) of the display panel PLN.

[0084] The data driver DDR may be implemented to include at least one source driver integrated circuit (SDIC).

[0085] Each source driver integrated circuit (SDIC) may include a shift register, a latch circuit, a digital-to-analog converter (DAC), and an output buffer.

[0086] Furthermore, the data driver DDR may further include at least one analog-to-digital converter (ADC).

[0087] Each source driver integrated circuit (SDIC) may be connected to a bonding pad of the display panel PLN in a tape automated bonding (TAB) type or a chip on chip (COG) type.

[0088] Alternatively, each source driver integrated circuit (SDIC) may be directly disposed on the display panel PLN.

[0089] In addition, each source driver integrated circuit (SDIC) may be provided by being integrated in the display panel PLN.

[0090] In addition, each source driver integrated circuit (SDIC) may be implemented in a chip on film (COF) type.

[0091] In this case, each source driver integrated circuit (SDIC) may be mounted on the circuit film.

[0092] Each source driver integrated circuit (SDIC) mounted on the circuit film may be electrically connected to the data line DL in the display panel PLN through the circuit film.

[0093] The gate driver GDR may include a plurality of gate driving circuits GDC.

[0094] The plurality of gate driving circuits GDC may correspond to the plurality of gate lines GL, respectively.

[0095] Each gate driving circuit GDC may include a shift register and a level shifter.

[0096] Each gate driving circuit GDC may be connected to a bonding pad of the display panel PLN in a tape automated bonding (TAB) type or a chip on chip (COG) type.

[0097] In addition, each gate driving circuit GDC may be implemented in a chip on film (COF) type.

[0098] In this case, each gate driving circuit GDC may be mounted on a circuit film.

[0099] Each gate driving circuit GDC mounted on the circuit film may be electrically connected to the gate line GL in the display panel PLN through the circuit film.

[0100] In addition, each gate driving circuit GDC may be implemented in a gate-in-panel (GIP) type and may be embedded in the display panel PLN.

[0101] Therefore, each gate driving circuit GDC may be directly formed in the display panel PLN.

[0102] Figure 2 is a plan view illustrating a partial region of a sub-pixel provided in a display region of a display panel according to an embodiment of the present disclosure.

[0103] Reference Figure 2 , at least one sub-pixel SP of the display device 100 according to an embodiment of the present disclosure may include a region overlapping with the bank 290 and a region overlapping with the opening OP of the bank 290 .

[0104] A region overlapping the bank 290 may include a non-light emitting region, and in the non-light emitting region, a plurality of signal lines 201 , 202 , 203 , 204 , 205 , 206 , 207 , and 208 , a light shielding portion 210 , and a plurality of active layers 220 , 230 , and 240 may be disposed.

[0105] The plurality of signal lines may include first to eighth signal lines 201 , 202 , 203 , 204 , 205 , 206 , 207 , and 208 , and the plurality of active layers may include first to third active layers 220 , 230 , and 240 .

[0106] Reference Figure 2 In a region overlapping the bank 290 , a plurality of transistors T1 , T2 , and T3 for driving the light emitting element provided in the sub-pixel SP and a storage capacitor Cst may be provided.

[0107] In the opening OP of the bank 290 , a light emitting element including a first electrode, an organic layer, and a second electrode may be disposed.

[0108] The color filters 281 and 282 may be disposed in a region overlapping the opening OP, but the present disclosure is not limited thereto.

[0109] For example, the color filters 281 and 282 may be provided in only some sub-pixels SP among a plurality of sub-pixels SP included in the display device 100 , or the color filters 281 and 282 may not be provided in any sub-pixel SP included in the display device 100 .

[0110] When the color filters 281 and 282 are disposed in the sub-pixel SP, as shown in FIG. Figure 2 As shown, the color filters 281 and 282 may overlap the plurality of light emitting areas EA1 and EA2.

[0111] Reference Figure 2 In the display device 100 according to the embodiment of the present disclosure, the plurality of light emitting areas EA1 and EA2 may be disposed in a region overlapping the opening OP of the bank 290 .

[0112] For example, in one opening OP provided in one sub-pixel SP, a plurality of first light emitting areas EA1 and a plurality of second light emitting areas EA2 may be provided, and a plurality of first non-light emitting areas NEA1 may be provided.

[0113] Reference Figure 2 , in a region overlapping the opening OP of the bank 290 , a plurality of first non-emission areas NEA1 may be disposed to be spaced apart from each other.

[0114] Each of the first non-emission areas NEA1 may be surrounded by the first emission areas EA1.

[0115] Each of the plurality of first light emitting areas EA1 may have a structure in which at least a portion of an outer portion thereof is surrounded by the second light emitting area EA2 .

[0116] The number of the first light emitting areas EA1 may be equal to the number of the first non-light emitting areas NEA1.

[0117] Reference Figure 2 The plurality of first non-emission areas NEA1 provided in at least one sub-pixel SP may be arranged in a hexagonal shape having some area openings, but is not limited thereto. The first non-emission areas NEA1 of the display device 100 according to the embodiment of the present disclosure may be arranged in various shapes.

[0118] Reference Figure 2 , a plurality of first non-emission areas NEA1 , a plurality of first emission areas EA1 , and a second emission area EA2 overlapping one opening OP in at least one sub-pixel SP may overlap the color filters 281 and 282 .

[0119] The plurality of first light emitting areas EA1 and one second light emitting area EA2 included in one sub-pixel SP may emit the same color.

[0120] The brightness of the plurality of first light emitting regions EA1 and the brightness of the second light emitting region EA2 included in one sub-pixel SP may be the same or substantially the same.

[0121] However, the optical characteristics of the display device 100 according to the embodiment of the present disclosure are not limited thereto, and the brightness of the plurality of first light emitting areas EA1 included in one subpixel SP may be lower than the brightness of one second light emitting area EA2 .

[0122] The second light emitting area EA2 may be disposed to surround at least a portion of each of the plurality of first light emitting areas EA1.

[0123] FIG. 3A to FIG. 3C is a diagram illustrating a light emitting area of ​​a display device according to an embodiment of the present disclosure.

[0124] Reference FIG. 3A to FIG. 3C In the display device 100 according to the embodiment of the present disclosure, a plurality of light emitting areas EA1 and EA2 and a plurality of first non-light emitting areas NEA1 may be provided in one sub-pixel.

[0125] For example, a plurality of light emitting areas EA1 and EA2 may be disposed in one opening OP of the bank, and as shown in FIG. Figure 3A As shown, a plurality of first non-emission areas NEA1 may be disposed in one opening OP of the bank.

[0126] Reference Figure 3A , the plurality of first non-emission areas NEA1 provided in one opening OP of the bank may be arranged in a structure in which a hexagonal shape having opening corners (for example, a hexagonal shape in the case where the first non-emission area NEA1 is not provided at each corner) is connected to each other. In addition, the plurality of first non-emission areas NEA1 provided in one opening OP of the bank may be arranged in a repeating pattern such as a repeated ring, a perforated ring, or an overlapped ring, but the embodiment is not limited thereto.

[0127] For example, six first non-emission regions NEA1 may form a hexagonal shape having open corners, and a structure in which a plurality of hexagonal shapes consisting of the plurality of first non-emission regions NEA1 are disposed may be provided.

[0128] One hexagonal shape may be arranged to share at least one first non-light emitting area NEA1 with another adjacent hexagonal shape.

[0129] Reference Figure 3A , a plurality of first non-emission areas NEA1 disposed in one opening OP of the bank may be disposed to be spaced apart from each other.

[0130] One first non-emission region NEA1 and another adjacent first non-emission region NEA1 may be spaced apart by a first distance a.

[0131] The first distance a may refer to the shortest straight-line distance between one point of one first non-emission area NEA1 and one point of another first non-emission area NEA1.

[0132] For example, when the first non-luminous area NEA1 has a shape having at least one corner or one side in a plan view (e.g., a polygonal shape), based on one corner or one side of one first non-luminous area NEA1, one corner or one side of another adjacent first non-luminous area NEA1 can be set at a position spaced apart by a first distance a as the shortest straight-line distance.

[0133] In addition, one side of one first non-emission region NEA1 disposed in one opening OP of the bank may be disposed to face one side of another first non-emission region NEA1 in a plan view.

[0134] One side of one first non-emission region NEA1 may be spaced apart from one side of another first non-emission region NEA1 facing the first non-emission region NEA1 by a second distance b. In other words, opposite sides of the first non-emission region NEA1 or oppositely facing first non-emission regions NEA1 may be spaced apart from each other by a second distance b.

[0135] Reference Figure 3A , when two first non-luminous areas NEA1 that are disposed farthest from each other in a plan view among six first non-luminous areas NEA1 forming a hexagonal shape are selected, the second distance b may refer to the shortest straight-line distance between one side (e.g., the first side) of one first non-luminous area NEA1 of the two first non-luminous areas NEA1 and one side (e.g., the side facing the first side) of the other first non-luminous area NEA1.

[0136] Reference Figure 3A , the first distance a may be shorter than the second distance b (eg, a<b).

[0137] For example, when each first non-luminous area NEA1 has a shape having a specific area in a plan view (e.g., a polygonal shape, a circular shape, an elliptical shape, a polygonal shape with rounded corners, etc.) and a hexagonal structure is formed as six first non-luminous areas NEA1 are arranged, the first distance a may be 5 μm to 15 μm (e.g., 10 μm), and the second distance b may be 10 μm to 20 μm (e.g., 15 μm).

[0138] However, the ranges of the first distance a and the second distance b are not limited thereto, and various distances may be selected depending on the shape of the pattern, the size of the opening OP of the bank, and the like.

[0139] Each of the plurality of first light emitting areas EA1 provided in one sub-pixel may be a region where light emitted from the light emitting layer is emitted to the outside of the substrate through a reflective electrode provided in the first non-light emitting area NEA1.

[0140] In this way, by adjusting the first distance a and the second distance b of the first non-luminous area NEA1, the area of ​​each first non-luminous area NEA1 set in the opening OP of the embankment can be reduced or minimized while improving the efficiency of light generated from the multiple first luminous areas EA1 due to the first non-luminous area NEA1.

[0141] In the above, refer to Figure 3A A case is described in which the plurality of first non-emission areas NEA1 , the plurality of first emission areas EA1 , and the plurality of second emission areas EA2 are disposed in the opening OP of the bank.

[0142] In the following, reference will be made to Figure 3B and Figure 3C A case in which a plurality of first non-emission areas NEA1, a plurality of first emission areas EA1, and a plurality of second emission areas EA2 are disposed at a boundary between the second emission areas EA2 and the second non-emission areas NEA2 will be described.

[0143] Figure 3B and Figure 3C The description of the first non-luminous area NEA1, the first luminous area EA1 and the second luminous area EA2 in Figure 3A The descriptions of the first non-emission area NEA1, the first emission area EA1 and the second emission area EA2 are basically the same.

[0144] Reference Figure 3B and Figure 3C , a plurality of first non-luminous areas NEA1, a plurality of first luminous areas EA1, and a plurality of second luminous areas EA2 may be disposed at a boundary between the second luminous area EA2 and the second non-luminous area NEA2, and a boundary between the second luminous area EA2 and the second non-luminous area NEA2 may have a concave shape and a convex shape.

[0145] Specifically, the boundary between the second light emitting area EA2 and the second non-light emitting area NEA2 may have a polygonal shape, and preferably, may be a hexagonal shape or a quadrilateral shape.

[0146] However, the concave and convex shapes of the boundary between the second light emitting area EA2 and the second non-light emitting area NEA2 are not necessarily limited to polygonal shapes, and may have various shapes such as a circular shape or an elliptical shape. For example, the boundary between the second light emitting area EA2 and the second non-light emitting area NEA2 may have a wrinkled edge, a wavy shape, or a curved shape (e.g., a leaf pattern or a clover pattern).

[0147] In addition, the boundary between the second light emitting area EA2 and the second non-light emitting area NEA2 is not necessarily limited to the concave shape and the convex shape, and may not have the concave shape and the convex shape.

[0148] Reference Figure 3B and Figure 3C , the concave shape and the convex shape of the boundary between the second light emitting area EA2 and the second non-light emitting area NEA2 may have the first shape and the second shape.

[0149] Specifically, a first shape may be formed on one side of the opening OP of the bank along a direction where the second light emitting area EA2 is located, and a second shape may be formed on the other side of the opening OP of the bank along a direction where the second non-light emitting area NEA2 is located.

[0150] Unlike the first shape, in the second shape, the first light emitting area EA1 may not exist along a direction in which the second non-light emitting area NEA2 is located.

[0151] exist Figure 3B , an example in which the first shape and the second shape are hexagonal shapes is illustrated, and an enlarged view of the first shape is shown.

[0152] exist Figure 3C , an example in which the first shape and the second shape are quadrangular shapes is shown, and an enlarged view of the first shape is shown.

[0153] It may be desirable that the first shape and the second shape are the same or substantially the same shape. However, the first shape and the second shape are not necessarily limited to the same or substantially the same shape, and may be different shapes.

[0154] Next, refer to Figure 4A , Figure 4B , Figure 5A as well as Figure 5B , the structure of the display device according to the embodiment of the present disclosure will be described in detail below.

[0155] Figure 4A and Figure 4B It is along Figure 2 A cross-sectional view taken along line AB of Figure 5A and Figure 5B It is along Figure 2A cross-sectional view taken along line CD.

[0156] Reference Figure 4A , Figure 4B , Figure 5A as well as Figure 5B , the first signal line 201 and the second signal line 202 may be disposed on the substrate 400 .

[0157] The first insulating layer 401 may be disposed on the first signal line 201 and the second signal line 202 .

[0158] The first insulating layer 401 may be a buffer layer, and may have a single-layer or multi-layer structure.

[0159] The second insulating layer 402 may be disposed on the first insulating layer 401 .

[0160] The second insulating layer 402 may be a gate insulating layer.

[0161] The first insulating layer 401 and the second insulating layer 402 may include an inorganic insulating material such as silicon oxide (SiOx), silicon nitride (SiNx), or silicon oxynitride (SiON), but the embodiments of the present disclosure are not limited thereto.

[0162] The fifth signal line 205 may be disposed on the second insulating layer 402 .

[0163] Each of the first signal line 201 , the second signal line 202 , and the fifth signal line 205 may include a conductive material.

[0164] For example, each of the signal lines 201, 202 and 205 may include a metal such as aluminum (Al), gold (Au), silver (Ag), copper (Cu), tungsten (W), molybdenum (Mo), chromium (Cr), tantalum (Ta) and titanium (Ti) or an alloy thereof, but the embodiments of the present disclosure are not limited thereto.

[0165] Figure 2 The third signal line 203 and the fourth signal line 204 shown may include the same or substantially the same material as the first signal line 201 and the second signal line 202 , but embodiments of the present disclosure are not limited thereto.

[0166] The third insulating layer 403 may be disposed on the fifth signal line 205 .

[0167] The color filter 280 may be disposed on the third insulating layer 403 .

[0168] The color filter 280 may include a first color filter 281 and a second color filter 282 , and the first color filter 281 and the second color filter 282 may be color filters of different colors.

[0169] For example, the first color filter 281 may be a red color filter, and the second color filter 282 may be a green color filter.

[0170] exist Figure 4A , Figure 4B , Figure 5A as well as Figure 5B , a structure in which the color filter 280 includes a first color filter 281 and a second color filter 282 is illustrated, but the structure of the display device 100 according to the embodiment of the present disclosure is not limited thereto. The color filter 280 disposed on the third insulating layer 403 may also include at least one color filter other than the first color filter 281 and the second color filter 282.

[0171] The additionally included color filter may be a color filter of a different color (eg, a blue color filter) from the first color filter 281 and the second color filter 282 or a color filter of the same color.

[0172] Reference Figure 4A , Figure 4B , Figure 5A as well as Figure 5B , one end of the first color filter 281 may overlap one end of the second color filter 282 .

[0173] A region where a portion of the first color filter 281 overlaps a portion of the second color filter 282 may function as a black matrix (eg, two or more different color filters may overlap each other to block light).

[0174] A fourth insulating layer 404 may be disposed on the color filter 280 .

[0175] The fourth insulating layer 404 may include an organic insulating material, but embodiments of the present disclosure are not limited thereto.

[0176] A plurality of anode electrodes 270 may be disposed on the fourth insulating layer 404 .

[0177] The anode electrode 270 may include a transparent conductive material.

[0178] For example, the anode electrode 270 may include at least one of ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), and IGZO (Indium Gallium Zinc Oxide), but the material of the anode electrode 270 according to the embodiment of the present disclosure is not limited thereto. Any combination including a material having high light transmittance and high electrical conductivity is sufficient.

[0179] Reference Figure 4A , Figure 4B , Figure 5A as well as Figure 5B , in one sub-pixel, a plurality of anode electrodes 270 may be disposed on the fourth insulating layer 404 to be spaced apart from each other.

[0180] Reference Figure 4A , Figure 4B , Figure 5A as well as Figure 5B , at least one recessed portion 410 may be defined in the fourth insulating layer 404 in a region between at least two anode electrodes 270 .

[0181] For example, refer to Figure 4A and Figure 4B , the first anode electrode 471 and the second anode electrode 472 may be disposed on the fourth insulating layer 404 to be spaced apart from each other.

[0182] At least one recessed portion 410 may be provided in the fourth insulating layer 404 to correspond to a region between the first anode electrode 471 and the second anode electrode 472 .

[0183] Each of the first anode electrode 471 and the second anode electrode 472 may be disposed to surround the recessed portion 410 of the fourth insulating layer 404 to expose a portion of an upper surface of the fourth insulating layer 404 .

[0184] In other words, in the region between the first anode electrode 471 and the second anode electrode 472, a portion of the upper surface of the fourth insulating layer 404 where the recessed portion 410 is not provided may not overlap the first anode electrode 471 and the second anode electrode 472. For example, the first anode electrode 471 and the second anode electrode 472 may be spaced apart from each other by the recessed portion 410 therebetween.

[0185] Reference Figure 5A and Figure 5B At least one recessed portion 410 may be provided between the first anode electrode 571 and the second anode electrode 572 provided on the fourth insulating layer 404 , and at least one recessed portion 410 may be provided between the second anode electrode 572 and the third anode electrode 573 .

[0186] Reference Figure 5A and Figure 5B , in the region between the first anode electrode 571 and the second anode electrode 572, a portion of the upper surface of the fourth insulating layer 404 where the recessed portion 410 is not provided may not overlap the first anode electrode 571 and the second anode electrode 572. For example, the first anode electrode 571 and the second anode electrode 572 may be spaced apart from each other by the recessed portion 410 therebetween.

[0187] In addition, in the region between the second anode electrode 572 and the third anode electrode 573 , a portion of the upper surface of the fourth insulating layer 404 where the recessed portion 410 is not provided may not overlap the second anode electrode 572 and the third anode electrode 573 .

[0188] Reference Figure 4A , Figure 4B , Figure 5A as well as Figure 5B , the bank 290 may be disposed on a portion of an upper surface of the anode electrode 270 disposed on the fourth insulating layer 404 .

[0189] The bank 290 may have at least one opening OP in one sub-pixel.

[0190] The bank 290 may be made of a transparent organic material or a black organic material.

[0191] For example, Figure 4A and Figure 4B As shown, the bank 290 may be disposed on a portion of the upper surface of the first anode electrode 471 and a portion of the upper surface of the second anode electrode 472. For example, the bank 290 may overlap with the edge of the anode electrode.

[0192] The opening OP of the bank 290 may be disposed on another portion of the upper surface of the first anode electrode 471 and another portion of the upper surface of the second anode electrode 472 .

[0193] like Figure 5A and Figure 5B As shown, the bank 290 may be disposed on a portion of the upper surface of the first anode electrode 571 and a portion of the upper surface of the third anode electrode 573 , and may not be disposed on the upper surface of the second anode electrode 572 .

[0194] The opening OP of the bank 290 may overlap another portion of the upper surface of the first anode electrode 571 , another portion of the upper surface of the third anode electrode 573 , and the entire upper surface of the second anode electrode 572 .

[0195] Reference Figure 4A , Figure 4B , Figure 5A as well as Figure 5B , the opening OP of the bank 290 may overlap with the recessed portion 410 of the fourth insulating layer 404 disposed between the anode electrodes 270 .

[0196] Reference Figure 4A , Figure 4B , Figure 5A as well as Figure 5B , the light emitting layer 492 may be disposed over the substrate 400 on which the anode electrode 270 and the bank 290 are disposed, and the cathode electrode 493 may be disposed on the light emitting layer 492 .

[0197] Figure 4A , Figure 4B , Figure 5A as well as Figure 5B A structure in which each of the light emitting layer 492 and the cathode electrode 493 is a single layer is illustrated, but the embodiments of the present disclosure are not limited thereto. At least one of the light emitting layer 492 and the cathode electrode 493 may have a multi-layer structure.

[0198] Reference Figure 4A , Figure 4B , Figure 5A as well as Figure 5B , the light emitting layer 492 and the cathode electrode 493 may be disposed on the bank 290 and the opening OP of the bank 290 .

[0199] The cathode electrode 493 may include a conductive material capable of reflecting light.

[0200] For example, the cathode electrode 493 may include a metal such as aluminum (Al), magnesium (Mg), gold (Au), silver (Ag), copper (Cu), tungsten (W), molybdenum (Mo), chromium (Cr), tantalum (Ta) and titanium (Ti), or an alloy thereof, but the embodiments of the present disclosure are not limited thereto.

[0201] Reference Figure 4A , Figure 4B , Figure 5A as well as Figure 5B , the light emitting layer 492 and the cathode electrode 493 may be disposed on the recessed portion 410 of the fourth insulating layer 404 overlapping the opening OP of the bank 290 .

[0202] The light emitting layer 492 and the cathode electrode 493 may be disposed even in a region X (hereinafter, referred to as an exposed region) where the anode electrode 270 exposes a portion of the fourth insulating layer 404 surrounding the recessed portion 410 of the fourth insulating layer 404. For example, the light emitting layer 492 and the cathode electrode 493 may continuously extend through adjacent anode electrodes and the recessed portion 410 between adjacent anode electrodes.

[0203] In the exposed region X and the recessed portion 410 , the light emitting layer 492 may contact an upper surface of the fourth insulating layer 404 .

[0204] Reference Figure 4A , Figure 4B , Figure 5A as well as Figure 5B The light emitting layer 492 and the cathode electrode 493 may be formed in the opening OP of the bank 290 along the morphology of the anode electrode 270 and the fourth insulating layer 404 .

[0205] Reference Figure 4A and 5A, the light emitting layer 492 and the cathode electrode 493 may have steps 494 and 495 in the opening OP of the bank 290. In addition, the steps 494 and 495 may also be referred to as stepped portions or inclined portions.

[0206] Specifically, each of the light emitting layer 492 and the cathode electrode 493 may have a first step 494 at a boundary between the exposed region X (a region in which the anode electrode 270 does not overlap with the upper surface of the fourth insulating layer 404 except for the recessed portion 410) and the anode electrode 270, and may have a second step 495 at a boundary between the exposed region X and the recessed portion 410. In one embodiment, the first step 494 of the cathode electrode 493 may overlap with an inclined side surface of the recessed portion 410 in the insulating layer 404, and the second step 495 of the cathode electrode 493 may overlap with a flat bottom surface of the recessed portion 410 in the insulating layer 404.

[0207] Therefore, the position of the cathode electrode 493 disposed on the exposure region X and the recessed portion 410 may be lower than the position of the cathode electrode 493 disposed on the anode electrode 270 .

[0208] The position of the cathode electrode 493 may be determined by the shortest straight line distance from the upper surface of the substrate 400 to the lower surface of the cathode electrode 493. For example, portions of the light emitting layer 492 and the cathode electrode 493 may be sunken into the recessed portion 410. In addition, the recessed portion 410 may be referred to as a groove or a concave portion, but the embodiment is not limited thereto.

[0209] Specifically, refer to Figure 4A and Figure 5A , the shortest straight-line distance between the lower surface of the cathode electrode 493 disposed on the anode electrode 270 and the upper surface of the substrate 400 may be longer than the shortest straight-line distance between the lower surface of the cathode electrode 493 disposed on the exposed region X and the recessed portion 410 and the upper surface of the substrate 400.

[0210] Therefore, a lower surface of the cathode electrode 493 disposed on the anode electrode 270 may be located higher than a lower surface of the cathode electrode 493 disposed on the exposed region X and the recessed portion 410 .

[0211] For example, refer to Figure 4B and Figure 5B , the light emitting layer 492 and the cathode electrode 493 may include a circular recess DPS in the opening OP of the bank 290 .

[0212] In order to form the circular recess DPS, it is preferred that the end of the recessed portion 410 and the end of the anode electrode 270 contact each other, but the embodiments of the present disclosure are not necessarily limited thereto.

[0213] The fact that the end of the recessed portion 410 and the end of the anode electrode 270 are in contact with each other may be interpreted as meaning that there is no Figure 4A and Figure 5A The exposed area X described in .

[0214] However, the embodiments of the present disclosure are not limited to the absence of the exposed region X, and even if the exposed region X exists, the recess DPS may have a circular shape.

[0215] Reference Figure 4A , Figure 4B , Figure 5A as well as Figure 5B , one sub-pixel may include: a first light emitting area EA1, a second light emitting area EA2, a first non-light emitting area NEA1, and a second non-light emitting area NEA2.

[0216] The first light emitting area EA1, the second light emitting area EA2, and the first non-light emitting area NEA1 may be defined where the opening OP of the bank 290 is provided.

[0217] The second non-emission area NEA2 may be a region in which the bank 290 is disposed.

[0218] Reference Figure 4A , Figure 4B , Figure 5A as well as Figure 5B , the first non-emission area NEA1 may overlap the concave portion 410 of the fourth insulating layer 404 .

[0219] Specifically, the first non-luminescent area NEA1 may correspond to an area where the straight-line distance between the substrate 400 and the lower surface of the cathode electrode 493 is shortest in the opening OP of the embankment 290 in a cross-sectional view (e.g., an area overlapping the central portion or the flat bottom portion of the recessed portion 410).

[0220] The recess portion 410 of the fourth insulating layer 404 may be composed of a flat portion and an inclined surface surrounding the contour of the flat portion, and the first non-emission area NEA1 may be an area corresponding to at least a portion of the flat portion of the recess portion 410 .

[0221] The first light emitting region EA1 may be a region corresponding to the exposed region X of the fourth insulating layer 404 and the inclined surface of the recess portion 410. The first light emitting region EA1 may surround the circumference of the first non-light emitting region NEA1.

[0222] The second light emitting region EA2 may be a region corresponding to a region in which the anode electrode 270 is disposed. The second light emitting region EA2 may surround a circumference of the first light emitting region EA1.

[0223] The second non-emission area NEA2 may surround the circumference of the second emission area EA2.

[0224] In the second light emitting area EA2, a portion of light generated from the light emitting layer 492 may be emitted from the light emitting layer 492 to the outside of the substrate 400 through the anode electrode 270 ( Figure 4A , Figure 4B , Figure 5A as well as Figure 5B The first light L1).

[0225] Another part of the light generated from the light emitting layer 492 may be emitted from the light emitting layer 492 toward the cathode electrode 493, but may be reflected by the cathode electrode 493 including the reflective conductive material, and may be emitted to the outside of the substrate 400 through the anode electrode 270 ( Figure 4A , Figure 4B , Figure 5A as well as Figure 5B The second light L2).

[0226] Another portion of the light generated from the light emitting layer 492 between the anode electrode 270 and the cathode electrode 493 may be emitted in a direction intersecting the direction in which the buffer layer 401 is stacked on the substrate 400, may be reflected from the cathode electrode 493 disposed in the first light emitting area EA1 to change the path along which it moves toward the substrate 400, and may be finally emitted to the outside of the substrate 400 (e.g., Figure 4A , Figure 4B , Figure 5A as well as Figure 5B In other words, some of the light generated from the light emitting layer 492 (e.g., horizontal light that may otherwise remain internally reflected or blocked) may be reflected out of the display device by the portion of the cathode electrode 493 that is sunken into the recessed portion 410, and the reflected light may pass between adjacent anodes and leave the display device without being blocked by the transparent anode. Thus, more light may be emitted from the sub-pixel with less power.

[0227] Specifically, refer to Figure 4A and Figure 5A , another portion of the light generated from the light emitting layer 492 located between the anode electrode 270 and the cathode electrode 493 can reach the area of ​​the first step 494 or the second step 495 of the cathode electrode 493, and can be reflected in the area of ​​the first step 494 or the second step 495 to change along its path, thereby being emitted to the outside of the substrate 400.

[0228] Similarly, due to the fact that in a sub-pixel the fourth insulating layer 404 includes at least one recessed portion 410 and is provided with an exposed area X in which the anode electrode 270 is arranged to expose the upper surface of the fourth insulating layer 404, the cathode electrode 493 may include an area of ​​at least one first step 494 and an area of ​​at least one second step 495 that can help reflect more light out of the sub-pixel.

[0229] Since light generated from the light emitting layer 492 can be emitted to the outside without loss through the regions of the first step 494 and the second step 495 (eg, without any loss since it must pass through the anode electrode), light efficiency can be improved.

[0230] In other words, the light emitted from the first light emitting region EA1 may be light emitted when a portion of light emitted by the anode electrode 270 , the light emitting layer 492 , and the cathode electrode 493 located in the second light emitting region EA2 is reflected.

[0231] Reference FIG. 3A to FIG. 3C , one first light emitting area EA1 may be disposed to surround the circumference of one first non-light emitting area NEA1.

[0232] Since the recessed portion 410 of the fourth insulating layer 404 may be simultaneously formed in a process of forming a contact hole for electrically connecting the anode electrode 270 disposed on the fourth insulating layer 404 and the transistor, a separate process for light extraction may not be added.

[0233] Fig. 6A and Figure 6B Along the Figure 3B (or Figure 3C ) is a cross-sectional view taken along lines a-a' and bb'.

[0234] Fig. 6A The substrate 400, the first to fourth insulating layers 401, 402, 403 and 404, the color filters 281 and 282, the signal lines 201 and 205, the anode electrode 270, the light emitting layer 492, the cathode electrode 493, the light emitting areas EA1 and EA2, and the non-light emitting area NEA are the same as those described above. FIG. 4A to FIG. 5B The described substrate 400, first to fourth insulating layers 401, 402, 403 and 404, color filters 281 and 282, signal lines 201 and 205, anode electrode 270, light emitting layer 492, cathode electrode 493, light emitting areas EA1 and EA2, and non-light emitting area NEA are substantially the same.

[0235] Reference Fig. 6A and Figure 6B , the light emitting layer 492 and the cathode electrode 493 may include a circular step in the first light emitting area EA1.

[0236] A circular step is formed due to the step of the fourth insulating layer 404 in the first light emitting area EA1.

[0237] Reference Fig. 6A , the circular step in the first light emitting area EA1 located at the boundary between the second light emitting area EA2 and the second non-light emitting area NEA2 may not overlap with the signal lines 201 and 205 .

[0238] However, the embodiments of the present disclosure are not limited thereto. Figure 6B , the circular step in the first light emitting area EA1 located at the boundary between the second light emitting area EA2 and the second non-light emitting area NEA2 may overlap the signal lines 201 and 205. Whether the circular step overlaps the signal lines 201 and 205 may vary depending on the position of the boundary between the second light emitting area EA2 and the second non-light emitting area NEA2.

[0239] Reference Fig. 6A and Figure 6B , in the second light emitting area EA2 adjacent to a boundary between the second light emitting area EA2 and the second non-light emitting area NEA2, there may be a region in which no bank is provided on the anode electrode 270.

[0240] That is, the bank may not be provided on one side and the other side of the boundary of the opening.

[0241] In the second light emitting region EA2 adjacent to a boundary between the second light emitting region EA2 and the second non-light emitting region NEA2, a region in which no bank is disposed on the anode electrode 270 may not exist.

[0242] Next, refer to Figure 7 and Figure 8 , a planar structure of a display device according to an embodiment of the present disclosure will be described below.

[0243] Figure 7 is a diagram illustrating a planar structure of four sub-pixels of a display device according to an embodiment of the present disclosure.

[0244] Figure 8 1 is a diagram illustrating a cross-sectional structure of opening regions of banks of four sub-pixels, a plurality of light-emitting regions, and one non-light-emitting region in a display device according to an embodiment of the present disclosure.

[0245] Reference Figure 7 and Figure 8 , the display device according to the embodiment of the present disclosure may include: a first sub-pixel SP1, a second sub-pixel SP2, a third sub-pixel SP3, and a fourth sub-pixel SP4.

[0246] The first to fourth sub-pixels SP1 , SP2 , SP3 , and SP4 may include light emitting regions emitting light of different colors.

[0247] For example, the first subpixel SP1 may include a light emitting region emitting red light, the second subpixel SP2 may include a light emitting region emitting white light, the third subpixel SP3 may include a light emitting region emitting blue light, and the fourth subpixel SP4 may include a light emitting region emitting green light.

[0248] like Figure 8 As shown, each of the light-emitting areas included in the sub-pixels SP1, SP2, SP3, and SP4 may include a first non-light-emitting area NEA1, a first light-emitting area EA1 surrounding the first non-light-emitting area NEA1, a third light-emitting area EA3 surrounding the first light-emitting area EA1, and a second light-emitting area EA2 surrounding the third light-emitting area EA3. The second light-emitting area EA2 may be surrounded by the second non-light-emitting area NEA2.

[0249] Will Figure 8 The structure of the non-luminous area and the luminous area Figure 3A , Figure 3B , FIG. 3C to FIG. 5A and Figure 5B The difference is that a third light emitting area EA3 is additionally provided between the first light emitting area EA1 and the second light emitting area EA2 (eg, corresponding to a region between an edge of the anode electrode and an upper edge of the recessed portion 410).

[0250] The first light emitting region EA1 may be a region corresponding to the inclined surface of the recess portion 410 , and the third light emitting region EA3 may be a region corresponding to a region of the upper surface of the fourth insulating layer 404 extending from the inclined surface not overlapping the anode electrode 270 .

[0251] Each of the first to fourth sub-pixels SP1 , SP2 , SP3 , and SP4 may include a circuit area CA for driving a light emitting element provided in each of the first to fourth sub-pixels SP1 , SP2 , SP3 , and SP4 .

[0252] Reference Figure 7 , each of the first to fourth sub-pixels SP1 , SP2 , SP3 , and SP4 may include a plurality of transistors T1 , T2 , and T3 and a storage capacitor Cst disposed in the circuit area CA.

[0253] For example, the circuit area CA of each of the first to fourth sub-pixels SP1 , SP2 , SP3 , and SP4 may include a first transistor T1 , a second transistor T2 , a third transistor T3 , and a storage capacitor Cst.

[0254] Reference Figure 7 , the circuit area CA of each of the first to fourth sub-pixels SP1 , SP2 , SP3 , and SP4 may overlap with the bank 290 .

[0255] In other words, the bank 290 may overlap the first transistor T1 , the second transistor T2 , the third transistor T3 , and the storage capacitor Cst.

[0256] Specifically, the bank 290 may overlap the gate electrode 245 and the first active layer 220 included in the first transistor T1, may overlap the second active layer 230 included in the second transistor T2 and the third active layer 240 included in the third transistor T3, and may overlap the light shielding portion 210 which is one of the electrodes of the storage capacitor Cst.

[0257] Reference Figure 7 , the bank 290 may overlap with a plurality of signal lines 201 , 202 , 203 , 204 , 205 , and 206 required for driving the light emitting elements.

[0258] Some of the plurality of signal lines 201 , 202 , 203 , 204 , 205 , 206 , 207 , and 208 may be used as any of a source electrode, a drain electrode, and a gate electrode of each of the transistors T1 , T2 , and T3 .

[0259] Reference Figure 7 and Figure 8 , the area in which the bank 290 is provided may be substantially the same as the second non-emission area NEA2 of the display area A / A.

[0260] Substantially the same in the present disclosure may refer to a degree of the same that takes into account slight differences due to errors in the process.

[0261] Reference Figure 7 , the bank 290 may include a first opening OP1 , a second opening OP2 , a third opening OP3 , and a fourth opening OP4 .

[0262] The first opening OP1 may be included in the first sub-pixel SP1 , the second opening OP2 may be included in the second sub-pixel SP2 , the third opening OP3 may be included in the third sub-pixel SP3 , and the fourth opening OP4 may be included in the fourth sub-pixel SP4 .

[0263] Reference Figure 7 and Figure 8 Each of the first to fourth openings OP1 , OP2 , OP3 , and OP4 may include a plurality of light emitting areas EA1 , EA2 , and EA3 and a plurality of first non-light emitting areas NEA1 .

[0264] Specifically, the following will be described as an example Figure 8 The structure shown is a structure where the second opening OP2 of the second sub-pixel SP2 overlaps the plurality of light emitting areas EA1, EA2 and EA3 and the plurality of first non-light emitting areas NEA1.

[0265] In the following description, the structure of the area corresponding to the second opening OP2 of the second sub-pixel SP2 will be described by way of example, but except for the configuration in which a color filter is additionally provided on the third insulating layer 403 in the first opening OP1 of the first sub-pixel SP1, the third opening OP3 of the third sub-pixel SP3, and the fourth opening OP4 of the fourth sub-pixel SP4, the rest of the configuration may be the same or substantially the same.

[0266] Reference Figure 8 The second opening OP2 of the second subpixel SP2 may include a first non-emission area NEA1, a first emission area EA1 surrounding the first non-emission area NEA1, a third emission area EA3 surrounding the first emission area EA1, and a second emission area EA2 surrounding the third emission area EA3.

[0267] Reference Figure 8 The first non-light emitting area NEA1 may correspond to an area corresponding to the flat portion 701 of the recess portion 410 of the fourth insulating layer 404 (eg, a middle and lowest portion of the recess portion 410 ).

[0268] The first light emitting region EA1 may correspond to a region corresponding to the inclined surface 702 of the recess portion 410 provided in the fourth insulating layer 404 .

[0269] The third light emitting region EA3 may correspond to a region where the anode electrode 270 is not disposed on the fourth insulating layer 404 and does not overlap the recess portion 410 (eg, a region between an edge of the anode electrode and an upper edge of the recess portion 410 ).

[0270] The second light emitting area EA2 may be an area including an area where the anode electrode 270 is disposed but in which the anode electrode 270 does not overlap the bank 290 .

[0271] The brightness of the third light emitting area EA3 may be lower than the brightness of the first light emitting area EA1 and the brightness of the second light emitting area EA2. However, the brightness characteristics of the display device according to the embodiment of the present disclosure are not limited thereto, and may be adjusted according to the structure of the recessed portion 410 of the fourth insulating layer 404, the positions of the anode electrode 270 and the recessed portion 410, and the taper angle of the anode electrode 270.

[0272] For example, the width L of the flat portion 701 (eg, bottom) of the recessed portion 410 of the fourth insulating layer 404 may be 0.5 μm to 3.5 μm (eg, 2.0 μm).

[0273] The width L of the flat portion 701 may be the shortest length in a direction intersecting a direction in which the first insulating layer 401 is stacked on the substrate 400 .

[0274] A height H of the recessed portion 410 of the fourth insulating layer 404 may be 0.4 μm to 1 μm (eg, 0.7 μm).

[0275] Reference Figure 8 , a gap K between the first anode electrode 471 and the second anode electrode 472 may be 3.7 μm to 5.5 μm.

[0276] The gap K may refer to the shortest straight-line distance between one end of the first anode electrode 471 and one end of the second anode electrode 472 in a direction perpendicular to a direction in which the first insulating layer 401 is stacked on the substrate 400 .

[0277] Reference Figure 8 In the remaining area except the recessed portion 410 of the fourth insulating layer 404 in the second opening OP2 , a width M of a region where the anode electrode 270 does not overlap the fourth insulating layer 404 may be 0.5 μm to 0.6 μm (eg, 0.55 μm).

[0278] Reference Figure 8 , the first angle c of the first anode electrode 471 may be 25° to 30° (eg, a taper angle of an edge of the first anode electrode 471 ).

[0279] In addition, the angle of the second anode electrode 472 may be the same as or substantially the same as the first angle c of the first anode electrode 471 .

[0280] The cathode electrode 493 disposed above the first anode electrode 471 and the second anode electrode 472 may include a second angle d and a third angle e. Figure 8 , the cathode electrode 493 may form a second angle d in a region where the first step 494 is provided, and may form a third angle e in a region where the second step 495 is provided.

[0281] The second angle d may be 30° to 50° (eg, 40°), and the third angle e may be 50° to 70° (eg, 60°).

[0282] exist Figure 8 In the figure, the first angle c may refer to the angle formed by the inclined surface of one end of the first anode electrode 471 relative to the surface of the substrate 400, and the second angle d and the third angle e may refer to the angle formed by the inclined surfaces of the first step 494 and the second step 495 of the cathode electrode 493 relative to the surface of the substrate 400.

[0283] Reference Figure 8 , the third angle e may be greater than the first angle c and the second angle d, and the second angle d may be greater than the first angle c (eg, e>d>c).

[0284] Reference Figure 8 , the second angle d of the cathode electrode 493 may be formed by one end of the anode electrode 470 where the first angle c of the anode electrode 470 is defined, and the third angle e of the cathode electrode 493 may be formed by a boundary of the recessed portion 410 of the fourth insulating layer 404 .

[0285] Through this structure, the cathode electrode 493 is provided with a first step 494 and a second step 495 forming a second angle d and a third angle e, and due to the first step 494 and the second step 495, the light generated from the light emitting layer 492 can be emitted to the outside of the substrate 400 by being reflected by the cathode electrode 493.

[0286] Therefore, at least one sub-pixel may have a structure including a plurality of light emitting regions.

[0287] Fig.9A and Fig. 9B According to the embodiment of the present disclosure, Figure 7 A cross-sectional view taken along line EF.

[0288] Reference Fig.9A and Fig. 9B , each of the first sub-pixel SP1 , the second sub-pixel SP2 , the third sub-pixel SP3 , and the fourth sub-pixel SP4 may include a plurality of first light emitting areas EA1 and a plurality of second light emitting areas EA2 .

[0289] Specifically, refer to Fig.9A and Fig. 9B In each of the first to fourth sub-pixels SP1 , SP2 , SP3 , and SP4 , at least one recessed portion 410 disposed in the fourth insulating layer 404 may be disposed in a region corresponding to the opening of the bank 290 .

[0290] In each of the first to fourth sub-pixels SP1 , SP2 , SP3 , and SP4 , a region corresponding to the flat portion 701 of the recessed portion 410 of the fourth insulating layer 404 may be a first non-emission region NEA1 .

[0291] At least one first non-emission area NEA1 may be disposed in each of the first to fourth sub-pixels SP1 , SP2 , SP3 , and SP4 , and may be disposed in the bank 290 .

[0292] Reference Fig.9A and Fig. 9B In each of the first subpixel SP1 , the third subpixel SP3 , and the fourth subpixel SP4 , the first non-emission area NEA1 may overlap the color filter 280 .

[0293] In each of the first to fourth sub-pixels SP1 , SP2 , SP3 , and SP4 , a region corresponding to the inclined surface 702 of the recessed portion 410 of the fourth insulating layer 404 may be included in the first light emitting region EA1 .

[0294] In addition, in the opening of the bank 290 of each of the first to fourth subpixels SP1, SP2, SP3 and SP4, a region where the anode electrode 270 does not overlap the fourth insulating layer 404 in the remaining region except the recessed portion 410 may also be included in the first emission region EA1.

[0295] Reference Fig.9A and Fig. 9B In the opening of the bank 290 of each of the first to fourth sub-pixels SP1, SP2, SP3, and SP4, a region where the fourth insulating layer 404 and the anode electrode 270 overlap each other may be a second light emitting region EA2.

[0296] In the first to fourth sub-pixels SP1 , SP2 , SP3 , and SP4 , a region overlapping the bank 290 may be a second non-emission area NEA2 .

[0297] Reference Fig.9A and Fig. 9B , the plurality of signal lines 202 , 203 , and 204 may be disposed to overlap the bank 290 .

[0298] Each of the plurality of signal lines 202 , 203 , and 204 may not overlap the first light emitting area EA1 and the second light emitting area EA2 .

[0299] Therefore, it is possible to reduce or prevent light emitted from the first and second light emitting areas EA1 and EA2 of the first to fourth subpixels SP1 , SP2 , SP3 , and SP4 from being lost due to the plurality of signal lines 202 , 203 , and 204 .

[0300] Reference Fig.9A and Fig. 9B As the first to fourth insulating layers 401 , 402 , 403 , and 404 and the bank 290 are disposed between the plurality of signal lines 202 , 203 , and 204 and the cathode electrode 493 , the distance between the plurality of signal lines 202 , 203 , and 204 and the cathode electrode 493 may increase.

[0301] Therefore, parasitic capacitance between the plurality of signal lines 202, 203, and 204 and the cathode electrode 493 can also be reduced. Therefore, noise can be reduced and brightness can be improved.

[0302] The distance between the plurality of signal lines 202 , 203 , and 204 and the cathode electrode 493 refers to the shortest straight line length between the upper surface of each of the plurality of signal lines 202 , 203 , and 204 and the lower surface of the cathode electrode 493 .

[0303] The plurality of first non-emission areas NEA1 disposed in each of the sub-pixels SP1, SP2, SP3, and SP4 may be disposed in a hexagonal shape having a partial area (eg, a corner portion) opened in a plan view, as shown in FIG. Figure 2 shown.

[0304] Here, the opening may also mean that the first non-light emitting area NEA1 is not provided.

[0305] However, the first non-light emitting region of each sub-pixel according to an embodiment of the present disclosure is not limited to being provided in a hexagonal shape having a partial region opened in a plan view, and may be provided in various shapes.

[0306] This will be referenced below Figures 10 to 12 Give a description.

[0307] Figures 10 to 12 are diagrams each illustrating a planar structure of a region corresponding to an opening of a bank provided in at least one sub-pixel in a display region of a display panel according to an embodiment of the present disclosure.

[0308] Reference Figures 10 to 12 In a region corresponding to the opening OP of the bank 290 in the display panel according to an embodiment of the present disclosure, a plurality of first non-emission regions NEA1, a plurality of first emission regions EA1, and a second emission region EA2 may be disposed.

[0309] Reference Figures 10 to 12 , the plurality of first non-emission areas NEA1 may be disposed to be spaced apart from each other.

[0310] The first light emitting area EA1 may be disposed to surround each of the first non-light emitting areas NEA1.

[0311] The second light emitting area EA2 may be disposed to surround the plurality of first light emitting areas EA1.

[0312] Figures 10 to 12 A structure in which the second light emitting area EA2 surrounds the first light emitting area EA1 is illustrated. However, the structure of the display panel according to the embodiment of the present disclosure is not limited thereto, and as Figure 8 As shown, the third light emitting area EA3 may be additionally disposed between the first light emitting area EA1 and the second light emitting area EA2.

[0313] Reference Fig.10 , some of the plurality of first non-luminescent regions NEA1 may be arranged such that their long sides are located in the first direction, and the remaining first non-luminescent regions NEA1 may be arranged such that their long sides are located in the second direction.

[0314] Reference Fig.10 , the plurality of first non-emission areas NEA1 whose long sides are located in the first direction and the plurality of first non-emission areas NEA1 whose long sides are located in the second direction may not overlap with each other in a plan view.

[0315] For example, at least four first non-emission areas NEA1 may be arranged in a quadrangular shape having open corners.

[0316] Reference Fig.10 The plurality of first non-emission areas NEA1 and the plurality of first emission areas EA1 surrounding the first non-emission areas NEA1 may be arranged in a quadrilateral shape having open corners in a plan view. For example, the plurality of first non-emission areas NEA1 may have a rectangular shape and may be arranged in a series of columns intersecting a series of rows.

[0317] In at least one sub-pixel, a plurality of quadrilateral shapes having open corners formed by the plurality of first non-emission areas NEA1 may be arranged in the first direction, and may also be arranged in the second direction.

[0318] Reference Fig.10 , a first non-emission area NEA1 and a first emission area EA1 surrounding the first non-emission area NEA1 may be provided.

[0319] However, the embodiments of the present disclosure are not limited thereto, and Fig.11As shown, at least four first non-emission areas NEA1 and the first emission areas EA1 surrounding them may be arranged in a rhombus shape with open corners. For example, the plurality of first non-emission areas NEA1 may have a rectangular shape and be arranged in a repeated "X" pattern.

[0320] In at least one sub-pixel, a plurality of rhombus shapes having open corners formed by the plurality of first non-emission areas NEA1 may be arranged in the first direction, and may also be arranged in the second direction.

[0321] Reference Fig.12 , at least two first non-emission areas NEA1 and the first emission areas EA1 surrounding them may be disposed in a direction that is the same as or similar to the first direction in a plan view.

[0322] Reference Fig.12 , at least four first non-emission areas NEA1 and the first emission areas EA1 surrounding them may be disposed to be spaced apart from each other in a plan view in a region between the first direction and the second direction.

[0323] Reference Fig.12 In an area corresponding to the opening of the bank provided in one sub-pixel, when the outer edges of the six first non-emission areas NEA1 and the first emission areas EA1 surrounding them are connected, a hexagonal shape may be formed. For example, the plurality of first non-emission areas NEA1 may be arranged in a star pattern or a spoke pattern around a common center point.

[0324] Reference Figures 10 to 12 The distance between a first non-luminous region NEA1 whose long side is located in the first direction and another first non-luminous region NEA1 located closest and whose long side is located in the first direction (hereinafter referred to as the second distance b) may be 10 μm to 20 μm (e.g., 15 μm).

[0325] In addition, the distance (second distance b) between one first non-luminescent area NEA1 whose long side is located in the second direction and another first non-luminescent area NEA1 located closest and whose long side is located in the second direction may also be 10 μm to 20 μm (for example, 15 μm).

[0326] As such, since the second distance b is within the range of 10 μm to 20 μm (eg, 15 μm), the display panel according to the embodiment of the present disclosure may achieve the effects of achieving high resolution and improving or maximizing light efficiency.

[0327] Fig.131 is a plan view illustrating the shape of a mask MASK used to manufacture a planar structure of a region corresponding to an opening of a bank provided in at least one sub-pixel in a display region of a display panel according to an embodiment of the present disclosure.

[0328] Reference Fig.13 , by using the mask MASK having the first slit S1 and the second slit S2 , a planar structure of a region corresponding to the opening OP of the bank provided in at least one sub-pixel in the display area of ​​the display panel according to an embodiment of the present disclosure may be manufactured.

[0329] exist Fig.13 In the embodiment, the case where the first slit S1 is a rectangular slit with a short side m and a long side n and the second slit S2 surrounding the first slit S1 has a thickness t will be described as an example. The shapes of the first slit S1 and the second slit S2 are not limited thereto and may be modified in various ways depending on the shape of the planar structure.

[0330] When viewed on a plane defined by the first direction FD and a second direction SD perpendicular to the first direction FD, one side of the second slit S2 may be disposed to face one side of another second slit S2.

[0331] One side of one second slit S2 may be spaced apart from one side of another second slit S2 facing the one second slit S2 by a second distance b.

[0332] In order to adjust the taper angle of the anode electrode 270 , the short side m and the long side n of the first slit S1 of the mask MASK and the thickness t of the second slit S2 may be adjusted.

[0333] Specifically, in order to reduce the taper angle of the anode electrode 270 , the short side m of the first slit S1 may be 1 μm to 5 μm, the long side n may be 1 μm to 10 μm and the thickness t of the second slit S2 may be 0.5 μm to 3 μm.

[0334] Fig.14 and Fig.15 is a graph comparing characteristics of light emitted from one sub-pixel of a display panel according to an embodiment of the present disclosure with characteristics of light emitted from one sub-pixel of a display panel according to a comparative example.

[0335] Specifically, Fig.14 is a graph comparing the light efficiency of a display panel according to an embodiment of the present disclosure with the light efficiency of a display panel according to a comparative example, and Fig.15 is a graph comparing power consumption of a display panel according to an embodiment of the present disclosure with power consumption of a display panel according to a comparative example.

[0336] according to Fig.14 and Fig.15 The structure of the display panel of the embodiment may be Figure 8 The structure shown.

[0337] As a general display panel structure, according to Fig.14 and Fig.15 The structure of the display panel of the comparative example may be a structure in which one sub-pixel is composed of one light-emitting region (a region corresponding to the opening of the bank) and a non-light-emitting region surrounding the light-emitting region.

[0338] Reference Fig.14 It can be seen that, under the same current density, the display panel according to the embodiment of the present disclosure has higher light efficiency than the display panel according to the comparative example.

[0339] Reference Fig.15 It can be seen that, under the same power consumption, the display panel according to the embodiment of the present disclosure has a higher brightness value than the display panel according to the comparative example.

[0340] In other words, it can be seen that the power consumption of the display panel according to the embodiment of the present disclosure is lower than that of the display panel according to the comparative example in order to achieve a specific brightness value P. Therefore, the display panel according to the embodiment of the present disclosure can use less power and provide greater brightness.

[0341] Figures 16 to 20 is a diagram schematically showing a manufacturing process of a display panel according to an embodiment of the present disclosure.

[0342] Reference Fig.16 , the first signal line 201 and the second signal line 202 may be disposed on the substrate 400 , and the first insulating layer 401 and the second insulating layer 402 may be sequentially disposed on the substrate 400 on which the first signal line 201 and the second signal line 202 are disposed.

[0343] The fifth signal line 205 and the third insulating layer 403 may be sequentially disposed on the second insulating layer 402 .

[0344] Thereafter, the color filter 280 may be disposed on the third insulating layer 403 .

[0345] Reference Fig.16 , a fourth insulating layer material 1404 may be disposed on the substrate 400 having the color filter 280 disposed thereover.

[0346] Reference Fig.17 , a plurality of anode electrodes 270 including a first anode electrode 471 and a second anode electrode 472 may be disposed on the fourth insulating layer material 1404 .

[0347] The plurality of anode electrodes 270 may be disposed to be spaced apart from each other, and may be disposed to expose a portion of an upper surface of the fourth insulating layer material 1404 .

[0348] Reference Fig.17 , the photoresist 1500 may be disposed on the plurality of anode electrodes 270 .

[0349] The photoresist 1500 may include at least one hole 1510 in one sub-pixel.

[0350] The hole 1510 of the photoresist 1500 may be formed to overlap a region where the plurality of anode electrodes 270 are not disposed.

[0351] For example, refer to Fig.17 , the hole 1510 of the photoresist 1500 may be formed to overlap with a region between the first anode electrode 471 and the second anode electrode 472 (eg, between two adjacent anode electrodes).

[0352] In addition, the hole 1510 of the photoresist 1500 may be disposed to overlap a portion of the upper surface of the fourth insulating layer material 1404 exposed by the first anode electrode 471 and the second anode electrode 472 .

[0353] Thereafter, a portion of the fourth insulating layer material 1404 may be patterned using the photoresist 1500 including the holes 1510 as a mask.

[0354] Specifically, refer to Fig.17 , when the dry etching process is performed in a state where the photoresist 1500 including the hole 1510 is provided, the fourth insulating layer material 1404 may be patterned in a region where the photoresist 1500 is not provided.

[0355] After patterning the fourth insulating layer material 1404 , the photoresist 1500 may be removed.

[0356] Therefore, if Fig.18 As shown, after the dry etching process of the fourth insulating layer material 1404, a fourth insulating layer 404 having a recessed portion 410 formed therein may be formed.

[0357] Specifically, refer to Fig.17 and Fig.18Since the hole 1510 of the photoresist 1500 is disposed between the first anode electrode 471 and the second anode electrode 472 to overlap with the portion of the upper surface of the fourth insulating layer material 1404 exposed by the plurality of anode electrodes 270, the fourth insulating layer material 1404 may be removed only in a partial region between the first anode electrode 471 and the second anode electrode 472. For example, a concave portion or a groove may be formed in the fourth insulating layer 404 between the first anode electrode 471 and the second anode electrode 472.

[0358] Therefore, the recessed portion 410 formed in the fourth insulating layer 404 may be disposed to be spaced apart from the first anode electrode 471 and the second anode electrode 472 .

[0359] Afterwards, if Fig.19 As shown, a bank 290 including an opening OP may be disposed over the substrate 400 .

[0360] A portion of the opening OP of the bank 290 may overlap the entire recess portion 410 of the fourth insulating layer 404 .

[0361] Afterwards, if Fig. 20 As shown, the light emitting layer 492 and the cathode electrode 493 can be sequentially disposed on the substrate 400 with the bank 290 disposed thereon. For example, a portion of the cathode electrode 493 can be sunken into or below the recessed portion 410, and some of the light generated from the light emitting layer 492 can be reflected out of the display device. For example, the reflected light can pass between adjacent anodes and leave the display device without being blocked by the transparent anode. Therefore, more light can be emitted from the sub-pixel with less power.

[0362] The following will refer to Fig.21 and Fig. 22 The structure of the display panel according to the embodiment of the present disclosure is further described.

[0363] Fig.21 and Fig. 22 are diagrams each showing a cross-sectional structure of a display panel according to an embodiment of the present disclosure.

[0364] Reference Fig.21 and Fig. 22 , the display panel according to the embodiment of the present disclosure may include a thin film transistor and a light emitting element disposed on a substrate 400 .

[0365] Specifically, a plurality of signal lines 1903 and 1909 and a light shielding portion 1906 may be provided on the substrate 400 .

[0366] Fig.21 and Fig. 22Each of the signal lines 1903 and 1909 can be Figure 7 Any one of the plurality of signal lines 201, 202, 203 and 204 shown.

[0367] Each of the signal lines 1903 and 1909 may include a plurality of layers.

[0368] For example, one signal line 1903 may include a first layer 1901 and a second layer 1902 disposed on the first layer 1901 , and another signal line 1909 may include a fifth layer 1907 and a sixth layer 1908 disposed on the fifth layer 1907 .

[0369] The light shielding portion 1906 may have a structure including a third layer 1904 and a fourth layer 1905 provided on the third layer 1904 .

[0370] The first layer 1901 , the third layer 1904 , and the fifth layer 1907 may include the same material as one another, and the second layer 1902 , the fourth layer 1905 , and the sixth layer 1908 may include the same or substantially the same material as one another.

[0371] The first insulating layer 401 and the second insulating layer 402 may be sequentially disposed on the plurality of signal lines 1903 and 1909 and the light shielding portion 1906 .

[0372] A thin film transistor and a plurality of electrodes may be disposed on the second insulating layer 402 .

[0373] Specifically, refer to Fig.21 and Fig. 22 In the display area of ​​the display panel, a first active layer 1910 , a second active layer 1911 , and a third active layer 1912 may be disposed on the second insulating layer 402 .

[0374] At least one active layer among the first to third active layers 1910 , 1911 , and 1912 may include an oxide semiconductor material.

[0375] As a semiconductor material whose conductivity is controlled and whose band gap is adjusted by doping an oxide material, the oxide semiconductor material may generally be a transparent semiconductor material having a wide band gap.

[0376] For example, oxide semiconductor materials may include: IGZO (indium gallium zinc oxide), ZnO (zinc oxide), IGO (indium gallium oxide), IZO (indium zinc oxide), CdO (cadmium oxide), InO (indium oxide), ZTO (zinc tin oxide), ZITO (zinc indium tin oxide), IGZTO (indium gallium zinc tin oxide), etc.

[0377] The gate insulating layer 1920 may be disposed on the first active layer 1910 and the second active layer 1911 .

[0378] Each of the first to third active layers 1910 , 1911 , and 1912 may be in a conductive state in a region in which each of the first to third active layers 1910 , 1911 , and 1912 does not overlap the gate insulating layer 1920 .

[0379] That is, a region in which each of the first to third active layers 1910 , 1911 , and 1912 overlaps the gate insulating layer 1920 may be a non-conductive region.

[0380] Reference Fig.21 and Fig. 22 , the third active layer 1912 may be made conductive to function as an electrode. The third active layer 1912 may form a storage capacitor Cst together with a signal line disposed under the third active layer 1912.

[0381] Reference Fig.21 and Fig. 22 , the gate insulating layer 1920 may be disposed on a portion of an upper surface of the first active layer 1910 and a portion of an upper surface of the second active layer 1911 .

[0382] In the display region, a source electrode 1931 , a drain electrode 1932 , and a gate electrode 1933 may be disposed on the gate insulating layer 1920 .

[0383] However, the embodiments of the present disclosure are not limited thereto, and the source electrode 1931 , the drain electrode 1932 , and the gate electrode 1933 may be disposed on the gate insulating layer 1920 .

[0384] In the non-display area of ​​the display panel, the electrode may be disposed at the same or substantially the same layer and include the same or substantially the same material as the source electrode 1931 , the drain electrode 1932 , and the gate electrode 1933 .

[0385] For example, Fig.21 and Fig. 22 As shown, the pad electrode 1935 may be disposed on the second insulating layer 402 .

[0386] The source electrode 1931 , the drain electrode 1932 , the gate electrode 1933 , and the pad electrode 1935 may be made of multiple layers.

[0387] For example, each of the source electrode 1931, the drain electrode 1932, the gate electrode 1933, and the pad electrode 1935 may be made of at least two layers. However, the embodiments of the present disclosure are not limited thereto, and at least one electrode may be made of a single layer.

[0388] The first layer 1931a of the source electrode 1931, the first layer 1932a of the drain electrode 1932, the first layer 1933a of the gate electrode 1933, and the first layer 1935a of the pad electrode 1935 may include the same or substantially the same material, and the second layer 1931b of the source electrode 1931, the second layer 1932b of the drain electrode 1932, the second layer 1933b of the gate electrode 1933, and the second layer 1935b of the pad electrode 1935 may include the same or substantially the same material. However, embodiments of the present disclosure are not limited thereto and may include different materials.

[0389] In the display region, the third insulating layer 403 may be disposed on the substrate 400 over which the source electrode 1931 , the drain electrode 1932 , and the gate electrode 1933 are disposed.

[0390] The color filter 280 may be disposed on the third insulating layer 403. The color filter 280 may overlap with the plurality of light emitting areas EA1 and EA2 defined in one sub-pixel.

[0391] A fourth insulating layer 404 may be disposed on the color filter 280 .

[0392] In one sub-pixel, the fourth insulating layer 404 may include at least two holes and at least one recessed portion 410 .

[0393] For example, refer to Fig.21 and Fig. 22 , the recessed portion 410 of the fourth insulating layer 404 may overlap a portion of the color filter 280 .

[0394] However, embodiments of the present disclosure are not limited thereto, and the recessed portion 410 of the fourth insulating layer 404 may be disposed even in a sub-pixel in which the color filter 280 is not disposed.

[0395] Reference Fig.21 and Fig. 22 , one hole of the fourth insulating layer 404 may be disposed above the source electrode 1931 and may overlap with the hole of the third insulating layer 403 to expose a portion of the upper surface of the source electrode 1931 .

[0396] Another hole of the fourth insulating layer 404 may be defined in a region overlapping the third active layer 1912 .

[0397] The first anode electrode 471 and the second anode electrode 472 may be disposed on the fourth insulating layer 404 .

[0398] The first anode electrode 471 and the second anode electrode 472 may be disposed to be spaced apart from each other in a cross-sectional view with at least one recess portion 410 of the fourth insulating layer 404 interposed therebetween.

[0399] Although the cross-sectional view shows a structure in which only the second anode electrode 472 is electrically connected to the source electrode 1931 of the thin film transistor, the first anode electrode 471 may also be electrically connected to the thin film transistor to which the second anode electrode 472 is electrically connected.

[0400] Specifically, the anode electrode 270 provided in one subpixel has a shape in which a plurality of holes are formed in the body of the anode electrode 270 , and the plurality of holes may correspond to regions where the anode electrode 270 and the fourth insulating layer 404 do not overlap each other in the opening of the bank 290 .

[0401] Therefore, the first anode electrode 471 and the second anode electrode 472 may be connected to each other (integrally formed) in a plan view, and may be electrically connected to the same thin film transistor.

[0402] Reference Fig.21 and Fig. 22 , the second anode electrode 472 may also be disposed in a portion of a hole overlapping the third active layer 1912 among the holes disposed in the fourth insulating layer 404 .

[0403] Therefore, the second anode electrode 472 may overlap the third active layer 1912 in the hole of the fourth insulating layer 404 to form the storage capacitor Cst.

[0404] In other words, each of the light shielding portion 1906 , the third active layer 1912 , and the second anode electrode 472 may serve as a storage capacitor electrode.

[0405] Reference Fig.21 and Fig. 22 , the bank 290 may be disposed on the substrate 400 on which the anode electrode 270 is disposed.

[0406] In one sub-pixel, the bank 290 may include one opening OP.

[0407] One opening OP of the bank 290 may include a plurality of light emitting areas EA1 and EA2 and at least one non-light emitting area NEA1.

[0408] Specifically, the opening OP of the bank 290 may overlap the first non-emission area NEA1, the first emission area EA1, and the second emission area EA2.

[0409] The first non-emission area NEA1 and the first emission area EA1 may correspond to an area where the anode electrode 270 does not overlap the fourth insulating layer 404 in the opening OP of the bank 290 .

[0410] In particular, the first non-emission area NEA1 may be an area corresponding to a flat portion of the recessed portion 410 of the fourth insulating layer 404 .

[0411] A portion of the first light emitting area EA1 may correspond to an inclined portion of the recess portion 410 of the fourth insulating layer 404 .

[0412] Another portion of the first light emitting region EA1 may be a region not overlapping the anode electrode 270 in a remaining region except for the recessed portion 410 of the fourth insulating layer 404 .

[0413] The second light emitting area EA2 may correspond to a region where the anode electrode 270 overlaps the fourth insulating layer 404 in the opening OP of the bank 290 .

[0414] Reference Fig.21 and Fig. 22 , a light emitting layer 492 and a cathode electrode 493 of the light emitting element may be sequentially disposed on the substrate 400 having the bank 290 disposed thereover.

[0415] Reference Fig.21 , each of the light emitting layer 492 and the cathode electrode 493 may include at least two steps in a region corresponding to the opening OP of the bank 290 .

[0416] Alternatively, if Fig. 22 As shown, each of the light emitting layer 492 and the cathode electrode 493 may include a circular recess DPS in a region corresponding to the opening OP of the bank 290 .

[0417] Reference Fig.21 Since the step of the cathode electrode 493 includes a reflective electrode, light emitted from a light emitting element disposed between the anode electrode 270 and the cathode electrode 493 may be reflected by the step of the cathode electrode 493 , and thus, the light may be additionally extracted to the outside of the substrate 400 .

[0418] Alternatively, refer to Fig. 22 Since the recess DPS of the cathode electrode 493 including the reflective electrode, light emitted from the light emitting element disposed between the anode electrode 270 and the cathode electrode 493 can be reflected by the recess DPS of the cathode electrode 493, and thus, the light can be additionally extracted to the outside of the substrate 400.

[0419] In addition, due to the structural characteristics, the phenomenon of light transmission from one sub-pixel to another adjacent sub-pixel can be reduced, thereby suppressing the light leakage phenomenon and improving the light extraction efficiency.

[0420] A brief description of the embodiments of the present disclosure described above is as follows.

[0421] A display panel according to an embodiment of the present disclosure may include: a substrate including a plurality of sub-pixels; an insulating layer disposed on the substrate and including at least one recessed portion in at least one sub-pixel; an anode electrode disposed on the insulating layer and not overlapping the recessed portion; a dam disposed on a portion of an upper surface of the anode electrode and the insulating layer and having an opening in each of the plurality of sub-pixels; a light-emitting layer disposed in the opening; and a cathode electrode disposed on the light-emitting layer, wherein each of the light-emitting layer and the cathode electrode overlaps the anode electrode in the opening and the recessed portion of the insulating layer and has a step in the opening.

[0422] In the display panel according to the embodiment of the present disclosure, in at least one sub-pixel, the anode electrode may have a hole overlapping the recessed portion in a region overlapping the opening.

[0423] In the display panel according to an embodiment of the present disclosure, the recessed portion may include a flat portion and an inclined portion extending from the flat portion, the insulating layer may include an upper surface extending from the inclined portion, and the hole of the anode electrode may overlap a portion of the upper surface.

[0424] In the display panel according to an embodiment of the present disclosure, the light emitting layer and the cathode electrode have a first step and a second step, wherein the first step may be disposed at a boundary between the anode electrode and the upper surface, and wherein the second step may be disposed at a boundary between the upper surface and the recessed portion.

[0425] In the display panel according to an embodiment of the present disclosure, a distance from an upper surface of the insulating layer to an upper surface in a region where the first step of the cathode electrode is located may be longer than a distance from an upper surface of the insulating layer to an upper surface in a region where the second step of the cathode electrode is located.

[0426] In the display panel according to the embodiment of the present disclosure, at least one sub-pixel may include a plurality of light emitting regions and at least one non-light emitting region in a region overlapping the opening.

[0427] In the display panel according to an embodiment of the present disclosure, a region corresponding to the flat portion of the recessed portion may be the first non-light emitting region.

[0428] In the display panel according to the embodiment of the present disclosure, a region corresponding to the inclined portion of the recessed portion and an upper surface of the insulating layer extending from the inclined portion and not overlapping the anode electrode may be the first light emitting region.

[0429] In the display panel according to an embodiment of the present disclosure, the first light emitting area may surround the first non-light emitting area.

[0430] In the display panel according to the embodiment of the present disclosure, a region in the opening where the insulating layer and the anode electrode overlap may be a second light emitting region.

[0431] In the display panel according to an embodiment of the present disclosure, the second light emitting area may surround the first light emitting area.

[0432] In the display panel according to an embodiment of the present disclosure, the brightness of the first light emitting area may be equal to or lower than the brightness of the second light emitting area.

[0433] In the display panel according to the embodiment of the present disclosure, a third light emitting area may be further included, the third light emitting area being disposed between the first light emitting area and the second light emitting area.

[0434] In the display panel according to an embodiment of the present disclosure, the first light emitting region may be a region corresponding to the inclined portion of the recessed portion, and the third light emitting region may be a region corresponding to an upper surface of the insulating layer extending from the inclined portion and not overlapping the anode electrode.

[0435] In the display panel according to an embodiment of the present disclosure, the brightness of the third light emitting area may be lower than the brightness of the first light emitting area and the second light emitting area.

[0436] In the display panel according to the embodiment of the present disclosure, the region overlapping the bank may be the second non-light emitting region.

[0437] In the display panel according to the embodiment of the present disclosure, the cathode electrode may include a reflective electrode.

[0438] In the display panel according to an embodiment of the present disclosure, the display device may further include a color filter disposed over the substrate in at least one sub-pixel and under the insulating layer, wherein the recessed portion overlaps a portion of the color filter.

[0439] In the display panel according to the embodiment of the present disclosure, the steps of the light emitting layer and the cathode electrode may overlap a portion of the color filter.

[0440] A display panel according to an embodiment of the present disclosure may include: a substrate including a plurality of sub-pixels; an insulating layer disposed on the substrate and including at least one recessed portion in at least one sub-pixel; an anode electrode disposed on the insulating layer and not overlapping the recessed portion; a dam disposed on a portion of an upper surface of the anode electrode and the insulating layer and having an opening in each of the plurality of sub-pixels; a light-emitting layer disposed in the opening; and a cathode electrode disposed on the light-emitting layer, wherein each of the light-emitting layer and the cathode electrode overlaps the anode electrode in the opening and the recessed portion of the insulating layer and has a circular recess in the opening.

[0441] In the display panel according to the embodiment of the present disclosure, one end of the recessed portion and one end of the anode electrode may contact each other.

[0442] In the display panel according to the embodiment of the present disclosure, the concave portion of each of the light emitting layer and the cathode electrode may overlap the concave portion.

[0443] A display device according to an embodiment of the present disclosure may include: a plurality of first non-luminous areas; a plurality of first luminous areas, the plurality of first luminous areas surrounding the first non-luminous areas; a second luminous area, the second luminous area surrounding the first luminous area; and a second non-luminous area surrounding the second luminous area, wherein the plurality of first non-luminous areas, the plurality of first luminous areas, the second luminous areas and the second non-luminous areas are arranged in one sub-pixel, and wherein the plurality of first non-luminous areas, the plurality of first luminous areas and the second luminous areas are arranged in at least one of the opening of the embankment or the boundary of the opening.

[0444] In a display device according to an embodiment of the present disclosure, a first light-emitting area may be disposed between a second light-emitting area and a second non-light-emitting area in at least a portion of a boundary of an opening, and a boundary between the second light-emitting area and the second non-light-emitting area may have a concave-convex shape, a wavy shape, or a curled shape.

[0445] In the display device according to the embodiment of the present disclosure, at the boundary between the second light emitting area and the second non-light emitting area, each of the concave shape and the convex shape may have a polygonal shape.

[0446] The above description is provided to enable any person skilled in the art to make and use the technical concept of the present disclosure, and is provided in the context of a specific application and its requirements. Various modifications, additions, and substitutions to the described embodiments are readily apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments and applications without departing from the technical concept and scope of the present disclosure. The above description and accompanying drawings provide examples of the technical concept of the present disclosure for illustrative purposes only. That is, the disclosed embodiments are intended to illustrate the scope of the technical concept of the present disclosure.

[0447] CROSS-REFERENCE TO RELATED APPLICATIONS

[0448] This application claims priority to Korean Patent Application No. 10-2023-0100793 filed in Korea on August 2, 2023, and Korean Patent Application No. 10-2023-0188036 filed on December 21, 2023, all of which are hereby incorporated by reference in their entirety for all purposes as if fully set forth herein.

Claims

1. A display panel, comprising: A plurality of sub-pixels, wherein the plurality of sub-pixels are arranged on a substrate; an insulating layer disposed on the substrate, and comprising at least one recessed portion in at least one sub-pixel among the plurality of sub-pixels; an anode electrode, the anode electrode being disposed on the insulating layer and not overlapping the recessed portion; a bank portion provided on a portion of an upper surface of the anode electrode and the insulating layer, and having an opening in each of the plurality of sub-pixels; a light emitting layer, the light emitting layer being disposed in the opening; as well as a cathode electrode, the cathode electrode being disposed on the light emitting layer, Each of the light emitting layer and the cathode electrode overlaps the anode electrode and the recessed portion of the insulating layer in the opening, and the cathode electrode has at least one step portion in the opening of the bank.

2. The display panel according to claim 1, wherein: The anode electrode is provided in at least one sub-pixel and has a hole overlapping with the recessed portion of the insulating layer in a region overlapping with the opening of the bank.

3. The display panel according to claim 2, wherein: The recessed portion includes a flat portion and an inclined portion extending from the flat portion, wherein the insulating layer includes an upper surface extending from the inclined portion, and The hole of the anode electrode overlaps a portion of the upper surface of the insulating layer.

4. The display panel according to claim 3, wherein: The at least one step portion of the cathode electrode includes a first step portion and a second step portion, wherein the first step portion is disposed at a boundary between the anode electrode and the upper surface of the insulating layer, and Wherein, the second step portion is disposed at a boundary between the upper surface of the insulating layer and the recessed portion.

5. The display panel according to claim 4, wherein: A distance from the upper surface of the insulating layer in a region where the first step portion is located to an upper surface of the cathode electrode is longer than a distance from the upper surface of the insulating layer in a region where the second step portion is located to the upper surface of the cathode electrode.

6. The display panel according to claim 1, wherein: The at least one sub-pixel includes a plurality of light emitting regions and at least one non-light emitting region in a region overlapping the opening of the bank.

7. The display panel according to claim 6, wherein: A region corresponding to the flat portion of the concave portion is a first non-light emitting region.

8. The display panel according to claim 6, wherein: A region corresponding to the inclined portion of the recessed portion and an upper surface of the insulating layer extending from the inclined portion and not overlapping the anode electrode is a first light emitting region.

9. The display panel according to claim 8, wherein: The first light emitting area surrounds the first non-light emitting area.

10. The display panel according to claim 6, wherein: A region of the opening of the bank overlapping the insulating layer and the anode electrode is a second light emitting region.

11. The display panel according to claim 10, wherein: The second light emitting area surrounds the first light emitting area.

12. The display panel according to claim 10, wherein: The brightness of the first light emitting area is equal to or lower than the brightness of the second light emitting area.

13. The display panel according to claim 10, further comprising: A third light emitting area is disposed between the first light emitting area and the second light emitting area.

14. The display panel according to claim 13, wherein: The first light emitting region corresponds to the inclined portion of the recessed portion, and The third light emitting region corresponds to an upper surface of the insulating layer extending from the inclined portion, and the third light emitting region does not overlap with the anode electrode.

15. The display panel according to claim 13, wherein: The brightness of the third light emitting area is lower than that of the first light emitting area and the second light emitting area.

16. The display panel according to claim 1, wherein: A region overlapping the bank is a second non-light emitting region.

17. The display panel according to claim 1, wherein: The cathode electrode includes a reflective electrode.

18. The display panel according to claim 1, further comprising: a color filter disposed above the substrate and below the insulating layer in the at least one sub-pixel, The concave portion overlaps a portion of the color filter.

19. The display panel according to claim 18, wherein: At least one stepped portion of the cathode electrode overlaps a portion of the color filter.

20. A display panel, comprising: A plurality of sub-pixels, wherein the plurality of sub-pixels are arranged on a substrate; an insulating layer disposed on the substrate, and comprising at least one recessed portion in at least one sub-pixel among the plurality of sub-pixels; an anode electrode, the anode electrode being disposed on the insulating layer and not overlapping the recessed portion; a bank portion provided on a portion of an upper surface of the anode electrode and the insulating layer, and having an opening in each of the plurality of sub-pixels; a light emitting layer, the light emitting layer being disposed in the opening; as well as a cathode electrode, the cathode electrode being disposed on the light emitting layer, Each of the light emitting layer and the cathode electrode overlaps the anode electrode in the opening and the recessed portion of the insulating layer, and the cathode electrode has a recess in the opening, the recess having a circular shape or a curved shape.

21. The display panel according to claim 20, wherein: One end of the recessed portion and one end of the anode electrode contact each other.

22. The display panel according to claim 20, wherein: The recessed portion in the cathode electrode overlaps the recessed portion in the insulating layer.

23. A display device, comprising: a plurality of first non-luminescent regions; A plurality of first light-emitting regions, wherein the plurality of first light-emitting regions surround the first non-light-emitting region; a second light emitting region, the second light emitting region surrounding each of the plurality of first light emitting regions; as well as a second non-luminous region, the second non-luminous region surrounding the second luminous region, The plurality of first non-luminous regions, the plurality of first luminous regions, the second luminous region and the second non-luminous region are arranged in the same sub-pixel, and The plurality of first non-luminescent regions, the plurality of first luminescent regions, and the second luminescent region are disposed in at least one of an opening of the embankment or a boundary of the opening of the embankment.

24. The display device according to claim 23, wherein: In at least a portion of the boundary of the opening, each of the multiple first light-emitting areas is arranged between the second light-emitting area and the second non-light-emitting area, and the boundary between the second light-emitting area and the second non-light-emitting area has a concave-convex shape, a wavy shape or a curved shape.

25. The display device according to claim 24, wherein: A boundary between the second light emitting area and the second non-light emitting area has a polygonal shape.

26. A display panel, comprising: A sub-pixel, wherein the sub-pixel is disposed on a substrate, and the sub-pixel comprises an anode electrode, a light-emitting layer, and a cathode electrode, wherein the anode electrode comprises a first anode electrode portion and a second anode electrode portion; an insulating layer, the insulating layer being disposed between the anode electrode and the substrate; a recessed portion in the insulating layer, the recessed portion being disposed between the first anode electrode portion and the second anode electrode portion, Wherein, the cathode electrode includes a lower cathode electrode portion overlapping the recessed portion in the insulating layer.

27. The display panel according to claim 26, wherein: The cathode electrode comprises a reflective material, and The lower cathode electrode portion is configured to reflect light emitted from the light emitting layer to pass between the first anode electrode portion and the second anode electrode portion and to exit from the display panel.

28. The display panel according to claim 26, wherein: A portion of the light emitting layer is disposed in the recessed portion in the insulating layer, wherein the light emitting layer comprises a concave portion overlapping the concave portion in the insulating layer, and Wherein, a portion of the cathode electrode is disposed in the concave portion in the light emitting layer.

29. The display panel according to claim 26, wherein: The cathode electrode includes a first step portion and a second step portion, and The first step portion of the cathode electrode overlaps with an inclined side surface of the recessed portion in the insulating layer, and the second step portion of the cathode electrode overlaps with a flat bottom surface of the recessed portion in the insulating layer.

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