Display device and method of manufacturing same

Abstract

According to an embodiment of the disclosure, a display device and a method of manufacturing the same are provided. The display device may include: a substrate in which a display area and a non-display area are defined, the non-display area including a pad area; a display section including a substrate and displaying an image; a pad portion disposed in the pad area and including a plurality of pads; a dam positioned between the pad portion and the display portion and surrounding at least one side of the display portion; and a filling layer disposed on the display portion surrounded by the dam to cover the display portion. The filling layer may include a transparent curable resin and be positioned in an uppermost layer in the display area.

Description

[0001] This application claims priority to and all benefits derived from Korean Patent Application No. 10-2023-0100091, filed on Jul. 31, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The present invention relates to a display device and a method of manufacturing the display device. Background Art

[0003] Recently, as interest in information display increases, research and development of display devices are being continuously conducted. Summary of the invention

[0004] The disclosure may provide a display device having improved manufacturing efficiency and reliability and a method of manufacturing the display device.

[0005] According to the disclosed embodiment, the display device may include: a substrate in which a display area and a non-display area are defined, the non-display area including a pad area; a display portion including the substrate and displaying an image; a pad portion provided in the pad area and including a plurality of pads; a dam positioned between the pad portion and the display portion and surrounding at least one side of the display portion; and a filling layer provided on the display portion surrounded by the dam to cover the display portion. The filling layer may include a transparent curable resin and be positioned in the uppermost layer in the display area.

[0006] In an embodiment, the filling layer may include at least one of an epoxy-based resin and a silicon-based resin. The dam may include a siloxane-based resin.

[0007] In an embodiment, the dam may have a width of about 0.5 mm to 5 mm.

[0008] In an embodiment, the dam may include a curable resin having a higher viscosity than the filling layer.

[0009] In an embodiment, the dam and the filling layer may include a curable resin, the viscosity of the curable resin being the same.

[0010] In an embodiment, the substrate may include a silicon wafer substrate.

[0011] In an embodiment, the display unit may include: a pixel circuit layer, which is arranged on a substrate; a light-emitting element layer, which includes a light-emitting element, and the light-emitting element is constructed by a first electrode arranged on the pixel circuit layer, a light-emitting layer arranged on the first electrode, and a second electrode arranged on the light-emitting layer; and a thin film encapsulation layer, which is arranged between the light-emitting element layer and the filling layer.

[0012] In an embodiment, the display part may further include an optical layer disposed between the thin film encapsulation layer and the filling layer.

[0013] In an embodiment, the dam may have a pencil hardness of 7H or greater, and the filling layer may have a pencil hardness of 4H or greater.

[0014] According to the disclosed embodiment, a method for manufacturing a display device may include the following steps: preparing a mother substrate, the mother substrate including a first display unit group and a second display unit group including a first display unit and a second display unit, respectively, and a cutting line of a shape corresponding to each of the first display unit and the second display unit; forming a dam surrounding a display portion of the first display unit and the second display unit; forming a filling layer on the display portion surrounded by the dam; and individually separating the first display unit and the second display unit by cutting the mother substrate by irradiating a laser beam. The first display unit group and the second display unit group are symmetrical with respect to the cutting line between the first display unit group and the second display unit group.

[0015] In an embodiment, each of the first display unit and the second display unit may include a display portion and a pad portion positioned around the display portion. The display portion may include a pixel circuit layer disposed on a mother substrate and a light-emitting element layer including a light-emitting element, the light-emitting element being configured by a first electrode disposed on the pixel circuit layer, a light-emitting layer disposed on the first electrode, and a second electrode disposed on the light-emitting layer.

[0016] In an embodiment, in a plan view, a display portion of each of the first display units and a display portion of each of the second display units in each of the first display unit group and the second display unit group may face each other in a column direction of the mother substrate.

[0017] In an embodiment, in each of the first display unit and the second display unit, a dam may be positioned between the display portion and the pad portion.

[0018] In an embodiment, in each of the first display unit group and the second display unit group, the dam may be coated and then cured to be formed along at least one outer periphery of the display portion of each of the first display unit and the second display unit.

[0019] In an embodiment, in each of the first display cell group and the second display cell group, a filling layer may be applied and then cured to fill the inside of one region of the mother substrate surrounded by the dam.

[0020] In an embodiment, in a plan view, the pad portion of each of the second display units of the first display unit group and the pad portion of each of the first display units of the second display unit group may face each other in a column direction of the mother substrate.

[0021] In an embodiment, the filling layer may include at least one of an epoxy-based resin and a silicon-based resin. The dam may include a siloxane-based resin.

[0022] In an embodiment, the dam may include a curable resin having a higher viscosity than the filling layer.

[0023] In an embodiment, the dam and the filling layer may include a curable resin, the viscosity of the curable resin being the same.

[0024] In an embodiment, the dam may be applied and then directly cured to be formed along at least one outer periphery of the display portion of each of the first display unit and the second display unit.

[0025] According to an embodiment, a dam formed of a curable resin having a certain level of viscosity or more is formed on a mother substrate including a first display unit group and a second display unit group to surround an area of ​​each of the first display unit group and the second display unit group. In addition, a space surrounded by the dam may be filled with a filling layer formed of a curable resin having a certain level of viscosity or more.

[0026] According to an embodiment, by ensuring sufficient supporting strength equal to that of the encapsulation glass (or cover glass) during laser cutting, and by applying a coating liquid formed of a curable resin having a viscosity of a certain level or higher and then curing the coating liquid, the mother substrate can be easily separated by using a dam and a filling layer formed to have strong hardness to protect each display unit in the first display unit group and the second display unit group.

[0027] Therefore, a display device having improved manufacturing efficiency may be provided by omitting a process of forming an encapsulation glass and a process of cutting the encapsulation glass.

[0028] The effects according to the embodiments are not limited to the above-exemplified contents, and more various effects are included in this specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 is a schematic plan view showing a mother substrate according to an embodiment.

[0030] Figure 2 It shows Figure 1 Schematic enlargement of the EA part.

[0031] Figure 3 It is along Figure 2 A schematic cross-sectional view taken along line II'.

[0032] Figure 4 It is along Figure 2 A schematic cross-sectional view taken along line II-II'.

[0033] Figure 5 is a schematic plan view showing a display device according to the embodiment.

[0034] Figure 6 is a schematic cross-sectional view showing a display panel according to an embodiment.

[0035] Figure 7 is a schematic exploded perspective view showing a display panel according to an embodiment.

[0036] Figure 8 It shows that the Figure 5 Schematic circuit diagram of the electrical connection relationship of components in each of the pixels shown in FIG.

[0037] Fig.9A , Fig. 9B , Fig. 9C and Fig.9D It is along Figure 5 A schematic cross-sectional view taken along line III-III'.

[0038] Fig.9E It shows Fig.9A Schematic diagram of the light-emitting layer.

[0039] Fig. 10A , Fig. 10B , Fig. 10C , Fig. 10D and Fig. 10E is with Figure 1 EA portion corresponds to a schematic plan view, which sequentially illustrates a method of manufacturing a display device according to an embodiment.

[0040] Fig.11A It is along Fig. 10A Schematic cross-sectional view taken along line IV-IV'.

[0041] Fig. 11B It is along Fig. 10B Schematic cross-sectional view taken along line IV-IV'.

[0042] Fig. 11C It is along Fig. 10C Schematic cross-sectional view taken along line IV-IV'.

[0043] Fig.11D It is along Fig. 10D Schematic cross-sectional view taken along line IV-IV'.

[0044] Fig.11E It is along Fig. 10E Schematic cross-sectional view taken along line IV-IV'.

[0045] Fig.12 is with Figure 2 A schematic cross-sectional view corresponding to line II' of FIG. 1 shows a mother substrate according to an embodiment.

[0046] Fig.13 is with Figure 2 A schematic cross-sectional view corresponding to line II' of FIG. 1 shows a mother substrate according to an embodiment.

[0047] Fig.14A and Fig. 14B It shows the formation Fig.13 A schematic cross-sectional view of a method for manufacturing a dam. DETAILED DESCRIPTION

[0048] The disclosure can be modified in various ways and have various forms. Therefore, specific embodiments will be shown in the drawings and will be described in detail in the specification. However, it should be understood that the disclosure is not intended to be limited to the specific forms disclosed, and the disclosure includes all modifications, equivalents and replacements within the disclosed technical scope.

[0049] When describing each of the accompanying drawings, similar reference numerals are used for similar components. In the accompanying drawings, for the sake of clarity of disclosure, the size of the structure is enlarged from the actual size. Terms such as "first", "second", etc. can be used to describe various components, but the components should not be limited by the terms. The terms are only used to distinguish one component from another component. For example, without departing from the scope of the disclosure, a first component can be referred to as a second component, and similarly, a second component can also be referred to as a first component.

[0050] It should be understood that, in the present application, the terms "including", "having" and the like are used to illustrate the existence of the features, quantities, steps, operations, components, parts or combinations thereof described in the specification, but do not exclude the possibility of the pre-existence or addition of one or more other features, quantities, steps, operations, components, parts or combinations thereof. In addition, for a part of a layer, film, region, plate, etc., it is referred to as "on" another part, it not only includes the case where the part is "directly on" the other part, but also includes the case where there is another part between the part and the other part. In addition, in the present specification, when a part of a layer, film, region, plate, etc. is formed on another part, the formation direction is not limited to the upper direction, but includes forming the part on the side surface or in the lower direction. On the contrary, when a part of a layer, film, region, plate, etc. is formed "under" another part, this not only includes the case where the part is "directly under" the other part, but also includes the case where there is another part between the part and the other part.

[0051] Hereinafter, the disclosed embodiments and other embodiments necessary for those skilled in the art to understand the disclosure will be described in detail with reference to the accompanying drawings. In the following description, unless the context clearly indicates otherwise, a singular expression includes a plural expression.

[0052] Figure 1is a schematic plan view showing a mother substrate MS according to an embodiment.

[0053] Reference Figure 1 For the convenience of the process, the mother substrate MS may be a substrate for simultaneously manufacturing a plurality of display units DC. The mother substrate MS may include at least one unit region. The unit region may be a portion corresponding to a separate display unit DC (or a separate display device), and a separate display unit DC may be formed in each unit region.

[0054] In an embodiment, the mother substrate MS may be a silicon wafer substrate formed using a semiconductor process. For example, the mother substrate MS may include a semiconductor material, such as a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor, but is not limited thereto. According to an embodiment, the mother substrate MS may include a transparent insulating material capable of transmitting light. For example, the mother substrate MS may be a rigid substrate or a flexible substrate. The rigid substrate may be, for example, one of a glass substrate, a quartz substrate, a glass ceramic substrate, and a crystallized glass substrate. The flexible substrate may be one of a film substrate and a plastic substrate including a polymerized organic material. For example, the flexible substrate may include at least one of polystyrene, polyvinyl alcohol, polymethyl methacrylate, polyether sulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, cellulose triacetate, and cellulose acetate propionate.

[0055] Each display unit DC may be individually separated to be used as a display device, and may be separated by a cutting process after a plurality of display units DC are simultaneously formed on the mother substrate MS. The display unit DC may be provided in plurality on the mother substrate MS, and may be arranged in a matrix form along rows (or display unit rows) extending in the first direction DR1 and columns (or display unit columns) extending in the second direction DR2, but is not limited thereto.

[0056] Figure 2 It shows Figure 1 Schematic enlargement of the EA part. Figure 3 It is along Figure 2 A schematic cross-sectional view taken along line II'. Figure 4 It is along Figure 2 A schematic cross-sectional view taken along line II-II'.

[0057] Reference Figures 1 to 4, a cutting line CUL of a shape corresponding to each of the display units DC (or display devices DD) may be provided in the mother substrate MS. The cutting line CUL may include a first cutting line CUL1 extending in the first direction DR1 and a second cutting line CUL2 extending in the second direction DR2. Each of the display units DC (or display devices DD) may be individually separated by a process of cutting the mother substrate MS along the cutting line CUL using a laser beam.

[0058] The mother substrate MS may be a substrate SUB that is a base material of the corresponding display cells DC after the display cells DC are individually separated.

[0059] Each of the display units DC may include a display part DPP and a pad part PDP. The display part DPP may be positioned in the display area DA, and the pad part PDP may be positioned in one area (eg, pad area PDA) of the non-display area NDA.

[0060] The display part DPP may include a substrate SUB, a pixel circuit layer PCL, a display element layer DPL, and an optical layer OPL (or a microlens array). The optical layer OPL may be selectively provided.

[0061] The substrate SUB may be a region of the mother substrate MS and may be a silicon wafer substrate. The substrate SUB may include a display area DA in which an image is displayed and a non-display area NDA in which no image is displayed.

[0062] The pixel circuit layer PCL may be disposed on the substrate SUB and may include circuit elements.

[0063] The display element layer DPL may be disposed on the pixel circuit layer PCL, and may include a light emitting element layer including a light emitting element and a thin film encapsulation layer disposed on the light emitting element layer.

[0064] The optical layer OPL may be disposed on the display element layer DPL, and may include a micro lens array for improving extraction efficiency of light emitted from the display element layer DPL, but is not limited thereto.

[0065] In an embodiment, the first display cell group DCG1 and the second display cell group DCG2 alternately arranged in the second direction DR2 (or column direction) may be defined in the mother substrate MS. For example, the first display cell group DCG1, the second display cell group DCG2, the first display cell group DCG1, the second display cell group DCG2, and ... may be sequentially arranged.

[0066] Each of the first display unit group DCG1 and the second display unit group DCG2 may include a first row R1 (e.g., a first display unit row) and a second row R2 (e.g., a second display unit row) extending in the first direction DR1. A plurality of first display units DC1 (or first display devices DD1) may be arranged in the first row R1, and a plurality of second display units DC2 (or second display devices DD2) may be arranged in the second row R2.

[0067] Each of the first display unit DC1 and the second display unit DC2 may include a display part DPP and a pad part PDP. After a process of separating the mother substrate MS in units of the display unit DC, an external connection terminal may be bonded to the pad part PDP. The display unit DC may be electrically connected to the outside through the external connection terminal bonded to the pad part PDP.

[0068] In each of the first display unit group DCG1 and the second display unit group DCG2, the display portion DPP may be positioned adjacent to the first cutting line CUL1 positioned between the first display unit DC1 and the second display unit DC2. For example, in each of the first display unit group DCG1 and the second display unit group DCG2, the display portion DPP of the first display unit DC1 and the display portion DPP of the second display unit DC2 may be positioned adjacent to the first cutting line CUL1 positioned between the first display unit DC1 and the second display unit DC2. In this case, in a plan view, the display portion DPP of each of the first display unit DC1 and the display portion DPP of each of the second display unit DC2 face each other in the second direction DR2 (or column direction).

[0069] In addition, in each of the first display cell group DCG1 and the second display cell group DCG2, the pad part PDP may be positioned away from the first cutting line CUL1 positioned between the first display cell DC1 and the second display cell DC2, compared to the display part DPP included in the corresponding display cell group DCG. For example, the pad part PDP may be positioned outside the display part DPP based on the first cutting line CUL1.

[0070] Two display cell groups DCG adjacent in the second direction DR2 may be symmetrical with respect to a first cutting line CUL1 positioned between the two display cell groups DCG. For example, the first display cell group DCG1 and the second display cell group DCG2 may be symmetrical with respect to the first cutting line CUL1 positioned between the first display cell group DCG1 and the second display cell group DCG2. In the two display cell groups DCG, the pad PDP of the second display cell DC2 of the preceding display cell group DCG and the pad PDP of the first display cell DC1 of the succeeding display cell group DCG may face each other based on the first cutting line CUL1 positioned between the two display cell groups DCG. For example, the pad PDP of the second display cell DC2 of the first display cell group DCG1 and the pad PDP of the first display cell DC1 of the second display cell group DCG2 may face each other based on the first cutting line CUL1 positioned between the first display cell group DCG1 and the second display cell group DCG2.

[0071] The dam DAM may be formed in each of the first display cell group DCG1 and the second display cell group DCG2 .

[0072] The dam DAM may be provided in a form surrounding at least one side of the display part DPP in each display unit group DCG. The dam DAM may be provided in a form surrounding at least one side of the display part DPP to include all the display parts DPP included in each display unit group DCG. The dam DAM may be positioned between the display part DPP and the pad part PDP in the non-display area NDA of each display unit DC. In an embodiment, the dam DAM may be constructed by including a curable resin having a viscosity at a certain level or higher. In an embodiment, a viscosity at a certain level or higher may mean a high viscosity within a range, wherein when a first coating liquid corresponding to a base material of the dam DAM is applied to a predetermined application area (or target area), the first coating liquid may be stably fixed in the predetermined application area without flowing or moving. For example, the dam DAM may be constructed by including a siloxane-based resin. The siloxane-based resin may have a viscosity (cps) of, for example, about 70,000 to about 270,000, and have a pencil hardness of 7H or more after being cured. In addition, the siloxane-based resin may have a light transmittance of about 94.34%. However, the material properties of the siloxane-based resin are not limited to the above-described embodiments.

[0073] For example, the dam DAM may have a thickness d of 600 μm or less in the third direction DR3 (e.g., perpendicular to the first direction DR1 and the second direction DR2), and may have a width w of about 2 mm in a direction parallel to the main surface (or upper surface) of the mother substrate MS (or substrate SUB) (e.g., in a plane defined by the first direction DR1 and the second direction DR2), but the dam DAM is not limited thereto. According to an embodiment, the dam DAM may have a width w of about 0.5 mm to about 5 mm in a direction parallel to the main surface of the mother substrate MS (or substrate SUB). The width w of the dam DAM may be determined within a range in which the first coating liquid applied between the display part DPP and the pad part PDP of each display unit DC does not invade each of the display part DPP and the pad part PDP.

[0074] The dam DAM may be a structure that stably fixes and supports the filling layer FIL and each display part DPP while defining the supply position of the filling layer FIL. In addition, the dam DAM may be a reinforcing member that improves the mechanical strength of the mother substrate MS together with the filling layer FIL cured by the curing process. In addition, the dam DAM may control the flow of the monomer of the thin film encapsulation layer included in the display part DPP to define the formation position of the monomer.

[0075] The filling layer FIL may be formed inside an area surrounded by the dam DAM of each of the first display unit group DCG1 and the second display unit group DCG2. The filling layer FIL may be provided in the form of filling the area surrounded by the dam DAM of each of the first display unit group DCG1 and the second display unit group DCG2. The filling layer FIL may be provided on the display portion DPP of the display unit DC of each of the first display unit group DCG1 and the second display unit group DCG2 to cover the display portion DPP. The filling layer FIL may include a curable resin having a viscosity of a certain level or higher. For example, the filling layer FIL may be constructed by including an epoxy resin or a silicone resin. The epoxy resin may have a viscosity (cps) of, for example, about 19 to about 5,400, and may have a pencil hardness of 4H or more after being cured. In addition, the epoxy resin may have a light transmittance of about 92.65%. However, the material properties of the epoxy resin are not limited to the above-described embodiments. The filling layer FIL may include a curable resin having a viscosity lower than that of the dam DAM, but is not limited thereto. According to an embodiment, the filling layer FIL may include a curable resin having the same viscosity as that of the dam DAM.

[0076] In each of the first display cell group DCG1 and the second display cell group DCG2, after applying the second coating liquid corresponding to the base material of the filling layer FIL in the area surrounded by the dam DAM, a curing process using light may be performed to finally form the filling layer FIL in the display cell DC. The filling layer FIL may be cured and fixed by performing the curing process after being coated while filling the inside of one area surrounded by the dam DAM of each of the first display cell group DCG1 and the second display cell group DCG2.

[0077] In the display area DA of each display unit DC, the filling layer FIL may be positioned as the uppermost layer. That is, the filling layer FIL may be positioned at the uppermost layer in the display area DA of each display unit DC to entirely cover the structure positioned thereunder. In an embodiment, the filling layer FIL may protect each display unit DC from external impacts, etc., and may provide an input surface and / or a display surface to a user. The filling layer FIL may be a covering member.

[0078] According to the above-mentioned embodiment, after a filling layer FIL including a curable resin having a viscosity of a certain level or higher is formed in an area surrounded by a dam DAM including a curable resin with high viscosity in each of the first display unit group DCG1 and the second display unit group DCG2, the mother substrate MS is cut along a cutting line CUL using a laser beam, and thus each display unit DC (or display device DD) can be finally formed.

[0079] Figure 5 is a schematic plan view showing a display device DD according to the embodiment.

[0080] Figure 5 The display device DD may be formed from a mother substrate (refer to Figure 2 "MS") separately separates a display unit (refer to Figure 2 of "DC").

[0081] exist Figure 5 , for convenience, the structure of the display device DD (eg, the display panel DP provided in the display device DD) is briefly illustrated based on the display area DA in which an image is displayed.

[0082] Reference Figures 1 to 5 The display device DD (or display panel DP) according to the embodiment may include a substrate SUB, pixels PXL disposed on the substrate SUB, a driving part driving the pixels PXL, and a line assembly electrically connecting the pixels PXL and the driving part.

[0083] The substrate SUB may include a semiconductor substrate. For example, the substrate SUB may include a silicon bulk wafer or an epitaxial wafer. The epitaxial wafer may include a crystalline material layer, i.e., an epitaxial layer, grown on a bulk substrate by an epitaxial process. The substrate SUB is not limited to a silicon bulk wafer or an epitaxial wafer, and may be formed using various wafers such as a polished wafer, an annealed wafer, and a silicon-on-insulator (SOI) wafer. However, the disclosure is not limited thereto, and according to an embodiment, the substrate SUB may include a transparent insulating material capable of transmitting light. The substrate SUB may be a region of a mother substrate MS.

[0084] One area of ​​the substrate SUB may be provided as a display area DA in which the display part DPP including the pixel PXL is provided, and the remaining area of ​​the substrate SUB may be provided as a non-display area NDA. For example, the substrate SUB may include a display area DA in which the pixel area PXA is defined, and a non-display area NDA provided around (or adjacent to) the display area DA, in which each pixel PXL is provided.

[0085] The non-display area NDA may be disposed on at least one side of the display area DA. The non-display area NDA may surround the circumference (or edge) of the display area DA. The line assembly and the driving part may be disposed in the non-display area NDA. For example, the non-display area NDA may be an area in which a fan-out line, a pad PD, and / or an embedded circuit part electrically connected to the pixel PXL are disposed to drive the pixel PXL.

[0086] The non-display area NDA may include a pad area PDA. The pad area PDA may be an area of ​​the non-display area NDA in which the pad part PDP is located, and may be located closest to an edge (or boundary) of the non-display area NDA. According to an embodiment, the non-display area NDA may include an anti-static circuit area in which an anti-static circuit electrically connected to a signal line located in the display area DA to prevent static electricity from being generated is located.

[0087] The pad PDP may include a plurality of pads PD. The pad PD may supply driving power and signals for driving the pixels PXL and / or the embedded circuit part disposed in the display area DA. The pad PD may be electrically connected to an external circuit board through a conductive adhesive member or the like.

[0088] Each of the pixels PXL may be disposed in the pixel area PXA. The pixels PXL may be arranged in the display area DA in a stripe arrangement structure, etc., but is not limited thereto.

[0089] In an embodiment, the dam DAM may be positioned in the non-display area NDA of the substrate SUB. The dam DAM may define a supply position of a filling layer FIL formed in one area of ​​each display unit DC provided in the mother substrate MS. In addition, the dam DAM may be a reinforcing member that improves the mechanical strength of the mother substrate MS (or the display unit DC) in a process of individually separating the mother substrate MS in units of the display unit DC by stably fixing the filling layer FIL. The dam DAM may include a light blocking material to prevent visibility of a structure (e.g., a fan-out line) positioned thereunder, and may be constructed of a curable resin having a certain level of viscosity or higher, but is not limited thereto.

[0090] The dam DAM may be positioned at least one side of the display device DD. The dam DAM may be positioned between the display part DPP and the pad part PDP in one area of ​​the non-display area NDA. The dam DAM may be applied to a target area so as not to overlap each of the display part DPP and the pad part PDP, and then cured.

[0091] Figure 6 is a schematic cross-sectional view of a display panel DP according to an embodiment. Figure 7 is a schematic exploded perspective view showing a display panel DP according to an embodiment.

[0092] Reference Figures 5 to 7 , the display panel DP may include a plurality of pixels PXL.

[0093] Each of the pixels PXL may include a plurality of sub-pixels SPX1, SPX2, and SPX3. For example, each pixel PXL may include a first sub-pixel SPX1, a second sub-pixel SPX2, and a third sub-pixel SPX3 arranged adjacent to each other, but is not limited thereto. According to an embodiment, each pixel PXL may include four sub-pixels or two sub-pixels.

[0094] The display panel DP may include a display part DPP and a filling layer FIL covering the display part DPP. The display part DPP may include a substrate SUB, and a pixel circuit layer PCL, a via layer VIA, a display element layer DPL, and an optical layer OPL sequentially disposed on the substrate SUB.

[0095] The substrate SUB may include a semiconductor substrate. For example, the substrate SUB may include a silicon bulk wafer or an epitaxial wafer.

[0096] The pixel circuit layer PCL may be disposed on the substrate SUB and may include a circuit element and at least one insulating layer positioned between the circuit elements. The circuit element may include a plurality of transistors and signal lines connected to the transistors. As an example, the transistor may be a MOSFET, but is not limited thereto. The circuit element may include, for example, a gate electrode, a source region / drain region, and a channel region.

[0097] The via layer VIA may be selectively disposed on the pixel circuit layer PCL. The via layer VIA may be disposed on the pixel circuit layer PCL to cover the pixel circuit layer PCL. The via layer VIA may be selectively disposed according to the material of the substrate SUB. For example, when the substrate SUB is a silicon wafer substrate, the via layer VIA may have a resonant structure to further improve the extraction efficiency of light emitted from the light emitting element layer LDL. In this case, the via layer VIA may be partially opened to include a through hole, and the circuit elements of the pixel circuit layer PCL and the first electrode EL1 of the light emitting element layer LDL may be electrically connected.

[0098] The display element layer DPL may be disposed on the via layer VIA. The display element layer DPL may include a light emitting element layer LDL, a thin film encapsulation layer TFE, and a color filter layer CFL.

[0099] The light emitting element layer LDL may include a light emitting element LD and a pixel defining layer PDL. The light emitting element LD may be disposed in each of the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3. The light emitting element LD may include a first electrode EL1, a light emitting layer EML, and a second electrode EL2. The first electrode EL1 may be an anode of the light emitting element LD, and the second electrode EL2 may be a cathode of the light emitting element LD.

[0100] Holes injected from the first electrode EL1 of each of the first subpixel SPX1, the second subpixel SPX2, and the third subpixel SPX3 and electrons injected from the second electrode EL2 of each of the first subpixel SPX1, the second subpixel SPX2, and the third subpixel SPX3 can be transferred to the light-emitting layer EML to form excitons, and when the excitons are transformed from an excited state to a ground state, light can be generated and the light can be emitted in the form of visible light.

[0101] The first electrode EL1 may be disposed on the via layer VIA. The first electrode EL1 may include a transparent conductive material capable of transmitting light and / or an opaque conductive material having a reflectivity capable of reflecting light.

[0102] The pixel defining layer PDL may be positioned on the first electrode EL1. The pixel defining layer PDL may include an opening OP exposing one region of the first electrode EL1.

[0103] The light emitting layer EML may be positioned on the first electrode EL1 exposed through the opening OP of the pixel defining layer PDL. In addition, the light emitting layer EML may be positioned on the side surface and the upper surface of the pixel defining layer PDL. The light emitting layer EML may be a common layer commonly provided to the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3, but is not limited thereto. The light emitting layer EML may include a light generating layer that emits light, an electron transport layer, a hole transport layer, and the like.

[0104] The second electrode EL2 may be positioned on the light emitting layer EML to cover the light emitting layer EML. The second electrode EL2 may be a common layer commonly provided to the first subpixel SPX1, the second subpixel SPX2, and the third subpixel SPX3.

[0105] A thin film encapsulation layer TFE may be positioned on the second electrode EL2. The thin film encapsulation layer TFE may cover the second electrode EL2 to prevent oxygen and / or moisture from penetrating into the light emitting element LD.

[0106] The color filter layer CFL may be positioned on the thin film encapsulation layer TFE. The color filter layer CFL may selectively transmit light emitted from the light emitting element LD in the image display direction (or the front surface direction) of the display device DD. The color filter layer CFL may be selectively set according to the type of the light emitting layer EML. For example, in the case where the light emitting layer EML is commonly set to the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 to emit white light, the color filter layer CFL may be set on the thin film encapsulation layer TFE to selectively transmit light of a specific wavelength range of the white light. According to an embodiment, in the case where the light emitting layer EML is individually set to the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 to emit light of different colors, the color filter layer CFL may be omitted.

[0107] The optical layer OPL may be disposed on the color filter layer CFL. The optical layer OPL may include a microlens array that improves light extraction effect by changing the advancing angle of light emitted from the light emitting element layer LDL through microlenses formed in a specific shape (such as a hemispherical shape) on the surface of the display element layer DPL, but is not limited thereto.

[0108] The filling layer FIL may be disposed on the optical layer OPL. The filling layer FIL may be disposed on the display part DPP to provide a display surface of the display device DD (or display panel DP). The filling layer FIL may be a configuration of the uppermost layer disposed in the display area DA, and may protect the display part DPP from external impact, etc. The filling layer FIL may be configured by including a transparent curable resin having a certain level of viscosity or higher.

[0109] Figure 8 It shows that the Figure 5 Schematic circuit diagram of the electrical connection relationship of components in each of the pixels PXL shown in FIG.

[0110] exist Figure 8 , for convenience, a pixel PXL located in a j-th pixel column of an i-th pixel row (or an i-th horizontal line) is shown, where i and j are positive integers.

[0111] Reference Figures 5 to 8 , each of the pixel PXL (or the first subpixel SPX1 , the second subpixel SPX2 , and the third subpixel SPX3 ) may include an emission component EMU generating light of brightness corresponding to a data signal and a pixel circuit PXC for driving the emission component EMU.

[0112] The emission component EMU may include a light emitting element LD connected between a first power line PL1 receiving a voltage of a first driving power VDD and a second power line PL2 receiving a voltage of a second driving power VSS. For example, the emission component EMU may include a first electrode EL1 connected to the first driving power VDD via a pixel circuit PXC and a first power line PL1 and a second electrode EL2 connected to the second driving power VSS via a second power line PL2. The first electrode EL1 may be an anode, and the second electrode EL2 may be a cathode. During the light emission period of the pixel PXL, the potential difference between the first driving power VDD and the second driving power VSS may be set to be higher than or equal to the threshold voltage of the light emitting element LD.

[0113] In the case where the pixel PXL (or one of the first subpixel SPX1, the second subpixel SPX2, and the third subpixel SPX3) is positioned at the i-th pixel row and the j-th pixel column in the display area DA, the pixel circuit PXC of the pixel PXL (or one of the first subpixel SPX1, the second subpixel SPX2, and the third subpixel SPX3) may be electrically connected to the i-th scan line Si and the j-th data line Dj. For example, the pixel circuit PXC may be electrically connected to the i-th control line CLi and the j-th sensing line SENj.

[0114] The pixel circuit PXC may include first to third transistors T1 , T2 , and T3 and a storage capacitor Cst.

[0115] The first transistor T1 may be a driving transistor for controlling a driving current applied to the light emitting element LD and may be electrically connected between the first driving power VDD and the light emitting element LD. The first transistor T1 may control the amount of driving current applied from the first driving power VDD to the light emitting element LD through the second node N2 according to a voltage applied to the first node N1.

[0116] The second transistor T2 may be a switching transistor that selects and activates the pixel PXL in response to a scan signal, and may be electrically connected between the j-th data line Dj and the first node N1. The second transistor T2 may be turned on when a scan signal of a gate-on voltage (e.g., a high level voltage) is supplied from the i-th scan line Si to electrically connect the j-th data line Dj and the first node N1.

[0117] The third transistor T3 may obtain a sensing signal through the j-th sensing line SENj by electrically connecting the first transistor T1 to the j-th sensing line SENj, and may detect characteristics of the pixel PXL including a threshold voltage of the first transistor T1, etc. using the sensing signal. The third transistor T3 may be an initialization transistor capable of initializing the second node N2, and may be turned on when a sensing control signal is supplied from the i-th control line CLi to supply a voltage of initialization power to the second node N2. Therefore, the storage capacitor Cst electrically connected to the second node N2 may be initialized.

[0118] The storage capacitor Cst may include a first storage electrode electrically connected to the first node N1 and a second storage electrode electrically connected to the second node N2. During one frame period, the storage capacitor Cst is charged with a data voltage corresponding to a data signal supplied to the first node N1. Therefore, the storage capacitor Cst may store a voltage corresponding to a difference between a voltage of the gate electrode of the first transistor T1 and a voltage of the second node N2.

[0119] exist Figure 8 , an embodiment in which all of the first to third transistors T1, T2, and T3 are N-type transistors is disclosed, but it is not limited thereto. For example, the structure of the pixel circuit PXC may be changed differently. For example, the pixel circuit PXC may also include at least one transistor element (such as a transistor element for initializing the first node N1 and / or a transistor element for controlling the light emitting time of the light emitting element LD) or other circuit elements (such as a boost capacitor for boosting the voltage of the first node N1). For example, the pixel circuit PXC may be constructed by including six transistor elements and two capacitors. According to an embodiment, the pixel circuit PXC may include seven transistor elements and two capacitors.

[0120] 9A to 9D It is along Figure 5 A schematic cross-sectional view taken along line III-III'. Fig.9E It shows Fig.9A Schematic diagram of the light-emitting layer EML.

[0121] FIG. 9B to FIG. 9D The embodiment shows Fig.9A Modified embodiments regarding the light emitting layer EML, the color filter layer CFL, the lens portion PS, etc.

[0122] Reference Figures 5 to 9E , the pixel PXL according to the embodiment may include a first sub-pixel SPX1 , a second sub-pixel SPX2 , and a third sub-pixel SPX3 .

[0123] Each of the first sub-pixel SPX1 , the second sub-pixel SPX2 , and the third sub-pixel SPX3 may include a substrate SUB, a pixel circuit layer PCL, a via layer VIA, a display element layer DPL, an optical layer OPL, and a filling layer FIL.

[0124] The substrate SUB may include a silicon wafer substrate formed using a semiconductor process. The substrate SUB may include a semiconductor material, for example, a Group IV semiconductor, a Group III-V compound semiconductor, or a Group II-VI compound semiconductor. For example, a Group IV semiconductor may include silicon, germanium, or silicon-germanium.

[0125] The pixel circuit layer PCL may be disposed on the substrate SUB. The pixel circuit layer PCL may include a circuit element CIE, a circuit insulating layer PC_INS, a contact plug CTP, and a circuit line SL.

[0126] The circuit element CIE may include a transistor (eg, a driving transistor). The circuit element CIE may include a gate insulating layer GI, a gate electrode GE, and a gate spacer GS. The first region FA and the second region SA may be disposed in the substrate SUB at both sides of the gate electrode GE. One of the first region FA and the second region SA may be a source region, and the other may be a drain region.

[0127] The gate insulating layer GI may be disposed on the substrate SUB. The gate insulating layer GI may include oxide, nitride, or a high dielectric constant (high-k) material. The high dielectric constant material may refer to a material having a dielectric constant greater than silicon oxide (SiO x ) is a dielectric material with a high dielectric constant.

[0128] The gate electrode GE may be disposed on the gate insulating layer GI. The gate electrode GE may include a conductive material. The conductive material may include, for example, a metal nitride (such as titanium nitride (TiN), tantalum nitride (TaN), or tungsten nitride (WN)), a metal material (such as aluminum (Al), tungsten (W), copper (Cu), or molybdenum (Mo)), and / or a semiconductor material (such as doped polysilicon). The gate electrode GE may be formed as a single layer or a double layer or more layers.

[0129] The gate spacer GS may be disposed on both side surfaces of the gate electrode GE and may insulate the first region FA and the second region SA from the gate electrode GE. According to an embodiment, the gate spacer GS may be formed as a multilayer structure. The gate spacer GS may be formed of oxide, nitride, and oxynitride, and may be formed of, for example, a low dielectric constant layer.

[0130] The first area FA and the second area SA may be disposed in the substrate SUB at both sides of the gate electrode GE. The first area FA and the second area SA may be semiconductor layers including silicon, and may include impurities of different types and / or concentrations.

[0131] The channel area CHA may be disposed in the substrate SUB under the gate electrode GE. The channel area CHA may be connected to the first area FA and the second area SA. The channel area CHA may be formed of a semiconductor material and may include, for example, at least one of silicon, silicon germanium, and germanium.

[0132] The contact plug CTP may recess the first area FA and the second area SA and contact the first area FA and the second area SA, and may be disposed along the upper surfaces of the first area FA and the second area SA to contact the upper surfaces of the first area FA and the second area SA, but is not limited thereto. The contact plug CTP may include, for example, a metal nitride (such as titanium nitride, tantalum nitride, or tungsten nitride) and / or a metal material (such as aluminum, tungsten, copper, or molybdenum), but is not limited thereto.

[0133] The circuit insulation layer PC_INS may be disposed on the circuit element CIE on the substrate SUB. The contact plug CTP may be electrically connected to the first area FA and the second area SA by passing through the circuit insulation layer PC_INS. The first area FA and the second area SA and the contact plug CTP may be electrically connected. The circuit line SL may be electrically connected to the contact plug CTP and may be disposed in a plurality of layers.

[0134] The pixel circuit layer PCL may further include scan lines and data lines disposed to cross the scan lines.

[0135] The transistor constructed by the circuit element CIE may be electrically connected to the first electrode of the corresponding sub-pixel. For example, the transistor constructed by the circuit element CIE in the first sub-pixel SPX1 may be electrically connected to the 1-1 electrode EL1_1, the transistor constructed by the circuit element CIE in the second sub-pixel SPX2 may be electrically connected to the 1-2 electrode EL1_2, and the transistor constructed by the circuit element CIE in the third sub-pixel SPX3 may be electrically connected to the 1-3 electrode EL1_3.

[0136] On the pixel circuit layer PCL, the first conductive pattern CP1, the second conductive pattern CP2, and the third conductive pattern CP3 may be disposed apart from each other. The first conductive pattern CP1, the second conductive pattern CP2, and the third conductive pattern CP3 may be simultaneously or continuously formed in the same process, but are not limited thereto.

[0137] The first conductive pattern CP1 may be disposed on the circuit insulation layer PC_INS in the first sub-pixel SPX1 and may be electrically connected to the transistor. For example, the first conductive pattern CP1 may be electrically connected to the circuit element CIE configuring the transistor through the corresponding circuit line SL.

[0138] The second conductive pattern CP2 may be disposed on the circuit insulation layer PC_INS in the second sub-pixel SPX2 and may be electrically connected to the transistor. For example, the second conductive pattern CP2 may be electrically connected to the circuit element CIE configuring the transistor through the corresponding circuit line SL.

[0139] The third conductive pattern CP3 may be disposed on the circuit insulation layer PC_INS in the third sub-pixel SPX3 and may be electrically connected to the transistor. For example, the third conductive pattern CP3 may be electrically connected to the circuit element CIE configuring the transistor through the corresponding circuit line SL.

[0140] The first conductive pattern CP1, the second conductive pattern CP2, and the third conductive pattern CP3 may be used as a reflective member that reflects light emitted from the light emitting layer EML and traveling in an upper direction (e.g., in a third direction DR3) to the pixel circuit layer PCL. The first conductive pattern CP1, the second conductive pattern CP2, and the third conductive pattern CP3 may include a metal material having a high reflectivity. For example, the first conductive pattern CP1, the second conductive pattern CP2, and the third conductive pattern CP3 may include a material such as aluminum or silver, but are not limited thereto.

[0141] The via layer VIA may be disposed on the first conductive pattern CP1, the second conductive pattern CP2, and the third conductive pattern CP3. The via layer VIA may cover the first conductive pattern CP1, the second conductive pattern CP2, and the third conductive pattern CP3, and may cover the circuit insulation layer PC_INS between adjacent conductive patterns. According to an embodiment, the via layer VIA may be used as a planarization layer for alleviating a step difference caused by a structure disposed thereunder, but is not limited thereto.

[0142] According to an embodiment, the via layer VIA may have a microcavity structure in which light emitted from the light emitting layer EML is reflected and re-reflected between metal patterns arranged to be vertically separated from each other. The via layer VIA may include a material having a high transmittance. For example, the via layer VIA may be an inorganic insulating layer including an inorganic material or an organic insulating layer including an organic material. The via layer VIA may be partially opened to include a through hole VIH exposing an area of ​​each of the first conductive pattern CP1, the second conductive pattern CP2, and the third conductive pattern CP3.

[0143] The via plug VP may be disposed in the through hole VIH. The via plug VP may include a first via plug VP1, a second via plug VP2, and a third via plug VP3. Each of the first via plug VP1, the second via plug VP2, and the third via plug VP3 may include a conductive material such as tungsten or copper used in a semiconductor process, but is not limited thereto.

[0144] The first via plug VP1 may be electrically connected to the first conductive pattern CP1 by passing through the via layer VIA in the first sub-pixel SPX1. For example, the first via plug VP1 may be electrically connected to the 1-1 electrode EL1_1 of the light emitting element layer LDL.

[0145] The second via plug VP2 may be electrically connected to the second conductive pattern CP2 by passing through the via layer VIA in the second sub-pixel SPX2. For example, the second via plug VP2 may be electrically connected to the 1-2 electrode EL1_2 of the light emitting element layer LDL.

[0146] The third via plug VP3 may be electrically connected to the third conductive pattern CP3 by passing through the via layer VIA in the third sub-pixel SPX3. For example, the third via plug VP3 may be electrically connected to the 1st to 3rd electrodes EL1-3 of the light emitting element layer LDL.

[0147] According to an embodiment, the via layer VIA may be omitted. In this case, the light emitting element layer LDL may be directly disposed on the pixel circuit layer PCL.

[0148] The display element layer DPL may be disposed on the via layer VIA. The display element layer DPL may include a light emitting element layer LDL, a thin film encapsulation layer TFE, and a color filter layer CFL. Fig.9D As shown in , the display element layer DPL may include only the light emitting element layer LDL and the thin film encapsulation layer TFE without including the color filter layer CFL.

[0149] The light emitting element layer LDL may include a light emitting element LD and a pixel defining layer PDL. The light emitting element LD may include a first light emitting element LD1 positioned in the first sub-pixel SPX1, a second light emitting element LD2 positioned in the second sub-pixel SPX2, and a third light emitting element LD3 positioned in the third sub-pixel SPX3. The first light emitting element LD1 may include a 1-1st electrode EL1_1, a light emitting layer EML, and a second electrode EL2. The second light emitting element LD2 may include a 1-2nd electrode EL1_2, a light emitting layer EML, and a second electrode EL2. The third light emitting element LD3 may include a 1-3rd electrode EL1-3, a light emitting layer EML, and a second electrode EL2.

[0150] Each of the 1-1st electrode EL1_1, the 1-2nd electrode EL1_2, and the 1-3rd electrode EL1_3 may be disposed and / or formed on the via layer VIA of the corresponding sub-pixel. The 1-1st electrode EL1_1, the 1-2nd electrode EL1_2, and the 1-3rd electrode EL1_3 may be disposed separately from each other on the via layer VIA. The 1-1st electrode EL1_1 may be an anode of the first light emitting element LD1, the 1-2nd electrode EL1_2 may be an anode of the second light emitting element LD2, and the 1-3rd electrode EL1_3 may be an anode of the third light emitting element LD3.

[0151] The 1-1st electrode EL1_1, the 1-2nd electrode EL1_2, and the 1-3rd electrode EL1_3 may include a transparent conductive material capable of transmitting light. For example, the transparent conductive material may include a conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO x ), indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO), conductive polymers such as poly (3,4-ethylenedioxythiophene) (PEDOT), etc., but are not limited thereto. According to an embodiment, the 1-1st electrode EL1_1, the 1-2nd electrode EL1_2, and the 1-3rd electrode EL1_3 may include an opaque conductive material capable of reflecting light in an upper direction.

[0152] The pixel defining layer PDL may be disposed on the 1-1th electrode EL1_1 , the 1-2th electrode EL1_2 , the 1-3th electrode EL1_3 , and the via layer VIA.

[0153] The pixel defining layer PDL can be positioned in the non-emission area NEA and can be partially opened to include an opening OP exposing a 1-1 electrode EL1_1 in at least one area of ​​the first emission area EMA1, another opening OP exposing a 1-2 electrode EL1_2 in at least one area of ​​the second emission area EMA2, and yet another opening OP exposing a 1-3 electrode EL1_3 in at least one area of ​​the third emission area EMA3.

[0154] The pixel defining layer PDL may be formed of an organic insulating layer including an organic material. According to an embodiment, the pixel defining layer PDL may include a light absorbing material, or may be coated with a light absorbing material to absorb light introduced from the outside. For example, the pixel defining layer PDL may include a carbon-based black pigment, but is not limited thereto.

[0155] The pixel defining layer PDL may protrude from a surface (or an upper surface) of the via layer VIA in the third direction DR3 .

[0156] According to an embodiment, Fig. 9B As shown in , the groove T may be provided in the pixel defining layer PDL. The groove T may be formed to pass through the pixel defining layer PDL and to dig into a portion of the via layer VIA, but is not limited thereto. The groove T may expose a region of the via layer VIA between the 1-1 electrode EL1_1 and the 1-2 electrode EL1_2 and a region of the via layer VIA between the 1-2 electrode EL1_2 and the 1-3 electrode EL1_3.

[0157] The light emitting layer EML may be disposed on the 1-1 electrode EL1_1 exposed by the opening OP of the pixel defining layer PDL, the 1-2 electrode EL1_2 exposed by another opening OP of the pixel defining layer PDL, and the 1-3 electrode EL1_3 exposed by yet another opening OP of the pixel defining layer PDL.

[0158] The light emitting layer EML may be disposed on the 1-1 electrode EL1_1, the 1-2 electrode EL1_2, and the 1-3 electrode EL1_3 exposed by the opening OP of the pixel defining layer PDL. For example, the light emitting layer EML may be disposed on the side surface and the upper surface of the pixel defining layer PDL. The light emitting layer EML may be a common layer commonly disposed to the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3.

[0159] The light-emitting layer EML may have a multilayer thin film structure including a light-generating layer that generates light. For example, the light-emitting layer EML may include a hole injection layer that injects holes, a hole transport layer that has excellent hole transport properties and suppresses the movement of electrons that are not recombined in the light-generating layer to increase the chance of recombination of holes and electrons, a light-generating layer that emits light by recombination of injected electrons and holes, a hole blocking layer for suppressing the movement of holes that are not recombined in the light-generating layer, an electron transport layer for smoothly transporting electrons to the light-generating layer, an electron injection layer for injecting electrons, and the like, but is not limited thereto.

[0160] In an embodiment, the light emitting layer EML may emit white light. Fig.9EAs shown in, the light-emitting layer EML may have a three-stacked series light-emitting structure. For example, the light-emitting layer EML may include a first light-emitting structure EU1, a second light-emitting structure EU2, and a third light-emitting structure EU3. Each light-emitting layer EML of the three-stacked series light-emitting structure may include a light-generating layer that generates light according to an applied current. For example, the first light-emitting structure EU1 may include a first light-generating layer LGL1, a first electron transport region ETR1, and a first hole transport region HTR1. The first light-generating layer LGL1 may be disposed between the first electron transport region ETR1 and the first hole transport region HTR1. The second light-emitting structure EU2 may include a second light-generating layer LGL2, a second electron transport region ETR2, and a second hole transport region HTR2. The second light-generating layer LGL2 may be disposed between the second electron transport region ETR2 and the second hole transport region HTR2. The third light-emitting structure EU3 may include a third light-generating layer LGL3, a third electron transport region ETR3, and a third hole transport region HTR3. The third light-generating layer LGL3 may be disposed between the third electron transport region ETR3 and the third hole transport region HTR3.

[0161] Each of the first hole transport region HTR1, the second hole transport region HTR2, and the third hole transport region HTR3 may include at least one of a hole injection layer and a hole transport layer, and may further include a hole buffer layer, an electron blocking layer, etc. as required by the occasion (situation). The first hole transport region HTR1, the second hole transport region HTR2, and the third hole transport region HTR3 may have the same or different configurations as each other.

[0162] Each of the first electron transport region ETR1, the second electron transport region ETR2, and the third electron transport region ETR3 may include at least one of an electron injection layer and an electron transport layer, and may further include an electron buffer layer, a hole blocking layer, etc. as required by the occasion. The first electron transport region ETR1, the second electron transport region ETR2, and the third electron transport region ETR3 may have the same or different configurations as each other.

[0163] The first connection layer CGL1 may be disposed between the first light emitting structure EU1 and the second light emitting structure EU2. The second connection layer CGL2 may be disposed between the second light emitting structure EU2 and the third light emitting structure EU3.

[0164] The first light generating layer LGL1, the second light generating layer LGL2, and the third light generating layer LGL3 may generate light of different colors. Light emitted from each of the first light generating layer LGL1, the second light generating layer LGL2, and the third light generating layer LGL3 may be mixed to generate white light. For example, the first light generating layer LGL1 may generate blue light, the second light generating layer LGL2 may generate green light, and the third light generating layer LGL3 may generate red light, but the disclosure is not limited thereto. According to an embodiment, the first light generating layer LGL1 and the third light generating layer LGL3 may generate blue light, and the second light generating layer LGL2 may generate yellow light. The second light generating layer LGL2 may further include a sub-light generating layer to improve purity.

[0165] In the above-mentioned embodiment, the light emitting layer EML is a 3-stack tandem light emitting structure, but is not limited thereto. According to the embodiment, the light emitting layer EML may have a single light emitting structure or a 2-stack tandem light emitting structure.

[0166] As in Fig. 9B In the embodiment shown in , in the case where the pixel defining layer PDL includes a groove T, the light emitting layer EML commonly provided to the first to third sub-pixels SPX1, SPX2, and SPX3 may be formed on each of the 1-1st electrode EL1_1, the 1-2nd electrode EL1_2, and the 1-3rd electrode EL1_3, and may be formed inside the groove T. Since the light emitting layer EML is formed inside the groove T, the light emitting layer EML formed on each of the 1-1st electrode EL1_1, the 1-2nd electrode EL1_2, and the 1-3rd electrode EL1_3 and the light emitting layer EML formed inside the groove T may be disconnected and not connected. Specifically, the first connection layer CGL1 and the second connection layer CGL2 (for example, see Fig.9E ) can be disconnected without being connected to the first connection layer CGL1 and the second connection layer CGL2 included in the light emitting layer EML of the adjacent sub-pixel. In this case, the transmission of leakage current through the light emitting layer EML to the pixel PXL can be reduced or minimized, and thus the reliability of each sub-pixel can be further improved.

[0167] The second electrode EL2 may be disposed on the light emitting layer EML. The second electrode EL2 may be a common layer commonly provided to the first subpixel SPX1, the second subpixel SPX2, and the third subpixel SPX3. The second electrode EL2 may be disposed in a plate shape throughout the entire area of ​​the display area DA.

[0168] The second electrode EL2 may be a thin metal layer having a thickness sufficient to transmit the light emitted from the light emitting layer EML of each of the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3. The second electrode EL2 may be formed of a metal material or a transparent conductive material to have a relatively thin thickness. For example, the second electrode EL2 may be formed of various transparent conductive materials. The second electrode EL2 may include at least one of various transparent conductive materials including indium tin oxide, indium zinc oxide, indium tin zinc oxide, aluminum zinc oxide, gallium zinc oxide, zinc tin oxide, and gallium tin oxide, and may be implemented as substantially transparent or translucent to meet a predetermined transmittance. Therefore, the light emitted from the light emitting layer EML positioned below the second electrode EL2 may pass through the second electrode EL2 and may be emitted in the upper direction of the thin film encapsulation layer TFE.

[0169] The thin film encapsulation layer TFE may be disposed and / or formed on the entire surface of the second electrode EL2.

[0170] The thin film encapsulation layer TFE may be in the shape of an encapsulation film formed of multiple layers. The thin film encapsulation layer TFE may include an inorganic layer and / or an organic layer. For example, the thin film encapsulation layer TFE may have a shape in which an inorganic layer, an organic layer, and an inorganic layer are sequentially stacked. The thin film encapsulation layer TFE may prevent external air and moisture from penetrating into the light emitting element layer LDL and the pixel circuit layer PCL.

[0171] The intermediate layer CTL may be disposed on the thin film encapsulation layer TFE.

[0172] The intermediate layer CTL may be positioned between the thin film encapsulation layer TFE and the color filter layer CFL, and may be a transparent viscous layer (or adhesive layer), for example, an optically transparent adhesive for enhancing adhesion between the thin film encapsulation layer TFE and the color filter layer CFL, but is not limited thereto. For example, the intermediate layer CTL may be formed of an insulating material having insulating and adhesive properties to protect the thin film encapsulation layer TFE. According to an embodiment, the intermediate layer CTL may be omitted.

[0173] The color filter layer CFL may be disposed on the intermediate layer CTL. The color filter layer CFL may include a color filter CF and a light blocking pattern BM.

[0174] The light blocking pattern BM may be positioned on one surface of the thin film encapsulation layer TFE to correspond to the pixel defining layer PDL. The light blocking pattern BM may include a light blocking material. For example, the light blocking pattern BM may be a black matrix. The light blocking pattern BM may be configured to include at least one light blocking material and / or a reflective material.

[0175] The color filter CF may include a first color filter CF1, a second color filter CF2, and a third color filter CF3. The first color filter CF1 may be disposed in the first sub-pixel SPX1, the second color filter CF2 may be disposed in the second sub-pixel SPX2, and the third color filter CF3 may be disposed in the third sub-pixel SPX3. Each of the first color filter CF1, the second color filter CF2, and the third color filter CF3 may include a colorant, such as a dye or pigment that absorbs light of a wavelength other than the corresponding color wavelength. The first color filter CF1 may be a red color filter, the second color filter CF2 may be a green color filter, and the third color filter CF3 may be a blue color filter. In the accompanying drawings, a case is shown in which adjacent color filters CF are disposed to be separated from each other and a light blocking pattern BM is placed between adjacent color filters CF, but adjacent color filters CF may be at least partially overlapped on the light blocking pattern BM.

[0176] According to an embodiment, the first, second, and third color filters CF1, CF2, and CF3 disposed to overlap each other in the non-emission area NEA of each subpixel may serve as a light blocking member to block light interference between adjacent subpixels instead of the light blocking pattern BM.

[0177] According to an embodiment, the light blocking pattern BM may be omitted. In this case, each of the first color filter CF1, the second color filter CF2, and the third color filter CF3 may be disposed on one surface of the thin film encapsulation layer TFE (or the intermediate layer CTL) to contact each other without being separated and overlapped with adjacent color filters. For example, one end (or the first end) of the second color filter CF2 may contact one end of the first color filter CF1 on one surface of the thin film encapsulation layer TFE, and the other end (or the second end) of the second color filter CF2 may contact one end of the third color filter CF3 on one surface of the thin film encapsulation layer TFE.

[0178] In the above-described embodiment, the light emitting layer EML is commonly provided to the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3, and different color filters CF are provided in the first to third sub-pixels SPX1, SPX2, and SPX3, but the disclosure is not limited thereto. Fig.9DAs shown in , the first light emitting element LD1 including the first light emitting layer EML1 can be positioned in the first sub-pixel SPX1, the second light emitting element LD2 including the second light emitting layer EML2 can be positioned in the second sub-pixel SPX2, and the third light emitting element LD3 including the third light emitting layer EML3 can be positioned in the third sub-pixel SPX3. Each of the first light emitting layer EML1, the second light emitting layer EML2, and the third light emitting layer EML3 can emit light of a different color. For example, the first light emitting layer EML1 can emit red light, the second light emitting layer EML2 can emit green light, and the third light emitting layer EML3 can emit blue light. Since red light is emitted from the first light emitting element LD1 including the first light emitting layer EML1, green light is emitted from the second light emitting element LD2 including the second light emitting layer EML2, and blue light is emitted from the third light emitting element LD3 including the third light emitting layer EML3, in Fig.9D In the embodiments, reference may be omitted Fig.9A A color filter layer CFL is described.

[0179] The optical layer OPL may be disposed on the display element layer DPL. The optical layer OPL may include a low refractive index layer that changes the path of light lost among the light emitted from the light emitting element layer LDL to the front surface direction (or the image display direction of the display device DD) by using a difference in refractive index to improve the brightness of the front surface light emission. For example, the optical layer OPL may include a microlens array that improves the light extraction effect by changing the advancing angle of light emitted from the light emitting element layer LDL by forming microlenses of a specific shape such as a hemispherical shape on the surface of the display element layer DPL.

[0180] In the case where the optical layer OPL includes a microlens array, the optical layer OPL may include a first lens LP1, a second lens LP2, and a third lens LP3. The first lens LP1 may be disposed on the first color filter CF1, the second lens LP2 may be disposed on the second color filter CF2, and the third lens LP3 may be disposed on the third color filter CF3. The distances between the first lens LP1, the second lens LP2, and the third lens LP3 may be set to be substantially equal to the distance between sub-pixels. Therefore, one lens may be set to correspond to one sub-pixel. In this case, the first lens to the third lens LP1, LP2, and LP3 may be formed so that all focal lengths are the same, but are not limited thereto. According to an embodiment, the distances between the first lens LP1, the second lens LP2, and the third lens LP3 may be set to be different from the distance between the sub-pixels so as to adjust the viewing angle toward the outside of the display device DD (or display panel DP). For example, each of the first lens LP1, the second lens LP2, and the third lens LP3 may be disposed on the corresponding color filter CF not only in the third direction DR3 (or vertical direction). For example, the first lens LP1 may not only be disposed on the first color filter CF1, but may be disposed throughout the first color filter CF1 and the adjacent color filter CF of the first color filter CF1, or may be disposed only on the adjacent color filter CF. The second lens LP2 may not only be disposed on the second color filter CF2, but may be disposed throughout the second color filter CF2 and the adjacent color filter CF of the second color filter CF2 (for example, the first color filter CF1 or the third color filter CF3), or may be disposed only on the adjacent color filter CF. The third lens LP3 may not only be disposed on the third color filter CF3, but may be disposed throughout the third color filter CF3 and the adjacent color filter CF of the third color filter CF3, or may be disposed only on the adjacent color filter CF. That is, each of the first lens LP1, the second lens LP2, and the third lens LP3 may not be directly disposed on the corresponding color filter CF in the vertical direction, and may be shifted and disposed relative to the corresponding color filter CF.

[0181] The filling layer FIL may be disposed on the optical layer OPL. The filling layer FIL may be disposed on the optical layer OPL in the display area DA to cover the lower member including the optical layer OPL. The filling layer FIL may prevent moisture or oxygen from entering the lower member.

[0182] When the display device DD is applied to a device for realizing virtual reality (VR), etc., refer to Fig. 9C , the lens portion PS may be disposed on the display device DD. The lens portion PS may include a flat lens using a reflective polarization method to reduce a distance between the display device DD and the lens portion PS, but is not limited thereto. According to an embodiment, the lens portion PS may include a polarization layer.

[0183] FIG. 10A to FIG. 10E is with Figure 1 EA portion corresponds to a schematic plan view, which sequentially shows a method of manufacturing a display device DD according to an embodiment. Fig.11A It is along Fig. 10A Schematic cross-sectional view taken along line IV-IV'. Fig. 11B It is along Fig. 10B Schematic cross-sectional view taken along line IV-IV'. Fig. 11C It is along Fig. 10C Schematic cross-sectional view taken along line IV-IV'. Fig.11D It is along Fig. 10D Schematic cross-sectional view taken along line IV-IV'. Fig.11E It is along Fig. 10E Schematic cross-sectional view taken along line IV-IV'.

[0184] exist FIG. 10A to FIG. 11E In the embodiment, the manufacturing steps of the display device DD are described as being performed sequentially, but unless the disclosed concept or the like is changed, it is obvious that some steps shown as being performed continuously may be performed simultaneously, the order of each step may be changed, some steps may be omitted, or another step may be further included between the steps.

[0185] exist FIG. 10A to FIG. 11E In order to avoid repeated description, the points different from the above-mentioned embodiment are mainly described.

[0186] Reference Figure 1 , Fig. 10A and Fig.11A , a plurality of display cells DC are formed on the mother substrate MS.

[0187] The mother substrate MS may include a plurality of unit regions divided along the cutting line CUL. Each unit region may be a portion corresponding to the display unit DC (or the display device DD), and a substrate SUB of the display unit DC (or the display device DD) may be formed for each unit region. The unit regions may have the same size, but are not limited thereto.

[0188] A corresponding display unit DC is formed for each unit area. The display unit DC may include a pad part PDP and a display part DPP. The display part DPP may be provided in the display area DA of the unit area of ​​the mother substrate MS, and the pad part PDP may be provided in the non-display area NDA of the unit area. In the non-display area NDA, one area in which the pad part PDP is located may be the pad area PDA.

[0189] A first display cell group DCG1 and a second display cell group DCG2 alternately arranged in a second direction DR2 may be defined in the mother substrate MS. Each of the first display cell group DCG1 and the second display cell group DCG2 may include a plurality of first display cells DC1 and a plurality of second display cells DC2. The first display cells DC1 may be some display cells DC arranged in a first row R1, and the second display cells DC2 may be some other display cells DC arranged in a second row R2.

[0190] In the first display unit group DCG1 and the second display unit group DCG2, the display portion DPP of each first display unit DC1 may face the display portion DPP of the second display unit DC2 positioned in the same column in the second direction DR2. In each of the first display unit group DCG1 and the second display unit group DCG2, the first display unit DC1 and the second display unit DC2 positioned in the same column may be symmetrical with the first cutting line CUL1 disposed between the first display unit DC1 and the second display unit DC2.

[0191] The pad PDP of each of the second display cells DC2 of the first display cell group DCG1 may face the pad PDP of the first display cell DC1 of the second display cell group DCG2 positioned in the same column. The second display cells DC2 of the first display cell group DCG1 and the first display cells DC1 of the second display cell group DCG2 positioned in the same column may be symmetrical with the first cutting line CUL1 interposed between the first display cell group DCG1 and the second display cell group DCG2.

[0192] Reference Figure 1 , Fig. 10A , Fig. 10B , Fig.11A and Fig. 11B The first coating liquid is applied to surround at least one side periphery of the display part DPP to include all the display parts DPP in each of the first display cell group DCG1 and the second display cell group DCG2, and then the first coating liquid is cured to form the dam DAM.

[0193] The dam DAM may be formed by including a curable resin having a certain level of viscosity or higher, applying the curable resin to a predetermined application area, and then curing the curable resin. For example, the dam DAM may include a light blocking material and a photocurable resin including a photopolymerization initiator that is crosslinked and cured by light such as ultraviolet rays and infrared rays. For example, the dam DAM may surround the display portion DPP in each of the first display unit group DCG1 and the second display unit group DCG2. Since the dam DAM includes a curable resin having a viscosity of at least a certain level (e.g., about 160,000), the dam DAM may have a pencil hardness of 7H or more in the curing process.

[0194] Since the display parts DPP are arranged to face each other in each of the first display cell group DCG1 and the second display cell group DCG2, the dam DAM may surround at least one side of the display part DPP of each display cell DC and may be positioned between the pad part PDP and the display part DPP of the corresponding display cell DC.

[0195] Generally, in a mother substrate, a plurality of display units may be designed so that their configurations (e.g., pads and display units) have the same arrangement. For example, each of the display units may be formed on a mother substrate so that the display unit and the pads are sequentially arranged in the column direction, or the pads and the display units are sequentially arranged in the column direction. At this time, a dam is formed to surround all edges (e.g., upper side, lower side, left side, and right side) of the display unit of each of the display units. In this case, the application area of ​​the coating liquid corresponding to the base material of the dam is narrow, so there occurs a defect that the coating liquid invades the display unit. In the above-described embodiment, since the display unit DPP of the first display unit DC1 and the display unit DPP of the second display unit DC2 in the same column positioned in each display unit group DCG of the mother substrate MS are arranged to face each other. Therefore, the area in which the first coating liquid is applied can be ensured by applying the first coating liquid in the form of surrounding at least one side periphery of the display unit DPP of each of the first display unit DC1 and the second display unit DC2. Therefore, a display unit DC (or display device DD) with improved reliability can be realized by reducing or preventing defects caused by the invasion of the first coating liquid into the display unit DPP.

[0196] In addition, in the above-mentioned embodiment, since the dam DAM is formed by applying the first coating liquid in a form including all the display parts DPP in each display cell group DCG around the periphery of the display part DPP and then curing the first coating liquid, the number of coatings can be reduced, compared with the case where the dam is formed by applying the coating liquid in a form surrounding all edges (for example, the upper side, the lower side, the left side, and the right side) of the display part and then curing the coating liquid, thereby improving the manufacturing efficiency of the display device DD.

[0197] Reference Figure 1 , FIG. 10A to FIG. 10C and FIG. 11A to FIG. 11C , apply the second coating liquid to the space surrounded by the dam DAM (refer to Fig. 10B and Fig. 11B The second coating liquid may include a curable resin having a viscosity of a certain level or more (e.g., about 2,000) and may be cured in a curing process to form a filling layer FIL having a pencil hardness of 4H or more.

[0198] The filling layer FIL may be positioned as the uppermost layer in the third direction DR3 in each display unit DC, and may provide a display surface and / or an input surface to the user. The filling layer FIL may be a protective layer or a covering member that protects each display unit DC from external impacts, etc. In each display unit group DCG, a filling layer FIL having a certain level or higher of hardness (e.g., a pencil hardness of 4H or higher) formed inside a space SP surrounded by the dam DAM may protect each display unit DC of the mother substrate MS instead of the cover glass (or encapsulation glass) of the existing display device.

[0199] Reference Figure 1 , FIG. 10A to FIG. 10D and FIG. 11A to FIG. 11D , a laser cutting device 10 is set on the mother substrate MS.

[0200] Reference Figure 1 , FIG. 10A to FIG. 10E and FIG. 11A to FIG. 11E , the mother substrate MS is divided into units of each display cell DC by irradiating a laser beam from the laser cutting device 10 to correspond to the cutting line CUL.

[0201] After the cutting process using the laser beam, a process such as polishing or rounding the edges of the individually separated display units DC may be further performed. For example, after the cutting process using the laser beam, a process of chemically strengthening the substrate SUB of each display unit DC may be further performed. For example, a cleaning process of removing foreign matter on the surface of the substrate SUB may be further performed before the strengthening process.

[0202] The separate display unit DC may be used in various electronic devices such as TVs, smart phones, and wearable devices, etc. For example, the separate display unit DC may be used in a device for realizing virtual reality or augmented reality (AR), etc.

[0203] The mechanical strength of the mother substrate MS can be substantially improved by the dam DAM having a pencil hardness of 7H or more and the filling layer FIL having a pencil hardness of 4H or more. In this case, in the process of separating the mother substrate MS into each display unit DC unit, the filling layer FIL can replace the encapsulation glass (or cover glass) to provide the display surface and / or input surface of the corresponding display unit DC while protecting the display part DPP of each display unit DC.

[0204] In the above-described embodiment, each display unit DC can be protected by using a filling layer FIL and a dam DAM including a curable resin instead of an encapsulation glass. Therefore, in the process of separating the mother substrate MS into each display unit DC unit, the process of covering the encapsulation glass on the mother substrate MS can be omitted, and the process of individually cutting the encapsulation glass can be omitted. Therefore, in the above-described embodiment, the manufacturing efficiency of the display device DD can be improved.

[0205] In addition, in the above-described embodiment, when the encapsulation glass is omitted, defects caused by foreign matter (eg, broken pieces of the encapsulation glass, etc.) moving to the pad PDP during cutting of the encapsulation glass can be prevented, thereby preventing the pad PDP from being damaged.

[0206] Fig.12 is with Figure 2 A schematic cross-sectional view corresponding to line II' of FIG. 1 shows the mother substrate MS according to the embodiment.

[0207] exist Fig.12 In the embodiment of the present invention, the points different from the above-mentioned embodiment are mainly described to avoid repeated description.

[0208] Reference Figure 2 and Fig.12 The filling layer FIL is formed in the space surrounded by the dam DAM of the mother substrate MS. The filling layer FIL may include a curable resin having the same viscosity as that of the dam DAM. For example, the filling layer FIL and the dam DAM may include a curable resin having a viscosity of about 160,000 (eg, high viscosity).

[0209] In the case where the filling layer FIL includes a high viscosity curable resin having the same high viscosity as that of the dam DAM, the first coating liquid as the base material of the dam DAM can be applied to a predetermined application area (for example, between the display part DPP and the pad part PDP of each display unit DC), and the second coating liquid as the base material of the filling layer FIL can be applied to an area of ​​the mother substrate MS surrounded by the first coating liquid, and then when the second coating liquid is cured, the first coating liquid can be cured together. Therefore, the dam DAM and the filling layer FIL can be formed at the same time. Since the first coating liquid includes a high viscosity curable resin, since the first coating liquid is fixed to the target area after being applied to the target area without moving or flowing to another area, the first coating liquid and the second coating liquid can be cured together after the second coating liquid is applied.

[0210] However, the disclosure is not limited to the above embodiments, and after forming the dam DAM by applying the first coating liquid to the target area and performing a curing process using light, the filling layer FIL can be formed by applying and curing the second coating liquid in an area of ​​the mother substrate MS surrounded by the dam DAM.

[0211] Fig.13 is with Figure 2 A schematic cross-sectional view corresponding to line II' of FIG. 1 shows the mother substrate MS according to the embodiment. Fig.14A and Fig. 14B It shows the formation Fig.13 A schematic cross-sectional view of a manufacturing method of a DAM.

[0212] exist Figures 13 to 14B In the embodiment of the present invention, the points different from the above-mentioned embodiment are mainly described to avoid repeated description.

[0213] Reference Figure 2 and Figures 13 to 14B , a first coating liquid COL1 is applied between the pad part PDP and the display part DPP in each display unit DC of the mother substrate MS. The first coating liquid COL1 may be applied to a predetermined application area by the coating liquid supply part 100. The first coating liquid COL1 may include a curable resin having the same viscosity as that of the filling layer FIL. For example, the first coating liquid COL1 may include a curable resin having a viscosity of about 2,000 (e.g., low viscosity).

[0214] In this case, the dam DAM is formed by applying the first coating liquid COL1 to a predetermined application area and then immediately performing a photocuring process using UV so that the first coating liquid COL1 does not move or flow. After the dam DAM is formed, the filling layer FIL is formed by applying the second coating liquid in an area of ​​the mother substrate MS surrounded by the dam DAM and then curing the second coating liquid.

[0215] Although the disclosure has been described with reference to the above embodiments, it will be understood by those skilled in the art or those of ordinary skill in the art that the disclosure may be variously modified and changed without departing from the technical field of the disclosure described in the claims.

[0216] Therefore, the disclosed technical scope should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims

1. A display device, comprising: a substrate, a display area and a non-display area being defined in the substrate, the non-display area including a pad area; a display unit including the substrate and displaying an image; a pad portion disposed in the pad region and comprising a plurality of pads; a dam positioned between the pad portion and the display portion and surrounding at least one side of the display portion; as well as a filling layer provided on the display portion surrounded by the dam to cover the display portion, Wherein, the filling layer includes a transparent curable resin and is positioned in the uppermost layer in the display area.

2. The display device according to claim 1, wherein: The filling layer includes at least one of epoxy resin and silicone resin, and The dam includes a siloxane-based resin.

3. The display device according to claim 2, wherein: The dam has a width of about 0.5 mm to 5 mm.

4. The display device according to claim 3, wherein: The dam includes a curable resin having a viscosity higher than that of the filling layer.

5. The display device according to claim 3, wherein: The dam and the filling layer include a curable resin, the viscosity of the curable resin being the same.

6. The display device according to claim 1, wherein: The substrate includes a silicon wafer substrate.

7. The display device according to claim 2, wherein: The display unit further includes: A pixel circuit layer is disposed on the substrate; a light emitting element layer, comprising a light emitting element, the light emitting element being constructed by a first electrode disposed on the pixel circuit layer, a light emitting layer disposed on the first electrode, and a second electrode disposed on the light emitting layer; and The thin film encapsulation layer is arranged between the light emitting element layer and the filling layer.

8. The display device according to claim 7, wherein: The display portion further includes an optical layer disposed between the thin film encapsulation layer and the filling layer.

9. The display device according to claim 1, wherein: The dam has a pencil hardness of 7H or more, and the filling layer has a pencil hardness of 4H or more.

10. A method for manufacturing a display device, the method comprising the following steps: preparing a mother substrate including a first display unit group and a second display unit group including first display units and second display units, respectively, and a cutting line having a shape corresponding to each of the first display unit and the second display unit; forming a dam surrounding display portions of the first display unit and the second display unit; forming a filling layer on the display portion surrounded by the dam; as well as cutting the mother substrate by irradiating a laser beam to individually separate the first display unit and the second display unit, The first display unit group and the second display unit group are symmetrical with respect to the cutting line between the first display unit group and the second display unit group.

11. The method according to claim 10, wherein: Each of the first display unit and the second display unit includes the display portion and a pad portion positioned around the display portion, and The display unit includes: a pixel circuit layer disposed on the mother substrate; and a light-emitting element layer including a light-emitting element, wherein the light-emitting element is constructed by a first electrode disposed on the pixel circuit layer, a light-emitting layer disposed on the first electrode, and a second electrode disposed on the light-emitting layer.

12. The method according to claim 11, wherein: The display section of each of the first display units and the display section of each of the second display units in each of the first display unit group and the second display unit group face each other in a column direction of the mother substrate in a plan view.

13. The method according to claim 12, wherein: In each of the first display unit and the second display unit, the dam is positioned between the display portion and the pad portion.

14. The method according to claim 13, wherein: In each of the first display unit group and the second display unit group, the dam is applied and then cured to be formed along at least one outer periphery of the display portion of each of the first display unit and the second display unit.

15. The method according to claim 14, wherein: In each of the first display cell group and the second display cell group, the filling layer is applied and then cured to fill the inside of a region of the mother substrate surrounded by the dam.

16. The method according to claim 11, wherein: The pad portion of each of the second display units of the first display unit group and the pad portion of each of the first display units of the second display unit group face each other in a column direction of the mother substrate in a plan view.

17. The method according to claim 10, wherein: The filling layer includes at least one of epoxy resin and silicone resin, and The dam includes a siloxane-based resin.

18. The method according to claim 10, wherein: The dam includes a curable resin having a viscosity higher than that of the filling layer.

19. The method according to claim 10, wherein: The dam and the filling layer include a curable resin, the viscosity of the curable resin being the same.

20. The method according to claim 19, wherein: The dam is applied and then directly cured to be formed along at least one outer periphery of the display portion of each of the first display unit and the second display unit.

Images