Memory device and computing system including the same

Abstract

A memory device and a computing system including the same are provided. A memory device configured to connect to a plurality of hosts through an interconnect device and to communicate with the plurality of hosts through a compute fast link (CXL) protocol includes a command scheduler, a memory, and a priority scheduler. The command scheduler schedules commands included in requests from the plurality of hosts. The memory generates internal data by performing a memory operation corresponding to the scheduled command. The priority scheduler designates a first host from the plurality of hosts as a priority host based on attribute information of each of the plurality of hosts, and generates output data by rearranging the internal data such that data requested by the first host is preferentially output.

Description

Technical Field

[0001] Example embodiments relate generally to semiconductor integrated circuits, and more particularly to a memory device capable of enhancing performance and a computing system including the memory device. Background Art

[0002] The system performs data processing (for example, the computing system may include a central processing unit (CPU), a memory device, an input and output device, and a root complex that transmits information between devices constituting the system, etc.). As an example, a device capable of configuring the computing system may send and receive requests and responses based on various types of protocols such as Peripheral Component Interconnect Express (PCIe), Compute Express Link (CXL), etc.

[0003] The computing system may include a memory device, and the memory device may be shared by one or more hosts. In some scenarios, data may be transmitted to a specific host among the multiple hosts. Summary of the invention

[0004] Some example embodiments may provide a memory device capable of enhancing performance by performing data scheduling.

[0005] Some example embodiments may provide a computing system including a memory device capable of enhancing performance by performing data scheduling.

[0006] According to an example embodiment, a memory device configured to be connected to a plurality of hosts through an interconnect device and to communicate with the plurality of hosts through a computing fast link (CXL) protocol includes a command scheduler, a memory, and a priority scheduler. The command scheduler schedules commands included in requests from the plurality of hosts. The memory generates internal data by performing memory operations corresponding to the scheduled commands. The priority scheduler designates a first host from the plurality of hosts as a priority host based on attribute information of each of the plurality of hosts, and generates output data by rearranging the internal data so that data requested by the first host is output with priority.

[0007] According to an example embodiment, a computing system includes: an interconnect device; a plurality of memory devices connected to the interconnect device; and a plurality of hosts connected to the interconnect device. The plurality of hosts generate requests to access the plurality of memory devices. The plurality of memory devices communicate with the plurality of hosts through a compute fast link (CXL) protocol. Each of the plurality of memory devices includes a command scheduler, a memory, and a priority scheduler. The command scheduler schedules commands included in requests from the plurality of hosts. The memory generates internal data by performing memory operations corresponding to the scheduled commands. The priority scheduler designates a first host from the plurality of hosts as a priority host based on attribute information of each of the plurality of hosts, and generates output data by rearranging the internal data so that data requested by the first host is output with priority.

[0008] According to an example embodiment, a memory device configured to be connected to a plurality of hosts through an interconnect device and to communicate with the plurality of hosts through a computing fast link (CXL) protocol includes a command scheduler, a memory, and a priority scheduler. The command scheduler schedules commands included in requests from the plurality of hosts. The memory generates internal data by performing a memory operation corresponding to the scheduled commands. The priority scheduler designates a first host from the plurality of hosts as a priority host based on attribute information of each of the plurality of hosts, and generates output data by rearranging the internal data so that data requested by the first host is outputted preferentially. The priority scheduler includes a host information register, a priority mode selector, and an arbitrator. The host information register stores the attribute information of each of the plurality of hosts based on information in a received data packet. The priority mode selector generates a priority mode signal based on the attribute information stored in the host information register. The arbitrator generates the output data by rearranging the internal data in response to the priority mode signal.

[0009] In a memory device and a computing system according to example embodiments, a priority scheduler may rearrange internal data provided from a storage area based on attribute information of hosts connected to a CXL switch so that data requested by a host designated as a priority host is output with priority. Therefore, the memory device and the computing system may reduce a load on the CXL switch and prevent performance degradation of a host designated as a priority host. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Example embodiments of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0011] Figure 1 is a block diagram illustrating a computing system according to an example embodiment.

[0012] Figure 2 is a block diagram illustrating a computing system according to an example embodiment.

[0013] Figure 3 is a diagram illustrating an exemplary embodiment of the Figure 2 A block diagram of an example of a CXL device in a computing system.

[0014] Figure 4 FIG. 1 illustrates an exemplary embodiment of the present invention. Figure 3 Example of the host information register in a CXL device.

[0015] Figure 5 The diagram shows Figure 3 An example of internal data provided to the controller by the memory in the CXL device.

[0016] Figure 6 The diagram shows Figure 3 Example of output data output by the controller in .

[0017] Figure 7 is a diagram illustrating an exemplary embodiment of the Figure 2 A block diagram of another example of a CXL device in a computing system.

[0018] Figure 8 is a diagram illustrating an exemplary embodiment of the Figure 2 A block diagram of another example of a CXL device in a computing system.

[0019] Fig. 9 is a flow chart illustrating a method of operating a CXL apparatus according to an example embodiment.

[0020] Fig.10 is a block diagram illustrating a computing system according to an example embodiment.

[0021] Fig.11 is a diagram illustrating an exemplary embodiment of the Fig.10 A block diagram of an example DRAM in a computing system.

[0022] Fig.12 is a block diagram illustrating a computing system according to an example embodiment.

[0023] Fig.13 is a diagram illustrating an exemplary embodiment of the Fig.12 Block diagram of a chiplet among multiple chiplets in a computing system.

[0024] Fig.14 and Fig.15is a block diagram illustrating a computing system employing the CXL protocol according to an example embodiment.

[0025] Fig.16 and Fig.17 is a diagram illustrating an example embodiment of a host included in a computing system according to an example embodiment.

[0026] Fig.18 is an example of a computing system when a memory device according to example embodiments corresponds to a type 3 memory device defined by the CXL protocol.

[0027] Fig.19 is a block diagram illustrating a computing system according to an example embodiment.

[0028] Fig. 20 is a block diagram illustrating a data center including a computing system according to an example embodiment. DETAILED DESCRIPTION

[0029] Various example embodiments will be described more fully hereinafter with reference to the accompanying drawings, in which some example embodiments are shown. In the accompanying drawings, like reference numerals refer to like elements throughout. Repeated descriptions may be omitted.

[0030] Figure 1 is a block diagram illustrating a computing system according to an example embodiment.

[0031] refer to Figure 1 , the computing system 10 may be variously referred to as a data processing system, etc., and may include one or more devices. As an example, the computing system 10 may include one or more memory devices and hosts that generate requests for access to the memory devices (e.g., to read data or write data). Since the devices requesting data access operate as hosts for the memory devices, these devices may be referred to as hosts or master devices. On the other hand, in terms of providing services such as supply or storage of data to the host, the memory devices may be referred to as slave devices.

[0032] For example, the computing system 10 may include a plurality of hosts 11, 12, and 13 and a plurality of memory devices 15, 16, and 17. Figure 1 4. A computing system 10 including three hosts and three memory devices is illustrated in FIG. 4, but example embodiments are not limited thereto and various numbers of devices may be included in the computing system 10.

[0033] Each of the plurality of memory devices 15, 16, and 17 may include or be one of various types of memory, and as examples, each memory device may include or be a solid state drive (SSD), flash memory, and magnetic RAM (MRAM), ferroelectric RAM (FRAM), phase change RAM (PRAM), and resistive RAM (RRAM). However, example embodiments are not necessarily limited thereto, and each of the plurality of memory devices 15, 16, and 17 may include or be a dynamic random access memory (DRAM) such as DDR SDRAM (double data rate synchronous dynamic random access memory), LPDDR (low power double data rate) SDRAM, graphic double data rate (GDDR) SDRAM, and Rambus dynamic random access memory (RDRAM). In addition, each of the plurality of memory devices 15, 16, and 17 may include or be a memory module or chiplet. The memory devices 15, 16 and 17 may have the same type and / or number of memory chips as each other, or may have different types and / or numbers of memory chips as each other, and each memory device 15, 16 and 17 may be or include a semiconductor package including terminals for connecting to a controller.

[0034] The devices included in the computing system 10 can communicate with each other through an interconnect device (or link) 18 that supports one or more protocols. Each of these devices may include internal components that perform protocol-based communications supported by the interconnect device 18. As an example, the protocol may include a PCIe peripheral component interconnect express (PCIe) protocol, a compute express link (CXL) protocol, an XBus protocol, an NVLink protocol, an Infinity Fabric protocol, an accelerator cache coherent interconnect (CCIX) protocol, and a coherent accelerator processor interface (CAPI). At least one selected protocol may be applicable to the interconnect device 18. In the following, example embodiments will be described mainly based on communications based on the CXL protocol, but various other protocols may be applied in addition to the above-mentioned protocols without limitation thereto.

[0035] Although the interconnection device 18 between the plurality of hosts 11, 12, and 13 and the plurality of memory devices 15, 16, and 17 is briefly illustrated for ease of description and explanation, the computing system 10 may include a root complex connected to the plurality of devices through a root port so that the plurality of hosts 11, 12, and 13 and the plurality of memory devices 15, 16, and 17 may communicate through the root complex. For example, the root complex may manage transactions between the plurality of hosts 11, 12, and 13 and the plurality of memory devices 15, 16, and 17. In addition, in some example embodiments, mutual communication may be performed based on various other configurations and functions according to the CXL standard, and as an example, may be based on a configuration such as a flex bus and a switch disclosed in the CXL standard. In this case, the plurality of hosts 11, 12, and 13 and the plurality of memory devices 15, 16, and 17 may be CXL-compatible hosts and memory devices. Moreover, at least some of the plurality of memory devices 15, 16, and 17 may be connected to at least one of the plurality of hosts 11, 12, and 13 through a bridge (e.g., a PCI bridge) based on a predetermined protocol that controls a communication path.

[0036] According to an embodiment, each of the plurality of hosts 11, 12, and 13 may include or be one of various types of devices. For example, in one embodiment, each of the plurality of hosts 11, 12, and 13 is a main processor, and controls a central processing unit (CPU), a graphics processing unit (GPU), or a neural processing unit (NPU), a component providing a fixed function such as an intellectual property (IP) core, and a reconfigurable component such as a field programmable gate array (FPGA) and a peripheral device such as a network interface card (NIC).

[0037] According to an example embodiment, at least one of the plurality of memory devices 15, 16, and 17 may be shared by the plurality of hosts 11, 12, and 13. For example, at least one of the plurality of memory devices 15, 16, and 17 may be a pooled memory shared by the plurality of hosts 11, 12, and 13, and commands executed by the plurality of hosts 11, 12, and 13 may be stored in at least one of the plurality of memory devices 15, 16, and 17, data input for computing processing may be stored in the plurality of memory devices 15, 16, and 17, and / or processing results may be stored in the plurality of memory devices 15, 16, and 17.

[0038] Each of the plurality of hosts 11, 12, and 13 may include a request generator RQG and a memory allocator MMA, respectively. The memory allocator MMA allocates a storage area exclusively accessed by the host to prevent memory conflicts caused by different hosts and maintain the consistency of data stored in the memory. The request generator RQG may generate a request for requesting memory access such as a write operation and a read operation based on an address corresponding to a storage area exclusively allocated to each host.

[0039] Each of the plurality of memory devices 15 , 16 , and 17 may include a corresponding one of a plurality of priority schedulers PS 15 a , 16 a , and 17 a and a corresponding one of a plurality of memories MEM 15 b , 16 b , and 17 b .

[0040] A corresponding one of the memories 15b, 16b, and 17b may generate internal data by performing a memory operation corresponding to a command included in a request from a plurality of hosts 11, 12, and 13, and a corresponding one of the priority schedulers 15a, 16a, and 17a may designate at least one host (i.e., a first host) from the plurality of hosts 11, 12, and 13 as a priority mode (e.g., a priority access host or simply a priority host) based on attribute information of each of the plurality of hosts 11, 12, and 13, and may generate output data by rearranging the internal data so that data requested by a host in the priority mode (i.e., the first host) is outputted preferentially. The memory operation may include one or more operations performed in the memory based on one or more commands received from an external device (e.g., a memory controller). For example, the one or more memory operations may include a read operation, a write operation, a refresh operation, and a precharge operation. In addition, the memory operation may include one or more calculations performed in a memory device having a processing-in-memory (PIM) feature. However, one or more embodiments of the present disclosure are not limited thereto and may include other memory operations executable in various types of memory devices.

[0041] For example, at least one host in the priority mode may be a host requesting high-throughput output or a host performing complex data computing operations.

[0042] Figure 2 is a block diagram illustrating a computing system according to an example embodiment.

[0043] refer to Figure 2 , computing system 100 may include a plurality of hosts 101, 102, and 103, a plurality of CXL devices 140, 180, and 185, and a CXL switch 110. Figure 24. A computing system 10 including three hosts and three memory devices is illustrated in FIG. 1 , but example embodiments are not limited thereto and various numbers of devices may be included in the computing system 100.

[0044] The plurality of hosts 101, 102, and 103 and the plurality of CXL devices 140, 180, and 185 may communicate with each other based on the CXL protocol through the CXL switch 110. The CXL switch 110 may correspond to Figure 1 The interconnect device 18 in the embodiment of the present invention, and the plurality of CXL devices 140, 180 and 185 may correspond to Figure 1 In other words, each of the plurality of CXL devices 140, 180, and 185 may be referred to as a memory device.

[0045] CXL switch 110 may include upstream ports USP1 , USP2 , and USP3 respectively coupled to multiple hosts 101 , 102 , and 103 , downstream ports DSP1 , DSP2 , and DSP3 respectively coupled to multiple CXL devices 140 , 180 , and 185 , a crossbar switch 120 , and a fabric manager 130 .

[0046] The crossbar switch 120 may connect at least one of the upstream ports USP1, USP2, and USP3 to at least one of the downstream ports DSP1, DSP2, and DSP3, and the fabric manager 130 may manage a port mapping table PMT 131 including port connection information about the connection between the upstream ports USP1, USP2, and USP3 and the downstream ports DSP1, DSP2, and DSP3. Therefore, at least a portion of the plurality of CXL devices 140, 180, and 185 may be shared by the plurality of hosts 101, 102, and 103 through the crossbar switch 120, and the fabric manager 130 may manage the connection relationship between the plurality of hosts 101, 102, and 103 and the plurality of CXL devices 140, 180, and 185.

[0047] Each of the plurality of CXL devices 140 , 180 , and 185 may include a corresponding one of the plurality of priority schedulers 151 , 181 , and 187 and a corresponding one of the plurality of memories 170 , 183 , and 189 .

[0048] A corresponding one of the memories 170, 183 and 189 can generate internal data by executing memory operations corresponding to commands included in requests REQ1, REQ2 and REQ3 from multiple hosts 101, 102 and 103, and a corresponding one of the priority schedulers 151, 181 and 187 can designate at least one host (i.e., the first host) from the multiple hosts 101, 102 and 103 as a priority mode (e.g., a priority host) based on attribute information of each of the multiple hosts 101, 102 and 103, and can generate output data by rearranging the internal data so that data requested by at least one host (i.e., the first host) having the priority mode is output preferentially.

[0049] The attribute information of each of the plurality of hosts 101, 102, and 103 may include an access count based on a corresponding one of the requests REQ1, REQ2, and REQ3 to the plurality of CXL devices 140, 180, and 185, and a (memory) allocation amount based on a device logical address of each of the memories 170, 183, and 189 included in the corresponding one of the requests REQ1, REQ2, and REQ3.

[0050] Figure 3 is a diagram illustrating an exemplary embodiment of the Figure 2 A block diagram of an example of a CXL device in a computing system.

[0051] exist Figure 3 , the configuration of the CXL device 140 among the plurality of CXL devices 140 , 180 , and 185 is illustrated, and each configuration of the CXL devices 180 and 185 may be substantially the same as the configuration of the CXL device 140 .

[0052] refer to Figure 3 A CXL device 140 , which may also be described as a CXL-compliant device, compliant and configured for communication using the CXL standard, may include a controller 145 and a memory 170 .

[0053] The controller 145 can be Figure 2 All or part of the multiple hosts 101, 102 and 103 receive data packets PKTa, PKTb and PKTc.

[0054] The data packet PKTa may include a host identifier HIDa and a request REQa, and the request REQa may include a command CMDa, a device logical address DLAa, and a chip select signal CSa. The host that issues the data packet PKTa may be identified by the host identifier HIDa.

[0055] The data packet PKTb may include a corresponding host identifier and a corresponding request, and the data packet PKTc may include a corresponding host identifier and a corresponding request.

[0056] The memory 170 may include a storage region MR divided into a plurality of logic devices LD1, LD2, ..., LDt. Here, t may be an integer greater than 2. The plurality of logic devices LD1, LD2, ..., LDt may be referred to as a plurality of logic (memory) regions.

[0057] The controller 145 may include a priority scheduler 150 and a command scheduler 165, and the priority scheduler 150 may include a host information register 151, a priority mode selector 155, a first buffer 157, an arbiter 161, and a second buffer 163. Components such as various schedulers, controllers, selectors, etc. described herein and depicted as blocks may be implemented with hardware (such as transistors and various passive and active circuit components such as logic circuits) and additional firmware or software.

[0058] The command scheduler 165 can provide the scheduled command CMD_S to the memory 170 by scheduling the command CMDs included in the data packets PKTa, PKTb and PKTc, and the memory 170 can generate internal data IDTAs by performing a memory operation corresponding to the scheduled command CMD_S, and can provide the internal data IDTAs to the first buffer 157.

[0059] The host information register 151 may receive the data packets PKTa, PKTb, and PKTc, and may store attribute information of each of all or some of the plurality of hosts 101, 102, and 103 based on the data packets PKTa, PKTb, and PKTc.

[0060] The priority mode selector 155 may designate a first host from the plurality of hosts 101, 102, and 103 as a priority host based on the attribute information of each of all or some of the plurality of hosts 101, 102, and 103 stored in the host information register 151, may generate a priority mode signal PMS indicating that the first host is designated as the priority host, and may provide the priority mode signal PMS to the arbitrator 161. By including the priority mode selector 155 in the memory 170, the power and load of a switch such as the CXL switch 110 can be reduced.

[0061] The arbiter 161 may receive the internal data IDTAs from the first buffer 157 , may generate rearranged data RDTA by rearranging the internal data IDTAs in response to the priority mode signal PMS, and may provide the rearranged data RDTA to the second buffer 163 .

[0062] The second buffer 163 may receive the rearranged data RDTA and may provide the rearranged data RDTA as output data ODTA to all or some of the plurality of hosts 101 , 102 , and 103 in a received order.

[0063] For example, the priority scheduler 150 can designate a first host from among the multiple hosts 101, 102, and 103 as a priority host based on attribute information of each of the multiple hosts 101, 102, and 103, and can generate output data ODTA by rearranging internal data IDTAs so that data requested by the first host is output with priority (e.g., output first).

[0064] Figure 4 FIG. 1 illustrates an exemplary embodiment of the present invention. Figure 3 Example of the host information register in a CXL device.

[0065] refer to Figure 4 , the host information register 151 may include a first column 152 , a second column 153 , and a third column 154 .

[0066] A host identifier HOST ID identifying multiple hosts 101, 102 and 103 may be stored in a first column 152, an access count based on a request included in data packets PKTa, PKTb and PKTc may be stored in a second column 153, and an allocation amount ALLOCATION based on a device logical address included in PKTa, PKTb and PKTc may be stored in a third column 154.

[0067] For a host having a host identifier HIDa, an access count CV1 and an allocation amount ALC1 as attribute information may be stored in the host information register 151, for a host having a host identifier HIDb, an access count CV2 and an allocation amount ALC2 as attribute information may be stored in the host information register 151, and for a host having a host identifier HIDc, an access count CV3 and an allocation amount ALC3 as attribute information may be stored in the host information register 151. The access count may, for example, refer to the number of accesses that will be required by the request or the host, and the allocation amount may refer to the amount of resources (e.g., memory space) required for the request. That is, the access count may indicate the number of accesses required for the corresponding request in the request, and the allocation amount may refer to (i.e., may indicate) the amount of logical storage area allocated for the corresponding request in the request. The logical storage area may correspond to Figure 3 For example, the logical storage region may include one or more memory cells among a plurality of memory cells in the memory device.

[0068] The priority mode selector 155 may designate (i.e., select) a first host from among the plurality of hosts 101, 102, and 103 as a priority host based on at least one of the maximum values ​​of the access counts CV1, CV2, and CV3 of the plurality of hosts 101, 102, and 103 during the reference time interval and the maximum values ​​of the allocation amounts ALC1, ALC2, and ALC3 on the plurality of hosts 101, 102, and 103. For example, when the access count CV1 is the largest of the access counts CV1, CV2, and CV3 and the allocation amount ALC1 is the largest of the allocation amounts ALC1, ALC2, and ALC3, the priority mode selector 155 may designate the host 101 from among the plurality of hosts 101, 102, and 103 as a priority mode. An algorithm may be used to determine which host is the priority host based on a combination of the access counts and allocation amounts of the respective hosts.

[0069] Figure 5 The diagram shows Figure 3 An example of internal data provided to the controller by the memory in the CXL device.

[0070] exist Figure 5 In the example, it is assumed that a plurality of hosts 101 , 102 , and 103 send requests associated with reading data to CXL device 140 in the order of host 102 , host 101 , and host 103 .

[0071] In addition, it is assumed that internal data IDTA11 is requested by the host 101 , internal data IDTA2 is requested by the host 102 , internal data IDTA12 is requested by the host 101 , and internal data IDTA3 is requested by the host 103 .

[0072] refer to Figure 5 , the CXL device 140 may provide the internal data IDTA11 , IDTA2 , IDTA12 , and IDTA3 according to the order requested by the plurality of hosts 101 , 102 , and 103 .

[0073] Figure 6 The diagram shows Figure 3 Example of output data output by the controller in .

[0074] exist Figure 6 In the example, it is assumed that a plurality of hosts 101 , 102 , and 103 send requests associated with reading data to CXL device 140 in the order of host 101 , host 102 , host 101 , and host 103 .

[0075] In addition, it is assumed that internal data IDTA11 is requested by host 101, internal data IDTA2 is requested by host 102, internal data IDTA12 is requested by host 101, and internal data IDTA3 is requested by host 103, and host 101 is designated as the priority host.

[0076] refer to Figure 3 and Figure 6 , the CXL device 140 may provide the internal data IDTA11, IDTA2, IDTA12, and IDTA3 to the first buffer 157 according to the order requested by the plurality of hosts 101, 102, and 103, and the arbiter 161 generates rearranged data IDTA11, IDTA12, IDTA2, and IDTA3 by rearranging the internal data IDTA11, IDTA2, IDTA12, and IDTA3 received from the first buffer 157 based on the priority mode signal PMS so that IDTA11 and IDTA12 requested by the host 101 are output with priority. The CXL device may store the rearranged data IDTA11, IDTA12, IDTA2, and IDTA3 in the second buffer 163.

[0077] The second buffer 163 may provide the rearranged data IDTA11 , IDTA12 , IDTA2 , and IDTA3 as output data ODTA to the plurality of hosts 101 , 102 , and 103 in the rearranged order.

[0078] exist Figure 6 In the embodiment, data packets PKT11 and PKT12 may be provided to host 101 through CXL switch 110, data packet PKT11 may include header H, internal data IDTA11 and cyclic redundancy check data CRC, and data packet PKT12 may include header H, internal data IDTA12 and cyclic redundancy check data CRC. Data packet PKT2 may be provided to host 102 through CXL switch 110, data packet PKT2 may include header H, internal data IDTA2 and cyclic redundancy check data CRC. Data packet PKT3 may be provided to host 103 through CXL switch 110, data packet PKT3 may include header H, internal data IDTA3 and cyclic redundancy check data CRC.

[0079] Figure 7 is a diagram illustrating an exemplary embodiment of the Figure 2 A block diagram of another example of a CXL device in a computing system.

[0080] exist Figure 7, the configuration of the CXL device 140 a is illustrated as an example of the CXL device 140 among the plurality of CXL devices 140 , 180 , and 185 , and each configuration of the CXL devices 180 and 185 may be substantially the same as the configuration of the CXL device 140 a .

[0081] refer to Figure 7 The CXL device 140 a may include a controller 145 a and a memory 170 .

[0082] The controller 145a can be Figure 2 All or part of the multiple hosts 101, 102 and 103 receive data packets PKTa, PKTb and PKTc.

[0083] The data packet PKTa may include a host identifier HIDa and a request REQa, and the request REQa may include a command CMDa, a device logical address DLAa, and a chip select signal CSa. The host that issues the data packet PKTa may be identified by the host identifier HIDa.

[0084] The data packet PKTb may include a corresponding host identifier and a corresponding request, and the data packet PKTc may include a corresponding host identifier and a corresponding request.

[0085] The memory 170 may include a storage region MR divided into a plurality of logic devices LD1 , LD2 , . . . , LDt.

[0086] The controller 145a may include a priority scheduler 150a, a first buffer 157a, an arbiter 161a, a second buffer 163a, and a command scheduler 165, and the priority scheduler (PS) 150a may include a host information register 151a and a priority mode selector 155a. As is conventional in the field of the disclosed technology, features and embodiments are described and illustrated in the accompanying drawings in terms of functional blocks, units, and / or modules. Those skilled in the art will appreciate that these blocks, units, and / or modules are physically implemented by electronic (or optical) circuits such as logic circuits, discrete components, microprocessors, hard-wired circuits, memory elements, wiring connections, etc., which can be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. In the case where the blocks, units, and / or modules are implemented by a microprocessor or the like, they can be programmed using software (e.g., microcode) to perform the various functions discussed herein, and can be optionally driven by firmware and / or software. Alternatively, each block, unit and / or module may be implemented by dedicated hardware, or as a combination of dedicated hardware for performing some functions and a processor (e.g., one or more programmed microprocessors and associated circuit systems) for performing other functions. Moreover, without departing from the scope of the inventive concept, each block, unit and / or module of the embodiment may be physically divided into two or more interacting and discrete blocks, units and / or modules. In addition, without departing from the scope of the inventive concept, the blocks, units and / or modules of the embodiment may be physically combined into more complex blocks, units and / or modules (e.g., as in Figure 7 151a and the priority mode selector 155a).

[0087] The command scheduler 165 can provide the scheduled command CMD_S to the memory 170 by scheduling the command CMDs included in the data packets PKTa, PKTb and PKTc, and the memory 170 can generate internal data IDTAs by performing a memory operation corresponding to the scheduled command CMD_S, and can provide the internal data IDTAs to the first buffer 157a.

[0088] The host information register 151 a may receive the data packets PKTa, PKTb, and PKTc, and may store attribute information of each of all or some of the plurality of hosts 101 , 102 , and 103 based on the data packets PKTa, PKTb, and PKTc.

[0089] The priority mode selector 155a can designate a first host from multiple hosts 101, 102 and 103 as a priority host based on attribute information of each of all or some of the multiple hosts 101, 102 and 103 stored in the host information register 151a, can generate a priority mode signal PMS indicating that the first host is designated as the priority host, and can provide the priority mode signal PMS to the arbitrator 161a.

[0090] The arbiter 161a may receive the internal data IDTAs from the first buffer 157a, may generate rearranged data RDTA by rearranging the internal data IDTAs in response to the priority mode signal PMS, and may provide the rearranged data RDTA to the second buffer 163a.

[0091] The second buffer 163 a may receive the rearranged data RDTA and may provide the rearranged data RDTA as output data ODTA to all or some of the plurality of hosts 101 , 102 , and 103 in a received order.

[0092] The priority scheduler 150a or the controller 145a can designate the first host from the multiple hosts 101, 102 and 103 as the priority host based on the attribute information of each of the multiple hosts 101, 102 and 103, and can generate output data ODTA by rearranging internal data IDTAs so that data requested by the first host is output with priority.

[0093] Figure 8 is a diagram illustrating an exemplary embodiment of the Figure 2 A block diagram of another example of a CXL device in a computing system.

[0094] exist Figure 8 , the configuration of the CXL device 140 b is illustrated as an example of the CXL device 140 among the plurality of CXL devices 140 , 180 , and 185 , and each configuration of the CXL devices 180 and 185 may be substantially the same as the configuration of the CXL device 140 b .

[0095] refer to Figure 8 , the CXL device 140b may include a controller 145b and a memory module 170b.

[0096] The controller 145b can be Figure 2 All or part of the multiple hosts 101, 102 and 103 receive data packets PKTa, PKTb and PKTc.

[0097] The data packet PKTa may include a host identifier HIDa and a request REQa, and the request REQa may include a command CMDa, a device logical address DLAa, and a chip select signal CSa. The host that issues the data packet PKTa may be identified by the host identifier HIDa.

[0098] The data packet PKTb may include a corresponding host identifier and a corresponding request, and the data packet PKTc may include a corresponding host identifier and a corresponding request.

[0099] The memory module 170b may include a plurality of (memory) chips 171, 172, ..., 17t and a plurality of data buffers DB1, DB2, ..., DBt. The plurality of data buffers DB1, DB2, ..., DBt may be connected to the plurality of chips 171, 172, ..., 17t, respectively, and may temporarily store internal data output from the plurality of chips 171, 172, ..., 17t.

[0100] The controller 145 b may include a priority scheduler 150 b , an arbiter 161 b , a buffer 163 b , and a command scheduler 165 , and the priority scheduler 150 b may include a host information register 151 b and a priority mode selector 155 b .

[0101] The command scheduler 165 can provide the scheduled command CMD_S to the memory module 170b by scheduling the command CMDs included in the data packets PKTa, PKTb and PKTc, and the memory chips 171, 172, ..., 17t in the memory module 170b generate internal data IDTAs by performing memory operations corresponding to the scheduled command CMD_S, and the memory chips 171, 172, ..., 17t can provide the internal data IDTAs to multiple data buffers DB1, DB2, ..., DBt.

[0102] The host information register 151 b may receive the data packets PKTa, PKTb, and PKTc, and may store attribute information of each of all or some of the plurality of hosts 101 , 102 , and 103 based on the data packets PKTa, PKTb, and PKTc.

[0103] The priority mode selector 155b can designate a first host from multiple hosts 101, 102 and 103 as a priority mode based on attribute information of each of all or some of the multiple hosts 101, 102 and 103 stored in the host information register 151b, and can generate a priority mode signal PMS indicating that the first host is designated as the priority host, and can provide the priority mode signal PMS to the arbitrator 161b.

[0104] The arbiter 161b may receive internal data IDTAs from a plurality of data buffers DB1, DB2, . . . , DBt, may generate rearranged data RDTA by rearranging the internal data IDTAs in response to a priority mode signal PMS, and may provide the rearranged data RDTA to the buffer 163b.

[0105] The buffer 163 b may receive the rearranged data RDTA and may provide the rearranged data RDTA as output data ODTA to all or some of the plurality of hosts 101 , 102 , and 103 according to a reception order.

[0106] The priority scheduler 150b or the controller 145b can designate the first host from the multiple hosts 101, 102 and 103 as the priority host based on the attribute information of each of the multiple hosts 101, 102 and 103, and can generate output data ODTA by rearranging internal data IDTAs so that data requested by the first host is output with priority.

[0107] Fig. 9 is a flow chart illustrating a method of operating a CXL apparatus according to an example embodiment.

[0108] refer to Figures 2 to 9 In a method of a memory device such as a CXL device 140 (e.g., a CXL compatible memory) connected to a plurality of hosts 101, 102, and 103 through a CXL switch 110 and communicating with the plurality of hosts 101, 102, and 103 through a CXL protocol, the CXL device 140 receives data packets PKTa, PKTb, and PKTc from the plurality of hosts 101, 102, and 103 (operation S110).

[0109] The memory 170 in the CXL device 140 generates internal data IDTAs by performing a memory operation corresponding to the command included in the data packets PKTa, PKTb, and PKTc (operation S120).

[0110] The first buffer 157 included in the controller 150 in the CXL device 140 performs data buffering to temporarily store the internal data IDTAs (operation S130 ).

[0111] The priority mode selector 155 in the priority scheduler 150 in the CXL device 140 designates the host 101 as a priority host based on the attribute information of each of the plurality of hosts 101, 102, and 103 stored in the host information register 151 (operation S140), and provides the arbitrator 161 with a priority mode signal PMS indicating that the host 101 is designated as the priority host.

[0112] The arbiter 161 generates rearranged data RDTA by rearranging the internal data IDTAs stored in the first buffer 157 in response to the priority mode signal PMS, and may provide the rearranged data RDTA to the buffer 163, and the second buffer 163 transmits the rearranged data RDTA as output data ODTA to the plurality of hosts 101, 102, and 103 through the CXL switch 110 (operation S150).

[0113] Figure 2 The method can be applied to reference Figure 1 The computing system 10 described includes multiple host devices 11 and 12 and multiple memory devices 13, 14 and 15 communicating through an interconnect device 18, and can be applied to Figure 3 , Figure 7 or Figure 8 Different embodiments of the memory device described in any of the.

[0114] Fig.10 is a block diagram illustrating a computing system according to an example embodiment.

[0115] refer to Fig.10 The computing system 100a may include a plurality of hosts 101, 102, 103, ..., 10K, a plurality of dynamic random access memories (DRAMs) 191, 192, 193, ..., 19M, and a CXL switch 110a. Here, K may be an integer greater than 3, and M may be an integer greater than 3.

[0116] A plurality of hosts 101 , 102 , 103 , . . . , 10K and a plurality of DRAMs 191 , 192 , 193 , . . . , 19M may communicate with each other based on the CXL protocol through the CXL switch 110 a .

[0117] CXL switch 110a may include upstream ports USP1, USP2, USP3, ..., USPK respectively coupled to multiple hosts 101, 102, 103, ..., 10K, downstream ports DSP1, DSP2, DSP3, ..., DSPM respectively coupled to multiple DRAMs 191, 192, 193, ..., 19M, a crossbar switch 120a, and a fabric manager 130a.

[0118] The crossbar switch 120a may connect at least one of the upstream ports USP1, USP2, USP3, ..., USPK to at least one of the downstream ports DSP1, DSP2, DSP3, ..., DSPM, and the fabric manager 130a may manage a port mapping table PMT 131a including port connection information about the connection between the upstream ports USP1, USP2, USP3, ..., USPK and the downstream ports DSP1, DSP2, DSP3, ..., DSPM. Therefore, at least a portion of the plurality of DRAMs 191, 192, 193, ..., 19M (e.g., some of them) may be shared by the plurality of hosts 101, 102, 103, ..., 10K through the crossbar switch 120a, and the fabric manager 130a may manage the connection relationship between the plurality of hosts 101, 102, 103, ..., 10K and the plurality of DRAMs 191, 192, 193, ..., 19M.

[0119] Each of the plurality of DRAMs 191, 192, 193, ..., 19M may include a corresponding one of the plurality of priority schedulers PS1, PS2, PS3, ..., PSM and a corresponding one of the plurality of storage regions MR1, MR2, MR3, ..., MRM. Each of the storage regions MR1, MR2, MR3, ..., MRM may include a logical device shared by at least a portion of the plurality of hosts 101, 102, 103, ..., 10K (e.g., some of them). For example, in one embodiment, the storage region MR1 may be shared by the hosts 101, 102, and 103, the storage region MR2 may be shared by the hosts 102, 103, and 10M, the storage region MR3 may be shared by the hosts 101, 103, and 10M, and the storage region MRM may be dedicated to the host 10M. Fig.10 The different types of shading in show which hosts share which storage areas.

[0120] A corresponding one of the multiple DRAMs 191, 192, 193, ..., 19M can generate internal data by executing a memory operation corresponding to a command included in a request from a plurality of hosts 101, 102, 103, ..., 10K, and a corresponding one of the priority schedulers PS1, PS2, PS3, ..., PSM can designate at least one host (i.e., the first host) from the multiple hosts 101, 102, 103, ..., 10K as a priority host based on attribute information of each of the multiple hosts 101, 102, 103, ..., 10K, and can generate output data by rearranging the internal data so that data requested by at least one host (i.e., the first host) in the priority mode is output preferentially.

[0121] Fig.11 is a diagram illustrating an exemplary embodiment of the Fig.10 A block diagram of an example DRAM in a computing system.

[0122] Each of the DRAMs 191, 192, 193, . . . , 19M may be referred to as a semiconductor memory device, and may be in the form of, for example, a semiconductor chip or a semiconductor package including one or more semiconductor chips.

[0123] refer to Fig.11 , the semiconductor memory device 400 may include a control logic circuit 410, an address register 420, a clock buffer 425, a memory bank control logic 430, a refresh counter 445, a row address (RA) multiplexer (MUX) 440, a column address (CA) latch 450, a row decoder 460, a column decoder 470, a memory cell array 510, a sense amplifier unit 485, an input / output (I / O) gating circuit 490, an error correction code (ECC) engine 550, a data I / O buffer 520, a host information register 523, a priority mode selector 525, an arbiter 530 and a buffer 535.

[0124] The memory cell array 510 includes first to eighth memory bank arrays 510a-510h. The row decoder 460 includes first to eighth row decoders 460a-460h coupled to the first to eighth memory bank arrays 510a-510h, respectively, the column decoder 470 includes first to eighth column decoders 470a-470h coupled to the first to eighth memory bank arrays 510a-510h, respectively, and the sense amplifier unit 485 includes first to eighth sense amplifiers 485a-485h coupled to the first to eighth memory bank arrays 510a-510h, respectively.

[0125] The first to eighth memory bank arrays 510a-510h, the first to eighth row decoders 460a-460h, the first to eighth column decoders 470a-470h, and the first to eighth sense amplifiers 485a-485h may form the first to eighth memory banks. Each of the first to eighth memory bank arrays 510a-510h may include a plurality of memory cells MC formed at intersections of a plurality of word lines WL and a plurality of bit lines BTL.

[0126] The address register 420 may receive an address ADDR including a bank address BANK_ADDR, a row address ROW_ADDR, and a column address COL_ADDR from at least a portion of the plurality of hosts 101, 102, 103, ..., 10K. The address register 420 may provide the received bank address BANK_ADDR to the bank control logic 430, may provide the received row address ROW_ADDR to the row address multiplexer 440, and may provide the received column address COL_ADDR to the column address latch 450.

[0127] The bank control logic 430 may generate a bank control signal in response to the bank address BANK_ADDR. One of the first to eighth row decoders 460a-460h corresponding to the bank address BANK_ADDR is activated in response to the bank control signal, and one of the first to eighth column decoders 470a-470h corresponding to the bank address BANK_ADDR is activated in response to the bank control signal.

[0128] The row address multiplexer 440 may receive the row address ROW_ADDR from the address register 420 and may receive the refresh row address REF_ADDR from the refresh counter 445. The row address multiplexer 440 may selectively output the row address ROW_ADDR or the refresh row address REF_ADDR as the row address RA. The row address RA output from the row address multiplexer 440 is applied to the first to eighth row decoders 460a-460h.

[0129] Under the control of the control logic circuit 410 , the refresh counter 445 may sequentially increase or decrease the refresh row address REF_ADDR and may output the refresh row address REF_ADDR.

[0130] One of the first to eighth row decoders 460a-460h activated by the bank control logic 430 may decode the row address RA output from the row address multiplexer 440 and may activate a word line corresponding to the row address RA. For example, the activated bank row decoder applies a word line driving voltage to the word line corresponding to the row address.

[0131] The column address latch 450 may receive the column address COL_ADDR from the address register 420 and may temporarily store the received column address COL_ADDR. In some embodiments, in burst mode, the column address latch 450 generates a column address COL_ADDR' incremented from the received column address COL_ADDR. The column address latch 450 may apply the temporarily stored column address COL_ADDR or the generated column address COL_ADDR' to the first to eighth column decoders 470a-470h.

[0132] An activated one of the first to eighth column decoders 470 a ˜ 470 h may activate a sense amplifier corresponding to the bank address BANK_ADDR and the column address COL_ADDR through the I / O gating circuit 490 .

[0133] The I / O gating circuit 490 may include a circuit for gating input / output data, and also include input data masking logic, a read data latch for storing data output from the first to eighth memory arrays 510a~510h, and a write driver for writing data to the first to eighth memory arrays 510a~510h.

[0134] The codeword CW read from one of the first to eighth memory bank arrays 510a-510h may be read by a sense amplifier coupled to the memory bank array from which the codeword CW is to be read, and may be stored in a read data latch. The codeword CW stored in the read data latch may be provided to the ECC engine 550, and the ECC engine 550 may generate data DTA by performing ECC decoding on the codeword CW to provide the data DTA to the data I / O buffer 520, and the data I / O buffer 520 may provide the data DTA as internal data IDTA to the arbiter 530.

[0135] Data DTA to be written in a selected one of the first to eighth memory bank arrays 510a-510h may be provided to the data I / O buffer 520 from at least a portion of the plurality of hosts 101, 102, 103, ..., 10K to the ECC engine 550. The data I / O buffer 520 may provide the data DTA to the ECC engine 550. The ECC engine 550 may perform ECC encoding on the data DTA to generate parity bits, and the ECC engine 550 may provide a codeword CW including the data DTA and the parity bits to the I / O gating circuit 490. The I / O gating circuit 490 may write the codeword CW in a target page in the selected one of the memory bank arrays through a write driver.

[0136] Under the control of the control logic circuit 410 , the ECC engine 550 may perform ECC encoding on the data DTA and perform ECC decoding on the codeword CW.

[0137] The clock buffer 425 may receive the clock signal CK, may generate an internal clock signal ICK by buffering the clock signal CK, and may provide the internal clock signal ICK to a circuit component processing a command CMD and an address ADDR.

[0138] The control logic circuit 410 may control the operation of the semiconductor memory device 400. For example, the control logic circuit 410 may generate a control signal for the semiconductor memory device 401a to perform a write operation or a read operation. The control logic circuit 410 may include a command decoder 411 that decodes a command CMD received from the smart controller 210 and a mode register 412 that sets an operation mode of the semiconductor memory device 400.

[0139] For example, the command decoder 411 may generate a control signal corresponding to the command CMD by decoding a write enable signal, a row address strobe signal, a column address strobe signal, a chip select signal, and the like.

[0140] The host information register 523 may store attribute information of at least some of the plurality of hosts 101, 102, 103, ..., 10K. The priority mode selector 525 may designate at least one host (i.e., the first host) from the plurality of hosts 101, 102, 103, ..., 10K as a priority host based on the attribute information stored in the host information register 523, may generate a priority mode signal PMS indicating that the first host is designated as the priority host, and may provide the priority mode signal PMS to the arbitrator 530.

[0141] The arbiter 530 may receive the data DTA stored in the data I / O buffer 520 as the internal data IDTA, may generate rearranged data RDTA by rearranging the internal data IDTA in response to the priority mode signal PMS so that data requested by the host designated as the priority mode is output with priority, and may provide the rearranged data RDTA to the buffer 535. The buffer 535 may receive the rearranged data RDTA, and may provide the rearranged data RDTA as output data ODTA to all or some of the plurality of hosts 101, 102, 103, ..., 10K in a rearranged order.

[0142] Fig.12 is a block diagram illustrating a computing system according to an example embodiment.

[0143] refer to Fig.12The computing system 100b may include a plurality of hosts 101, 102, 103, ..., 10K, a plurality of chiplets 191a, 192a, 193a, ..., 19Ma, and a CXL switch 110a.

[0144] Multiple hosts 101, 102, 103, ..., 10K and multiple chiplets 191a, 192a, 193a, ..., 19Ma can communicate with each other based on the CXL protocol through the CXL switch 110a.

[0145] The computing system 100b differs from the computing system 100a in that a plurality of chiplets 191a, 192a, 193a, ..., 19M are connected to the CXL switch 110a instead of a plurality of DRAMs 191, 192, 193, ..., 19M. Fig.10 Description of similar parts.

[0146] Each of the plurality of chiplets 191a, 192a, 193a, ..., 19Ma may include a corresponding one of the plurality of priority schedulers PS1a, PS2a, PS3a, ..., PSMa and a corresponding one of the plurality of storage regions MR1a, MR2a, MR3a, ..., MRMa. Each of the storage regions MR1a, MR2a, MR3a, ..., MRMa may include a logic device shared by at least a portion of the plurality of hosts 101, 102, 103, ..., 10K (e.g., some of them). The storage region MR1a may be shared by the hosts 101, 102, and 103, the storage region MRa2 may be shared by the hosts 102, 103, and 10M, the storage region MR3a may be shared by the hosts 101, 103, and 10M, and the storage region MRMa may be dedicated to the host 10M.

[0147] A corresponding one of the multiple chiplets 191a, 192a, 193a, ..., 19Ma can generate internal data by executing a memory operation corresponding to a command included in a request from a plurality of hosts 101, 102, 103, ..., 10K, and a corresponding one of the priority schedulers PS1a, PS2a, PS3a, ..., PSMa can designate at least one host (i.e., the first host) from the multiple hosts 101, 102, 103, ..., 10K as a priority mode based on attribute information of each of the multiple hosts 101, 102, 103, ..., 10K, and can generate output data by rearranging the internal data so that data requested by at least one host (i.e., the first host) in the priority mode is output preferentially.

[0148] Fig.13 is a diagram illustrating an exemplary embodiment of the Fig.12Block diagram of a chiplet among multiple chiplets in a computing system.

[0149] exist Fig.13 For example, the configuration of chiplet 191a among multiple chiplets 191a, 192a, 193a, ..., 19Ma is illustrated, and each configuration of multiple chiplets 192a, 193a, ..., 19Ma can be substantially the same as the configuration of chiplet 191a.

[0150] refer to Fig.13 , the chiplet 191a may have a 3D chiplet structure including a base die BD and a computing die CD stacked on the base die BD. A plurality of functional block IPs may be arranged on at least one of the base die BD and the computing die CD. Fig.13 , the plurality of function blocks IP are illustrated as being arranged on the computing die CD, but example embodiments are not limited thereto, and the plurality of function blocks IP may also be arranged on the base die BD.

[0151] In this case, each of the multiple functional block IPs may include a chip designed to perform a specified specific function. For example, each of the multiple functional block IPs may include a CPU chip, an input / output interface chip, a chip in which a circuit for artificial intelligence (AI) operations is implemented, a graphics chip, a media chip, etc. Some of the multiple functional block IPs may include chips that perform the same function.

[0152] In the chiplet 191a, the types of a plurality of functional block IPs arranged on the base die BD and the computing die CD may be modified differently according to the purpose of the chiplet 191a. Therefore, the chiplet 191a may have improved reusability and scalability compared to a system on chip (SoC) of a comparative example in which the SoC is implemented as one functional block.

[0153] The memory die MD may be arranged on the computing die CD of the chiplet 191a. The memory die MD may be electrically connected to the computing die CD via a plurality of interconnection paths, and the interconnection paths may constitute signal paths.

[0154] Fig.14 and Fig.15 is a block diagram illustrating a computing system employing the CXL protocol according to an example embodiment. Fig.14 and Fig.15 The plurality of hosts 201 , 202 , and 203 shown in FIG. 1 may include various types of devices, such as a CPU, a GPU, an NPU, an FPGA, and peripheral devices.

[0155] The computing system 200 may include a root complex 210 and hosts 201, 202, and 203, and the root complex 210 may include a DMA (Direct Memory Access) engine 211 and one or more root ports, for example, a first root port RP1 213 connected to a memory device and a second root port RP2 214. According to an example embodiment, the root complex 210 may further include a fabric manager 212 that transfers data or requests through a fabric such as Ethernet, and may be connected to an endpoint through the fabric. Fig.14 and Fig.15 An example is shown in which the fabric manager 212 is included in the root complex 210 , but is not limited thereto.

[0156] According to an example embodiment, fabric manager 212 may be included in CXL switch 220. In an example embodiment, fabric manager 212 may be implemented in the form of firmware. As examples, endpoints may include flash-based memories such as SSD and UFS, volatile memories such as DRAM and SDRAM (Synchronous DRAM), and non-volatile memories such as PRAM, MRAM, RRAM, and FRAM. Fig.14 and Fig.15 , the root complex 210 is illustrated as a component separate from the host device, but the root complex 210 may be implemented in each of the hosts 201, 202, and 203 in an integrated form.

[0157] The root complex 210 may provide data communication based on various types of protocols between the hosts 201, 202, and 203 and the plurality of memory devices 230, 240, and 250. In some example embodiments, the root complex 210 and the plurality of memory devices 230, 240, and 250 may perform interfaces including various protocols defined in CXL (e.g., I / O protocol (CXL.io)).

[0158] Meanwhile, each of the plurality of memory devices 230, 240, and 250 may correspond to a type 3 device defined in the CXL protocol, and therefore, each of the plurality of memory devices 230, 240, and 250 may include a memory expander, and the memory expander may include a controller. In some example embodiments, a memory device including a plurality of storage areas and a memory expander may be implemented as separate devices.

[0159] Fig.14 and Fig.15 A CXL switch 220 according to the CXL standard is illustrated.

[0160] According to an example embodiment, the computing system 200 may support multiple virtual channels. The virtual channels may provide multiple transmission paths that are logically separated within one physical interface. Fig.14 and Fig.15 In the exemplary embodiment of FIG. 2 , a first virtual channel 221 corresponding to the first root port 213 and a second virtual channel 222 corresponding to the second root port 214 are illustrated, but the virtual channels of the computing system 200 may be implemented in various other forms. In addition, the hosts 201, 202, and 203, the root complex 210, and the components of the virtual channels may be considered to constitute a host system.

[0161] A single root port may be connected to multiple different devices through a virtual channel, or two or more root ports may be connected to a single device. For example, the first root port 213 may be connected to the memory device 240 through a path including one or more virtual PCI to PCI bridges (vPPBs), and likewise the first root port 213 may be connected to the memory device 230 through another path including one or more vPPBs. Similarly, the second root port 214 may be connected to the memory device 230 through one path including one or more vPPBs, and connected to the third memory device 250 through another path including one or more vPPBs.

[0162] The computing system 200 may provide multiple logic devices (MLDs) supported by the CXL protocol. Fig.14 and Fig.15 In the structure of the computing system 200 shown, the memory device 230 communicates with two or more host devices through the first root port 213 and the second root port 214. The memory device 230 may include first to t-th logical devices LD1, LD2, ..., LDt assigned to different host devices. As an example, the logical device LD1 may be assigned to the host 201 and may communicate with the host 201 through the first root port 213. Also, the logical device LD2 may be assigned to the host 202 and may communicate with the host 202 through the second root port 214. Meanwhile, each of the memory devices 240 and 250 may communicate through any one root port and may correspond to a single logical device (SLD).

[0163] The memory device 230 may include a priority scheduler 231, and the priority scheduler 231 may designate a first host from multiple hosts 201, 202 and 203 as a priority host based on attribute information of each of the multiple hosts 201, 202 and 203, may generate output data by rearranging internal data so that data requested by the first host is output with priority, and may provide the output data to all or some of the multiple hosts 201, 202 and 203.

[0164] Fabric manager 212 may manage a port mapping table 212 a including port connection information between upstream ports USP1 and USP2 and downstream ports DSP1 , DSP2 , and DSP3 included in each CXL switch 220 . Fig.14 shows the state where some vPPBs are not connected to physical ports (UNB), and Fig.15 The state of the corresponding vPPB connected to the physical port (e.g., downstream port DSP2) is shown. Through the virtual-physical connection (VP binding) between the vPPB and the downstream ports DSP1, DSP2, and DSP3, the mapping between the upstream ports USP1 and USP2 and the downstream ports DSP1, DSP2, and DSP3 can be implemented, and as a result, the connection between the devices connected to the physical ports can be controlled. Such virtual-physical connection (VP binding) can be controlled by the fabric manager 212. The fabric manager 212 can manage the port mapping table 212a, which includes the port connection information between the upstream ports USP1 and USP2 and the downstream ports DSP1, DSP2, and DSP3 included in the CXL switch 220.

[0165] Fig.16 and Fig.17 is a diagram illustrating an example embodiment of a host included in a computing system according to an example embodiment.

[0166] Fig.16 and Fig.17 A link based on the CXL protocol is illustrated as an example of an interconnection device between devices.

[0167] refer to Fig.16 , system 300 may include various types of host devices. Although host processor 310 and accelerator 320 (e.g., GPU and FPGA) are Fig.16 300. The host processor 310 and the accelerator 320 may be configured to send messages and / or data to each other or receive messages and / or data from each other through the link 350 configured to support the CXL protocol. In some example embodiments, the host processor 310 as a main processor may be a CPU configured to control the overall operation of the system 300.

[0168] In addition, the system 300 may further include a host memory 330 connected to the host processor 310 and a device memory 340 installed at the accelerator 320. The host memory 330 connected to the host processor 310 may support cache coherence. The device memory 340 may be managed by the accelerator 320 independently of the host memory 330. The host memory 330 and the device memory 340 may be accessed by multiple host devices. As an example, the accelerator 320 and a device such as a NIC may access the host memory 330 in a PCIeDMA manner.

[0169] In some example embodiments, link 350 may support multiple protocols (e.g., sub-protocols) defined in the CXL protocol, and may transmit messages and / or data through the multiple protocols. For example, the protocols may include a non-coherent protocol (or I / O protocol CXL.io), a coherent protocol (or cache protocol CXL.cache), and a memory access protocol (or memory protocol CXL.memory).

[0170] The I / O protocol CXL.io may be an I / O protocol similar to PCIe. A shared memory (eg, pooled memory) included in the system 300 may communicate with a host based on PCIe or the I / O protocol CXL.io. Figure 1 The memory device according to the example embodiment shown in FIG. 1 can be accessed by the host processor 310 and the accelerator 320 through an interconnect device based on PCIe or I / O protocol CXL.io. In addition, the cache protocol CXL.cache can provide a protocol by which the accelerator 320 can access the host memory 330, and the memory protocol CXL.memory can provide a protocol by which the host processor 310 can access the device memory 340.

[0171] The accelerator 320 may refer to any device configured to provide functionality to the host processor 310. For example, at least some of the computational operations and I / O operations running on the host processor 310 may be offloaded to the accelerator 320. In some embodiments, the accelerator 320 may include any one or any combination of programmable components (e.g., GPU and NPU), components configured to provide fixed functions (e.g., IP cores), and reconfigurable components (e.g., FPGA).

[0172] The accelerator 320 may include a physical layer 321, a multi-protocol multiplexer (MUX) 322, an interface circuit 323, and an accelerator logic 324, and may communicate with the device memory 340. The accelerator logic 324 may communicate with the host processor 310 through the multi-protocol MUX 322 and the physical layer 321 using multiple protocols.

[0173] The interface circuit 323 may determine one of a plurality of protocols based on a message and / or data for communication between the accelerator logic 324 and the host processor 310. The interface circuit 323 may be connected to at least one protocol queue included in the multi-protocol MUX 322, and transmit and receive a message and / or data to and from the host processor 310 through the at least one protocol queue.

[0174] The multi-protocol MUX 322 may include at least one protocol queue, and transmit and receive messages and / or data to and from the host processor 310 through the at least one protocol queue. In some example embodiments, the multi-protocol MUX 322 may include a plurality of protocol queues respectively corresponding to a plurality of protocols supported by the link 350. In some embodiments, the multi-protocol MUX 322 may arbitrate between communications of different protocols, and perform communications based on the selected protocol.

[0175] The device memory 340 may be connected to the accelerator 320 and is referred to as a device-attached memory. The accelerator logic 324 may communicate with the device memory 340 based on a protocol that is independent of the link 350 (i.e., a device-specific protocol). In some embodiments, the accelerator 320 may include a controller as a component for accessing the device memory 340, and the accelerator logic 324 may access the device memory 340 through the controller. The controller may access the device memory 340 of the accelerator 320, and likewise, enable the host processor 310 to access the device memory 340 through the link 350. In some embodiments, the device memory 340 may correspond to a CXL-based device-attached memory.

[0176] The host processor 310 may be a main processor (eg, a CPU) of the system 300. In some example embodiments, the host processor 310 may be a CXL-based host processor or a host. Fig.16 As shown, the host processor 310 may be connected to a host memory 330 , and includes a physical layer 311 , a multi-protocol MUX 312 , an interface circuit 313 , a coherency / cache circuit 314 , a bus circuit 315 , at least one core 316 , and an I / O device 317 .

[0177] At least one core 316 can execute instructions and is connected to the coherence / cache circuit 314. The coherence / cache circuit 314 can include a cache hierarchy and is referred to as coherence / cache logic. Fig.16As shown, the coherence / cache circuit 314 can communicate with at least one core 316 and the interface circuit 313. For example, the coherence / cache circuit 314 can enable communication through at least two protocols including a coherence protocol and a memory access protocol. In some example embodiments, the coherence / cache circuit 314 may include a DMA circuit. The I / O device 317 may be used to communicate with the bus circuit 315. For example, the bus circuit 315 may be PCIe logic, and the I / O device 317 may be a PCIe I / O device.

[0178] The interface circuit 313 may enable communication between components of the host processor 310 (e.g., the coherence / cache circuit 314 and the bus circuit 315) and the accelerator 320. In some example embodiments, the interface circuit 313 may enable communication between components of the host processor 310 and the accelerator 320 according to a plurality of protocols (e.g., a non-coherent protocol, a coherent protocol, and a memory protocol). For example, the interface circuit 313 may determine one of the plurality of protocols based on messages and / or data for communication between components of the host processor 310 and the accelerator 320.

[0179] The multi-protocol MUX 312 may include at least one protocol queue. The interface circuit 313 may be connected to the at least one protocol queue, and send messages and / or data to and receive messages and / or data from the accelerator 320 through the at least one protocol queue. In some example embodiments, the interface circuit 313 and the multi-protocol MUX 312 may be integrally formed into one component. In some embodiments, the multi-protocol MUX 312 may include a plurality of protocol queues corresponding to a plurality of protocols supported by the link 350, respectively. In some embodiments, the multi-protocol MUX 312 may arbitrate communications of different protocols and provide selected communications to the physical layer 311.

[0180] Furthermore, according to an example embodiment, Figure 1 The host's request generator RQG in may correspond to Fig.16 The various components shown in the figure may be included in these components. For example, the function of the request generator RQG may be provided by Fig.16 316 and I / O devices 317.

[0181] Fig.17 The diagram shows the Fig.16 An example of multiple protocols for communication in computing system 200. Also, Fig.17 An example is illustrated in which each of the host processor 310 and the accelerator 320 includes a memory controller. Fig.17The memory controller shown may include Fig.16 Some of the components included in each of the devices shown in the drawings may be implemented separately from the components.

[0182] The host processor 310 can communicate with the accelerator 320 based on multiple protocols. According to the above CXL example, the multiple protocols may include a memory protocol CXL.memory (or MEM), a consistency protocol CXL.cache (or CACHE), and an inconsistency protocol CXL.io (or IO). The memory protocol MEM may define transactions between the master and the subordinate. For example, the memory protocol MEM may define transactions from the master to the subordinate and transactions from the subordinate to the master. The consistency protocol cache may define the interaction between the accelerator 320 and the host processor 310. For example, the interface of the consistency protocol CACHE may include three channels including request, response, and data. The inconsistency protocol IO may provide an inconsistency load / store interface for the I / O device.

[0183] The accelerator 320 may include a memory controller 325 configured to communicate with and access the device memory 340. In some example embodiments, the memory controller 325 may be external to the accelerator 320 and integrated with the device memory 340. In addition, the host processor 310 may include a memory controller 318 configured to communicate with and access the main memory 330. In some example embodiments, the memory controller 318 may be external to the host processor 310 and integrated with the host memory 330.

[0184] Fig.18 is an example of a computing system when a memory device according to example embodiments corresponds to a type 3 memory device defined by the CXL protocol.

[0185] refer to Fig.18 , computing system 600 may include a root complex 610 , a CXL memory expander 620 connected to root complex 610 , and a memory device 630 .

[0186] The root complex 610 may include a home agent 611 and an I / O bridge 613, and the home agent 610 may communicate with the CXL memory expander 620 based on the coherent protocol CXL.mem, and the I / O bridge 613 may communicate with the CXL memory expander 620 based on a non-coherent protocol (i.e., the I / O protocol CXL.io). In the CXL protocol library, the home agent 610 may correspond to an agent arranged on the host side to solve the overall coherence of the computing system 600 for a given address.

[0187] CXL memory expander 620 may include a memory controller 621 .

[0188] In addition, CXL memory expander 620 may output data to root complex 610 via I / O bridge 613 based on I / O protocol CXL.io or PCIe.

[0189] The memory device 630 may include a storage region MR divided into a plurality of logical devices LD1, LD2, ..., LDt, and a priority scheduler 631. The priority scheduler 631 may designate a first host from among a plurality of hosts connected to the root complex 610 as a priority host based on attribute information of each of the plurality of hosts, may generate output data by rearranging internal data so that data requested by the first host is output with priority, and may provide the output data to all or some of the plurality of hosts.

[0190] Fig.19 is a block diagram illustrating a computing system according to an example embodiment.

[0191] refer to Fig.19 , the computing system (or system) 700 may include a first CPU 721 and a second CPU 731, and a first DDR (Double Data Rate) memory 722 and a second DDR memory 732 respectively connected to the first CPU 721 and the second CPU 731. The first CPU 721 and the second CPU 731 may be connected through an interconnection system based on a processor interconnection technology. Fig.19 The interconnect system shown in may provide at least one CPU-to-CPU coherent link between CPUs.

[0192] The system 700 may include a first input-output device 723 and a first accelerator 724 in communication with a first CPU 721, and a first device memory 725 coupled to the first accelerator 724. The first CPU 721 may communicate with the first input-output device 723 and the first accelerator 724 through a bus. In addition, the system 700 may include a second input-output device 733 and a second accelerator 734 in communication with a second CPU 731, and a second device memory 735 connected to the second accelerator 734. The second CPU 731 may communicate with the second input-output device 733 and the second accelerator 734 through a bus. In some example embodiments, at least one of the first device memory 725 and the second device memory 735 may be omitted from the system 700.

[0193] The system 700 may also include a remote far memory 740. The first CPU 721 and the second CPU 731 may be connected to the remote far memory 740 through a bus, respectively. The remote far memory 740 may be used for memory expansion in the system 700. In some example embodiments, the remote far memory 740 may be omitted from the system 700.

[0194] System 700 can perform communication based on at least some of the multiple protocols through the bus. Taking CXL as an example, information such as initial settings is sent based on the I / O protocol (CXL.io), and data and / or messages are sent based on the cache protocol (CXL.cache) and / or the memory protocol (CXL.mem).

[0195] exist Fig.19 In the illustrated system 700, remote far memory 740 may be shared by at least two hosts. Fig.19 It is shown that the first CPU 721 and the second CPU 731 share the remote far memory 740, but various other host devices may also share the remote far memory 740. When the memory device according to the example embodiment is applicable to the remote far memory 740, the remote far memory 740 may include a priority scheduler 741.

[0196] Fig. 20 is a block diagram illustrating a data center including a computing system according to an example embodiment.

[0197] In some example embodiments, the system described above with reference to the drawings may be used as an application server and / or a storage server and included in the data center 2000. In addition, the storage area allocation and / or the control of the signal transmission path according to the example embodiments may be applicable to each of the application server and / or the storage server.

[0198] refer to Fig. 20 The data center 2000 can collect various pieces of data and provide services, and is also called a data storage center. For example, the data center 2000 may be a system configured to operate a search engine and a database or a computing system used by a company such as a bank or a government agency. Fig. 20 As shown, the data center 2000 may include application servers 50_1 to 50_n and storage servers 60_1 to 60_m (where m and n are each an integer greater than 1). The number n of application servers 50_1 to 50_n and the number m of storage servers 60_1 to 60_m may be selected differently according to the embodiment. The number n of application servers 50_1 to 50_n may be different from the number m of storage servers 60_1 to 60_m.

[0199] The application servers 50_1 to 50_n may include any one or any combination of processors 51_1 to 51_n, memories 52_1 to 52_n, switches 53_1 to 53_n, NICs 54_1 to 54_n, and storage devices 55_1 to 55_n. The processors 51_1 to 51_n may control all operations of the application servers 50_1 to 50_n, access the memories 52_1 to 52_n, and run instructions and / or data loaded in the memories 52_1 to 52_n. Non-limiting examples of the memories 52_1 to 52_n may include DDR SDRAM, high bandwidth memory (HBM), hybrid memory cube (HMC), dual inline memory module (DIMM), Optane DIMM, or non-volatile DIMM (NVDIIMM).

[0200] According to example embodiments, the number of processors and memories included in the application servers 50_1 to 50_n may be selected differently according to the embodiment. In some embodiments, the processors 51_1 to 51_n and the memories 52_1 to 52_n may provide a processor-memory pair. In some embodiments, the number of processors 51_1 to 51_n may be different from the number of memories 52_1 to 52_n. The processors 51_1 to 51_n may include a single-core processor or a multi-core processor. In some embodiments, as Fig. 20 As shown in FIG. 1 and FIG. 2 , the storage devices 55_1 to 55_n may be omitted from the application servers 50_1 to 50_n. The number of storage devices 55_1 to 55_n included in the application servers 50_1 to 50_n may be selected differently according to the embodiment. The processors 51_1 to 51_n, the memories 52_1 to 52_n, the switches 53_1 to 53_n, the NICs 54_1 to 54_n and / or the storage devices 55_1 to 55_n may communicate with each other through the links described above with reference to the accompanying drawings.

[0201] The storage servers 60_1 to 60_m may include any one or any combination of processors 61_1 to 61_m, memories 62_1 to 62_m, switches 63_1 to 63_m, NICs 64_1 to 64_n, and storage devices 65_1 to 65_m. The processors 61_1 to 61_m and memories 62_1 to 62_m may work similarly to the processors 51_1 to 51_n and memories 52_1 to 52_n of the above-mentioned application servers 50_1 to 50_n.

[0202] The application servers 50_1 to 50_n can communicate with the storage servers 60_1 to 60_m through the network 70. In some embodiments, the network 70 can be implemented using Fiber Channel (FC) or Ethernet. FC can be a medium for relatively high-speed data transmission. An optical switch that provides high performance and high availability can be used as FC. According to the access method of the network 70, the storage servers 60_1 to 60_m can be provided as file storage devices, block storage devices, or object storage devices.

[0203] In some example embodiments, the network 70 may be a storage-only network, such as a storage area network (SAN). For example, the SAN may be an FC-SAN, which may be implemented using an FC network and using an FC protocol (FCP). In another case, the SAN may be an Internet Protocol (IP)-SAN, which uses a Transmission Control Protocol / Internet Protocol (TCP / IP) network and is implemented according to a SCSI or Internet SCSI (iSCSI) protocol based on TCP / IP. In some embodiments, the network 70 may be a general-purpose network, such as a TCP / IP network. For example, the network 70 may be implemented according to a protocol such as FC over Ethernet (FCoE), network attached storage (NAS), or non-volatile memory express (NVMe) (NVMe-oF) based on fabric.

[0204] The following will mainly describe the application server 50_1 and the storage server 60_1, but it can be noted that the description of the application server 50_1 can also be applied to another application server (e.g., 50_n), and the description of the storage server 60_1 can also be applied to another storage server (e.g., 60_m).

[0205] The application server 50_1 may store data requested to be stored by a user or client in one of the storage servers 60_1 to 60_m through the network 70. In addition, the application server 50_1 may obtain data requested to be read by a user or client from one of the storage servers 60_1 to 60_m through the network 70. For example, the application server 50_1 may be implemented as a web server or a database management system (DBMS).

[0206] The application server 50_1 can access the memory 52_n and / or the storage device 55_n included in another application server 50_n through the network 70, and / or access the memory 62_1 to 62_m and / or the storage devices 65_1 to 65_m included in the storage servers 60_1 to 60_m through the network 70. Therefore, the application server 50_1 can perform various operations on the data stored in the application servers 50_1 to 50_n and / or the storage servers 60_1 to 60_m. For example, the application server 50_1 can execute instructions to migrate or copy data between the application servers 50_1 to 50_n and / or the storage servers 60_1 to 60_m. In this case, data can be migrated to the storage 52_1 to 52_n of the application servers 50_1 to 50_n through the storage 62_1 to 62_m of the storage servers 60_1 to 60_m or directly from the storage devices 65_1 to 65_m of the storage servers 60_1 to 60_m. In some embodiments, for security or privacy, the data migrated through the network 70 can be encrypted data.

[0207] In the storage server 60_1, the interface IF can provide a physical connection between the processor 61_1 and the controller CTRL and a physical connection between the NIC 64_1 and the controller CTRL. For example, the interface IF can be implemented using a direct attached storage (DAS) method in which the storage device 65_1 is directly connected to a dedicated cable. For example, the interface IF can be implemented using various interface methods such as the following: Advanced Technology Attachment (ATA), Serial ATA (SATA), External SATA (e-SATA), Small Computer Small Interface (SCSI), Serial Attached SCSI (SAS), PCI, PCIe, NVMe, IEEE 1394, Universal Serial Bus (USB), Secure Digital (SD) Card, Multimedia Card (MMC), Embedded MMC (eMMC), UFS, Embedded UFS (eUFS) and Compact Flash (CF) Card Interface.

[0208] In the storage server 60_1 , the switch 63_1 may selectively connect the processor 61_1 to the storage device 65_1 or selectively connect the NIC 64_1 to the storage device 65_1 based on the control of the processor 61_1 .

[0209] In some example embodiments, the NIC 64_1 may include a network interface card (NIC) and a network adapter. The NIC 54_1 may be connected to the network 70 via a wired interface, a wireless interface, a Bluetooth interface, or an optical interface. The NIC 54_1 may include an internal memory, a digital signal processor (DSP), and a host bus interface, and is connected to the processor 61_1 and / or the switch 63_1 via the host bus interface. In some embodiments, the NIC 64_1 may be integrated with any one or any combination of the processor 61_1, the switch 63_1, and the storage device 65_1.

[0210] In the application servers 50_1 to 50_n or the storage servers 60_1 to 60_m, the processors 51_1 to 51_m and the processors 61_1 to 61_n can send commands to the storage devices 55_1 to 55_n and the storage devices 65_1 to 65_m or the memories 52_1 to 52_n and the memories 62_1 to 62_m, and program or read the data. In this case, the data can be data whose errors are corrected by an error correction code (ECC) engine. The data can be data processed using a data bus inversion (DBI) or a data mask (DM) and include cyclic redundancy code (CRC) information. For security or privacy, the data can be encrypted data.

[0211] In response to the read command received from the processors 51_1 to 51_m and the processors 61_1 to 61_n, the storage devices 55_1 to 55_n and the storage devices 65_1 to 65_m can send control signals and command / address signals to the non-volatile memory device (e.g., NAND flash memory device) NVM. The storage devices 55_1 to 55_n and the storage devices 65_1 to 65_m can process commands according to the various embodiments described above, for example, by prioritizing a specific processor and targeting data access. Therefore, when reading data from the non-volatile memory device NVM, a read enable signal can be input as a data output control signal to output data to the DQ bus. The read enable signal can be used to generate a data strobe signal. The command and address signals can be latched according to the rising edge or falling edge of the write enable signal.

[0212] The controller CTRL may control all operations of the storage device 65_1. In an embodiment, the controller CTRL may include a static RAM (SRAM). The controller CTRL may write data to the non-volatile memory device NVM in response to a write command, or read data from the non-volatile memory device NVM in response to a read command. For example, a write command and / or a read command may be generated based on a request provided from a host (e.g., a processor 61_1 of a storage server 60_1, a processor 61_m of another storage server 60_m, or processors 51_1 to 51_n of application servers 50_1 to 50_n). The buffer BUF may temporarily store (or buffer) data to be written to the non-volatile memory device NVM or data read from the non-volatile memory device NVM. In some embodiments, the buffer BUF may include a DRAM. The buffer BUF may store metadata. Metadata may refer to user data or data generated by the controller CTRL to manage the non-volatile memory device NVM. For security or privacy, the storage device 65_1 may include a secure element (SE).

[0213] The present disclosure may be applicable to various electronic devices and systems including high storage capacity memory devices. For example, the present disclosure may be applicable to systems such as: personal computers (PCs), server computers, data centers, workstations, mobile phones, smart phones, tablet computers, laptop computers, personal digital assistants (PDAs), portable multimedia players (PMPs), digital cameras, portable game consoles, music players, video cameras, video players, navigation devices, wearable devices, Internet of Things (IoT) devices, Internet of Everything (IoE) devices, e-book readers, virtual reality (VR) devices, augmented reality (AR) devices, robotic devices, drones, etc.

[0214] The foregoing describes example embodiments and should not be construed as limiting thereof. Although a few example embodiments have been described, those skilled in the art will readily appreciate that many modifications are possible in the example embodiments without materially departing from the inventive concept.

Claims

1. A memory device, the memory device being configured to be connected to a plurality of hosts through an interconnect device and to communicate with the plurality of hosts through a computing fast link protocol, the memory device comprising: a command scheduler configured to schedule commands included in requests from the plurality of hosts; a memory configured to generate internal data by executing a memory operation corresponding to the scheduled command; as well as A priority scheduler, the priority scheduler being configured to: designating a first host from the plurality of hosts as a priority host based on attribute information of each of the plurality of hosts; and Output data is generated by rearranging the internal data so that data requested by the first host is output with priority.

2. The memory device according to claim 1, further comprising: a controller, wherein the command scheduler and the priority scheduler are included in the controller, The priority scheduler is configured to receive data packets from the plurality of hosts, and Each of the data packets includes a corresponding request in the requests and a host identifier identifying a corresponding host in the multiple hosts.

3. The memory device according to claim 2, wherein: The priority scheduler comprises: a host information register configured to store the attribute information of each of the plurality of hosts based on the data packet; and A priority mode selector is configured to generate a priority mode signal indicating that the first host is designated as the priority host based on the attribute information stored in the host information register.

4. The memory device according to claim 3, wherein: The host information register is further configured to store, as the attribute information of the corresponding host among the plurality of hosts, an access count based on the corresponding request among the requests and an allocation amount based on the device logical address included in the corresponding request among the requests, and The access count indicates the number of accesses required for a corresponding request in the requests, and the allocation amount indicates the amount of the logical storage area allocated for the corresponding request in the requests.

5. The memory device according to claim 4, wherein: The priority mode selector is further configured to generate the priority mode signal based on the access count and the allocation amount stored in the host information register so that data requested by the first host is output with priority.

6. The memory device according to claim 3, wherein: The priority scheduler also includes: an arbitrator configured to rearrange the internal data in response to the priority mode signal; a first buffer configured to buffer the internal data and provide the buffered data to the arbitrator; and A second buffer is configured to provide the output data by buffering the rearranged data output from the arbiter.

7. The memory device according to claim 3, wherein: The controller further comprises: an arbitrator configured to rearrange the internal data in response to the priority mode signal; a first buffer configured to buffer the internal data and provide the buffered data to the arbitrator; and A second buffer is configured to provide the output data by buffering the rearranged data output from the arbiter.

8. The memory device according to claim 3, wherein: The memory comprises: multiple chips; and A plurality of data buffers corresponding to the plurality of chips, the plurality of data buffers being configured to buffer the internal data.

9. The memory device according to claim 3, wherein: The controller further comprises: an arbitrator configured to rearrange the internal data in response to the priority mode signal; and A buffer is configured to provide the output data by buffering the rearranged data output from the arbiter.

10. The memory device according to claim 1, wherein: The memory includes a storage area, and The storage area is divided into a plurality of logical devices shared by the plurality of hosts.

11. A computing system, comprising: Interconnection devices; a plurality of memory devices connected to the interconnection means; as well as a plurality of hosts connected to the interconnect device and configured to generate requests to access the plurality of memory devices, The plurality of memory devices are configured to communicate with the plurality of hosts via a computing fast link protocol, and Wherein, each of the plurality of memory devices comprises: a command scheduler configured to schedule commands included in the requests from the plurality of hosts; a memory configured to generate internal data by executing a memory operation corresponding to the scheduled command; and A priority scheduler is configured to designate a first host from the plurality of hosts as a priority host based on attribute information of each of the plurality of hosts, and to generate output data by rearranging the internal data so that data requested by the first host is output with priority.

12. The computing system of claim 11, wherein: Each of the plurality of memory devices further comprises: a controller, wherein the command scheduler and the priority scheduler are included in the controller, The priority scheduler is configured to receive data packets from the plurality of hosts, and Each of the data packets includes a corresponding request in the requests and a host identifier identifying a corresponding host in the multiple hosts.

13. The computing system of claim 12, wherein: The priority scheduler comprises: a host information register configured to store the attribute information of each of the plurality of hosts based on the data packet; and a priority mode selector configured to generate a priority mode signal indicating that the first host is designated as the priority host based on the attribute information stored in the host information register, and The host information register is further configured to store an access count based on a corresponding request among the requests and an allocation amount based on a device logical address included in the corresponding request among the requests as the attribute information about the corresponding host among the plurality of hosts.

14. The computing system of claim 13, wherein: The priority mode selector is further configured to generate the priority mode signal based on the access count and the allocation amount stored in the host information register so that data requested by the first host is output with priority.

15. The computing system of claim 13, wherein: The priority scheduler also includes: an arbitrator configured to rearrange the internal data in response to the priority mode signal; a first buffer configured to buffer the internal data and provide the buffered data to the arbitrator; and A second buffer is configured to provide the output data by buffering the rearranged data output from the arbiter.

16. The computing system of claim 11, in, The interconnect device includes a computing fast link switch, the computing fast link switch includes a fabric manager configured to manage connection relationships between the plurality of hosts and the plurality of memory devices, and The memory includes a storage area, and the storage area is divided into a plurality of logical devices shared by the plurality of hosts.

17. The computing system of claim 11, wherein: Each memory device of the plurality of memory devices includes dynamic random access memory.

18. The computing system of claim 11, wherein: Each memory device of the plurality of memory devices includes a chiplet.

19. The computing system of claim 11, wherein: Each memory device of the plurality of memory devices includes a memory module.

20. A memory device, the memory device being configured to be connected to a plurality of hosts via an interconnection device and to communicate with the plurality of hosts via a computing fast link protocol, the memory device comprising: a command scheduler configured to schedule commands included in requests from the plurality of hosts; a memory configured to generate internal data by executing a memory operation corresponding to the scheduled command; as well as A priority scheduler, the priority scheduler being configured to: designating a first host from the plurality of hosts as a priority host based on attribute information of each of the plurality of hosts; and generating output data by rearranging the internal data so that data requested by the first host is outputted with priority, Wherein, the priority scheduler includes: a host information register configured to store the attribute information of each of the plurality of hosts based on information in a received data packet; a priority mode selector configured to generate a priority mode signal based on the attribute information stored in the host information register; and An arbitrator configured to generate the output data by rearranging the internal data in response to the priority mode signal.

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