Memory system

Abstract

The embodiment of the invention provides a memory system which can reduce the size of a data buffer used when a nonvolatile memory is accessed. According to one embodiment, a memory system includes a nonvolatile memory chip, a write buffer, and a controller. The nonvolatile memory chip includes a memory cell array. The write buffer is capable of storing data received in response to a write request from a reception host. The controller performs a plurality of data transfer operations for transferring data of a second size from the write buffer to the nonvolatile memory chip, the data of the second size being smaller than the data of the first size written by one write operation for the nonvolatile memory chip. The controller writes, to the memory cell array, a plurality of second-size data transferred to the non-volatile memory chip by a plurality of data transfer operations.

Description

[0001] [Related applications]

[0002] This application is based on Japanese Patent Application No. 2023-131077 (filing date: August 10, 2023) and claims the priority. This application incorporates all the contents of the basic application by reference. Technical Field

[0003] An embodiment of the present invention relates to a technology for controlling a nonvolatile memory. Background Art

[0004] In recent years, memory systems with nonvolatile memory have become widely used. As one of such memory systems, a solid state drive (SSD) with NAND (Not-AND) type flash memory is known. SSD is used as a main storage device for various computing devices.

[0005] When a non-volatile memory is accessed from a host, the memory system generally has a data buffer. Accessing the non-volatile memory from the host is, for example, an action of receiving data from the host and writing it to the non-volatile memory, and an action of reading data from the non-volatile memory and sending it to the host. The data buffer includes, for example, a write buffer and a read buffer. The write buffer stores data to be written to the non-volatile memory. The read buffer stores data read from the non-volatile memory. The memory system can effectively send and receive data with the host, and write and read data to the non-volatile memory by having a data buffer.

[0006] The size of the data buffer may be greatly affected by the writing method and writing order for the non-volatile memory. For example, when the writing method and writing order are optimized in a way that the size of the write buffer is reduced, the size of the read buffer may become larger. On the other hand, when the writing method and writing order are optimized in a way that the size of the read buffer is reduced, the size of the write buffer may become larger. Summary of the invention

[0007] One embodiment provides a memory system capable of reducing the size of a data buffer used when accessing a nonvolatile memory.

[0008] According to an embodiment, a memory system includes a nonvolatile memory chip, a write buffer, and a controller. The nonvolatile memory chip includes a memory cell array. The write buffer can store data received in response to a write request from an accepting host. The controller performs the following data transfer actions multiple times: data of a second size smaller than data of a first size written in one write action to the nonvolatile memory chip is transferred from the write buffer to the nonvolatile memory chip. The controller writes the plurality of data of the second size transferred to the nonvolatile memory chip through the multiple data transfer actions into the memory cell array.

[0009] According to the memory system having the above configuration, the size of the data buffer used when accessing the nonvolatile memory can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 This is a block diagram showing a configuration example of an information processing system including the memory system according to the first embodiment.

[0011] Figure 2 This is a block diagram showing a configuration example of a nonvolatile memory chip included in the memory system according to the first embodiment.

[0012] Figure 3 It is a perspective view showing a configuration example of blocks included in the memory system according to the first embodiment.

[0013] Figure 4 This is a diagram showing a circuit configuration example of a block included in the memory system according to the first embodiment.

[0014] Figure 5 This is a diagram showing an example of a writing order in the nonvolatile memory chip included in the memory system according to the first embodiment.

[0015] Figure 6 FIG. 1 is a diagram showing an example of a writing order in a plurality of nonvolatile memory chips included in a memory system of a comparative example.

[0016] Figure 7 It is a diagram showing a writing operation to a nonvolatile memory chip in a memory system of a comparative example.

[0017] Figure 8 It is a diagram showing a read operation from a nonvolatile memory chip in a memory system of a comparative example.

[0018] Fig. 9 FIG. 1 is a diagram showing another example of the writing order in a plurality of nonvolatile memory chips included in the memory system of the comparative example.

[0019] Fig.10This is a diagram showing an example of a write operation to a nonvolatile memory chip included in the memory system according to the first embodiment.

[0020] Fig.11 This is a diagram showing an example of a command sequence for the nonvolatile memory chip included in the memory system according to the first embodiment.

[0021] Fig. 12A This is a flowchart showing an example of the procedure of the write control process executed in the memory system according to the first embodiment.

[0022] Fig. 12B It means continuation Fig. 12A A flowchart of an example of the sequence of a write control process.

[0023] Fig.13A This is a flowchart showing an example of a procedure of a nonvolatile process executed in the memory system according to the second embodiment.

[0024] Fig. 13B It means continuation Fig.13A A flowchart of an example of the sequence of nonvolatile processing.

[0025] Fig.14 This is a diagram showing an example of a command sequence for a nonvolatile memory chip included in the memory system according to the third embodiment.

[0026] Fig.15 This is a flowchart showing an example of a procedure of a nonvolatile process executed in the memory system according to the third embodiment. DETAILED DESCRIPTION

[0027] Hereinafter, embodiments will be described with reference to the drawings.

[0028] (First embodiment)

[0029] First reference Figure 1 , the configuration of an information processing system 1 including the memory system of the first embodiment will be described. The information processing system 1 includes a host device 2 and a memory system 3 .

[0030] The host device 2 may be a storage server that stores a large amount of various data in the storage system 3, or may be a personal computer. Hereinafter, the host device 2 is also referred to as a host 2.

[0031] The memory system 3 is a storage device configured to write data to a nonvolatile memory and read data from the nonvolatile memory. The nonvolatile memory is, for example, a NAND flash memory. The memory system 3 is also referred to as a storage device or a semiconductor storage device. The memory system 3 is implemented, for example, as a solid-state drive (SSD) having a NAND flash memory or a universal flash storage (UFS) device.

[0032] The memory system 3 can be used as a storage device of the host 2. The memory system 3 may be built in the host 2, or may be connected to the host 2 via a cable or a network.

[0033] The interface for connecting the host 2 and the memory system 3 is based on the high-speed peripheral component interconnect TM (PeripheralComponent Interconnect Express, PCIe TM ), Ethernet TM , Fibre Channel, high-speed non-volatile memory TM (Non-Volatile Memory Express, NVMe TM ), UFS and other specifications.

[0034] The memory system 3 includes, for example, a memory device 4 and a controller 6. The memory system 3 may further include a DRAM (Dynamic Random Access Memory) 5.

[0035] The memory device 4 includes one or more nonvolatile memory chips 41. The one or more nonvolatile memory chips 41 are, for example, nonvolatile memory chips 41-0, 41-1, 41-2, 41-3, ... In the following, the case where the memory device 4 includes four nonvolatile memory chips 41-0, 41-1, 41-2, and 41-3 is mainly exemplified. An unspecified one of the nonvolatile memory chips 41-0, 41-1, 41-2, 41-3, ... is also referred to as the nonvolatile memory chip 41. In addition, the i-th nonvolatile memory chip among the nonvolatile memory chips 41-0, 41-1, 41-2, 41-3, ... is represented as the i-th nonvolatile memory chip 41. The nonvolatile memory chip 41 is, for example, a NAND flash memory die.

[0036] The nonvolatile memory chip 41 includes a plurality of blocks. One block functions as the minimum unit of data erasing operation. Blocks are sometimes referred to as "erase blocks" or "physical blocks". Each of the plurality of blocks includes a plurality of pages. Each of the plurality of pages includes a plurality of storage cells connected to a single word line. One page functions as a unit of data writing operation and data reading operation. In addition, a word line can function as a unit of data writing operation and data reading operation.

[0037] There is an upper limit to the number of program / erase cycles (P / E (Program / Erase) cycles) for each block, which is called the maximum number of P / E cycles. One P / E cycle of a block includes a data erase operation for setting all storage cells in the block to an erased state and a data programming operation for writing data to each page of the block. In addition, writing data to a block (more specifically, a storage cell) is equivalent to programming the data into the block (storage cell).

[0038] The nonvolatile memory chip 41 can be realized as a flash memory configured to store a plurality of bits per memory cell.

[0039] Flash memories that are configured to store multiple bits in each storage cell are, for example, multi-level cell (MLC (Multiple Level Cell), or 4LC) flash memories, triple-level cell (TLC (Triple Level Cell), or 8LC) flash memories, and quad-level cell (QLC (Quadrable Level Cell), or 16LC) flash memories. MLC flash memories can store 2 bits of data in each storage cell. TLC flash memories can store 3 bits of data in each storage cell. QLC flash memories can store 4 bits of data in each storage cell. In addition, flash memories that are configured to store 1 bit in each storage cell are also referred to as single-level cell (SLC (Single Level Cell), or 2LC) flash memories.

[0040] In the case where the non-volatile memory chip 41 is implemented as an MLC flash memory, 2 pages of data are usually written to multiple storage cells connected to the same word line. The 2 pages of data are composed of lower-order (Lower) page data and upper-order (Upper) page data. Thus, 2 bits can be written to each storage cell. Any area in the MLC flash memory (for example, any one or more blocks) can be used as an area (SLC area) that can store only 1 bit in each storage cell. In the action of writing data to the SLC area, only 1 page of data (lower-order page data) is written to multiple storage cells connected to the same word line. Thus, in each block used as the SLC area, only 1 bit can be written to each storage cell, just like each block (SLC block) in the SLC flash memory. As a result, each block used as the SLC area functions as a pseudo-SLC block.

[0041] When the non-volatile memory chip 41 is implemented as a TLC flash memory, 3 pages of data are usually written to multiple storage cells connected to the same word line. The 3 pages of data are composed of lower-order page data, middle-order page data, and upper-order page data. Thus, 3 bits can be written to each storage cell. Any area (for example, any block or more) within the TLC flash memory can be used as the SLC area, or as an MLC area that can store 2 bits in each storage cell. In addition, the SLC area and the MLC area can be set by a unit smaller than a block. In the MLC area, only 2 pages of data are written to multiple storage cells connected to the same word line. Thus, in the MLC area, only 2 bits can be written to each storage cell.

[0042] When the non-volatile memory chip 41 is implemented as a QLC flash memory, 4 pages of data are usually written to multiple storage cells connected to the same word line. Thus, 4 bits can be written to each storage cell. Any area (for example, any block or more) within the QLC flash memory can be used as an SLC area, or as an MLC area, or as a TLC area that can store 3 bits in each storage cell. In addition, the SLC area, the MLC area, and the TLC area can be set by a unit smaller than a block. In the TLC area, only 3 pages of data are written to multiple storage cells connected to the same word line. Thus, in the TLC area, 3 bits can be written to each storage cell.

[0043] Furthermore, the nonvolatile memory chip 41 may be configured to store 5 bits or more per memory cell. Even in this case, any area of ​​the nonvolatile memory chip 41 can be used as an area for writing only 4 bits or less of data per memory cell.

[0044] The DRAM 5 is a volatile memory and includes, for example, a storage area for firmware (FW) 51 and a storage area for a logical-to-entity address conversion table 52 .

[0045] FW51 is a program for controlling the operation of the controller 6. FW51 is loaded from the memory device 4 to the DRAM 5, for example.

[0046] The controller 6 can be implemented by a circuit such as a system-on-a-chip (SoC). The controller 6 is configured to control the memory device 4. The functions of each part of the controller 6 can be implemented by dedicated hardware in the controller 6 or by a processor that executes FW.

[0047] The controller 6 can function as a flash translation layer (FTL) configured to perform data management and block management of the memory device 4. The data management performed by the FTL includes: (1) management of matching information indicating the correspondence between each logical address and each physical address of the memory device 4; and (2) processing for hiding the difference between the data read / write operation of the page unit and the data erase operation of the block unit. The block management includes management of bad blocks, wear leveling, and garbage collection.

[0048] The logical address is used by the host 2 to specify the address of the storage area of ​​the memory system 3. The logical address is, for example, a logical block address (Logical Block Address, LBA).

[0049] The management of the matching between each logical address and each physical address is performed, for example, using a logical-physical address conversion table 52. The controller 6 uses the logical-physical address conversion table 52 to manage the matching between each logical address and each physical address in a specific management size unit. The physical address corresponding to a certain logical address represents the physical storage location in the memory device 4 where the data of the logical address is written. The controller 6 uses the logical-physical address conversion table 52 to manage multiple storage areas after the storage area of ​​the memory device 4 is logically divided. The multiple storage areas correspond to multiple logical addresses, respectively. That is, each of the multiple storage areas is specified by 1 logical address. The logical-physical address conversion table 52 can be loaded from the memory device 4 to the DRAM 5 when the memory system 3 is started.

[0050] Data can only be written to one page once in each P / E cycle. Therefore, the controller 6 writes the updated data corresponding to a certain logical address to another physical storage location, rather than the physical storage location corresponding to the logical address storing the previous data. Moreover, the controller 6 invalidates the previous data by updating the logical physical address conversion table 52 in a manner of associating the logical address with the other physical storage location. The data referenced from the logical physical address conversion table 52 (that is, the data associated with the logical address) is called valid data. In addition, data that is not associated with any logical address is called invalid data. Valid data is data that may be read from the host 2 in the future. Invalid data is data that can no longer be read from the host 2.

[0051] In addition, the controller 6 is, for example, any one of the SLC method, the MLC method, the TLC method, and the QLC method, and can perform a write operation on the nonvolatile memory chip 41. The SLC method is a method of writing 1 bit to each storage cell. The MLC method is a method of writing 2 bits to each storage cell. The TLC method is a method of writing 3 bits to each storage cell. The QLC method is a method of writing 4 bits to each storage cell.

[0052] The controller 6 may include, for example, a host interface circuit (host I / F (Interface)) 11, a memory interface circuit (memory I / F) 12, a DRAM interface circuit (DRAM I / F) 13, a static random access memory (Static Random Access Memory, SRAM) 14, and a CPU (Central Processing Unit: Central Processing Unit) 15. The host I / F 11, the memory I / F 12, the DRAM I / F 13, the SRAM 14, and the CPU 15 may be connected via a bus 10.

[0053] The host I / F 11 functions as a circuit for receiving various commands, such as input / output (I / O) commands, various control commands, or data from the host 2. The I / O commands include, for example, write commands and read commands. The control commands include, for example, flush commands. In addition, the host I / F 11 functions as a circuit for sending responses to commands or data to the host 2.

[0054] The memory I / F 12 electrically connects the controller 6 and the memory device 4. The memory I / F 12 complies with interface standards such as Toggle DDR and Open NAND Flash Interface (ONFI).

[0055] The memory I / F 12 functions as a NAND control circuit configured to control the memory device 4. The memory I / F 12 can be connected to a plurality of nonvolatile memory chips 41 in the memory device 4 via a plurality of channels ch0, ch1, ch2, ch3, ..., respectively. By driving the plurality of nonvolatile memory chips 41 in parallel, access to the entire memory device 4 can be widened.

[0056] The DRAM I / F 13 functions as a DRAM control circuit configured to control access to the DRAM 5 .

[0057] SRAM14 is a volatile memory. In SRAM14, for example, a buffer area for temporarily storing data is set. The buffer area includes, for example, a write buffer 141 and a read buffer 142. The write buffer 141 temporarily stores user data to be written to the non-volatile memory chip 41. The read buffer 142 temporarily stores user data read from the non-volatile memory chip 41. In addition, the storage area of ​​DRAM5 can be allocated as the write buffer 141 and the read buffer 142. In addition, the storage area of ​​SRAM14 can be allocated as the storage area of ​​FW51 and the storage area of ​​the logical entity address conversion table 52. In the case where the storage area of ​​SRAM14 is allocated as the storage area of ​​the write buffer 141, the read buffer 142, the storage area of ​​FW51, and the storage area of ​​the logical entity address conversion table 52, the memory system 3 may not have DRAM5.

[0058] The CPU 15 is a processor configured to control the host I / F 11, the memory I / F 12, the DRAM I / F 13, and the SRAM 14. The CPU 15 performs various processes by executing the FW 51 loaded from the memory device 4 to the DRAM 5. The FW 51 is a control program including a command group for causing the CPU 15 to perform various processes. The CPU 15 can perform command processing for processing various commands from the host 2. The operation of the CPU 15 is controlled by the FW 51 executed by the CPU 15.

[0059] The functions of each part in the controller 6 may be realized by dedicated hardware in the controller 6 or by causing the CPU 15 to execute FW51 .

[0060] The CPU 15 functions as, for example, a write control unit 151 and a read control unit 152. The CPU 15 functions as the above-described units by, for example, executing FW51.

[0061] The write control unit 151 controls the operation of receiving user data from the host 2 and writing the user data to the nonvolatile memory chip 41 in response to a write request (e.g., a write command) received from the host 2. The read control unit 152 controls the operation of reading user data from the nonvolatile memory chip 41 and sending the data to the host 2 in response to a read request (e.g., a read command) received from the host 2.

[0062] Here, the configuration of the nonvolatile memory chip 41 will be described in more detail. Figure 2 2 is a block diagram showing a configuration example of the nonvolatile memory chip 41 .

[0063] The nonvolatile memory chip 41 includes, for example, T planes 45. T is an integer greater than 1. Figure 2, an example is shown in which the T planes 45 are four planes 45 - 0 , 45 - 1 , 45 - 2 , and 45 - 3 .

[0064] Each of the T planes 45 includes a peripheral circuit 31 , a latch 32 , and a memory cell array 33 .

[0065] The peripheral circuit 31 is a circuit for controlling the memory cell array 33. The peripheral circuit 31 includes, for example, a row decoder, a column decoder, and a sense amplifier. The peripheral circuit 31 can perform programming operations (writing operations), sensing operations (reading operations), and erasing operations on the memory cell array 33.

[0066] The latch 32 is a circuit including a storage area for temporarily storing data transmitted between the controller 6 and the non-volatile memory chip 41. The latch 32 is also called a register or a buffer. During the data writing operation, the data received from the controller 6 is temporarily stored in the latch 32 and then programmed into the memory cell array 33. Hereinafter, the operation of transmitting (inputting) the data received from the controller 6 and stored in the write buffer 141 to the latch 32 is referred to as a data input operation. In addition, the operation of programming the data stored in the latch 32 into the memory cell array 33 is referred to as a programming operation. The latch 32 includes, for example, one data input latch (DL) 321 and M programming latches (PL) 322. M is an integer greater than 1.

[0067] The data input latch 321 temporarily stores the data transferred from the write buffer 141 .

[0068] Each of the M programming latches 322 temporarily stores data transmitted from the data input latch 321. All the data stored in the M programming latches 322 are written to the memory cell array 33, for example, in one programming operation. Specifically, when data is written to the memory cell array 33 in a TLC manner, for example, three pages of data stored in three programming latches 322 are written to the memory cell array 33 in one programming operation. The three programming latches 322 are also referred to as the 0th programming latch (0th PL) 322-0, the 1st programming latch (1st PL) 322-1, and the 2nd programming latch (2nd PL) 322-2.

[0069] The memory cell array 33 includes a plurality of blocks. Each of the plurality of blocks includes a plurality of nonvolatile memory cell transistors arranged in a matrix. Hereinafter, the nonvolatile memory cell transistors are referred to as memory cells. Figure 2 , an example is shown in which the multiple blocks are blocks B0, B1, B2, . . . .

[0070] Each of the plurality of blocks includes a plurality of string units. Figure 2, an example is shown in which each block includes four string units SU0, SU1, SU2, and SU3.

[0071] Each of the plurality of string units is a set of memory cells. Each string unit includes, for example, a plurality of NAND strings NS. Each NAND string NS is a set of memory cells connected in series.

[0072] refer to Figure 3 and Figure 4 , the configuration of the blocks included in the memory cell array 33 will be described in more detail. Figure 3 and Figure 4 , an example of the configuration of block B0 is shown, but other blocks in the memory cell array 33 also have the same configuration.

[0073] Figure 3 It is a perspective view showing a configuration example of the block B0.

[0074] Block B0 includes four string units SU0, SU1, SU2, and SU3.

[0075] The four string units SU0, SU1, SU2, and SU3 are arranged in a direction stacked with a plurality of word lines WL0, ..., WLx ( Figure 3 The direction perpendicular to the vertical direction) Figure 3 Each of the four string units SU0, SU1, SU2, and SU3 includes a plurality of NAND strings NS.

[0076] One end of each NAND string NS is connected to a corresponding bit line in a plurality of bit lines BL0, ..., BLy. Each NAND string NS extends in a vertical direction. Control gates of a plurality of memory cells included in each NAND string NS are respectively connected to a plurality of word lines WL0, ..., WLx.

[0077] Figure 4 An example of the circuit configuration of block B0 is shown.

[0078] Each NAND string NS includes, for example, a plurality of memory cells MT0, ..., MTx, and two selection transistors ST1 and ST2. Each of the plurality of memory cells MT0, ..., MTx includes a control gate and a charge accumulation layer, and stores data in a non-volatile manner. The plurality of memory cells MT0, ..., MTx are connected in series between the source of the selection transistor ST1 and the drain of the selection transistor ST2. The drain of the selection transistor ST1 is connected to the corresponding bit line in the plurality of bit lines BL0, ..., BLy. The source of the selection transistor ST2 is connected to a common source line SL in the plurality of string units SU0, SU1, SU2, and SU3.

[0079] The gate of the selection transistor ST1 in the string unit SU0 is connected to the selection gate line SGD0 corresponding to the string unit SU0. The gate of the selection transistor ST1 in the string unit SU1 is connected to the selection gate line SGD1 corresponding to the string unit SU1. The gate of the selection transistor ST1 in the string unit SU2 is connected to the selection gate line SGD2 corresponding to the string unit SU2. The gate of the selection transistor ST1 in the string unit SU3 is connected to the selection gate line SGD3 corresponding to the string unit SU3.

[0080] The gates of the selection transistors ST2 in the string units SU0, SU1, SU2, and SU3 are commonly connected to the selection gate line SGS. In addition, the gates of the selection transistors ST2 in the string units SU0, SU1, SU2, and SU3 can be connected to a selection gate line that is different for each string unit. The control gates of the memory cells MT0, ..., MTx included in the block B0 are commonly connected to the word lines WL0, ..., WLx, respectively.

[0081] Each of the programming operation and the sensing operation of the peripheral circuit 31 can be collectively performed on a plurality of memory cells connected to one word line in one string unit. In each of the programming operation and the sensing operation, a set of memory cells collectively selected is called a memory cell group.

[0082] When one storage cell stores 1 bit of data, the size of the data stored in each storage cell group is called 1 page of data. For example, when one storage cell stores 3 bits of data, the size of the data stored in each storage cell group is 3 pages of data.

[0083] The erasing operation of the peripheral circuit 31 is performed, for example, in units of blocks. That is, the data stored in all the memory cells included in one block are erased at once.

[0084] Next, the relationship between the writing method and writing order to the nonvolatile memory chip 41 and the size (capacitance) of the write buffer 141 and the read buffer 142 is described. The writing order indicates the order of addresses to which data is written in the nonvolatile memory chip 41. The writing order is also called write addressing.

[0085] The sizes of the write buffer 141 and the read buffer 142 may be affected by the writing method and writing order for the nonvolatile memory chip 41. For example, when the writing method and writing order are optimized so as to reduce the size of the write buffer 141, the size of the read buffer 142 may become larger. On the other hand, when the writing method and writing order are optimized so as to reduce the size of the read buffer 142, the size of the write buffer 141 may become larger.

[0086] The following is an example of using a full sequence program (FPS) action as a writing method for the non-volatile memory chip 41. The FPS action is an action of programming multiple pages of data into one or more blocks in one programming action. For example, in the case of programming data into a block in the non-volatile memory chip 41 in a TLC manner, in the FSP action, 3 pages of data (lower-order page data, middle-order page data, and upper-order page data) are transferred (input) to the non-volatile memory chip 41, and the transferred 3 pages of data are uniformly programmed into one block. In addition, the following description is not limited to the example of using the TLC method, and can be similarly applied to any example of programming a fixed amount of data into one or more blocks.

[0087] One FSP operation may be performed on a single block or on multiple blocks included in each of multiple planes 45 in one nonvolatile memory chip 41. Blocks included in a plane 45 are also called plane blocks (PlaneBlock, PB). Performing one programming operation on multiple plane blocks included in each of multiple planes 45 is also called multi-plane programming. When the nonvolatile memory chip 41 includes multiple planes 45, multi-plane programming is generally used to emphasize programming performance.

[0088] Figure 5 An example of the writing order in one nonvolatile memory chip 41 is shown. Here, it is assumed that the TLC method and the FSP operation of multi-plane programming are performed on the nonvolatile memory chip 41 including four planes 45. The four planes 45 are the 0th plane 45-0, the first plane 45-1, the second plane 45-2, and the third plane 45-3.

[0089] The four blocks of writing objects contained in each of the four planes 45 are called plane blocks PB0, PB1, PB2, and PB3. Specifically, plane block PB0 is a block of writing objects contained in the 0th plane 45-0 in the TLC mode. Plane block PB1 is a block of writing objects contained in the 1st plane 45-1 in the TLC mode. Plane block PB2 is a block of writing objects contained in the 2nd plane 45-2 in the TLC mode. Plane block PB3 is a block of writing objects contained in the 3rd plane 45-3 in the TLC mode. The position within each plane block where data is written in one FSP action is specified by, for example, the string number.

[0090] like Figure 5As shown, in the FSP action corresponding to the string number "0", page data is input (transmitted) to the non-volatile memory chip 41 in the following order (0) to (11). (0) Lower-order page data for plane block PB0 (1) Lower-order page data for plane block PB1 (2) Lower-order page data for plane block PB2 (3) Lower-order page data for plane block PB3 (4) Middle-order page data for plane block PB0 (5) Middle-order page data for plane block PB1 (6) Middle-order page data for plane block PB2 (7) Middle-order page data for plane block PB3 (8) Upper-order page data for plane block PB0 (9) Upper-order page data for plane block PB1 (10) Upper-order page data for plane block PB2 (11) Upper-order page data for plane block PB3. In addition, the numbers and Figure 5 In the corresponding string number (here string number "0"), the value in the box specified by any one of the lower-level page, middle-level page, and upper-level page corresponds to any one of the plane blocks PB0, PB1, PB2, and PB3.

[0091] The 12 pages of data input in the order of (0) to (11) are written in one FSP operation. The 12 pages of data are programmed into plane blocks PB0, PB1, PB2, and PB3 in the order of input.

[0092] Next, the writing order of data is advanced in the string direction. Specifically, the string number is increased from 0 to 1. In the FSP action corresponding to the string number "1", 12 pages of data are input to the non-volatile memory chip 41 in the order of (12) to (23). The specific page data input in the order of (12) to (23) is the same as (0) to (11). The input 12 pages of data are programmed to the plane blocks PB0, PB1, PB2, and PB3 in the order of input.

[0093] Likewise, FSP actions corresponding to the increasing string numbers can be performed sequentially thereafter.

[0094] In order to improve programming performance, the memory system 3 may perform an interleaved write operation. The interleaved write operation is a write operation performed on a plurality of nonvolatile memory chips 41 in parallel.

[0095] Here, reference Figure 6 and Figure 7 , an interleaved writing operation on a plurality of nonvolatile memory chips in a memory system of a comparative example is described.

[0096] Figure 6An example of the writing order in a plurality of nonvolatile memory chips included in a memory system of a comparative example is shown. Here, it is assumed that the memory system of the comparative example includes four nonvolatile memory chips, and the TLC method and the FSP action of multi-plane programming are performed on the four nonvolatile memory chips each including four planes. The four nonvolatile memory chips are the 0th nonvolatile memory chip 41A-0, the 1st nonvolatile memory chip 41A-1, the 2nd nonvolatile memory chip 41A-2, and the 3rd nonvolatile memory chip 41A-3. In each of the nonvolatile memory chips 41A-0, 41A-1, 41A-2, and 41A-3, the four blocks of the writing objects included in each of the four planes are called plane blocks PB0, PB1, PB2, and PB3.

[0097] like Figure 6 As shown, in the FSP action corresponding to the string number "0", first, page data is input to the 0th nonvolatile memory chip 41A-0 in the order of (0) to (11). The page data input in the order of (0) to (11) is compared with the reference Figure 5 The page data input in the order of (0) to (11) is the same. Figure 6 In the corresponding combination of string number and non-volatile memory chip (here, the combination of string number "0" and the 0th non-volatile memory chip 41A-0), the value in the box specified by any one of the lower-level page, middle-level page, and upper-level page, and any one of the plane blocks PB0, PB1, PB2, and PB3 corresponds.

[0098] The 12 pages of data input in the order of (0) to (11) are written to the 0th nonvolatile memory chip 41A-0 in one FSP operation. The 12 pages of data are programmed to the plane blocks PB0, PB1, PB2, and PB3 of the 0th nonvolatile memory chip 41A-0 in the order of input.

[0099] When interleaving write operations are performed on a plurality of nonvolatile memory chips, after data is input to the 0th nonvolatile memory chip 41A-0 in the order of (0) to (11), the write sequence is advanced along the chip direction rather than the string direction. Here, the write sequence is advanced from the 0th nonvolatile memory chip 41A-0 to the 1st nonvolatile memory chip 41A-1.

[0100] Therefore, next, page data is input to the first nonvolatile memory chip 41A-1 in the order of (12) to (23). The specific page data input in the order of (12) to (23) is the same as the page data input in the order of (0) to (11), and the object of the data input operation is replaced from the 0th nonvolatile memory chip 41A-0 to the first nonvolatile memory chip 41A-1.

[0101] The 12 pages of data input in the order of (12) to (23) are written to the first nonvolatile memory chip 41A-1 in one FSP operation. The 12 pages of data are programmed to the plane blocks PB0, PB1, PB2, and PB3 of the first nonvolatile memory chip 41A-1 in the order of input.

[0102] Next, page data is input to the second nonvolatile memory chip 41A-2 in the order of (24) to (35). The specific page data input in the order of (24) to (35) is the same as the page data input in the order of (0) to (11), and the object of the data input operation is replaced from the 0th nonvolatile memory chip 41A-0 to the second nonvolatile memory chip 41A-2.

[0103] The 12 pages of data input in the order of (24) to (35) are written into the second nonvolatile memory chip 41A-2 in one FSP operation. The 12 pages of data are programmed into the plane blocks PB0, PB1, PB2, and PB3 of the second nonvolatile memory chip 41A-2 in the order of input.

[0104] Then, page data is input to the third nonvolatile memory chip 41A-3 in the order of (36) to (47). The specific page data input in the order of (36) to (47) is the same as the page data input in the order of (0) to (11), and the object of the data input operation is replaced from the 0th nonvolatile memory chip 41A-0 to the third nonvolatile memory chip 41A-3.

[0105] The 12 pages of data input in the order of (36) to (47) are written to the third nonvolatile memory chip 41A-3 in one FSP operation. The 12 pages of data are programmed to the plane blocks PB0, PB1, PB2, and PB3 of the third nonvolatile memory chip 41A-3 in the order of input.

[0106] After the data input operation is performed on the four nonvolatile memory chips 41A-0, 41A-1, 41A-2, and 41A-3 in the order of (0) to (47), the writing order is advanced in the string direction (that is, in the direction of increasing the string number). In the following, similarly, the FSP operation can be performed on the nonvolatile memory chips 41A-0, 41A-1, 41A-2, and 41A-3 in order according to the increasing string number.

[0107] In the write process corresponding to the write request from the host, the data received from the host is sequentially programmed into the non-volatile memory chips 41A-0, 41A-1, 41A-2, and 41A-3. In order to perform the FSP action for each of the non-volatile memory chips 41A-0, 41A-1, 41A-2, and 41A-3, it is necessary to input 12 pages of data (= 3 pages × 4PB of data) to one non-volatile memory chip. In other words, if 12 pages of data are not input, the FSP action for one non-volatile memory chip cannot be performed. Therefore, the controller of the memory system of the comparative example starts to input (transmit) the accumulated 12 pages of data to the non-volatile memory chip after accumulating 12 pages of data in the write buffer, for example.

[0108] Figure 7 In the memory system 3A of the comparative example, Figure 6 In the case of the writing sequence shown, the writing operation is performed on the nonvolatile memory chips 41A-0, 41A-1, 41A-2, and 41A-3. The memory system 3A performs the writing operation in response to a writing request from the host 2A.

[0109] The memory system 3A includes a memory device 4A and a controller 6A. The memory device 4A includes nonvolatile memory chips 41A-0, 41A-1, 41A-2, and 41A-3. Each of the nonvolatile memory chips 41A-0, 41A-1, 41A-2, and 41A-3 includes four planes. Figure 7 In the 0th nonvolatile memory chip 41A-0, four plane blocks PB0, PB1, PB2, and PB3 included in four planes are allocated as blocks to be written in the TLC method.

[0110] The controller 6A includes a write control unit 151A for controlling a write operation and a write buffer 141A. The write control unit 151A stores user data transmitted from the host 2A in response to a write request from the host 2A in the write buffer 141A ( Figure 7 (1) in the figure.

[0111] The write control unit 151A stores the user data 61A required for one FSP operation for the four plane blocks PB0, PB1, PB2, and PB3 in the write buffer 141A, and performs a data input operation of inputting the user data 61A from the write buffer 141A to the 0th nonvolatile memory chip 41A-0 ( Figure 7 (2) in FIG. 1 ). The user data 61A required for one FSP operation on the four plane blocks PB0, PB1, PB2, and PB3 is 12 pages of user data.

[0112] Furthermore, the write control unit 151A performs a program operation to program the user data 61A into the four plane blocks PB0, PB1, PB2, and PB3 ( Figure 7 (3) in FIG. 1 ). Thus, one FSP operation is completed for the 0th nonvolatile memory chip 41A-0 (more specifically, the four plane blocks PB0, PB1, PB2, and PB3 in the 0th nonvolatile memory chip 41A-0).

[0113] When the data input operation of inputting the user data 61A from the write buffer 141A to the 0th nonvolatile memory chip 41A-0 is completed, the storage area of ​​the write buffer 141A storing the user data 61A is released. And, for example, the user data required for the FSP operation for the next 1st nonvolatile memory chip 41A-1 (that is, the user data of the other 12 pages) is stored again in the write buffer 141A. As in the case of the 0th nonvolatile memory chip 41A-0, the write control unit 151A performs the data input operation and programming operation for the 1st nonvolatile memory chip 41A-1. In addition, the write control unit 151A similarly performs the data input operation and programming operation for each of the 2nd nonvolatile memory chip 41A-2 and the 3rd nonvolatile memory chip 41A-3.

[0114] In this way, according to Figure 6 In the case of the write order shown in FIG. 1 , the size of the storage area allocated as the write buffer 141A can be the size of the data required for one FSP operation of one nonvolatile memory chip 41A (here, the size of 12 pages). Figure 6 The write order shown is optimized in a manner that reduces the size of the write buffer 141A.

[0115] On the other hand, after reading out the nonvolatile memory chips 41A-0, 41A-1, 41A-2, and 41A-3, Figure 6 When user data is written in the write order shown and transmitted to the host 2A, the size of the read buffer in the controller 6A that temporarily stores the read user data tends to become larger.

[0116] Figure 8 In the memory system 3A of the comparative example, the nonvolatile memory chips 41A-0, 41A-1, 41A-2, and 41A-3 are read out in accordance with Figure 6 The memory system 3A performs a read operation in response to a read request from the host 2A.

[0117] The controller 6A and the four nonvolatile memory chips 41A-0, 41A-1, 41A-2, and 41A-3 are connected by four-channel data buses ch0, ch1, ch2, and ch3, respectively. The four nonvolatile memory chips 41A-0, 41A-1, 41A-2, and 41A-3 can output data to the controller 6A in parallel via the corresponding channel data buses ch0, ch1, ch2, and ch3.

[0118] The controller 6A includes a read control unit 152A for controlling the read operation and four read buffers 142A. The four read buffers 142 are a 0th read buffer 142A-0, a 1st read buffer 142A-1, a 2nd read buffer 142A-2, and a 3rd read buffer 142A-3. The four read buffers 142A-0, 142A-1, 142A-2, and 142A-3 correspond to the four nonvolatile memory chips 41A-0, 41A-1, 41A-2, and 41A-3, respectively.

[0119] The read control unit 152A reads user data from the four nonvolatile memory chips 41A-0, 41A-1, 41A-2, and 41A-3 in parallel in response to a read request received from the host 2A, and stores the read user data in the read buffers 142A-0, 142A-1, 142A-2, and 142A-3 ( Figure 8 . Specifically, the read control unit 152A stores the user data 62A-0 read from the 0th nonvolatile memory chip 41A-0 in the 0th read buffer 142A-0. The read control unit 152A stores the user data 62A-1 read from the 1st nonvolatile memory chip 41A-1 in the 1st read buffer 142A-1. The read control unit 152A stores the user data 62A-2 read from the 2nd nonvolatile memory chip 41A-2 in the 2nd read buffer 142A-2. The read control unit 152A stores the user data 62A-3 read from the 3rd nonvolatile memory chip 41A-3 in the 3rd read buffer 142A-3.

[0120] Then, the reading control unit 152A presses Figure 6The writing order shown is to transmit user data 62A-0, 62A-1, 62A-2, and 62A-3 to the host 2A ( Figure 8 That is, the reading control unit 152A reads the Figure 6 The write order shown controls the order in which the user data 62A-0, 62A-1, 62A-2, and 62A-3 stored in the read buffers 142A-0, 142A-1, 142A-2, and 142A-3 are transferred to the host 2A.

[0121] For example, in Figure 6 In the writing order shown, the focus is on the 0th nonvolatile memory chip 41A-0. After the 12 pages of user data (0) to (11) are input to the 0th nonvolatile memory chip 41A-0, the 12 pages of user data (48) to (59) are input.

[0122] Moreover, between the 12 pages of user data input from (0) to (11) and the 12 pages of user data input from (48) to (59), 36 pages of user data from (12) to (47) are input to the first non-volatile memory chip 41A-1, the second non-volatile memory chip 41A-2, and the third non-volatile memory chip 41A-3.

[0123] Therefore, in the read operation, after 12 pages of user data from (0) to (11) are transferred to the host 2A, user data from (48) to (59) are not transferred to the host 2A until 36 pages of user data from (12) to (47) from the first non-volatile memory chip 41A-1, the second non-volatile memory chip 41A-2, and the third non-volatile memory chip 41A-3 are transferred to the host 2A.

[0124] In this way, after reading out the nonvolatile memory chips 41A-0, 41A-1, 41A-2, and 41A-3, Figure 6 In the case where user data written in the write order shown in FIG. 1 is read and transmitted to the host 2A, the amount of user data waiting to be transmitted in the read buffers 142A-0, 142A-1, 142A-2, and 142A-3 increases in order to transmit to the host 2A in the write order. Therefore, the size of the storage area allocated as the read buffers 142A-0, 142A-1, 142A-2, and 142A-3 increases. Figure 6 In the writing order shown, although the size of the write buffer 141A can be reduced, the sizes of the read buffers 142A-0, 142A-1, 142A-2, and 142A-3 may increase.

[0125] In this regard, a description will be given of an optimized write order for reducing the sizes of the read buffers 142A-0, 142A-1, 142A-2, and 142A-3.

[0126] Fig. 9 Another example of the writing order in the plurality of nonvolatile memory chips included in the memory system of the comparative example is shown. Figure 6 Similarly, it is assumed that the memory system 3A of the comparative example includes four nonvolatile memory chips 41A-0, 41A-1, 41A-2, and 41A-3, and the TLC method and the FSP operation of multi-plane programming are performed on the four nonvolatile memory chips 41A-0, 41A-1, 41A-2, and 41A-3 each including four planes. In each of the nonvolatile memory chips 41A-0, 41A-1, 41A-2, and 41A-3, the four blocks of writing objects included in the four planes are called plane blocks PB0, PB1, PB2, and PB3.

[0127] like Fig. 9 As shown, in the FSP action corresponding to the string number "0", first, the page data is input to the 0th non-volatile memory chip 41A-0 in the following order (0) to (3). (0) Lower-order page data for plane block PB0 (1) Lower-order page data for plane block PB1 (2) Lower-order page data for plane block PB2 (3) Lower-order page data for plane block PB3. In addition, the numbers and Fig. 9 In the corresponding combination of string number and non-volatile memory chip (here, the combination of string number "0" and the 0th non-volatile memory chip 41A-0), the value in the box specified by any one of the lower-level page, middle-level page, and upper-level page, and any one of the plane blocks PB0, PB1, PB2, and PB3 corresponds.

[0128] After the lower-order page data is input to the 0th nonvolatile memory chip 41A-0 in the order of (0) to (3), the writing order of the data proceeds in the chip direction rather than the page direction.

[0129] Therefore, next, the lower-order page data is input to the first nonvolatile memory chip 41A-1 in the order of (4) to (7). The specific page data input in the order of (4) to (7) is the same as the page data input in the order of (0) to (3), and the object of the data input operation is replaced from the 0th nonvolatile memory chip 41A-0 to the first nonvolatile memory chip 41A-1.

[0130] Next, the next-order page data is input to the second nonvolatile memory chip 41A-2 in the order of (8) to (11). The specific page data input in the order of (8) to (11) is the same as the page data input in the order of (0) to (3), and the object of the data input operation is replaced from the 0th nonvolatile memory chip 41A-0 to the second nonvolatile memory chip 41A-2.

[0131] Then, the next-order page data is input to the third nonvolatile memory chip 41A-3 in the order of (12) to (15). The specific page data input in the order of (12) to (15) is the same as the page data input in the order of (0) to (3), and the object of the data input operation is replaced from the 0th nonvolatile memory chip 41A-0 to the third nonvolatile memory chip 41A-3.

[0132] After inputting the lower-order page data for the 0th nonvolatile memory chip 41A-0, the 1st nonvolatile memory chip 41A-1, the 2nd nonvolatile memory chip 41A-2, and the 3rd nonvolatile memory chip 41A-3 in the order of (0) to (15), the writing order proceeds along the page direction.

[0133] Therefore, the middle-order page data is input to the 0th nonvolatile memory chip 41A-0, the 1st nonvolatile memory chip 41A-1, the 2nd nonvolatile memory chip 41A-2, and the 3rd nonvolatile memory chip 41A-3 in the order of (16) to (31). Then, the upper-order page data is input to the 0th nonvolatile memory chip 41A-0, the 1st nonvolatile memory chip 41A-1, the 2nd nonvolatile memory chip 41A-2, and the 3rd nonvolatile memory chip 41A-3 in the order of (32) to (47).

[0134] The 12 pages of data input in the order of (0) to (3), (16) to (19), and (32) to (35) are written to the 0th nonvolatile memory chip 41A-0 in one FSP operation. The 12 pages of data are programmed to the plane blocks PB0, PB1, PB2, and PB3 of the 0th nonvolatile memory chip 41A-0 in the order of input.

[0135] Similarly, the 12 pages of data input in the order of (4) to (7), (20) to (23), and (36) to (39) are written to the first nonvolatile memory chip 41A-1 by one FSP operation. The 12 pages of data are programmed to the plane blocks PB0, PB1, PB2, and PB3 of the first nonvolatile memory chip 41A-1 in the order of input.

[0136] Similarly, 12 pages of data are programmed into each of the second nonvolatile memory chip 41A-2 and the third nonvolatile memory chip 41A-3.

[0137] After data is input to the four nonvolatile memory chips 41A-0, 41A-1, 41A-2, and 41A-3 in the order of (0) to (47), the writing order is advanced in the string direction. Afterwards, similarly, FSP actions corresponding to increasing string numbers can be performed in sequence.

[0138] As reference Figure 8 As described above, when the controller 6A receives a read request from the host 2A, it stores the user data 62A-0, 62A-1, 62A-2, and 62A-3 read from the nonvolatile memory chips 41A-0, 41A-1, 41A-2, and 41A-3 in the read buffers 142A-0, 142A-1, 142A-2, and 142A-3. Furthermore, the controller 6A performs control so that the user data 62A-0, 62A-1, 62A-2, and 62A-3 stored in the read buffers 142A-0, 142A-1, 142A-2, and 142A-3 are transferred to the host 2A in the order in which they are written.

[0139] Here, in Fig. 9 The writing sequence shown focuses on the 0th nonvolatile memory chip 41A-0. After 4 pages of user data are input in the order of (0) to (3), 4 pages of user data are input in the order of (16) to (19) in the 0th nonvolatile memory chip 41A-0.

[0140] Moreover, between the 4 pages of user data input from (0) to (3) and the 4 pages of user data input from (16) to (19), 12 pages of user data from (4) to (15) are input to the first non-volatile memory chip 41A-1, the second non-volatile memory chip 41A-2, and the third non-volatile memory chip 41A-3.

[0141] Therefore, in the read operation, 4 pages of user data from (0) to (3) are transferred to the host 2A, 12 pages of user data from (4) to (15) are transferred from the first non-volatile memory chip 41A-1, the second non-volatile memory chip 41A-2, and the third non-volatile memory chip 41A-3 to the host 2A, and then 4 pages of user data from (16) to (19) are transferred to the host 2A.

[0142] In this regard, using Figure 6In the read operation in the write order shown, as described above, after the user data from (0) to (11) are transferred to the host 2A, 12 pages of user data from (48) to (59) are stored in the read buffer 142A-0 until 36 pages of user data from (12) to (47) from the first non-volatile memory chip 41A-1, the second non-volatile memory chip 41A-2, and the third non-volatile memory chip 41A-3 are transferred to the host 2A.

[0143] Therefore, when reading out the nonvolatile memory chips 41A-0, 41A-1, 41A-2, and 41A-3, Fig. 9 The user data is written in the order shown and transmitted to the host 2A, with the use of Figure 6 Compared to the case of the writing order shown, the amount of user data waiting to be transferred in the read buffers 142A-0, 142A-1, 142A-2, and 142A-3 after reading is reduced. Therefore, the size of the storage area allocated as the read buffers 142A-0, 142A-1, 142A-2, and 142A-3 becomes smaller.

[0144] On the other hand, when using Fig. 9 In the case of the writing order shown, the controller 6A, for example, starts to input the accumulated 36 pages of data to the non-volatile memory chip 41A after accumulating 36 pages of data corresponding to (0) to (35) in the write buffer 141A in order to perform one FSP action on the 0th non-volatile memory chip 41A-0.

[0145] In this regard, using Figure 6 In the case of the writing order shown, the size of the storage area allocated as the write buffer 141A may be the size of data required for the FSP operation of one nonvolatile memory chip 41A (for example, 12 pages).

[0146] Therefore, in Fig. 9 When writing user data to the nonvolatile memory chips 41A-0, 41A-1, 41A-2, and 41A-3 in the writing order shown in FIG. Figure 6 Compared with the case of the writing order shown, the size of the storage area allocated as the write buffer 141A becomes larger.

[0147] Thus, in the memory system 3A of the comparative example, when using Figure 6 In the case of the write order shown in FIG. 1 , the size of the write buffer 141A can be reduced, but the size of the read buffer 142A cannot be reduced. Fig. 9In the case of the writing order shown, the size of the read buffer 142A can be reduced, but the size of the write buffer 141A cannot be reduced. Therefore, in the memory system 3A of the comparative example, the sizes of both the write buffer 141A and the read buffer 142A cannot be reduced.

[0148] In view of this, in the memory system 3 of the first embodiment, two write operations are performed to reduce the size of the write buffer 141 and the size of the read buffer 142. Specifically, the controller 6 performs a plurality of data input operations to transfer user data of a second size smaller than the user data of the first size written in one write operation to the nonvolatile memory chip 41 from the write buffer 141 to the nonvolatile memory chip 41 (more specifically, the latch 32). Furthermore, the controller 6 writes the plurality of user data of the second size transferred to the nonvolatile memory chip 41 by the plurality of data input operations respectively into the memory cell array 33. The total size of the plurality of user data of the second size is, for example, equal to the first size.

[0149] In this way, in the memory system 3, the data transfer operation of transferring the user data of the second size from the write buffer 141 to the non-volatile memory chip 41 is performed multiple times. Therefore, in the memory system 3, not only the write buffer 141 but also the non-volatile memory chip 41 (more specifically, the latch 32) is used as a storage area for buffering the user data of the second size. Therefore, in the memory system 3, for example, the size of the write buffer 141 can be reduced compared to the memory system 3A of the comparative example, and the memory system 3A starts the data input operation to the non-volatile memory chip 41A after accumulating the user data of the first size in the write buffer 141A. In addition, in the memory system 3, by using Fig. 9 The writing order shown can also reduce the size of the read buffer 142. Therefore, in the memory system 3, the size of the data buffer (eg, the write buffer 141 and the read buffer 142) used when the host 2 accesses the nonvolatile memory chip 41 can be reduced.

[0150] The writing operation in the memory system 3 according to the first embodiment will be described in detail.

[0151] Fig.10 41 shows an example of a write operation to the nonvolatile memory chip 41. Fig. 9The write order shown in FIG. 1 is an interleaved write operation for four nonvolatile memory chips 41-0, 41-1, 41-2, and 41-3. That is, it is assumed that the TLC method and the FSP operation of multi-plane programming are performed for four nonvolatile memory chips 41A-0, 41A-1, 41A-2, and 41A-3 each including four planes 45. The memory system 3 performs a write operation in response to a write request from the host 2. The write operation is controlled by, for example, the CPU 15 functioning as a write control unit 151.

[0152] exist Fig.10 In the example shown, in the 0th nonvolatile memory chip 41A-0, four plane blocks PB0, PB1, PB2, and PB3 included in four planes 45-0, 45-1, 45-2, and 45-3 are allocated as blocks to be written in the TLC method. The operation of writing user data to the four plane blocks PB0, PB1, PB2, and PB3 in the 0th nonvolatile memory chip 41A-0 will be described.

[0153] The write control unit 151 stores the user data transmitted from the host 2 in response to the write request received from the host 2 in the write buffer 141 ( Fig.10 (1) in the figure.

[0154] The write control unit 151 performs the following operation (data input operation): transfers user data of a second size smaller than the user data of the first size written in one FSP operation to the 0th nonvolatile memory chip 41-0 from the write buffer 141 to the data input latch (DL) 321 of the 0th nonvolatile memory chip 41-0 ( Fig.10 (2) in the above). The user data of the first size is, for example, 12 pages of data. The user data of the second size is, for example, 1 page of user data 61. In addition, the second size is, for example, smaller than the size of the user data received from the host 2 in response to the write request from the host 2. The write control unit 151 performs a data input operation, for example, each time the user data of the second size is accumulated in the write buffer 141. The user data stored in the write buffer 141 is data that has not yet been written to the non-volatile memory chip 41 (more specifically, the memory cell array 33). The write control unit 151 releases the storage area in the write buffer 141 storing the user data of the second size, based on the fact that the user data of the second size has been transferred to the data input latch 321. The released storage area can be used to store new user data.

[0155] When one page of user data 61 is stored in the data input latch 321 in all the planes 45-0, 45-1, 45-2, and 45-3 by the data input operation, the write control unit 151 performs an operation (data movement operation) of moving the user data 61 stored in the data input latch 321 to the 0th programming latch (0th PL) 322-0 in each of the planes 45-0, 45-1, 45-2, and 45-3. Fig.10 (3) in FIG. 1 ). The data stored in the 0th programming latch 322-0 is, for example, data programmed into the plane blocks PB0, PB1, PB2, and PB3 as lower-level page data.

[0156] The operation of the 0th program latch 322-0 for storing data programmed as lower level page data in the plane blocks PB0, PB1, PB2, and PB3 in each of the planes 45-0, 45-1, 45-2, and 45-3 will be described in more detail.

[0157] First, for example, the write control unit 151 transfers one page of user data 61 from the write buffer 141 to the data input latch 321 of the 0th plane 45-0, based on the accumulation of one page of user data 61 in the write buffer 141. The write control unit 151 releases the storage area in the write buffer 141 storing the transferred one page of user data 61. The released storage area can be used to store new user data.

[0158] Next, the write control unit 151 transfers one page of user data 61 from the write buffer 141 to the data input latch 321 of the first plane 45-1, based on the fact that one page of user data 61 is newly accumulated in the write buffer 141. The write control unit 151 releases the storage area in the write buffer 141 storing the transferred one page of user data 61.

[0159] Similarly, the write control unit 151 transfers one page of user data 61 from the write buffer 141 to the data input latch 321 of the second plane 45-2. Then, the write control unit 151 transfers one page of user data 61 from the write buffer 141 to the data input latch 321 of the third plane 45-3.

[0160] The write control unit 151 moves the user data 61 stored in the data input latch 321 to the 0th programming latch 322-0 in each of the planes 45-0, 45-1, 45-2, and 45-3, based on the fact that one page of user data 61 is stored in the data input latch 321 in all the planes 45-0, 45-1, 45-2, and 45-3. Thus, the data programmed into each of the plane blocks PB0, PB1, PB2, and PB3 as the lower-order page data is stored in the 0th programming latch 322-0 in each of the planes 45-0, 45-1, 45-2, and 45-3.

[0161] Next, the write control unit 151 performs an operation for storing the data programmed as the middle-order page data in the plane blocks PB0, PB1, PB2, and PB3 in the first programming latch (first PL) 322-1 of each of the planes 45-0, 45-1, 45-2, and 45-3. The specific operation is equivalent to replacing the 0th programming latch 322-0 with the first programming latch 322-1 in the data input operation and data shift operation for storing the lower-order page data in the 0th programming latch 322-0.

[0162] Then, the write control unit 151 performs an operation for storing the data programmed as the middle-order page data in the plane blocks PB0, PB1, PB2, and PB3 in the second programming latch (second PL) 322-2 of each of the planes 45-0, 45-1, 45-2, and 45-3. The specific operation is equivalent to replacing the 0th programming latch 322-0 with the second programming latch 322-2 in the data input operation and data shift operation for storing the lower-order page data in the 0th programming latch 322-0.

[0163] Thus, in all the planes 45-0, 45-1, 45-2, and 45-3, the lower-order page data is stored in the 0th programming latch 322-0, the middle-order page data is stored in the 1st programming latch 322-1, and the upper-order page data is stored in the 2nd programming latch 322-2. That is, by performing the data input operation of inputting one page of data (that is, the second-size user data) to the 0th nonvolatile memory chip 41-0 12 times, the state of inputting 12 pages of data (that is, the first-size data) required for one FSP operation for the 0th nonvolatile memory chip 41-0 is achieved.

[0164] Furthermore, the write control unit 151 programs the data stored in the programming latches 322-0, 322-1, and 322-2 into the corresponding plane blocks PB0, PB1, PB2, or PB3 in each of the planes 45-0, 45-1, 45-2, and 45-3 ( Fig.10 (4) in the above). That is, the write control unit 151 performs the FSP action on the 0th non-volatile memory chip 41-0. Specifically, the write control unit 151 programs the lower-order page data stored in the 0th programming latch 322-0, the middle-order page data stored in the 1st programming latch 322-1, and the upper-order page data stored in the 2nd programming latch 322-2 to the 0th plane block PB0 in the 0th plane 45-0. Similarly, the write control unit 151 programs the lower-order page data, the middle-order page data, and the upper-order page data to the corresponding plane block PB1, PB2, or PB3 for each of the 1st plane 45-1, the 2nd plane 45-2, and the 3rd plane 45-3.

[0165] Through the above-mentioned writing operation, the writing control unit 151 can perform the TLC method and the FSP operation of the multi-plane programming on the 0th nonvolatile memory chip 41-0. Fig. 9 In the writing order shown, the first nonvolatile memory chip 41-1, the second nonvolatile memory chip 41-2, and the third nonvolatile memory chip 41-3 also perform the TLC method and the FSP operation of the multi-plane programming. Thus, the writing control unit 151 can perform the interleaved writing operation on the four nonvolatile memory chips 41-0, 41-1, 41-2, and 41-3.

[0166] In the above-described write operation, the write control unit 151 transfers user data of a second size smaller than the user data of the first size written in one FSP operation to the nonvolatile memory chip 41 from the write buffer 141 to the data input latch 321. For example, the write control unit 151 sequentially transfers the user data of the second size accumulated in the write buffer 141 to the data input latch 321. Then, the write control unit 151 releases the storage area in the write buffer 141 storing the user data of the second size transferred to the data input latch 321. The released storage area can be used to store new user data.

[0167] Therefore, in the memory system 3 of the first embodiment, for example, compared with the memory system 3A of the comparative example, the size of the write buffer 141 can be reduced, and after the memory system 3A accumulates the first size data (for example, 12 pages of data) programmed into the non-volatile memory chip 41A by one FSP action in the write buffer 141A, the memory system 3A inputs the data into the non-volatile memory chip 41A.

[0168] In addition, regarding the read operation in the memory system 3, the data read from the nonvolatile memory chip 41 and stored in the read buffer 142 according to the read request of the host 2 is processed in accordance with the Fig. 9 The write order shown is not Figure 6 The write sequence shown is transmitted to the host 2, and Figure 8 The read operation in the memory system 3A of the comparative example shown is the same. Specifically, the read control unit 152 reads user data from, for example, four nonvolatile memory chips 41-0, 41-1, 41-2, and 41-3 in parallel in response to a read request from the host 2, and stores the read user data in the read buffer 142. Then, the read control unit 152 executes Fig. 9 The read control unit 152 transmits the user data stored in the read buffer 142 to the host 2 in the order shown in the write order. Fig. 9 Thus, as shown in the reference Fig. 9 As described above, the size of the read buffer 142 can be reduced.

[0169] Fig.11 An example of an instruction sequence for a nonvolatile memory chip 41 is shown. The instruction sequence corresponds to one FSP action for one nonvolatile memory chip 41. Here, it is assumed that the nonvolatile memory chip 41 is subjected to an FSP action of TLC method and multi-plane programming. The instruction sequence is output to the nonvolatile memory chip 41 by the memory I / F 12 under the control of the write control unit 151, for example. The nonvolatile memory chip 41 includes T planes 45. T plane blocks PBx, ..., PBy contained in each of the T planes 45 are allocated as blocks of write objects in the TLC method. The plane 45 containing the plane block PBx is called the plane 45-x. The plane 45 containing the plane block PBy is called the plane 45-y.

[0170] Fig.11The instruction sequence shown includes a sequence from the beginning to time A, a sequence from time A to time B, and a sequence from time B to termination. The sequence from the beginning to time A is a sequence for inputting lower-order page data. The sequence from time A to time B is a sequence for inputting middle-order page data. The sequence from time B to termination is a sequence for inputting upper-order page data and programming the input lower-order page data, middle-order page data, and upper-order page data into a plane block. Instructions to the nonvolatile memory chip 41 are performed in units of, for example, a group of a first instruction, an address, data, and a second instruction. Below, the sequence from the beginning to time A, the sequence from time A to time B, and the sequence from time B to termination are described in sequence.

[0171] (Sequence from the beginning to time A: input next page data)

[0172] First, the memory I / F 12 outputs the first instruction 701, the address 702, the lower-level page data 703, and the second instruction 704 to the plane 45-x of the non-volatile memory chip 41. The first instruction 701 is instruction "80h" or "85h". Instructions "80h" and "85h" are instructions for starting data input. Address 702 specifies the plane block PBx into which the lower-level page data 703 is written. The lower-level page data 703 is user data for the lower-level page that should be written to the plane block PBx. The second instruction 704 is instruction "11h". Instruction "11h" is an instruction to directly retain the input data in the latch 32 (here, the latch 321 for data input). In addition, as an example of the value defined by each instruction, a value defined by a specification or style is used. The lower-order page data 703 transferred from the write buffer 141 is stored (input) in the data input latch 321 of the plane 45 - x by the first command 701 , the address 702 , the lower-order page data 703 , and the second command 704 .

[0173] The memory I / F 12 similarly executes a sequence for storing the lower-order page data transferred from the write buffer 141 in the data input latch 321 in the corresponding plane 45 for each of the remaining planes 45 excluding the plane 45 - x and the plane 45 - y from the T planes 45 .

[0174] Then, the memory I / F12 outputs the first instruction 705, the address 706, the lower-level page data 707, and the second instruction 708 to the plane 45-y of the non-volatile memory chip 41. The first instruction 705 is an instruction "80h" or "85h". The address 706 specifies the plane block PBy into which the lower-level page data 707 is written. The lower-level page data 707 is user data for the lower-level page that should be written to the plane block PBy. The second instruction 708 is an instruction "1Ah". The instruction "1Ah" is an instruction to move the data input latch 321 input to T planes 45 to the programming latch 322 to prepare for the data input of the next page.

[0175] The lower-order page data 707 transmitted from the write buffer 141 is stored in the data input latch 321 of the plane 45-y by the first instruction 705, the address 706, the lower-order page data 707, and the second instruction 708. In addition, in each of the T planes 45, the lower-order page data stored in the data input latch 321 is moved to the 0th programming latch 322-0. Specifically, the lower-order page data 703 stored in the data input latch 321 of the plane 45-x is moved to the 0th programming latch 322-0 of the plane 45-x. In addition, the lower-order page data 707 stored in the data input latch 321 of the plane 45-y is moved to the 0th programming latch 322-0 of the plane 45-y. Therefore, through the sequence from the beginning to the time A, in all the T planes 45, the lower-order page data is stored in the 0th programming latch 322-0.

[0176] (Sequence from time A to time B: Input of intermediate page data)

[0177] Next, the memory I / F 12 outputs the first instruction 709, the address 710, the intermediate page data 711, and the second instruction 712 to the plane 45-x of the non-volatile memory chip 41. The first instruction 709 is an instruction "80h" or "85h". The address 710 specifies the plane block PBx where the intermediate page data 711 is written. The intermediate page data 711 is user data for the intermediate page that should be written to the plane block PBx. The second instruction 712 is an instruction "11h". Through the first instruction 709, the address 710, the intermediate page data 711, and the second instruction 712, the intermediate page data 711 transmitted from the write buffer 141 is stored in the data input latch 321 of the plane 45-x.

[0178] The memory I / F 12 similarly executes a sequence for transferring the middle-order page data to the data input latch 321 in the corresponding plane 45 for each of the remaining planes 45 excluding the plane 45 - x and the plane 45 - y from the T planes 45 .

[0179] Furthermore, the memory I / F 12 outputs the first instruction 713, the address 714, the middle-order page data 715, and the second instruction 716 to the plane 45-y of the nonvolatile memory chip 41. The first instruction 713 is an instruction "80h" or "85h". The address 714 specifies the plane block PBy where the middle-order page data 715 is written. The middle-order page data 715 is user data for the middle-order page to be written to the plane block PBy. The second instruction 716 is an instruction "1Ah".

[0180] The intermediate-order page data 715 transmitted from the write buffer 141 is stored in the data input latch 321 of the plane 45-y by the first instruction 713, the address 714, the intermediate-order page data 715, and the second instruction 716. In addition, in each of the T planes 45, the intermediate-order page data stored in the data input latch 321 is moved to the first programming latch 322-1. Specifically, the intermediate-order page data 711 stored in the data input latch 321 of the plane 45-x is moved to the first programming latch 322-1 of the plane 45-x. In addition, the intermediate-order page data 715 stored in the data input latch 321 of the plane 45-y is moved to the first programming latch 322-1 of the plane 45-y. Therefore, through the sequence from time A to time B, in all the T planes 45, the intermediate-order page data is stored in the first programming latch 322-1.

[0181] (Sequence from time B to termination: input and programming of upper-level page data)

[0182] Next, the memory I / F 12 outputs the first instruction 717, the address 718, the upper-level page data 719, and the second instruction 720 to the plane 45-x of the non-volatile memory chip 41. The first instruction 717 is an instruction "80h" or "85h". The address 718 specifies the plane block PBx into which the upper-level page data 719 is written. The upper-level page data 719 is user data for the upper-level page that should be written to the plane block PBx. The second instruction 720 is an instruction "11h". Through the first instruction 717, the address 718, the upper-level page data 719, and the second instruction 720, the upper-level page data 719 transmitted from the write buffer 141 is stored in the data input latch 321 of the plane 45-x.

[0183] The memory I / F 12 similarly executes a sequence for transferring the upper-order page data to the data input latch 321 in the corresponding plane 45 for the remaining planes 45 excluding the plane 45 - x and the plane 45 - y from the T planes 45 .

[0184] Then, the memory I / F 12 outputs the first instruction 721, the address 722, the upper page data 723, and the second instruction 724 to the plane 45-y of the non-volatile memory chip 41. The first instruction 721 is an instruction "80h" or "85h". The address 722 specifies the plane block PBy where the upper page data 723 is written. The upper page data 723 is user data for the upper page of the plane block PBy that should be written. The second instruction 724 is an instruction "10h" or "15h". The instruction "10h" or "15h" is an instruction to start a program based on the specified content.

[0185] Through the first instruction 721, address 722, upper-level page data 723, and second instruction 724, the upper-level page data 723 transmitted from the write buffer 141 is stored in the data input latch 321 of plane 45-y. In each of the T planes 45, the upper-level page data stored in the data input latch 321 is moved to the second programming latch 322-2, and the lower-level page data, middle-level page data, and upper-level page data stored in the programming latches 322-0, 322-1, and 322-3, respectively, are programmed into the plane block.

[0186] Specifically, the upper-level page data 719 stored in the data input latch 321 of the plane 45-x is moved to the second programming latch 322-2 of the plane 45-x. Furthermore, in the plane 45-x, the lower-level page data 703 stored in the 0th programming latch 322-0, the middle-level page data 711 stored in the first programming latch 322-1, and the upper-level page data 719 stored in the second programming latch 322-2 are programmed to the plane block PBx.

[0187] In addition, the upper-level page data 723 stored in the data input latch 321 of the plane 45-y is moved to the second programming latch 322-2 of the plane 45-y. Then, in the plane 45-y, the lower-level page data 707 stored in the 0th programming latch 322-0, the middle-level page data 715 stored in the first programming latch 322-1, and the upper-level page data 723 stored in the second programming latch 322-2 are programmed to the plane block PBy.

[0188] Through the above command sequence, the memory I / F 12 can perform a TLC method and a single FSP operation of multi-plane programming on the nonvolatile memory chip 41 including T planes 45. In the command sequence, for example, each time one page of user data is accumulated in the write buffer 141, the one page of user data is transferred from the write buffer 141 to the data input latch 321 of the nonvolatile memory chip 41. As the user data is transferred to the data input latch 321, the storage area in the write buffer 141 storing the user data is released. In addition, the user data stored in the data input latch 321 is moved to the programming latch 322. Therefore, in the memory system 3, as a buffer for user data to be written to the nonvolatile memory chip 41, not only the write buffer 141 but also the data input latch 321 and the programming latch 322 are used. Therefore, in the memory system 3, for example, the size of the write buffer 141 can be reduced compared to the memory system 3A of the comparative example, and after the memory system 3A accumulates all pages of user data (here, T×3 pages of user data) programmed into the non-volatile memory chip 41A by one FSP action in the write buffer 141A, the memory system 3A inputs the user data into the non-volatile memory chip 41A.

[0189] In addition, when performing an interleaved write operation on a plurality of nonvolatile memory chips 41, the memory I / F 12 performs, for example, interleaved write operation on each of the plurality of nonvolatile memory chips 41 in parallel. Fig.11 The types of instructions, the number of latches 32, and other configurations described above are examples, and the write operation in the memory system 3 of the first embodiment can be applied to any configuration that writes a fixed amount of data to one or more blocks at a time.

[0190] Fig. 12A and Fig. 12B 1 is a flowchart showing an example of the sequence of write control processing performed by CPU 15. Write control processing is a process for writing user data to memory device 4. CPU 15 performs write control processing, for example, based on receiving a write instruction from host 2. Here, a case where user data is written to S non-volatile memory chips 41 in parallel is illustrated. Each of the S non-volatile memory chips 41 includes T planes 45. S is an integer greater than 1. T is an integer greater than 1. In addition, in the write control processing, data is written to a block (plane block) in a first manner. The first manner is a manner of writing M pages of data in one programming action (that is, writing M bits of data to each storage cell). In the following, M is an integer greater than 2.

[0191] First, CPU15 sets each of variables i, j, and k to 0 (step S101). Variable i is used to specify one of the S non-volatile memory chips 41. Variable j is used to specify one of the T planes 45. Variable k is used to specify one page of data within the M pages of data written to one plane block in one programming action. For example, in the case where 3 pages of data are written to one plane block in one programming action (that is, the first method is the TLC method), variable k specifies any one of the lower-level page, the middle-level page, and the upper-level page. Specifically, for example, 0, that is, variable k represents the lower-level page, 1, that is, variable k represents the middle-level page, and 2, that is, variable k represents the upper-level page.

[0192] Next, the CPU 15 determines whether one page of user data is stored in the write buffer 141 (step S102 ).

[0193] If one page of user data is not stored in the write buffer 141 (No in step S102 ), the CPU 15 returns to step S102 . That is, the CPU 15 waits until one page of user data is stored in the write buffer 141 .

[0194] When one page of user data is stored in the write buffer 141 (Yes in step S102), the CPU 15 transfers one page of user data from the write buffer 141 to the data input latch 321 of the j-th plane 45 in the i-th nonvolatile memory chip 41 (step S103). The CPU 15 releases the storage area in the write buffer 141 storing the transferred user data (step S104). The CPU 15 updates the variable j by adding 1 to the variable j (step S105). Then, the CPU 15 determines whether the updated variable j is equal to the number of planes T (step S106).

[0195] When the updated variable j is smaller than the number of planes T (No in step S106), the processing of the CPU 15 returns to step S102. That is, the CPU 15 further performs processing for transferring one page of user data to the data input latch 321 of the j-th plane 45 in the i-th nonvolatile memory chip 41 based on the updated variable j. Therefore, the CPU 15 repeats the sequence of steps S102 to S106 until one page of user data is transferred to the data input latch 321 of each of the T planes 45 in the i-th nonvolatile memory chip 41.

[0196] When the updated variable j is equal to the number of planes T (Yes in step S106), Fig. 12BAs shown, the CPU 15 moves one page of user data from the data input latch 321 to the kth programming latch 322 in each of the T planes 45 in the i-th nonvolatile memory chip 41 (step S107). The CPU 15 sets the variable j to 0 (step S108). Then, the CPU 15 determines whether the variable k is equal to the value obtained by subtracting 1 from the number of pages M (step S109).

[0197] When variable k is smaller than the value obtained by subtracting 1 from the number of pages M (No in step S109), CPU 15 updates variable i by adding 1 to variable i (step S110). Then, CPU 15 determines whether the updated variable i is equal to the number of nonvolatile memory chips S (step S111).

[0198] When the updated variable i is less than the number of nonvolatile memory chips S (No in step S111), Fig. 12A As shown, the processing of the CPU 15 returns to step S102. That is, the CPU 15 further performs processing for transferring one page of user data to the k-th programming latch 322-k of each plane 45 for the i-th nonvolatile memory chip 41 based on the updated variable i.

[0199] When the updated variable i is equal to the number of nonvolatile memory chips S (Yes in step S111), the CPU 15 sets the variable i to 0 (step S112). Then, the CPU 15 updates the variable k by adding 1 to the variable k (step S113). Fig. 12A That is, the CPU 15 further performs processing for transferring one page of user data to the k-th program latch 322 - k of each plane 45 for each of the S nonvolatile memory chips 41 based on the updated variable k.

[0200] In addition, when the variable k is equal to the value of the number of pages M minus 1 (yes in step S109), the CPU 15 performs the FSP operation on the i-th nonvolatile memory chip 41 (step S114). When the variable k is equal to the value of the number of pages M minus 1, the user data to be written in the FSP operation on the i-th nonvolatile memory chip 41 is stored in the M programming latches 322 of each of the T planes 45 in the i-th nonvolatile memory chip 41. In the FSP operation, the CPU 15 programs the stored user data to the T plane blocks included in each of the T planes 45. That is, in each of the T planes 45, the user data of the M pages stored in the M programming latches 322 are written to the plane blocks in the corresponding plane 45.

[0201] Next, the CPU 15 updates the variable i by adding 1 to the variable i (step S115 ). The CPU 15 determines whether the updated variable i is equal to the number S of nonvolatile memory chips (step S116 ).

[0202] When the updated variable i is less than the number of nonvolatile memory chips S (No in step S116), Fig. 12A As shown, the processing of the CPU 15 returns to step S102. That is, the CPU 15 further performs processing for transferring one page of user data to the k-th programming latch 322-k of each plane 45 for the i-th nonvolatile memory chip 41 based on the updated variable i.

[0203] When the updated variable i is equal to the number of nonvolatile memory chips S (Yes in step S116), the CPU 15 determines whether data needs to be written to the subsequent string (step S117). For example, the CPU 15 determines whether data needs to be written to the subsequent string based on a write request from the host 2.

[0204] In the case where there is data to be written to the subsequent string (Yes in step S117), Fig. 12A As shown, the processing of the CPU 15 returns to step S101 to perform processing for writing data to the subsequent string.

[0205] When data is not written to a string described later (No in step S117 ), the CPU 15 ends the write control process.

[0206] Through the above write control processing, when the CPU 15 performs the FSP action for each of the S nonvolatile memory chips 41 in parallel, the size of the write buffer 141 provided in the memory system 3 can be reduced. Specifically, the CPU 15 does not wait for all the user data written in one FSP action to be accumulated in the write buffer 141, but transfers one page of user data stored in the write buffer 141 to the data input latch 321. The CPU 15 also transfers one page of user data stored in the data input latch 321 to the programming latch 322. As a result, since the user data written in one FSP action is held by the latch 32, the time it stays in the write buffer 141 is shortened, so the size of the write buffer 141 provided in the memory system 3 can be reduced.

[0207] In addition, by using Fig. 9 The writing order shown as the writing order for the S nonvolatile memory chips 41 can also reduce the size of the read buffer 142.

[0208] Therefore, in the memory system 3 , the size of the data buffer used when the host 2 accesses the nonvolatile memory chip 41 can be reduced.

[0209] (Second embodiment)

[0210] In the memory system 3 of the first embodiment, the controller 6 performs a plurality of data transfer operations to transfer user data of a second size smaller than user data of a first size written in one write operation (e.g., one FSP operation) to the nonvolatile memory chip 41 from the write buffer 141 to the latch 32. Furthermore, the controller 6 writes the plurality of user data of the second size respectively transferred to the latch 32 in the plurality of data transfer operations into the memory cell array 33.

[0211] In this regard, the memory system 3 of the second embodiment also has the following structure, which is used to make the user data non-volatile when a non-volatile request for user data is accepted from the host 2 during the period when the size (third size) of the user data that has not yet been written to the storage cell array 33 of the non-volatile memory chip 41 after being received from the host 2 has not reached the first size.

[0212] The configuration of the memory system 3 of the second embodiment is the same as that of the memory system 3 of the first embodiment. The difference between the memory system 3 of the second embodiment and the memory system 3 of the first embodiment is that the memory system 3 of the second embodiment has a configuration for making user data nonvolatile. The following mainly describes the differences from the first embodiment.

[0213] The write control unit 151 of the controller 6 transfers the user data of the second size to the data input latch 321 of the nonvolatile memory chip 41 based on the accumulation of the user data of the second size in the write buffer 141. That is, the write control unit 151 starts data input to the nonvolatile memory chip 41 before receiving the user data of the first size written in one FSP operation to the nonvolatile memory chip 41 from the host 2. In this case, after starting the data input to the nonvolatile memory chip 41, the user data required for one FSP operation may not be received from the host 2.

[0214] When the third size of the user data that has not yet been written to the memory cell array 33 of the nonvolatile memory chip 41 after receiving it from the host 2 does not reach the first size, the write control unit 151 transmits dummy data of a fourth size obtained by subtracting the third size from the first size to the latch 32 of the nonvolatile memory chip 41 when accepting a request for non-volatilization of the user data (for example, a refresh command) from the host 2. Then, the write control unit 151 writes the user data of the third size and the dummy data of the fourth size to the memory cell array 33.

[0215] Thus, after starting to input data to the nonvolatile memory chip 41 and before receiving user data required for one FSP operation from the host 2, even if a nonvolatile request is received from the host 2, the user data received from the host 2 can be made nonvolatile.

[0216] Therefore, in the memory system 3 of the second embodiment, the sizes of the write buffer 141 and the read buffer 142 can be reduced, and processing corresponding to the nonvolatile request from the host 2 can be executed.

[0217] Fig.13A and Fig. 13B 1 is a flowchart showing an example of the sequence of non-volatile processing executed by the CPU 15 (more specifically, the write control unit 151). The non-volatile processing is a process for non-volatileizing the user data received from the host 2 but not yet written to the non-volatile memory chip 41 (that is, writing to the non-volatile memory chip 41). The CPU 15 executes the reference Fig. 12A and Fig. 12B During the write control process, a nonvolatile request is received from the host 2 and the nonvolatile process is executed. The values ​​of the variables i, j, and k used in the nonvolatile process are respectively the values ​​of the variables i, j, and k in the write control process during the execution. In addition, the number of nonvolatile memory chips S, the number of planes T, and the number of pages M are common to the write control process.

[0218] First, the CPU 15 determines whether user data is stored in the write buffer 141 (step S201 ).

[0219] When user data is stored in the write buffer 141 (Yes in step S201 ), the CPU 15 determines whether the user data stored in the write buffer 141 is user data of one page or more (step S202 ).

[0220] When the user data stored in the write buffer 141 is more than one page of user data (step S202), the CPU 15 transfers one page of user data from the write buffer 141 to the data input latch 321 of the jth plane 45 in the i-th non-volatile memory chip 41 (step S203), and proceeds to step S205.

[0221] When the user data stored in the write buffer 141 is less than 1 page of user data (No in step S202), the CPU 15 transfers 1 page of data including the user data and virtual data to the data input latch 321 of the jth plane 45 in the i-th non-volatile memory chip 41 (step S204), and proceeds to step S205.

[0222] Then, the CPU 15 releases the storage area in the write buffer 141 storing the transferred user data (step S205 ), and proceeds to step S207 .

[0223] In addition, when no user data is stored in the write buffer 141 (No in step S201), the CPU 15 transfers one page of virtual data to the data input latch 321 of the jth plane 45 in the i-th non-volatile memory chip 41 (step S206), and proceeds to step S207.

[0224] Next, the CPU 15 updates the variable j by adding 1 to the variable j (step S207 ). Then, the CPU 15 determines whether the updated variable j is equal to the number of planes T (step S208 ).

[0225] When the updated variable j is smaller than the number of planes T (No in step S208), the processing of the CPU 15 returns to step S201. That is, the CPU 15 further performs processing for transferring one page of data to the data input latch 321 of the j-th plane 45 in the i-th nonvolatile memory chip 41 based on the updated variable j. Therefore, the CPU 15 repeats the sequence of steps S201 to S208 until one page of data is transferred to the data input latch 321 of each of the T planes 45 in the i-th nonvolatile memory chip 41. In addition, the transferred one page of data is composed of at least one of user data and dummy data.

[0226] When the updated variable j is equal to the number of planes T (Yes in step S208), Fig. 13B As shown, the CPU 15 moves one page of data from the data input latch 321 to the kth programming latch 322 in each of the T planes 45 in the i-th nonvolatile memory chip 41 (step S209).

[0227] The following sequence of steps S210 to S218 is similar to the reference sequence Fig. 12A and Fig. 12B The order of steps S108 to S116 of the write control process is the same. Fig. 12B In step S107 of the write control process shown in FIG. 1 , one page of user data is transferred from the data input latch 321 to the k-th programming latch 322-k. Fig. 13BIn step S209 of the nonvolatile processing shown in FIG. 1 , one of the one-page user data transferred to the data input latch 321 in step S203, one-page data including the user data and dummy data transferred to the data input latch 321 in step S204, and one-page dummy data transferred in step S206 is transferred to the k-th programming latch 322-k. The transferred data is written to the plane block by the FSP action in each nonvolatile memory chip 41.

[0228] Through the above non-volatile processing, even when the amount of user data received from the host 2 is less than the amount of data required for the FSP operation, the CPU 15 can make the user data received from the host 2 non-volatile according to the non-volatile request. The CPU 15 can input the data required for the FSP operation into the non-volatile storage chip 41 by transferring dummy data to the data input latch 321 and the programming latch 322.

[0229] (Third embodiment)

[0230] In the memory system 3 of the first embodiment, the controller 6 performs a plurality of data transfer operations to transfer user data of a second size smaller than the user data of the first size written in one write operation to the nonvolatile memory chip 41 from the write buffer 141 to the latch 32. Furthermore, the controller 6 writes the plurality of user data of the second size respectively transferred to the latch 32 in the plurality of data transfer operations into the memory cell array 33 in the first manner.

[0231] In addition, the memory system 3 of the second embodiment also has the following structure, which is used to make data with virtual data added to the user data non-volatile in the first manner when a non-volatile request for user data is accepted from the host 2 during a period in which the third size of the user data that has not yet been written to the storage cell array 33 of the non-volatile memory chip 41 after being received from the host 2 has not reached the first size.

[0232] In this regard, the memory system 3 of the third embodiment has the following structure, which is used to non-volatile the user data input to the latch 32 in a second manner different from the first manner when a request for non-volatile data is accepted from the host 2 during a period when the user data input to the latch 32 has not reached the first size.

[0233] The configuration of the memory system 3 of the third embodiment is the same as that of the memory system 3 of the first and second embodiments. The memory system 3 of the third embodiment is different from the memory system 3 of the first and second embodiments in that the memory system 3 of the third embodiment has a configuration for making user data nonvolatile in the second manner. The following mainly describes the differences from the first and second embodiments.

[0234] The write control unit 151 of the controller 6 performs a plurality of data transfer operations: user data of a second size smaller than the user data of the first size written in one write operation to the nonvolatile memory chip 41 is transferred from the write buffer 141 to the latch 32 of the nonvolatile memory chip 41. Then, the write control unit 151 writes the plurality of user data of the second size to the memory cell array 33 in the first manner.

[0235] When a total size of one or more second-size user data transferred to the latch 32 of the nonvolatile memory chip 41 and not yet written to the memory cell array 33 does not reach the first size, and when a request for non-volatile user data is received from the host 2, the write control unit 151 non-volatiles at least a portion of the user data input to the latch 32 in a second manner different from the first manner. The user data input to the latch 32 is, for example, user data stored in at least one of the data input latch 321, the 0th programming latch 322-0, the first programming latch 322-1, and the second programming latch 322-2. Specifically, the write control unit 151 writes at least a portion of the user data input to the latch 32 in the second manner to other blocks in the plane 45 including the block to be written in the first manner (for example, plane blocks PB0, PB1, PB2, or PB3).

[0236] The first method is a method of writing M bits of data to each memory cell. The second method is a method of writing N bits of data to each memory cell. M is an integer greater than 2. N is a number less than M. For example, when the TLC method is used as the first method, the SLC method is used as the second method. Therefore, the size of data required for one programming operation in the second method is smaller than the size of data required for one programming operation in the first method.

[0237] Fig.14An example of a command sequence for the nonvolatile memory chip 41 is shown. The command sequence corresponds to one nonvolatile operation for one nonvolatile memory chip 41. Here, it is assumed that a nonvolatile operation is performed on a nonvolatile memory chip 41 including a plurality of planes 45. The command sequence is output to the nonvolatile memory chip 41 by the memory I / F 12, for example, under the control of the write control unit 151. The instruction to the nonvolatile memory chip 41 is performed in units of a group of, for example, a first prefix instruction, a second prefix instruction, a first instruction, an address, and a second instruction.

[0238] First, the memory I / F 12 outputs the first prefix instruction 801, the second prefix instruction 802, the first instruction 803, the address 804, and the second instruction 805 to the nonvolatile memory chip 41. The first prefix instruction 801 is, for example, any one of the instructions "01h", "02h", and "03h". The instructions "01h", "02h", and "03h" are instructions for specifying the latch 32 storing the data to be programmed among the data input latch 321 and the programming latches 322-0, 322-1, and 322-2. The latch 32 specified by the first prefix instruction 801 is called the first object latch 32. The data stored in the first object latch 32 is called the first data. The second prefix instruction 802 is, for example, the instruction "A2h". The instruction "A2h" is an instruction for specifying the second method of programming data. The first instruction 803 is instruction "80h" or "85h". Instructions "80h" and "85h" are instructions for starting data input. Address 804 specifies a block (hereinafter referred to as the first block) in which the first data is to be programmed in the second manner. The first block is another block within the plane 45 that includes a block in which the first data is scheduled to be programmed in the first manner. Address 804 can further specify a string within the first block in which the first data is to be programmed in the second manner. The second instruction 805 is, for example, instruction "11h". Instruction "11h" is an instruction to directly retain the input data in the latch 32. The memory I / F 12 outputs instruction "11h" as the second instruction 805 when performing non-volatile operations on other planes 45 included in the non-volatile memory chip 41 in parallel.

[0239] The first prefix instruction 801, the second prefix instruction 802, the first instruction 803, the address 804, and the second instruction 805 specify that the first data stored in the first object latch 32 is programmed into the first block (more specifically, the string in the first block) in the second manner.

[0240] Similarly, the memory I / F 12 executes a sequence for designating that the data input to any latch 32 is to be programmed in the second manner to a block different from the block to be programmed in the first manner for the other planes 45 .

[0241] Then, the memory I / F 12 outputs the first prefix instruction 806, the second prefix instruction 807, the first instruction 808, the address 809, and the second instruction 810 to the non-volatile memory chip 41. The first prefix instruction 806 is, for example, any one of the instructions "01h", "02h", and "03h". The latch 32 specified by the first prefix instruction 806 is called the second object latch 32. The data stored in the second object latch 32 is called the second data. The second prefix instruction 807 is, for example, the instruction "A2h". The first instruction 808 is the instruction "80h" or "85h". The address 809 specifies the block (hereinafter referred to as the second block) in which the second data is programmed in the second manner. The second block is another block within the plane 45 that includes the block in which the second data is scheduled to be programmed in the first manner. The address 809 can further specify a string within the second block in which the second data is programmed in the second manner. The second command 810 is, for example, command “10h.” Command “10h” is a command to start a program based on designated contents.

[0242] The data stored in the designated latch 32 is programmed to the designated block (more specifically, the designated string in the designated block) in a designated manner through the first prefix instruction 806, the second prefix instruction 807, the first instruction 808, the address 809, and the second instruction 810. Specifically, the first data stored in the first object latch 32 is programmed to the first block in a second manner. In addition, the second data stored in the second object latch 32 is programmed to the second block in a second manner. In addition, when the designated latch 32 is the data input latch 321, the data stored in the data input latch 321 can be programmed to the designated block after being moved to the programming latch 322.

[0243] In addition, when data exceeding the size programmed by the one-time programming operation of the second method is stored in the data input latch 321 and the programming latch 322 of each plane 45, the memory I / F 12 repeatedly executes the program operation while changing the latch 32 designated by the first prefix instruction 801 and 806. Fig.14 The size of data written in the one-shot writing operation of the second method is, for example, one page of data in the one-shot writing operation of the SLC method.

[0244] Through the above instruction sequence, the memory I / F12 can perform a non-volatile memory chip 41 including a plurality of planes 45. In the instruction sequence, the memory I / F12 writes the data input to the latch 32 to the block in the second mode (for example, the SLC mode). That is, the memory I / F12 can, for example, write one page of data to the block in the SLC mode without being restricted by the FSP action when programming the data. In addition, there is no need to input dummy data to the non-volatile memory chip 41 in order to write the data input to the latch 32 in the first mode (for example, the TLC mode). Therefore, in the memory system 3, the data input to the latch 32 can be non-volatile at a high speed. Therefore, the memory system 3 can respond to the non-volatile request from the host 2 with low latency.

[0245] Fig.15 12 is a flowchart showing an example of the sequence of nonvolatile processing performed by CPU 15. Nonvolatile processing is a process for nonvolatileizing user data received from host 2 but not yet written to nonvolatile memory chip 41. CPU 15 performs nonvolatile processing, for example, based on receiving a nonvolatile request from host 2 during the execution of the write control processing described in reference FIG. 12. CPU 15 performs the nonvolatile processing on each of S nonvolatile memory chips 41. The number of nonvolatile memory chips S and the number of planes T are the same as those in the write control processing. In addition, in the nonvolatile processing, data is programmed to the block by the second method. The second method is a method of programming N pages of data in one programming action (that is, programming N bits of data to each storage cell).

[0246] First, the CPU 15 determines whether user data is stored in the P program latches 322 of each plane 45 in the nonvolatile memory chip 41 (step S301). P is an integer greater than or equal to 1 and less than or equal to the number of pages M.

[0247] When user data is not stored in any of the program latches 322 of each plane 45 (No in step S301 ), the processing of the CPU 15 proceeds to step S306 .

[0248] When user data is stored in the P programming latches 322 of each plane 45 (yes in step S301), CPU15 sets variable k to 0 (step S302). Variable k is used to specify one of the P programming latches 322 storing user data. In each of the T planes 45, CPU15 programs the user data stored in the k-th programming latch 322-k to the block of the corresponding plane 45 in the second manner (step S303). The block in which data is programmed in the second manner is a block different from the block in which data is programmed in the first manner (for example, the block that is the object of the FSP action in the write control process). CPU15 can perform the programming of user data in the second manner in T planes 45 in parallel. Next, CPU15 updates variable k by adding 1 to variable k (step S304). CPU15 determines whether the updated variable k does not reach the number P of programming latches 322 storing user data (step S305).

[0249] If the updated variable k does not reach P (Yes in step S305 ), the CPU 15 returns to step S303 . That is, the CPU 15 further performs processing for writing the user data stored in the kth program latch 322 in the second mode based on the updated variable k.

[0250] When the updated variable k is equal to P (No in step S305 ), the processing of the CPU 15 proceeds to step S306 .

[0251] Next, the CPU 15 determines whether user data is stored in the data input latch 321 in the Q planes 45 in the nonvolatile memory chip 41 (step S306). Q is an integer greater than or equal to 1 and less than or equal to the number of planes T.

[0252] In the case where user data is stored in the data input latch 321 on the Q planes 45 (Yes in step S306), the CPU 15 programs the user data stored in the data input latch 321 to the block in the corresponding plane 45 in the second manner in each of the Q planes 45 (step S307), and the non-volatile processing ends. In addition, when Q is 2 or more, the CPU 15 can write the user data in the second manner in parallel in the Q planes 45. In addition, the CPU 15 can also write the user data stored in the data input latch 321 in the second manner after transferring it to the programming latch 322.

[0253] When user data is not stored in the data input latch 321 of any plane 45 (No in step S306 ), the CPU 15 ends the nonvolatile processing.

[0254] Through the above non-volatile processing, the CPU 15 can make the user data stored in the data input latch 321 and the user data stored in the programming latch 322 non-volatile in the second manner according to the non-volatile request from the host 2. Compared with the case where the user data and the virtual data are made non-volatile in the first manner of writing M bits of data to each storage cell, the CPU 15 can respond to the non-volatile request with low latency by making the user data non-volatile in the second manner of writing N bits of data to each storage cell. In addition, since the data is programmed in a small-size data unit (for example, a 4KB unit) corresponding to the second manner, for example, it is not necessary to input the virtual data as the data required for the FSP action to the non-volatile memory chip 41. In addition, the CPU 15 can also write the user data stored in the write buffer 141 to the block in the second manner according to the non-volatile request from the host 2.

[0255] As described above, according to the first to third embodiments, the size of the data buffer used when accessing the nonvolatile memory can be reduced. The write control unit 151 performs multiple data transfer operations: data of a second size smaller than the data of the first size written in one write operation to the nonvolatile memory chip 41 is transferred from the write buffer 141 to the nonvolatile memory chip 41 (more specifically, the latch 32). The write control unit 151 writes the multiple data of the second size transferred to the nonvolatile memory chip 41 through the multiple data transfer operations to the memory cell array 33 of the nonvolatile memory chip 41.

[0256] Thus, the memory system 3 can reduce the size of the write buffer 141 compared to the memory system 3A of the comparative example, and the memory system 3A starts data transfer to the nonvolatile memory chip 41A after accumulating the user data of the first size in the write buffer 141A. Fig. 9 The writing order shown can also reduce the size of the read buffer 142. Therefore, in the memory system 3, the sizes of the write buffer 141 and the read buffer 142 used when the host 2 accesses the nonvolatile memory chip 41 can be reduced.

[0257] Each of the various functions described in the first to third embodiments can be implemented by a circuit (processing circuit). In the example of the processing circuit, a processor programmed like a central processing unit (CPU) is included. The processor executes the various functions described by executing a computer program (command group) stored in a memory. The processor may be a microprocessor including a circuit. In the example of the processing circuit, a digital signal processor (DSP: Digital Signal Processing), an integrated circuit for a specific purpose (ASIC: Application Specific Integrated Circuit), a microcontroller, a controller, and other circuit parts are also included. Each of the other components except the CPU described in the embodiments can also be implemented by a processing circuit.

[0258] Although several embodiments of the present invention have been described, the embodiments are presented as examples and are not intended to limit the scope of the invention. The novel embodiments can be implemented in various other ways, and various omissions, substitutions, and changes can be made without departing from the scope of the invention. The embodiments or their variations are included in the scope or spirit of the invention, and are included in the invention described in the claims and their equivalents.

[0259] [Explanation of Symbols]

[0260] 1: Information Processing System

[0261] 2: Host

[0262] 3: Memory system

[0263] 4: Memory devices

[0264] 5. DRAM

[0265] 6: Controller

[0266] 11:Host I / F

[0267] 12: Memory I / F

[0268] 13: DRAM I / F

[0269] 14:SRAM

[0270] 15:CPU

[0271] 141: Write buffer

[0272] 142: Read buffer

[0273] 151: Write control unit

[0274] 152: Reading control unit

[0275] 31: Peripheral circuit

[0276] 32: Latch

[0277] 321: Data input latch

[0278] 322: Programming latch

[0279] 322-0: 0th programming latch

[0280] 322-1: 1st programming latch

[0281] 322-2: Second programming latch

[0282] 33: Memory cell array

[0283] 41: Non-volatile memory chip

[0284] 41-0: No. 0 non-volatile memory chip

[0285] 41-1: No. 1 non-volatile memory chip

[0286] 41-2: Second non-volatile memory chip

[0287] 41-3: The third non-volatile memory chip

[0288] 45: Plane

[0289] 45-0: Plane 0

[0290] 45-1: Plane 1

[0291] 45-2: Plane 2

[0292] 45-3: Plane 3

[0293] 51:FW

[0294] 52: Logical entity address translation table

[0295] 61: User data.

Claims

1. A memory system comprising: A non-volatile memory chip including a memory cell array; A write buffer capable of storing data received in response to a write request from the receiving host; and Controller, composed of performing a data transfer operation of transferring data of a second size smaller than data of a first size written in one write operation to the nonvolatile memory chip from the write buffer to the nonvolatile memory chip a plurality of times, and The plurality of data of the second size transferred to the nonvolatile memory chip in the plurality of data transfer operations are written into the memory cell array.

2. The memory system according to claim 1, wherein the controller is configured as follows: During a period in which the third size of the data that has not yet been written to the storage cell array after being received from the host has not reached the first size, when a request for non-volatile data is accepted from the host, virtual data of a fourth size obtained by subtracting the third size from the first size is transmitted to the non-volatile memory chip, and the data of the third size and the virtual data of the fourth size are written to the storage cell array.

3. The memory system of claim 1 , wherein the memory cell array comprises: a first block in which data is written in a first manner, and a second block in which data is written in a second manner different from the first manner, and The controller is configured as follows: writing the plurality of data of the second size into the first block in the first manner, During the period when the total size of one or more data of the second size that are transmitted to the nonvolatile memory chip and have not yet been written to the storage cell array has not reached the first size, when a request for non-volatile data is accepted from the host, at least a portion of the one or more data of the second size are written to the second block in the second manner.

4. The memory system of claim 3, wherein The first method is to write M bits of data to each storage cell. The second method is a method of writing N bits of data to each memory cell. The M is an integer greater than 2, and The N is a number smaller than the M.

5. The memory system according to claim 1, wherein the controller is further configured to release a storage area in the write buffer storing the data of the second size after performing the data transfer operation of transferring the data of the second size to the nonvolatile memory chip. The memory system according to claim 1 , wherein a total size of the plurality of data of the second size is equal to the first size.

7. The memory system of claim 1, wherein the nonvolatile memory chip comprises a plurality of latch circuits; The plurality of data of the second size are respectively stored in the plurality of latch circuits; and The controller is configured to write the plurality of data of the second size respectively stored in the plurality of latch circuits into the memory cell array.

8. The memory system according to claim 1, wherein the nonvolatile memory chip comprises a first latch circuit and a second latch circuit; and The controller is configured as follows: transferring the first data of the second size stored in the write buffer to the first latch circuit; The first data stored in the first latch circuit is moved to the second latch circuit, and the first data stored in the second latch circuit is written into the memory cell array.

9. The memory system according to claim 1, wherein the non-volatile memory chip comprises a first plane and a second plane; and The controller is configured as follows: performing a data transfer operation of transferring the first data of the second size from the write buffer to the first plane, performing a data transfer operation of transferring the second data of the second size from the write buffer to the second plane, and An operation of writing the first data into the blocks in the first plane and an operation of writing the second data into the blocks in the second plane are performed in parallel.

10. The memory system of claim 1, wherein the nonvolatile memory chip comprises a block; and The memory is constituted as performing a data transfer operation of transferring the first data of the second size from the write buffer to the nonvolatile memory chip, performing a data transfer operation of transferring the second data of the second size from the write buffer to the nonvolatile memory chip, The first data and the second data are written into the block in a manner of writing M bits of data into each storage cell, and The M is an integer greater than or equal to 2. The memory system of claim 1 , wherein the write buffer is disposed within the controller.

12. The memory system according to any one of claims 1 to 11, further comprising a read buffer capable of storing data read from the nonvolatile memory chip in response to a read request from the host.

13. A memory system comprising: A nonvolatile memory chip having: a first plane including a first memory cell array, a first latch circuit, and a second latch circuit; and a second plane including a second memory cell array, a third latch circuit, and a fourth latch circuit; A write buffer capable of storing data received in response to a write request from the receiving host; and The controller is configured to send the following instruction group to the non-volatile memory chip: a first instruction group including a first instruction for instructing to start data input, a first address indicating a first block in the first storage cell array, first data to be written into the first block, and a second instruction for causing the first latch circuit to hold the first data; a second instruction group including a third instruction for instructing to start data input, a second address indicating a second block in the second storage cell array, second data to be written into the second block, and a fourth instruction for moving the first data held by the first latch circuit to the second latch circuit and moving the second data input into the third latch circuit to the fourth latch circuit; a third instruction group including a fifth instruction for instructing to start data input, a third address indicating the first block, third data to be written into the first block, and a sixth instruction for causing the first latch circuit to hold the third data; and The 4th instruction group includes the 7th instruction indicating the start of data input, the 4th address representing the 2nd block, the 4th data to be written to the 2nd block, and the 8th instruction indicating programming the 1st data, the 2nd data, the 3rd data, and the 4th data to the 1st storage cell array and the 2nd storage cell array.

14. The memory system according to claim 13, wherein the received data is data of a first size, and The first data is data of a second size smaller than the first size.

15. The memory system according to claim 13, wherein each of the first data, the second data, the third data, and the fourth data is data of a second size smaller than data of a third size written in one write operation to the nonvolatile memory chip; and The controller is configured as follows: During a period in which the fourth size of the data that has not yet been written to the memory cell array in the nonvolatile memory chip including the first memory cell array and the second memory cell array after being received from the host does not reach the third size, when a request for non-volatile data is accepted from the host, dummy data of a fifth size obtained by subtracting the fourth size from the third size is transmitted to the nonvolatile memory chip, and The data of the fourth size and the dummy data of the fifth size are written into the memory cell array.

16. The memory system of claim 13, wherein Each of the first data, the second data, the third data, and the fourth data is data of a second size smaller than data of a third size written in one write operation to the nonvolatile memory chip; The first memory cell array includes the first block in which data is written in a first manner, and a third block in which data is written in a second manner different from the first manner; and The memory controller is configured to write the first data and the third data into the first block in the first manner, During a period when the total size of the data of the second size that is transmitted to the nonvolatile memory chip and has not yet been written to one or more storage cell arrays in the nonvolatile memory chip including the first storage cell array and the second storage cell array does not reach the third size, when a request for non-volatile data is accepted from the host, at least a portion of the one or more data of the second size is written to the third block in the second manner.

17. A memory system according to claim 16, wherein the controller is configured to send an instruction group to the non-volatile memory chip, and the instruction group includes a 9th instruction representing the 5th latch circuit in the 1st plane storing the 5th data in the one or more data of the second size, a 10th instruction specifying the second mode, an 11th instruction indicating the start of data input, specifying the 5th address of the 3rd block, and a 12th instruction indicating that the 5th latch circuit should hold the 5th data or program the 5th data into the 1st storage cell array.

18. The memory system of claim 16, wherein The first method is to write M bits of data to each storage cell. The second method is a method of writing N bits of data to each memory cell. The M is an integer greater than 2, The N is a number smaller than the M.

19. A memory system according to any one of claims 14 to 18, wherein the controller is further configured to release a storage area in the write buffer storing the data of the second size after performing a data transfer operation of transferring the data of the second size from the write buffer to the non-volatile memory chip.

20. The memory system of claim 13, wherein the write buffer is disposed within the controller.

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