Double-layer epitaxial isolation structure and process method

Abstract

The invention discloses a double-layer epitaxial isolation structure and a process method, a semiconductor substrate of a first conduction type is provided with a first epitaxial layer of a second conduction type, and the surface layer of the first epitaxial layer is provided with an injection layer of a second conduction type formed by ion injection as a buried layer; a second epitaxial layer of the first conductive type is arranged above the buried layer, and ion implantation is carried out in the second epitaxial layer to form a deep trap of the second conductive type; the surface layer of the second epitaxial layer is provided with a shallow trench isolation structure formed by etching and filling, and the shallow trench isolation structure is internally provided with a deep trench which is etched and filled with a semiconductor material. According to the invention, the low-resistance substrate is combined with the lightly doped first epitaxial layer, the high-concentration (low-resistance) substrate can inhibit the starting of a parasitic NPN tube, the Vhold is improved, the lightly doped first epitaxial layer optimizes the electric field distribution, the PN junction breakdown voltage performance of the DTI is improved, and the application requirement of the DTI when the substrate is suspended is met.

Description

Technical Field

[0001] The invention relates to the field of semiconductor device design and manufacturing, and in particular to a double-layer epitaxial isolation structure.

[0002] The invention also relates to a process method for the double-layer epitaxial isolation structure. Background Art

[0003] Deep Trench Isolation (DTI) structure is an isolation technology used in integrated circuit manufacturing. It uses photolithography and etching technology to form deep trenches that usually reach the silicon substrate, effectively preventing crosstalk and leakage between devices and achieving higher device density.

[0004] A deep trench isolation DTI structure, wherein the DTI deep trench passes through the N-type deep well and N-type buried layer in the conventional P-type epitaxy and goes deep into the lightly doped P-type epitaxy. The bottom of the DTI is close to the low-resistance (heavily doped) P-type substrate. The P-type bottom injection region at the bottom of the DTI prevents the N-type regions on both sides from punching through. The N-type regions on both sides of the DTI are led out through the N-type heavily doped region, with one end connected to a high potential and the other end connected to a low potential.

[0005] The isolation capability of DTI is strongly correlated with the PN junction breakdown voltage of DTI (PN junction breakdown voltage between N-type buried layer / P-type substrate). The lighter the concentration of P-type substrate, the higher the PN junction breakdown voltage of DTI. Since the DTI structure needs to meet the working requirements of P-type substrate suspension, if the P-type substrate is suspended, the parasitic BJT (N-type buried layer / P-type substrate / N-type buried layer) is easily turned on, resulting in isolation failure; if the concentration of the P-type bottom injection area at the bottom of DTI is increased to suppress the opening of the parasitic NPN tube, the PN junction breakdown voltage of DTI will be reduced. Summary of the invention

[0006] The technical problem to be solved by the present invention is to provide a deep trench isolation structure.

[0007] The invention also provides a process method for the deep trench isolation structure.

[0008] In order to solve the above problems, a process method for a double-layer epitaxial isolation structure described in the present invention comprises the following process steps: Providing a semiconductor substrate of the first conductivity type, growing a first epitaxial layer of the first conductivity type on the semiconductor substrate of the first conductivity type; then performing ion implantation to form an implantation layer of the second conductivity type as a buried layer on the epitaxial layer; Continue epitaxial growth to grow a second epitaxial layer of the first conductivity type, then perform ion implantation of the second conductivity type in the second epitaxial layer to form a deep well of the second conductivity type in the epitaxial layer of the first conductivity type; Performing a first photolithography, etching and filling process to form a shallow trench isolation structure on the surface of the epitaxial layer; Performing high aspect ratio etching in the shallow trench isolation structure to form a deep trench; the area of ​​the deep trench is smaller than that of the shallow trench isolation structure; performing ion implantation in the bottom substrate layer of the deep trench to form a first conductive type trench bottom implantation region; and filling the deep trench with a material to fill the deep trench completely; The second photolithography opens an ion implantation window and performs ion implantation to form a well region of the second conductivity type outside the shallow trench isolation structure.

[0009] The semiconductor substrate is a heavily doped low-resistance substrate, and its material is a silicon substrate, a silicon germanium substrate, a gallium arsenide substrate, a gallium nitride substrate or a silicon carbide substrate.

[0010] The injection layer is heavily doped with the second conductivity type to form a buried layer structure.

[0011] Furthermore, the first photolithography, etching and filling process is completed synchronously by sharing the active area photolithography and filling process; the shallow trench isolation structure is filled with silicon oxide material.

[0012] Furthermore, the first epitaxial layer is a lightly doped epitaxial layer of the first conductivity type.

[0013] Furthermore, the deep trench is filled with polysilicon material.

[0014] Furthermore, it also includes forming a heavily doped region of the second conductivity type in the well region as a lead-out region.

[0015] Furthermore, the heavily doped region is formed synchronously by an ion implantation process when the shared active region source and drain region are implanted.

[0016] Furthermore, the first conductivity type is P type, and the second conductivity type is N type; when manufacturing opposite type devices, the first conductivity type and the second conductivity type can be inverted.

[0017] A double-layer epitaxial isolation structure described in the present invention comprises a first epitaxial layer of a second conductivity type on a semiconductor substrate of a first conductivity type, and an implanted layer of the second conductivity type formed by ion implantation as a buried layer on the surface of the first epitaxial layer; A second epitaxial layer of the first conductivity type is provided above the buried layer, and ion implantation is performed in the second epitaxial layer to form a deep well of the second conductivity type; A shallow trench isolation structure formed by etching and filling is provided on the surface of the second epitaxial layer, and a deep trench etched and filled with semiconductor material is provided in the shallow trench isolation structure, and the deep trench is etched downward to a depth that passes through the buried layer and its bottom is located in the first epitaxial layer; The shallow trench isolation structure has a well region of the second conductivity type.

[0018] Furthermore, the semiconductor substrate is a heavily doped low-resistance substrate, including a silicon substrate, a silicon germanium substrate, a gallium arsenide substrate, a gallium nitride substrate or a silicon carbide substrate.

[0019] Furthermore, the first epitaxial layer is a lightly doped epitaxial layer.

[0020] Furthermore, the bottom of the deep trench also has a trench bottom implantation region of the first conductivity type to prevent the second conductivity type regions on both sides of the deep trench from penetrating.

[0021] Furthermore, the well region also has a heavily doped region as a lead-out region formed by synchronous injection of source and drain into the active region.

[0022] Furthermore, the material filled in the deep trench is polysilicon.

[0023] Furthermore, the first conductivity type is P type, and the second conductivity type is N type; when manufacturing opposite type devices, the first conductivity type and the second conductivity type can be inverted.

[0024] The double-layer epitaxial isolation structure described in the present invention adopts a low-resistance substrate combined with a lightly doped first epitaxial layer. The high-concentration (low-resistance) substrate can suppress the NPN from turning on, thereby increasing Vhold (holding voltage / clamping voltage). The lightly doped first epitaxial layer optimizes the electric field distribution, thereby increasing the PN junction breakdown voltage performance of the DTI and meeting the application requirements of the DTI when the substrate is suspended. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figures 1 to 6 It is a schematic diagram of the process steps of the present invention.

[0026] Figure 7 It is a breakdown voltage simulation curve diagram of the present invention and the existing structure.

[0027] Figure 8 It is a process flow chart of the present invention.

[0028] 101-2—low-resistance P-type substrate, 102—lightly doped P-type epitaxy, 103—N-type buried layer, 104—N-type deep well on conventional P-type epitaxy, 105—shallow trench isolation, 106—deep trench isolation, 107—P-type implantation, 108—N-well, 109—N-type heavily doped region. DETAILED DESCRIPTION

[0029] The following is a specific implementation of the present invention in conjunction with the accompanying drawings, and the technical solutions in the present invention are clearly and completely described, but the present invention is not limited to the following implementations. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. According to the following description and claims, the advantages and features of the present invention will be clearer. It should be noted that the drawings are all in a very simplified form and use non-precise ratios, which are only used to conveniently and clearly assist in explaining the embodiments of the present invention. All other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0030] The present invention can be implemented in different forms and should not be interpreted as being limited to the embodiments proposed herein. On the contrary, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the present invention to those skilled in the art. In the accompanying drawings, for clarity, the size and relative size of the layers and zones may be exaggerated, and the same reference numerals represent the same elements from beginning to end. In the description of the present application, it should be noted that the orientation or positional relationship indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inside", "outside", etc. is based on the orientation or positional relationship shown in the accompanying drawings, only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation to the present application. In addition, the terms "first", "second", and "third" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance.

[0031] In order to solve the technical problems introduced in the background technology part, the present invention provides a new structure. The embodiment mainly adopts a low-resistance P-type substrate 101-2 combined with a lightly doped P-type epitaxial 102. The high-concentration (low-resistance) P-type substrate 101-2 can suppress the opening of the parasitic NPN tube and improve Vhold (holding voltage / clamping voltage). The lightly doped P-type epitaxial ensures that the PN junction breakdown voltage of the DTI will not decrease or even increase, which meets the application of DTI when the P-type substrate is suspended.

[0032] Specifically, the double-layer epitaxial isolation structure described in the present invention has a structure as follows: Figure 6As shown, a P-type first epitaxial layer 102 is provided on a P-type semiconductor substrate 101-2, and an N-type implantation layer formed by ion implantation is provided on the surface of the first epitaxial layer 102 as a buried layer 103. The substrate is a heavily doped low-resistance substrate, such as a silicon substrate, or other semiconductor materials such as a germanium silicon substrate, a gallium arsenide substrate, a gallium nitride substrate, or a silicon carbide substrate. The first epitaxial layer is a lightly doped P-type epitaxial layer, and its doping concentration is much lower than that of the substrate below it.

[0033] A conventional P-type second epitaxial layer 104 is provided above the buried layer 103 , and ion implantation is performed in the second epitaxial layer to form an N-type deep well 104 .

[0034] The surface layer of the second epitaxial layer has a shallow trench isolation structure 105 formed by etching and filling, and the shallow trench isolation structure has a deep trench etched and filled with polysilicon 106, and the deep trench is etched downward to a depth that passes through the buried layer 103 and its bottom is located in the first epitaxial layer 102. The substrate at the bottom of the deep trench has a P-type trench bottom injection region 107, and the trench bottom injection region 107 can suppress the penetration of the N-type regions on both sides of the deep trench.

[0035] The shallow trench isolation structure has an N-type well region 108 .

[0036] The well region 108 also has a heavily doped region as a lead-out region 109 formed by simultaneous injection of source and drain implants into the active region.

[0037] The process method of the double-layer epitaxial isolation structure of the present invention is as follows: Figures 1 to 6 As shown, the process steps include: A P-type heavily doped low-resistance silicon substrate 101-2 is provided, and a lightly doped P-type first epitaxial layer 102 is grown on the substrate 101-2. Then, ion implantation is performed to form an N-type implantation layer as a buried layer 103 on the epitaxial layer. Figure 1 shown.

[0038] The epitaxial growth is continued to grow a conventional P-type second epitaxial layer, and then N-type ions are implanted in the second epitaxial layer to form an N-type deep well 104 in the first conductivity type epitaxial layer. Figure 2 shown.

[0039] like Figure 3 As shown, the first photolithography, etching and silicon oxide filling processes are performed synchronously by sharing the active area photolithography and filling processes to form a shallow trench isolation structure 105 on the surface of the epitaxial layer. A high aspect ratio etching is performed in the shallow trench isolation structure to form a deep trench. The area of ​​the deep trench is smaller than that of the shallow trench isolation structure. P-type ion implantation is performed in the bottom substrate layer of the deep trench to form a P-type bottom trench implantation region 107; the deep trench is filled with polysilicon material to fill the deep trench 106. Figure 4 shown.

[0040] like Figure 5 As shown, the second photolithography opens an ion implantation window and performs ion implantation to form an N-type well region 108 outside the shallow trench isolation structure 105 .

[0041] Optionally, an N-type heavily doped region is formed in the well region 108 as a lead-out region 109. Figure 6 As shown, the lead-out region 109 on one side is connected to the high voltage end, and the lead-out region 109 on the other side is connected to the low voltage end, and is isolated by a deep trench isolation structure to prevent crosstalk or leakage between devices.

[0042] By inverting the P-type or N-type in each of the above structures or steps, a device of the opposite type can be produced.

[0043] The double-layer epitaxial deep trench isolation structure described in the present invention uses a low-resistance substrate combined with a lightly doped first epitaxial layer. The high-concentration (low-resistance) substrate can suppress the NPN from turning on, improve Vhold (holding voltage / clamping voltage), and the lightly doped first epitaxial layer optimizes the electric field distribution, ensuring that the PN junction breakdown voltage of DTI will not decrease or even increase, meeting the application requirements of DTI when the substrate is suspended. For details, please refer to Figure 7 The simulation curve diagram shown in FIG. In the simulation diagram, the horizontal axis represents the breakdown voltage, and Vhold is an inflection point on the curve. It can be seen that the Vhold of the structure of the present invention is significantly improved, and the PN junction breakdown voltage BV is also improved compared with the original structure.

[0044] The above are only preferred embodiments of the present invention and are not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A process for a double-layer epitaxial isolation structure, characterized in that: The process steps include: Providing a semiconductor substrate of the first conductivity type, growing a first epitaxial layer of the first conductivity type on the semiconductor substrate of the first conductivity type; then performing ion implantation to form an implantation layer of the second conductivity type as a buried layer on the epitaxial layer; Continue epitaxial growth to grow a second epitaxial layer of the first conductivity type, then perform ion implantation of the second conductivity type in the second epitaxial layer to form a deep well of the second conductivity type in the epitaxial layer of the first conductivity type; Performing a first photolithography, etching and filling process to form a shallow trench isolation structure on the surface of the epitaxial layer; Performing high aspect ratio etching in the shallow trench isolation structure to form a deep trench; the area of ​​the deep trench is smaller than that of the shallow trench isolation structure; performing ion implantation in the bottom substrate layer of the deep trench to form a first conductive type trench bottom implantation region; and filling the deep trench with a material to fill the deep trench completely; The second photolithography opens an ion implantation window and performs ion implantation to form a well region of the second conductivity type outside the shallow trench isolation structure.

2. The process for producing a double-layer epitaxial isolation structure according to claim 1, wherein: The semiconductor substrate is a heavily doped low-resistance substrate, and its material is a silicon substrate, a silicon germanium substrate, a gallium arsenide substrate, a gallium nitride substrate or a silicon carbide substrate.

3. The process for producing a double-layer epitaxial isolation structure according to claim 1, wherein: The injection layer is heavily doped with the second conductivity type to form a buried layer structure.

4. The process for producing a double-layer epitaxial isolation structure according to claim 1, wherein: The first photolithography, etching and filling process is completed synchronously by sharing the active area photolithography and filling process; the shallow trench isolation structure is filled with silicon oxide material.

5. The process for producing a double-layer epitaxial isolation structure according to claim 1, wherein: The first epitaxial layer is a lightly doped epitaxial layer of the first conductivity type.

6. The process for producing a double-layer epitaxial isolation structure according to claim 1, wherein: The deep trench is filled with polysilicon material.

7. The process for producing a double-layer epitaxial isolation structure according to claim 1, wherein: It also includes forming a heavily doped region of the second conductivity type in the well region as a lead-out region.

8. The process for producing a double-layer epitaxial isolation structure according to claim 7, wherein: The heavily doped region is formed synchronously by an ion implantation process when the shared active region source and drain region are implanted.

9. The process for the double-layer epitaxial isolation structure according to any one of claims 1 to 8, characterized in that: The first conductivity type is P type, and the second conductivity type is N type; when manufacturing a device of opposite type, the first conductivity type and the second conductivity type can be inverted.

10. A double-layer epitaxial isolation structure, characterized in that: A first epitaxial layer of a second conductivity type is provided on a semiconductor substrate of a first conductivity type, and an implanted layer of the second conductivity type formed by ion implantation is provided on a surface layer of the first epitaxial layer as a buried layer; A second epitaxial layer of the first conductivity type is provided above the buried layer, and ion implantation is performed in the second epitaxial layer to form a deep well of the second conductivity type; A shallow trench isolation structure formed by etching and filling is provided on the surface of the second epitaxial layer, and a deep trench etched and filled with semiconductor material is provided in the shallow trench isolation structure, and the deep trench is etched downward to a depth that passes through the buried layer and its bottom is located in the first epitaxial layer; The shallow trench isolation structure has a well region of the second conductivity type.

11. The double-layer epitaxial isolation structure according to claim 10, characterized in that: The semiconductor substrate is a heavily doped low-resistance substrate, including a silicon substrate, a silicon germanium substrate, a gallium arsenide substrate, a gallium nitride substrate or a silicon carbide substrate.

12. The double-layer epitaxial isolation structure according to claim 10, characterized in that: The first epitaxial layer is a lightly doped epitaxial layer.

13. The double-layer epitaxial isolation structure according to claim 10, characterized in that: The bottom of the deep trench also has a trench bottom implantation region of the first conductivity type to prevent the second conductivity type regions on both sides of the deep trench from penetrating.

14. The double-layer epitaxial isolation structure according to claim 10, characterized in that: The well region also has a heavily doped region as a lead-out region formed by synchronous injection of source and drain injection into the active region.

15. The double-layer epitaxial isolation structure according to claim 10, characterized in that: The material filled in the deep trench is polysilicon.

16. The double-layer epitaxial isolation structure according to any one of claims 10 to 15, characterized in that: The first conductivity type is P type, and the second conductivity type is N type; when manufacturing a device of opposite type, the first conductivity type and the second conductivity type can be inverted.

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