Screening method for parallel current sharing of power semiconductor chips and electronic equipment

Abstract

The invention provides a screening method for parallel current sharing of power semiconductor chips and electronic equipment, and the method comprises the steps: obtaining chip parameters corresponding to each power semiconductor chip, sorting the plurality of power semiconductor chips according to the plurality of chip parameters, and obtaining a chip combination, the chip parameters are parameters representing the characteristics of the power semiconductor chip; circuit parameters corresponding to all branches in the power module are obtained, the multiple branches are sorted according to the multiple circuit parameters, a branch combination is obtained, and the circuit parameters are parameters representing the characteristics of the branches; and connecting the power semiconductor chips in the chip combination into the branches in the branch combination in sequence to obtain a target power module. According to the method and the device, the problem of low chip utilization rate caused by the fact that the threshold voltage of the chip is required to be consistent in a chip screening method based on threshold voltage consistency in the prior art is solved.

Description

Technical Field

[0001] The present application relates to the technical field of electronic chips, and in particular to a screening method for current sharing of parallel power semiconductor chips, a computer-readable storage medium, a computer program product, and an electronic device. Background Art

[0002] With the rapid development of electronic technology and power systems, the demand for high-performance power devices is increasing. Traditional silicon-based power semiconductor devices have been widely used in many industrial fields, especially in power systems. However, with the continuous improvement of application requirements, the performance limitations of traditional silicon-based materials under high voltage and high temperature conditions have gradually emerged, and it is difficult to meet the requirements of modern industry for higher voltage and higher reliability. Silicon carbide (SiC), as a wide bandgap semiconductor material, has gradually become an ideal choice for high-power and high-temperature applications due to its significantly superior properties to silicon (Si) materials. SiC MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) has a higher breakdown electric field and a wider bandgap width, enabling it to operate stably at higher voltages and temperatures. Specifically, the critical breakdown electric field of SiC is about ten times that of silicon, allowing SiC devices to withstand higher voltages while having lower on-resistance. In addition, the thermal conductivity of SiC is more than three times that of silicon, which means that SiC devices can dissipate heat more effectively under high power and high temperature conditions, thereby improving the reliability and efficiency of the system. SiC devices also have higher electron saturation velocity and lower switching losses, making them excel in high-frequency applications.

[0003] However, in practical applications, there is a problem of uneven current distribution when SiC MOSFETs are used in parallel, which is mainly caused by differences in parasitic parameters and manufacturing processes. Uneven current distribution can cause reliability problems and even module failure. Specifically, the mismatch of circuit parasitic inductance caused by asymmetric circuit layout is an important factor leading to uneven current distribution.

[0004] The prior art solution is to screen chips based on consistent threshold voltages. By screening chips with similar threshold voltages and connecting them in parallel, the dynamic current sharing of the chips under a symmetrical layout can achieve better results, which is only applicable to power modules with symmetrical layouts. However, for asymmetric layouts, circuit parameters do not match, and the dynamic current distribution current of parallel chips is still unbalanced, and cannot be associated with circuit layout parameters, and this method cannot achieve static current sharing of parallel chips. Screening chips based on consistent threshold voltages is difficult in actual operation. Due to differences in manufacturing processes, even devices produced in the same batch have a certain distribution range of threshold voltages. Therefore, it is a very challenging task to find devices with completely consistent threshold voltages. The screening process requires a lot of time and labor costs, and the qualified rate after screening is low, resulting in a decrease in production efficiency. Secondly, this method does not take into account the influence of inconsistent parasitic inductances of each branch caused by asymmetric circuit layout. There is still a large dynamic unbalanced current between parallel chips, which is not effective in practical applications. Summary of the invention

[0005] The main purpose of the present application is to provide a screening method for parallel current sharing of power semiconductor chips, a computer-readable storage medium, a computer program product and an electronic device, so as to at least solve the problem in the prior art that the method for chip screening based on threshold voltage consistency requires the threshold voltage of the chip to be consistent, resulting in low chip utilization.

[0006] In order to achieve the above-mentioned purpose, according to one aspect of the present application, a screening method for parallel current sharing of power semiconductor chips is provided. There are multiple power semiconductor chips, and the power module includes multiple parallel branches. The power semiconductor chips are used to be connected to the branches one by one. The method includes: obtaining chip parameters corresponding to each of the power semiconductor chips, and sorting the multiple power semiconductor chips according to the multiple chip parameters to obtain a chip combination, and the chip parameters are parameters that characterize the characteristics of the power semiconductor chips; obtaining circuit parameters corresponding to each of the branches in the power module, and sorting the multiple branches according to the multiple circuit parameters to obtain a branch combination, and the circuit parameters are parameters that characterize the characteristics of the branches; connecting the power semiconductor chips in the chip combination to the branches in the branch combination in sequence to obtain a target power module.

[0007] Optionally, chip parameters corresponding to each of the power semiconductor chips are obtained, and the multiple power semiconductor chips are sorted according to the multiple chip parameters to obtain a chip combination, including: obtaining a threshold voltage corresponding to each of the power semiconductor chips, and sorting and numbering the multiple power semiconductor chips in sequence according to the sizes of the corresponding threshold voltages to obtain the chip combination, wherein the power semiconductor chip with a smaller serial number in the chip combination has a smaller threshold voltage.

[0008] Optionally, circuit parameters corresponding to each branch in the power module are obtained, and multiple branches are sorted according to the multiple circuit parameters to obtain a branch combination, including: obtaining a branch current corresponding to each branch, and sorting and numbering the multiple branches in sequence according to the magnitude of the corresponding branch current to obtain the branch combination, wherein the branch with a smaller serial number in the branch combination has a smaller branch current.

[0009] Optionally, obtaining the branch current corresponding to each of the branches includes: modeling the circuit topology structure of the power module, and obtaining the branch current corresponding to each of the branches according to the modeled circuit topology structure.

[0010] Optionally, there are k power modules, each of which includes m branches, and there are N power semiconductor chips, k=N / m. The power semiconductor chips in the chip combination are sequentially connected to the branches in the branch combination, including: grouping the chip combination according to the serial numbers of the power semiconductor chips in the chip combination to obtain m first combinations arranged in order, each of the first combinations including k power semiconductor chips, wherein the serial numbers of all the power semiconductor chips in the first first combination are 1~k, the serial numbers of all the power semiconductor chips in the second first combination are k+1~2k, and the serial numbers of all the power semiconductor chips in the mth first combination are Nk~N; sorting and numbering the k power modules in turn to obtain a module combination; and connecting the power semiconductor chip in the ith first combination to the ith branch of each power module in turn according to the serial numbers of the power modules in the module combination.

[0011] Optionally, there are k power modules, each of which includes m branches, and there are N power semiconductor chips, mk<N<m(k+1), and the power semiconductor chips in the chip combination are sequentially connected to the branches in the branch combination, including: removing all the power semiconductor chips after the nth power semiconductor chip in the chip combination to obtain a target chip combination, wherein n=mk, and the serial numbers of all the power semiconductor chips in the target chip combination are 1 to n; grouping the target chip combination according to the serial numbers of the power semiconductor chips in the target chip combination to obtain m first combinations arranged in sequence, each of which includes k power semiconductor chips, wherein all the power semiconductor chips in the first first combination are serially numbered 1 to k, all the power semiconductor chips in the second first combination are serially numbered k+1 to 2k, and all the power semiconductor chips in the mth first combination are serially numbered nk to n; the k power modules are sequentially sorted and numbered to obtain module combinations; and according to the serial numbers of the power modules in the module combinations, the power semiconductor chips in the ith first combination are sequentially connected to the ith branch of each power module.

[0012] Optionally, after obtaining the target power module, the method further includes: packaging the target power module.

[0013] According to another aspect of the present application, a computer-readable storage medium is provided, wherein the computer-readable storage medium includes a stored program, wherein when the program is run, the device where the computer-readable storage medium is located is controlled to execute any one of the screening methods for parallel current sharing of power semiconductor chips.

[0014] According to another aspect of the present application, a computer program product is provided, comprising computer instructions, wherein when the computer instructions are executed by a processor, any one of the screening methods for current sharing of parallel power semiconductor chips is implemented.

[0015] According to another aspect of the present application, an electronic device is provided, comprising: one or more processors, a memory, and one or more programs, wherein the one or more programs are stored in the memory and are configured to be executed by the one or more processors, and the one or more programs include a method for executing any one of the screening methods for parallel current sharing of power semiconductor chips.

[0016] Applying the technical solution of the present application, firstly, the chip parameters corresponding to each power semiconductor chip are obtained, and according to a plurality of chip parameters, a plurality of power semiconductor chips are sorted to obtain a chip combination, and then the circuit parameters corresponding to each branch in the power module are obtained, and according to a plurality of circuit parameters, a plurality of branches are sorted to obtain a branch combination, and finally the power semiconductor chips in the chip combination are sequentially connected to the branches in the branch combination to obtain a target power module. Compared with the problem that the chip utilization rate is low due to the chip threshold voltage consistency method based on the prior art, the present application screens the chip according to the chip parameters and the circuit parameters, so that the chip screening index can be associated with the circuit parameters, ensuring that even if the circuit layout of the power module is asymmetric, the parallel current sharing can be achieved based on the simultaneous regulation of the chip parameters and the circuit parameters, without requiring the chip threshold voltage to be consistent, and for the dispersed chips, a good current sharing effect can also be achieved, ensuring a high chip utilization rate. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The drawings constituting part of the present application are used to provide a further understanding of the present application. The exemplary embodiments and descriptions of the present application are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0018] Figure 1 It is a hardware structure block diagram of a mobile terminal for executing a screening method for parallel current sharing of power semiconductor chips provided in an embodiment of the present application;

[0019] Figure 2 It is a flow chart of a method for screening current sharing of power semiconductor chips in parallel provided in an embodiment of the present application;

[0020] Figure 3 It is a schematic diagram of an output characteristic curve of a power semiconductor chip provided according to an embodiment of the present application.

[0021] The above drawings include the following reference numerals:

[0022] 102, processor; 104, memory; 106, transmission device; 108, input and output devices. DETAILED DESCRIPTION

[0023] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0024] In order to enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of this application.

[0025] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequential order. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present application described here. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0026] As introduced in the background technology, the circuit layout of the chip screening method based on consistent threshold voltage in the prior art is asymmetric, resulting in mismatch of circuit parasitic inductance, and unable to achieve static current sharing of parallel chips. The screening is difficult and inefficient. To solve the above problems, the embodiments of the present application provide a screening method for parallel current sharing of power semiconductor chips, a computer-readable storage medium, a computer program product and an electronic device.

[0027] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the accompanying drawings in the embodiments of the present invention.

[0028] The method embodiments provided in the embodiments of the present application can be executed in a mobile terminal, a computer terminal or a similar computing device. Taking running on a mobile terminal as an example, Figure 1 1 is a hardware structure block diagram of a mobile terminal of a method for screening power semiconductor chips in parallel and current sharing according to an embodiment of the present invention. Figure 1 As shown, the mobile terminal may include one or more ( Figure 1 Only one is shown in the figure) a processor 102 (the processor 102 may include but is not limited to a processing device such as a microprocessor MCU or a programmable logic device FPGA) and a memory 104 for storing data, wherein the mobile terminal may also include a transmission device 106 and an input / output device 108 for communication functions. It can be understood by those skilled in the art that Figure 1 The structure shown is only for illustration and does not limit the structure of the mobile terminal. Figure 1 More or fewer components as shown, or with Figure 1 Different configurations are shown.

[0029] The memory 104 can be used to store computer programs, for example, software programs and modules of application software, such as the computer program corresponding to the screening method for parallel current sharing of power semiconductor chips in the embodiment of the present invention. The processor 102 executes various functional applications and data processing by running the computer program stored in the memory 104, that is, to implement the above method. The memory 104 may include a high-speed random access memory, and may also include a non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some examples, the memory 104 may further include a memory remotely arranged relative to the processor 102, and these remote memories can be connected to the mobile terminal via a network. Examples of the above-mentioned network include but are not limited to the Internet, an intranet, a local area network, a mobile communication network, and a combination thereof. The transmission device 106 is used to receive or send data via a network. The above-mentioned specific examples of the network may include a wireless network provided by a communication provider of the mobile terminal. In one example, the transmission device 106 includes a network adapter (Network Interface Controller, referred to as NIC), which can be connected to other network devices through a base station so as to communicate with the Internet. In one example, the transmission device 106 may be a radio frequency (RF) module, which is used to communicate with the Internet wirelessly.

[0030] In this embodiment, a method for screening parallel current sharing of power semiconductor chips running on a mobile terminal, a computer terminal or a similar computing device is provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and although a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0031] Figure 2 FIG. 1 is a flow chart of a method for screening power semiconductor chips for current sharing in parallel according to an embodiment of the present application. Figure 2 As shown, the method comprises the following steps:

[0032] Step S201, obtaining chip parameters corresponding to each power semiconductor chip, and sorting multiple power semiconductor chips according to the multiple chip parameters to obtain a chip combination, where the chip parameters are parameters that characterize the characteristics of the power semiconductor chip;

[0033] Step S202, obtaining circuit parameters corresponding to each branch in the power module, and sorting the multiple branches according to the multiple circuit parameters to obtain a branch combination, where the circuit parameters are parameters that characterize the characteristics of the branches;

[0034] Step S203, connecting the power semiconductor chips in the chip combination to the branches in the branch combination in sequence to obtain a target power module.

[0035] Through the above embodiments, firstly, the chip parameters corresponding to each power semiconductor chip are obtained, and according to a plurality of chip parameters, a plurality of power semiconductor chips are sorted to obtain a chip combination, and then the circuit parameters corresponding to each branch in the power module are obtained, and according to a plurality of circuit parameters, a plurality of branches are sorted to obtain a branch combination, and finally the power semiconductor chips in the chip combination are sequentially connected to the branches in the branch combination to obtain a target power module. Compared with the problem that the chip utilization rate is low due to the chip screening method based on threshold voltage consistency in the prior art, which requires the chip threshold voltage to be consistent, this application screens the chip according to chip parameters and circuit parameters, so that the chip screening index can be associated with the circuit parameters, ensuring that even if the circuit layout of the power module is asymmetric, parallel current sharing can be achieved based on the simultaneous regulation of chip parameters and circuit parameters, without the need for the chip threshold voltage to be consistent, and for chips with dispersion, a good current sharing effect can also be achieved, ensuring a high chip utilization rate.

[0036] It should be noted that chip parameters refer to the characteristics of the chip itself, such as threshold voltage and transfer curve, and circuit parameters refer to the parasitic parameters of each branch in the power module.

[0037] Specifically, the chip parameters may include but are not limited to maximum power, operating frequency, threshold voltage, on-resistance and other parameters.

[0038] According to some exemplary embodiments of the present application, chip parameters corresponding to each power semiconductor chip are obtained, and multiple power semiconductor chips are sorted according to the multiple chip parameters to obtain a chip combination, including: obtaining a threshold voltage corresponding to each power semiconductor chip, and sorting and numbering the multiple power semiconductor chips in sequence according to the magnitude of their corresponding threshold voltages to obtain a chip combination, wherein the power semiconductor chip with a smaller serial number in the chip combination has a smaller threshold voltage.

[0039] In this embodiment, the chip combination sorted and numbered according to the threshold voltage size can be used to implement the selection and configuration according to the characteristics of the power semiconductor chip in the parallel current sharing. By sorting according to the threshold voltage size, it can be ensured that the current distribution borne by each power semiconductor chip in the parallel current sharing process is more uniform. It can also be used to make it easier to locate and replace the problem chip when a fault occurs, thereby improving the efficiency of maintenance and management.

[0040] Figure 3 It is a schematic diagram of the output characteristic curve of the power semiconductor chip, such as Figure 3 As shown, the threshold voltage parameters of the power semiconductor chip are obtained. The threshold voltage is the gate-source voltage when the drain current of the chip reaches 5mA during the turn-on process, that is, V th The threshold voltage of the power semiconductor chip is tested using a power analyzer or other test platform. The threshold voltage is selected as the sorting parameter. Assuming that there are N chips in total, all chips are sorted in order from small to large according to the threshold voltage, 1 to N respectively.

[0041] According to some exemplary embodiments of the present application, circuit parameters corresponding to each branch in the power module are obtained, and multiple branches are sorted according to multiple circuit parameters to obtain a branch combination, including: obtaining a branch current corresponding to each branch, and sorting and numbering the multiple branches in sequence according to the magnitude of their corresponding branch currents to obtain a branch combination, wherein the smaller the sequence number of the branch in the branch combination, the smaller the branch current.

[0042] In this embodiment, sorting and numbering the branches according to their current magnitudes helps determine the current magnitude of each branch, so that each branch can bear a relatively uniform current load, effectively avoiding malfunctions or failures caused by branch overloads.

[0043] Specifically, the branches are sorted and named according to the current distribution size of each branch. The branch with the smallest current is ranked 1, and then the branches are sorted in ascending order according to the branch current size. Assuming there are m branches, the branch with the largest current is named branch m.

[0044] According to some exemplary embodiments of the present application, obtaining branch currents corresponding to each branch includes: modeling a circuit topology structure of a power module, and obtaining branch currents corresponding to each branch according to the modeled circuit topology structure.

[0045] In this embodiment, modeling the circuit topology of the power module helps to understand the connection method and relationship between the various parts in the circuit, so as to better analyze the performance and working status of the circuit. According to the modeled circuit topology, the branch current corresponding to each branch can be calculated, so as to understand the current distribution of each branch.

[0046] Specifically, the current distribution of the internal parallel chips is analyzed through power module modeling, the circuit topology is modeled according to the internal structure of the applied power module, and the current distribution characteristics of the parallel branches are analyzed without considering the chip parameter differences.

[0047] It should be noted that the parallel branches refer to the branches in the power module. The parasitic inductance of each branch may be different. Each branch corresponds to a chip. The power module is a module in which multiple chips are packaged into one through welding, bonding and other packaging processes.

[0048] Specifically, the branch current corresponding to each branch in the power module is obtained without considering the chip parameter difference. Not considering the chip parameter difference means that the inherent characteristics of the default chip are the same, that is, the parameters such as the threshold voltage and the transfer curve are consistent.

[0049] According to some exemplary embodiments of the present application, there are k power modules, the power modules include m branches, there are N power semiconductor chips, k=N / m, and the power semiconductor chips in the chip combination are connected to the branches in the branch combination in sequence, including: grouping the chip combinations according to the serial numbers of the power semiconductor chips in the chip combination to obtain m first combinations arranged in order, each first combination includes k power semiconductor chips, wherein the serial numbers of all the power semiconductor chips in the first first combination are 1~k, the serial numbers of all the power semiconductor chips in the second first combination are k+1~2k, and the serial numbers of all the power semiconductor chips in the mth first combination are Nk~N; sorting and numbering the k power modules in sequence to obtain a module combination; according to the serial numbers of the power modules in the module combination, connecting the power semiconductor chip in the ith first combination to the ith branch of each power module in sequence.

[0050] In this embodiment, by grouping the power semiconductor chips in the chip combination according to the serial numbers and connecting the power semiconductor chips in each first combination to the branches of each power module in turn, it can be ensured that the current load of the power semiconductor chips in each power module is relatively balanced. By sorting and numbering the power modules in the module combination, the modules can be conveniently managed and monitored, making system maintenance more convenient.

[0051] Specifically, when grouping power semiconductor chips, if there are N power semiconductor chips that can use m branches, there are k power modules, where k = N / m, and the chip parameters are sorted from small to large, k power semiconductor chips are taken in sequence and placed in m branches, that is, power semiconductor chips No. 1-k are used in branch 1, power semiconductor chips No. k+1 to 2k are used in branch 2, and so on, power semiconductor chips No. nk to n are used in branch m.

[0052] According to some exemplary embodiments of the present application, there are k power modules, the power modules include m branches, there are N power semiconductor chips, mk<N<m(k+1), and the power semiconductor chips in the chip combination are sequentially connected to the branches in the branch combination, including: removing all power semiconductor chips located after the nth power semiconductor chip in the chip combination to obtain a target chip combination, wherein n=mk, and the serial numbers of all the power semiconductor chips in the target chip combination are 1~n; grouping the target chip combination according to the serial numbers of the power semiconductor chips in the target chip combination to obtain m first combinations arranged in sequence, each first combination including k power semiconductor chips, wherein the serial numbers of all the power semiconductor chips in the first first combination are 1~k, the serial numbers of all the power semiconductor chips in the second first combination are k+1~2k, and the serial numbers of all the power semiconductor chips in the mth first combination are nk~n; sorting and numbering the k power modules in sequence to obtain a module combination; according to the serial numbers of the power modules in the module combination, connecting the power semiconductor chips in the ith first combination to the ith branch of each power module in sequence.

[0053] In this embodiment, by grouping and connecting the power semiconductor chips in a specified order and determining the order and quantity of the power semiconductor chips included in each module, overloading of the power semiconductor chips in some modules can be effectively avoided.

[0054] Specifically, when N / m has a remainder, the remaining power semiconductor chips cannot be used. Assuming that there are t power semiconductor chips remaining, t power semiconductor chips can be taken starting from the power semiconductor chip with the largest ranking. The number of remaining power semiconductor chips is n=Nt, which can just achieve k=n / m.

[0055] In some other optional solutions of the present application, after obtaining the target power module, the method further includes: packaging the target power module.

[0056] In this embodiment, the packaging of the target power module can protect the power semiconductor chip and prevent it from being damaged by the external environment. Through packaging, the heat and electrical signals between the parallel chips can be effectively isolated, ensuring that each chip can share the load in a balanced manner during operation. It can also reduce mutual interference between parallel chips, thereby improving the reliability and stability of the module and facilitating the installation and use of the module.

[0057] Specifically, k power modules are packaged, power module 1 takes the power semiconductor chip with the smallest chip ranking in each group, power module 2 takes the power semiconductor chip with the second smallest chip ranking in each group, and so on, power module k takes the power semiconductor chip with the largest chip ranking in each group, and the k power modules packaged in this way all use chip parameters to adjust packaging parameters, taking into account the overall adjustment effect.

[0058] The technical solution provided by the above-mentioned embodiment of the present invention solves the problem in the prior art that chip screening parameters cannot be associated with circuit parameters. It does not require the threshold voltage of the chip to be consistent. For chips with dispersion, a good current sharing effect can also be achieved, thereby improving the utilization rate of parallel applications of power semiconductor chips. In addition, most modules on the market are mostly asymmetric in layout for higher power density. The method based on threshold voltage compensation uses chip parameters to compensate for the influence caused by the difference in parasitic parameters of each branch to achieve the purpose of dynamic current sharing. It is more extensive in practical applications and has better effects, significantly improves the current distribution of SiC MOSFET, and improves the reliability and performance of the system.

[0059] From the above, it can be seen that in an embodiment of the present invention, a method for parallel current sharing screening of power semiconductor chips is proposed. The screening parameters proposed by the screening method are simple and easy to measure, and can be associated with circuit parameters. That is, for branches with large parasitic parameters, chips with small threshold voltages should be selected. This can be used for dynamic parallel current sharing regulation based on chip parameters and circuit parameters, and can meet the dynamic parallel current sharing application of multiple groups of chips. The screening results can minimize the overall unbalanced current of multiple groups of chips. Compared with the traditional method based on consistent threshold voltage, the chip utilization rate is greatly improved.

[0060] In summary, the screening method for parallel current sharing of power semiconductor chips provided in an embodiment of the present invention takes into account various factors, and the proposed chip screening indicators can be associated with circuit parameters, which can be used in a technical solution for realizing dynamic parallel current sharing based on simultaneous regulation of chip parameters and circuit parameters. At the same time, it can be used for parallel current sharing applications among multiple groups of chips, so that the overall unbalanced current of multiple groups of parallel chips is minimized, greatly improving the effective utilization rate of the chips, and has been verified by experiments. The experimental results show that the power semiconductor chip screening method proposed in this article can realize the dynamic current sharing application of parallel chips.

[0061] In order to enable those skilled in the art to more clearly understand the technical solution of the present application, the implementation process of the method for screening parallel current sharing of power semiconductor chips of the present application will be described in detail below in combination with specific embodiments.

[0062] This embodiment relates to a specific method for screening power semiconductor chips for current sharing in parallel, wherein there are multiple power semiconductor chips, and a power module includes multiple parallel branches. The power semiconductor chips are used to be connected to the branches one by one, and the method specifically includes the following steps:

[0063] Step S1: Select a measuring device to obtain the threshold voltage of all power semiconductor chips;

[0064] Step S2: sort all power semiconductor chips according to threshold voltage and number them from 1 to N;

[0065] Step S3: Model the power module. When the default threshold voltage is consistent, obtain the branch current of each branch and label them. The branch with the smallest current is ranked No. 1. Assuming there are m branches, the branch with the largest current is No. m.

[0066] Step S4: Grouping the power semiconductor chips: If there are N power semiconductor chips, each power semiconductor chip has m branches, k power modules can be packaged, where k = N / m (if N / m has a remainder, the remaining power semiconductor chips cannot be used. Assuming that there are t chips left, t chips can be taken from the chip with the largest ranking), the number of remaining chips is n = Nt, which can just achieve k = n / m; according to the order of threshold voltage from small to large, k chips are taken in sequence and put into m branches, that is, chips No. 1-k are applied to branch 1, chips No. k+1 to No. 2k are applied to branch 2, and so on, chips No. nk to No. n are applied to branch m;

[0067] Step S5: packaging into k power modules: power module 1 takes the smallest power semiconductor chip in each group, power module 2 takes the second smallest power semiconductor chip in each group, and so on, power module k takes the largest power semiconductor chip in each group.

[0068] It should be noted that the steps shown in the flowcharts of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and that, although a logical order is shown in the flowcharts, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0069] An embodiment of the present invention provides a computer-readable storage medium, wherein the computer-readable storage medium includes a stored program, wherein when the program is executed, a device where the computer-readable storage medium is located is controlled to execute a Z method.

[0070] Specifically, the screening method for parallel current sharing of power semiconductor chips includes:

[0071] Step S201, obtaining chip parameters corresponding to each power semiconductor chip, and sorting multiple power semiconductor chips according to the multiple chip parameters to obtain a chip combination, where the chip parameters are parameters that characterize the characteristics of the power semiconductor chip;

[0072] Step S202, obtaining circuit parameters corresponding to each branch in the power module, and sorting the multiple branches according to the multiple circuit parameters to obtain a branch combination, where the circuit parameters are parameters that characterize the characteristics of the branches;

[0073] Step S203, connecting the power semiconductor chips in the chip combination to the branches in the branch combination in sequence to obtain a target power module.

[0074] Optionally, chip parameters corresponding to each power semiconductor chip are obtained, and multiple power semiconductor chips are sorted according to the multiple chip parameters to obtain a chip combination, including: obtaining a threshold voltage corresponding to each power semiconductor chip, and sorting and numbering the multiple power semiconductor chips in sequence according to the size of their corresponding threshold voltages to obtain a chip combination, wherein the power semiconductor chip with a smaller serial number in the chip combination has a smaller threshold voltage.

[0075] Optionally, circuit parameters corresponding to each branch in the power module are obtained, and multiple branches are sorted according to multiple circuit parameters to obtain a branch combination, including: obtaining a branch current corresponding to each branch, and sorting and numbering the multiple branches in sequence according to the size of their corresponding branch currents to obtain a branch combination, wherein the branch with a smaller serial number in the branch combination has a smaller branch current.

[0076] Optionally, obtaining the branch current corresponding to each branch includes: modeling the circuit topology structure of the power module, and obtaining the branch current corresponding to each branch according to the modeled circuit topology structure.

[0077] Optionally, there are k power modules, the power modules include m branches, there are N power semiconductor chips, k=N / m, and the power semiconductor chips in the chip combination are connected to the branches in the branch combination in sequence, including: grouping the chip combination according to the serial numbers of the power semiconductor chips in the chip combination to obtain m first combinations arranged in order, each first combination includes k power semiconductor chips, wherein the serial numbers of all the power semiconductor chips in the first first combination are 1~k, the serial numbers of all the power semiconductor chips in the second first combination are k+1~2k, and the serial numbers of all the power semiconductor chips in the mth first combination are Nk~N; sorting and numbering the k power modules in sequence to obtain a module combination; according to the serial numbers of the power modules in the module combination, connecting the power semiconductor chip in the ith first combination to the ith branch of each power module in sequence.

[0078] Optionally, there are k power modules, the power modules include m branches, there are N power semiconductor chips, mk<N<m(k+1), and the power semiconductor chips in the chip combination are sequentially connected to the branches in the branch combination, including: removing all power semiconductor chips located after the nth power semiconductor chip in the chip combination to obtain a target chip combination, wherein n=mk, and the serial numbers of all the power semiconductor chips in the target chip combination are 1~n; grouping the target chip combination according to the serial numbers of the power semiconductor chips in the target chip combination to obtain m first combinations arranged in sequence, each first combination includes k power semiconductor chips, wherein the serial numbers of all the power semiconductor chips in the first first combination are 1~k, the serial numbers of all the power semiconductor chips in the second first combination are k+1~2k, and the serial numbers of all the power semiconductor chips in the mth first combination are nk~n; sorting and numbering the k power modules in sequence to obtain a module combination; and connecting the power semiconductor chip in the ith first combination to the ith branch of each power module in sequence according to the serial numbers of the power modules in the module combination.

[0079] Optionally, after obtaining the target power module, the method further includes: packaging the target power module.

[0080] The present application also provides a computer program product, including computer instructions, which, when executed by a processor, implement at least the following method steps: step S201, obtaining chip parameters corresponding to each power semiconductor chip, and sorting the multiple power semiconductor chips according to multiple chip parameters to obtain a chip combination, wherein the chip parameters are parameters characterizing the characteristics of the power semiconductor chip; step S202, obtaining circuit parameters corresponding to each branch in the power module, and sorting the multiple branches according to multiple circuit parameters to obtain a branch combination, wherein the circuit parameters are parameters characterizing the characteristics of the branches; step S203, connecting the power semiconductor chips in the chip combination to the branches in the branch combination in sequence to obtain a target power module.

[0081] Optionally, chip parameters corresponding to each power semiconductor chip are obtained, and multiple power semiconductor chips are sorted according to the multiple chip parameters to obtain a chip combination, including: obtaining a threshold voltage corresponding to each power semiconductor chip, and sorting and numbering the multiple power semiconductor chips in sequence according to the size of their corresponding threshold voltages to obtain a chip combination, wherein the power semiconductor chip with a smaller serial number in the chip combination has a smaller threshold voltage.

[0082] Optionally, circuit parameters corresponding to each branch in the power module are obtained, and multiple branches are sorted according to multiple circuit parameters to obtain a branch combination, including: obtaining a branch current corresponding to each branch, and sorting and numbering the multiple branches in sequence according to the size of their corresponding branch currents to obtain a branch combination, wherein the branch with a smaller serial number in the branch combination has a smaller branch current.

[0083] Optionally, obtaining the branch current corresponding to each branch includes: modeling the circuit topology structure of the power module, and obtaining the branch current corresponding to each branch according to the modeled circuit topology structure.

[0084] Optionally, there are k power modules, the power modules include m branches, there are N power semiconductor chips, k=N / m, and the power semiconductor chips in the chip combination are connected to the branches in the branch combination in sequence, including: grouping the chip combination according to the serial numbers of the power semiconductor chips in the chip combination to obtain m first combinations arranged in order, each first combination includes k power semiconductor chips, wherein the serial numbers of all the power semiconductor chips in the first first combination are 1~k, the serial numbers of all the power semiconductor chips in the second first combination are k+1~2k, and the serial numbers of all the power semiconductor chips in the mth first combination are Nk~N; sorting and numbering the k power modules in sequence to obtain a module combination; according to the serial numbers of the power modules in the module combination, connecting the power semiconductor chip in the ith first combination to the ith branch of each power module in sequence.

[0085] Optionally, there are k power modules, the power modules include m branches, there are N power semiconductor chips, mk<N<m(k+1), and the power semiconductor chips in the chip combination are sequentially connected to the branches in the branch combination, including: removing all power semiconductor chips located after the nth power semiconductor chip in the chip combination to obtain a target chip combination, wherein n=mk, and the serial numbers of all the power semiconductor chips in the target chip combination are 1~n; grouping the target chip combination according to the serial numbers of the power semiconductor chips in the target chip combination to obtain m first combinations arranged in sequence, each first combination includes k power semiconductor chips, wherein the serial numbers of all the power semiconductor chips in the first first combination are 1~k, the serial numbers of all the power semiconductor chips in the second first combination are k+1~2k, and the serial numbers of all the power semiconductor chips in the mth first combination are nk~n; sorting and numbering the k power modules in sequence to obtain a module combination; and connecting the power semiconductor chip in the ith first combination to the ith branch of each power module in sequence according to the serial numbers of the power modules in the module combination.

[0086] Optionally, after obtaining the target power module, the method further includes: packaging the target power module.

[0087] An embodiment of the present application also provides an electronic device, comprising: one or more processors, a memory, and one or more programs, wherein the one or more programs are stored in the memory and are configured to be executed by the one or more processors, and the one or more programs include a screening method for executing any one of parallel current sharing of power semiconductor chips.

[0088] Obviously, those skilled in the art should understand that the above modules or steps of the present invention can be implemented by a general computing device, they can be concentrated on a single computing device, or distributed on a network composed of multiple computing devices, they can be implemented by a program code executable by a computing device, so that they can be stored in a storage device and executed by the computing device, and in some cases, the steps shown or described can be executed in a different order than here, or they can be made into individual integrated circuit modules, or multiple modules or steps therein can be made into a single integrated circuit module for implementation. Thus, the present invention is not limited to any specific combination of hardware and software.

[0089] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application may adopt the form of a computer program product implemented in one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that include computer-usable program code.

[0090] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0091] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0092] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0093] In a typical configuration, a computing device includes one or more processors (CPU), input / output interfaces, network interfaces, and memory.

[0094] The memory may include non-permanent memory in a computer-readable medium, random access memory (RAM) and / or non-volatile memory in the form of read-only memory (ROM) or flash RAM. The memory is an example of a computer-readable medium.

[0095] Computer readable media include permanent and non-permanent, removable and non-removable media that can be implemented by any method or technology to store information. Information can be computer readable instructions, data structures, program modules or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disk read-only memory (CD-ROM), digital versatile disk (DVD) or other optical storage, magnetic cassettes, magnetic tape disk storage or other magnetic storage devices or any other non-transmission media that can be used to store information that can be accessed by a computing device. As defined herein, computer readable media does not include temporary computer readable media (transitory media), such as modulated data signals and carrier waves.

[0096] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0097] From the above description, it can be seen that the above embodiments of the present application achieve the following technical effects:

[0098] In the screening method for parallel current sharing of power semiconductor chips of the present application, firstly, the chip parameters corresponding to each power semiconductor chip are obtained, and the multiple power semiconductor chips are sorted according to multiple chip parameters to obtain a chip combination, and then the circuit parameters corresponding to each branch in the power module are obtained, and the multiple branches are sorted according to multiple circuit parameters to obtain a branch combination, and finally the power semiconductor chips in the chip combination are sequentially connected to the branches in the branch combination to obtain a target power module. Compared with the method of chip screening based on threshold voltage consistency in the prior art, which requires the threshold voltage of the chip to be consistent, resulting in low chip utilization, the present application screens the chips according to chip parameters and circuit parameters, so that the chip screening index can be associated with the circuit parameters, ensuring that even if the circuit layout of the power module is asymmetric, parallel current sharing can be achieved based on the simultaneous regulation of chip parameters and circuit parameters, without the need for the threshold voltage of the chip to be consistent, and for chips with dispersion, a good current sharing effect can also be achieved, ensuring a high chip utilization.

[0099] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A method for screening power semiconductor chips for current sharing in parallel, characterized in that: There are multiple power semiconductor chips, and the power module includes multiple parallel branches. The power semiconductor chips are used to be connected to the branches one by one. The method includes: Acquire chip parameters corresponding to each of the power semiconductor chips, and sort the multiple power semiconductor chips according to the multiple chip parameters to obtain a chip combination, wherein the chip parameters are parameters characterizing the characteristics of the power semiconductor chips; Obtaining circuit parameters corresponding to each branch in the power module, and sorting the multiple branches according to the multiple circuit parameters to obtain a branch combination, wherein the circuit parameters are parameters that characterize the characteristics of the branches; The power semiconductor chips in the chip combination are sequentially connected to the branches in the branch combination to obtain a target power module.

2. The method for screening power semiconductor chips for parallel current sharing according to claim 1, characterized in that: Obtaining chip parameters corresponding to each of the power semiconductor chips, and sorting the multiple power semiconductor chips according to the multiple chip parameters to obtain a chip combination, including: The threshold voltage corresponding to each of the power semiconductor chips is obtained, and the multiple power semiconductor chips are sorted and numbered in sequence according to the magnitude of the corresponding threshold voltage to obtain the chip combination, wherein the power semiconductor chip with a smaller sequence number in the chip combination has a smaller threshold voltage.

3. The method for screening power semiconductor chips for current sharing in parallel according to claim 2, characterized in that: Obtaining circuit parameters corresponding to each branch in the power module, and sorting the multiple branches according to the multiple circuit parameters to obtain a branch combination, including: The branch current corresponding to each of the branches is obtained, and the multiple branches are sequentially sorted and numbered according to the magnitudes of the corresponding branch currents to obtain the branch combination, wherein the branch with a smaller sequence number in the branch combination has a smaller branch current.

4. The method for screening power semiconductor chips for current sharing in parallel according to claim 3, characterized in that: Obtaining branch currents corresponding to the branches, including: The circuit topology structure of the power module is modeled, and the branch current corresponding to each branch is obtained according to the modeled circuit topology structure.

5. The method for screening power semiconductor chips for current sharing in parallel according to claim 3, characterized in that: There are k power modules, each of which includes m branches, and there are N power semiconductor chips, where k=N / m. The power semiconductor chips in the chip combination are sequentially connected to the branches in the branch combination, including: According to the serial numbers of the power semiconductor chips in the chip combinations, the chip combinations are grouped to obtain m first combinations arranged in sequence, each of the first combinations includes k power semiconductor chips, wherein the serial numbers of all the power semiconductor chips in the first first combination are 1 to k, the serial numbers of all the power semiconductor chips in the second first combination are k+1 to 2k, and the serial numbers of all the power semiconductor chips in the mth first combination are Nk to N; sorting and numbering the k power modules in sequence to obtain a module combination; According to the serial numbers of the power modules in the module combination, the power semiconductor chip in the i-th first combination is sequentially connected to the i-th branch of each power module.

6. The method for screening power semiconductor chips for current sharing in parallel according to claim 3, characterized in that: There are k power modules, each of which includes m branches, and there are N power semiconductor chips, mk<N<m(k+1). The power semiconductor chips in the chip combination are sequentially connected to the branches in the branch combination, including: Removing all the power semiconductor chips located after the nth power semiconductor chip in the chip combination to obtain a target chip combination, wherein n=mk, and the serial numbers of all the power semiconductor chips in the target chip combination are 1 to n; According to the serial numbers of the power semiconductor chips in the target chip combination, the target chip combination is grouped to obtain m first combinations arranged in order, each of the first combinations includes k power semiconductor chips, wherein the serial numbers of all the power semiconductor chips in the first first combination are 1 to k, the serial numbers of all the power semiconductor chips in the second first combination are k+1 to 2k, and the serial numbers of all the power semiconductor chips in the mth first combination are nk to n; sorting and numbering the k power modules in sequence to obtain a module combination; According to the serial numbers of the power modules in the module combination, the power semiconductor chip in the i-th first combination is sequentially connected to the i-th branch of each power module.

7. The method for screening power semiconductor chips for current sharing in parallel according to claim 1, characterized in that: After obtaining the target power module, the method further includes: The target power module is packaged.

8. A computer-readable storage medium, characterized in that: The computer-readable storage medium includes a stored program, wherein when the program is executed, the device where the computer-readable storage medium is located is controlled to execute the method for screening parallel current sharing of power semiconductor chips as described in any one of claims 1 to 7.

9. A computer program product comprising computer instructions, characterized in that When the computer instructions are executed by the processor, the method for screening the parallel current sharing of power semiconductor chips as described in any one of claims 1 to 7 is implemented.

10. An electronic device, characterized in that: include: One or more processors, a memory, and one or more programs, wherein the one or more programs are stored in the memory and are configured to be executed by the one or more processors, and the one or more programs include a screening method for executing parallel current sharing of power semiconductor chips as described in any one of claims 1 to 7.

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