Signal transmission system and method in isolation driving circuit

Abstract

According to the signal transmission system and method in the isolation driving circuit, a fully differential structure is adopted to transmit signals, the high common-mode transient suppression capability is achieved, the signal frequency spectrum is expanded through the jitter frequency oscillation circuit on the coding side, and the EMI problem of the circuit is optimized. The dual band-pass characteristics of rough frequency selection and accurate frequency selection on the decoding side optimize noise suppression, common-mode control, signal shaping and a positive feedback full-wave comparator greatly improve the decoding rate and reliability, and signal delay is reduced. The clutter filtering module and the dead time generation module ensure the correctness and integrity of the signals, the safety coefficient of the circuit is improved, and compared with the prior art, the circuit provided by the embodiment of the invention has higher common-mode transient suppression and noise suppression capability, lower signal delay and more enough reliability and safety.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of digital isolation technology, and in particular to a signal transmission system and method in an isolation drive circuit. Background Art

[0002] With the continuous development of the integrated technology field, the driving technology is becoming more and more perfect, and the demand for isolated driving technology is also increasing. Isolated transmission can achieve complete isolation between two independent systems when transmitting signals or energy, preventing the mutual crosstalk of voltage and current from damaging the circuit or device, while greatly increasing the safety factor of the system. Therefore, isolation chips with isolated transmission function are widely used in electronic communication systems. Typical applications include industrial automation control, medical electronics, motor drive, isolated bus, photovoltaic inverter, hybrid electric vehicle, etc.

[0003] According to the different isolation media, digital isolators can be divided into optocoupler isolators, magnetic coupler isolators and capacitive isolators. Optocoupler isolators are widely used due to their simple structure and low cost, but their development is limited by the problems of easy aging of optocoupler devices, high transmission delay, slow speed, nonlinearity, etc. With the development and growth of silicon-based technology, inductive isolators and capacitive isolators of CMOS process have gradually replaced optocoupler isolators due to their superior performance such as small size, fast speed and low power consumption. Inductive isolation formed by on-chip transformers can transmit both signals and power, but it is abandoned in many occasions due to the large area of ​​on-chip inductance and weak anti-magnetic field interference ability. Capacitive isolation uses on-chip capacitors for isolated communication, which occupies a small area and has strong anti-magnetic field interference ability, but it is difficult to transmit power, and the signal and noise share the same channel, so the noise interference is large. Since the electronic equipment in the application environment of the isolator chip needs to work stably and reliably in very harsh environments such as strong magnetic fields, high surges, and high noise, it is a great challenge to ensure that the isolator continues to transmit accurate data in such harsh environments. The design of the isolator circuit poses a great challenge. Therefore, the use of capacitive isolators and dual-channel differential transmission has the advantages of high transmission rate, high isolation withstand voltage, long life, strong noise suppression, and low EMI (Electromagnetic Interference, which refers to the electromagnetic waves generated by electronic equipment during its own operation, which are emitted externally and interfere with other parts of the equipment or other external devices), which can adapt to most applications.

[0004] The signal modulation technologies that match capacitive isolation transmission mainly include pulse signal modulation schemes based on iCoupler technology, modulation schemes based on ordinary OOK technology (such as: high-speed capacitive isolation OOK signal modulation and demodulation circuits), and modulation schemes based on the combination of pulse signals and OOK technology (such as a digital isolator circuit based on Efficient-OOK).

[0005] The pulse signal modulation scheme based on icoupler technology has poor noise suppression ability for single-channel transmission and is easily interfered with to form bit errors. Although the refresh circuit can be used to refresh the signal in real time to prevent bit errors, interference may also occur during the refresh time and cannot be completely avoided. In addition, the refresh circuit greatly increases the complexity of the circuit. For the technical scheme of OOK differential transmission, the ring oscillator circuit on the encoding side of the "high-speed capacitor isolation OOK signal modulation and demodulation circuit" only uses one frequency spectrum, which is too concentrated and has large EMI. The common-mode level of the differential oscillation signal transmitted to the full-wave detector in the decoding method cannot be accurately controlled, and drift will occur under different conditions, affecting the decoding reliability. The full-wave detection response rate is slow, which will increase the signal delay. The "digital isolator circuit based on Efficient-OOK" sets oscillators on both the encoding and decoding sides, which will increase the power consumption of the circuit. There are also problems of common-mode point drift of the oscillation signal and slow response of the full-wave detector. Summary of the invention

[0006] To this end, an embodiment of the present invention provides a signal transmission system and method in an isolation driving circuit to solve the technical problem that interference cannot be completely avoided in signal transmission of the isolation driving circuit to cause bit errors and large signal delay.

[0007] In order to achieve the above purpose, the embodiment of the present invention provides the following technical solutions:

[0008] According to a first aspect of an embodiment of the present invention, an embodiment of the present application provides a signal transmission system in an isolation driving circuit, the system comprising:

[0009] A signal encoding module, used for receiving the first control signal and modulating it into a double oscillation signal;

[0010] Dual isolation channels for transmitting the dual oscillation signals to a decoding side;

[0011] A signal decoding module, used for receiving the dual isolation channel signal and decoding it into a second control signal;

[0012] A clutter filtering module, used for filtering out error pulses near the rising edge of the second control signal to obtain a third control signal;

[0013] The dead time generating module is used to process the third control signal to generate two fourth control signals with preset dead time.

[0014] Furthermore, the signal encoding module includes:

[0015] A fast start unit, used for quickly powering on and stabilizing the voltage to supply power to the internal sub-circuit upon receiving the first control signal;

[0016] A frequency jitter oscillation unit, used for modulating the first control signal into a first oscillation signal that changes randomly within a preset frequency range;

[0017] A voltage limiting output and undervoltage lockout unit, used to output a high level signal when the power-on voltage is greater than or equal to a first preset threshold or the undervoltage is greater than or equal to a second preset threshold;

[0018] The encoding side dual high-pass filter channel comprises: a first high-pass filter and a second high-pass filter; the first oscillation signal and the high-level signal are transmitted together through an AND gate circuit, and the output end of the AND gate circuit is connected to the input end of the first high-pass filter and the input end of the second high-pass filter through a first inverter group and a second inverter group respectively;

[0019] The first inverter group and the second inverter group have different preset numbers of first inverters INV1 , the first inverter group includes four first inverters INV1 , and the second inverter group includes three first inverters INV1 .

[0020] Further, the frequency-jittering oscillation unit includes: a random number generator and a ring oscillator, and the ring oscillator includes: a first PMOS tube MP1, a second PMOS tube MP2, a third PMOS tube MP3, a fourth PMOS tube MP4, a first NMOS tube MN1, a second NMOS tube MN2, a third NMOS tube MN3, and a fourth NMOS tube MN4; the gate of the first PMOS tube MP1 and the first NMOS tube MN1, the drain of the first PMOS tube MP1 and the first NMOS tube MN1, the gate of the second PMOS tube MP2 and the second NMOS tube MN2, the drain of the second PMOS tube MP2 and the second NMOS tube MN2, the gate of the third PMOS tube MP3 and the third NMOS tube MN3, the drain of the third PMOS tube MP3 and the third NMOS tube MN3, the gate of the fourth PMOS tube MP4 and the fourth NMOS tube MN4, and the drain of the fourth PMOS tube MP4 and the fourth NMOS tube MN4 are respectively connected to form a first connection point AP1, a second connection point AP2, and a third connection point AP3. The first connection point AP1 is connected to a ninth connection point AP9 between the sixth connection point AP6 and the seventh connection point AP7. The eighth connection point AP8 forms an output end OUT of the frequency-jittering oscillation unit. The sources of the first PMOS tube MP1, the second PMOS tube MP2, the third PMOS tube MP3 and the fourth PMOS tube MP4 are connected to the internal power supply line. The sources of the first NMOS tube MN1, the second NMOS tube MN2, the third NMOS tube MN3 and the fourth NMOS tube MN4 are grounded. The output ends of the random number generator are connected to the source grounding line of the first NMOS tube MN1 through an NMOS tube to form an access point. A resistor is arranged between two adjacent access points.

[0021] Furthermore, the signal decoding module includes: a coarse frequency selection unit, a precise frequency selection unit, a common mode control and signal shaping unit, and a positive feedback full-wave comparison unit; the coarse frequency selection unit includes: a dual high-pass filter channel on the decoding side and a three-stage cascade differential positive feedback amplifier; the precise frequency selection unit includes: a differential bandpass operational amplifier; the dual isolation channel signals are sent to the three-stage cascade differential positive feedback amplifier via the dual high-pass filter channel on the decoding side to generate a differential signal; the differential signal is processed by the precise frequency selection unit and the common mode control and signal shaping unit in turn and then input into the positive feedback full-wave comparison unit, and a second control signal is obtained after decoding.

[0022] Further, the decoding side dual high-pass filter channel includes: a third high-pass filter, a fourth high-pass filter, a thirty-first PMOS tube MP31 and a forty-second NMOS tube MN42; the third high-pass filter includes: a third capacitor C3 and a fourteenth resistor R14, the fourth high-pass filter includes: a fourth capacitor C4 and a fifteenth resistor R15, one end of the third capacitor C3 and the fourth capacitor C4 respectively form the input end of the third high-pass filter and the fourth high-pass filter, the other end of the third capacitor C3 and the fourth capacitor C4 respectively form the output end of the third high-pass filter and the fourth high-pass filter, the fourteenth resistor R 12 and one end of the thirteenth resistor R13 are respectively connected to the other ends of the third capacitor C3 and the fourth capacitor C4, the other ends of the fourteenth resistor R14 and the fifteenth resistor R15 are connected to form a tenth connection point AP10; the source of the thirty-first PMOS tube MP31 is connected to the internal power supply line, the source of the forty-second NMOS tube MN42 is grounded, the gate and drain of the thirty-first PMOS tube MP31 are connected to the eleventh connection point AP11, the gate and drain of the forty-second NMOS tube MN42 are connected to the eleventh connection point AP11, and the tenth connection point AP10 is connected to the eleventh connection point AP11.

[0023] Further, the common-mode control and signal shaping unit includes: a nineteenth PMOS tube MP19, a twentieth PMOS tube MP20, a twenty-first PMOS tube MP21, a twenty-fifth NMOS tube MN25, a twenty-sixth NMOS tube MN26, a twenty-seventh NMOS tube MN27, a twenty-eighth NMOS tube MN28, a thirteenth capacitor C13, a fourteenth capacitor C14, an eighteenth resistor R18, a nineteenth resistor R19, a twentieth resistor R20, a twenty-first resistor R21, a twenty-second resistor R22, a twenty-third resistor R23, and an operational amplifier OPA; the source of the nineteenth PMOS tube MP19 is connected to the internal power supply line, and the drain of the nineteenth PMOS tube MP19 is connected to the The sources of the twentieth PMOS transistor MP20 and the twenty-first PMOS transistor MP21, the sources of the twenty-fifth NMOS transistor MN25 and the twenty-sixth NMOS transistor MN26 are grounded, the gates of the twenty-fifth NMOS transistor MN25 and the twenty-sixth NMOS transistor MN26 are connected, the gate and the drain of the twenty-fifth NMOS transistor MN25 are connected and then connected to the internal power supply line together, the drain of the twenty-sixth NMOS transistor MN26 is connected to the sources of the twenty-seventh NMOS transistor MN27 and the twenty-eighth NMOS transistor MN28, the gate of the twentieth PMOS transistor MP20 is connected to the gate of the twenty-seventh NMOS transistor MN27 to form a fourteenth connection point AP 14, the drain of the 20th PMOS tube MP20 is connected to the drain of the 27th NMOS tube MN27 to form a 15th connection point AP15, the gate of the 21st PMOS tube MP21 is connected to the gate of the 28th NMOS tube MN28 to form a 16th connection point AP16, the drain of the 21st PMOS tube MP21 is connected to the drain of the 28th NMOS tube MN28 to form a 17th connection point AP17, one end of the 13th capacitor C13 is connected to the 14th connection point AP14, the other end of the 13th capacitor C13 is connected to one end of the 18th resistor R18, and the other end of the 18th resistor R18 forms the common mode control and signal shaping to the outside. The first input terminal INA3 of the unit, one end of the fourteenth capacitor C14 is connected to the sixteenth connection point AP16, the other end of the fourteenth capacitor C14 is connected to one end of the twenty-third resistor R23, the other end of the twenty-third resistor R23 forms the second input terminal INB3 of the common-mode control and signal shaping unit, the two ends of the nineteenth resistor R19 are respectively connected to the fourteenth connection point AP14 and the fifteenth connection point AP15, the fifteenth connection point AP15 is connected to the seventeenth connection point AP17 via the twentieth resistor R20 and the twenty-first resistor R21 in sequence, and the eighteenth connection point AP18 is formed between the twentieth resistor R20 and the twenty-first resistor R21,The two ends of the 22nd resistor R22 are respectively connected to the 16th connection point AP16 and the 17th connection point AP17, the first input end of the operational amplifier OPA is connected to the first preset reference level V1, the second input end of the operational amplifier OPA is connected to the 18th connection point AP18, the output end of the operational amplifier OPA is connected to the gate of the 19th PMOS tube MP19, and the drains of the 28th NMOS tube MN28 and the 27th NMOS tube MN27 respectively form the first output end OUTA3 and the second output end OUTB3 of the common mode control and signal shaping unit.

[0024] Further, the positive feedback full-wave comparison unit includes: a twenty-second PMOS tube MP22, a twenty-third PMOS tube MP23, a twenty-fourth PMOS tube MP24, a twenty-fifth PMOS tube MP25, a twenty-sixth PMOS tube MP26, a twenty-seventh PMOS tube MP27, a twenty-eighth PMOS tube MP28, a twenty-ninth PMOS tube MP29, a thirtieth PMOS tube MP30, a thirty-second PMOS tube MP32, a thirty-third PMOS tube MP33, a thirty-fourth PMOS tube MP34, a twenty-ninth NMOS tube MN29, a thirtieth NMOS tube MN30, a thirty-first NMOS tube MN31, a thirty-second NMOS tube MN32, a thirty-third the third NMOS tube MN33, the thirty-fourth NMOS tube MN34, the thirty-fifth NMOS tube MN35, the thirty-sixth NMOS tube MN36, the thirty-seventh NMOS tube MN37, the thirty-eighth NMOS tube MN38, the thirty-ninth NMOS tube MN39, the fortieth NMOS tube MN40, the forty-first NMOS tube MN41, the twenty-fourth resistor R24, the twenty-fifth resistor R25, the twenty-sixth resistor R26, the twenty-seventh resistor R27, and the twenty-eighth resistor R28; the thirty-second PMOS tube MP32, the thirty-fourth PMOS tube MP34, the twenty-second PMOS tube MP22, the twenty-third PMOS tube MP23, the twenty-fifth PMOS tube MP34, the twenty-second PMOS tube MP22, the twenty-third PMOS tube MP23, the twenty-fifth PMOS tube MP34, the twenty-third ... The sources of the PMOS tube MP25, the twenty-seventh PMOS tube MP27, and the twenty-ninth PMOS tube MP29 are connected to the internal power supply terminal line, the sources of the thirty-third PMOS tube MP33, the twenty-fourth PMOS tube MP24, the twenty-sixth PMOS tube MP26, the twenty-eighth PMOS tube MP28, and the thirtieth PMOS tube MP30 are respectively connected to the drains of the thirty-fourth PMOS tube MP34, the twenty-third PMOS tube MP23, the twenty-fifth PMOS tube MP25, the twenty-seventh PMOS tube MP27, and the twenty-ninth PMOS tube MP29, and the thirty-second PMOS tube MP32, the twenty-second PMOS tube MP33, the twenty-fourth PMOS tube MP24, the twenty-sixth PMOS tube MP26, the twenty-eighth PMOS tube MP28, and the thirtieth PMOS tube MP30 are respectively connected to the drains of the thirty-fourth PMOS tube MP34, the twenty-third PMOS tube MP23, the twenty-fifth PMOS tube MP25, the twenty-seventh PMOS tube MP27, and the twenty-ninth PMOS tube MP29. The gate and drain of the OS transistor MP22 are connected to the ground, the gate of the thirty-fourth PMOS transistor MP34 is connected to the drain of the thirty-third PMOS transistor MP33 and is grounded, the gate of the thirty-second PMOS transistor MP32 is connected to the gates of the thirty-third PMOS transistor MP33, the twenty-fourth PMOS transistor MP24, and the thirtieth PMOS transistor MP30, the gate of the twenty-second PMOS transistor MP22 is connected to the gates of the twenty-sixth PMOS transistor MP26 and the twenty-eighth PMOS transistor MP28, the gate of the thirty-fourth PMOS transistor MP34 is connected to the gates of the twenty-third PMOS transistor MP23 and the twenty-ninth PMOS transistor MP29,The gate of the twenty-fifth PMOS transistor MP25 is connected to the gate of the twenty-seventh PMOS transistor MP27, the gate of the twenty-fifth PMOS transistor MP25 is connected to the drain of the twenty-sixth PMOS transistor MP26 and connected to the drains of the thirty-fourth NMOS transistor MN34 and the thirty-fifth NMOS transistor MN35, the sources of the thirty-first NMOS transistor MN31, the thirty-second NMOS transistor MN32, and the thirty-third NMOS transistor MN33 are grounded, the drain of the thirty-first NMOS transistor MN31 is connected to the source of the thirty-sixth NMOS transistor MN36 and forms a nineteenth connection point AP19, the drain of the thirty-second NMOS transistor MN32 is connected to the drain of the thirty-third NMOS transistor MN33. The sources of the seventh NMOS tube MN37 are connected to form a twentieth connection point AP20, the gate and drain of the thirty-first NMOS tube MN31 are connected, the gate and drain of the thirty-second NMOS tube MN32 are connected, the gate and drain of the thirty-third NMOS tube MN33 are connected, the nineteenth connection point AP19 and the twentieth connection point AP20 form the first input terminal INA4 and the second input terminal INB4 of the positive feedback full-wave comparison unit, the drains of the thirty-sixth NMOS tube MN36 and the thirty-seventh NMOS tube MN37 are connected to the sources of the thirty-fourth NMOS tube MN34 and the thirty-fifth NMOS tube MN35, respectively, and the thirty-fourth NMOS tube MN The gate of the thirty-fifth NMOS tube MN34 is connected to the gate of the thirty-fifth NMOS tube MN35 to form a twenty-first connection point AP21, the gate of the thirty-sixth NMOS tube MN36 is connected to the gate of the thirty-seventh NMOS tube MN37 to form a twenty-second connection point AP22, the source of the twenty-ninth NMOS tube MN29 is connected to the drain of the thirtieth NMOS tube MN30, the drain of the twenty-ninth NMOS tube MN29 is connected to one end of the twenty-fourth resistor R24 ​​to form a twenty-third connection point AP23, the other end of the twenty-fourth resistor R24 ​​is connected to the drain of the twenty-fourth PMOS tube MP24 to form a twenty-fourth connection point AP24, the thirtieth NMOS tube MN3 The source of the third NMOS transistor MN30 is connected to one end of the twenty-fifth resistor R25 and the twenty-sixth resistor R26, the other ends of the twenty-fifth resistor R25 and the twenty-sixth resistor R26 are respectively connected to the sources of the thirty-sixth NMOS transistor MN36 and the thirty-seventh NMOS transistor MN37, the drain of the thirty-third NMOS transistor MN33 is connected to the source of the thirty-ninth NMOS transistor MN39 to form a twenty-fifth connection point AP25, the drain of the thirty-ninth NMOS transistor MN39 is connected to the source of the thirty-eighth NMOS transistor MN38, the drain of the thirty-eighth NMOS transistor MN38 is connected to the drain of the twenty-eighth PMOS transistor MP28 to form a twenty-sixth connection point AP26,The twenty-sixth connection point AP26 forms the output terminal OUT4 of the positive feedback full-wave comparison unit, the gate of the 30th NMOS tube MN30 is connected to the twenty-third connection point AP23 and connected to the gate of the thirty-ninth NMOS tube MN39, the gate of the twenty-ninth NMOS tube MN29 is connected to the twenty-fourth connection point AP24 and connected to the gate of the thirty-eighth NMOS tube MN38, the twenty-fifth connection point AP25 is connected to the source of the forty-first NMOS tube MN41 via the twenty-eighth resistor R28, the drain of the forty-first NMOS tube MN41 is connected to the source of the fortieth NMOS tube MN40, The drain of the 40th NMOS transistor MN40 is connected to one end of the 27th resistor R27 to form a 27th connection point AP27, the other end of the 27th resistor R27 is connected to the drain of the 30th PMOS transistor MP30 to form a 28th connection point AP28, the gate of the 41st NMOS transistor MN41 is connected to the 27th connection point AP27 and connected to the 22nd connection point AP22, the gate of the 40th NMOS transistor MN40 is connected to the 28th connection point AP28 and connected to the 21st connection point AP21, and the drain and gate of the 33rd NMOS transistor MN33 are connected to the second preset reference level V2.

[0025] Further, the clutter filtering module includes: a thirty-fifth PMOS tube MP35, a thirty-sixth PMOS tube MP36, a thirty-seventh PMOS tube MP37, a thirty-eighth PMOS tube MP38, a forty-third NMOS tube MN43, a forty-fourth NMOS tube MN44, a forty-fifth NMOS tube MN45, a forty-sixth NMOS tube MN46, a second inverter INV2, a third inverter INV3, a fourth inverter INV4, a fifth inverter INV5, a sixth inverter INV6, a twenty-ninth resistor R29, a fifteenth capacitor C15, and a sixteenth capacitor C16; the second The input end of the inverter INV2 forms the input end IN5 of the clutter filtering module externally, the output end of the second inverter INV2 is connected to the input end of the sixth inverter INV6 through the third inverter INV3, the twenty-ninth resistor R29, and the fifth inverter INV5 in sequence, one end of the fifteenth capacitor C15 and the sixteenth capacitor C16 are connected to the twenty-ninth connection point AP29 between the twenty-ninth resistor R29 and the fifth inverter INV5, the other end of the fifteenth capacitor C15 is connected to the internal power supply line, and the other end of the sixteenth capacitor C16 is grounded;The output end of the second inverter INV2 is connected to the gates of the thirty-fifth PMOS tube MP35 and the forty-fourth NMOS tube MN44 through the fourth inverter INV4. The sources of the thirty-fifth PMOS tube MP35 and the thirty-seventh PMOS tube MP37 are connected to the internal power supply line. The drains of the thirty-fifth PMOS tube MP35 and the thirty-seventh PMOS tube MP37 are connected to the sources of the thirty-sixth PMOS tube MP36 and the thirty-eighth PMOS tube MP38, respectively. The drains of the thirty-sixth PMOS tube MP36 and the forty-third NMOS tube MN43 are connected to form a thirtieth connection point AP30. The gates of the thirty-sixth PMOS tube MP36 and the forty-third NMOS tube MN43 are connected to form a thirty-first connection point AP31. The drains of the thirty-eighth PMOS tube MP38 and the forty-fifth NMOS tube MN45 are connected to form a thirty-second connection point AP32. The drains of the thirty-eighth PMOS tube MP38 and the forty-third NMOS tube MN43 are connected to form a thirty-first connection point AP33. The gates of the forty-fifth NMOS tube MN45 are connected to form a thirty-third connection point AP33, the sources of the forty-third NMOS tube MN43 and the forty-fifth NMOS tube MN45 are connected to the drains of the forty-fourth NMOS tube MN44 and the forty-sixth NMOS tube MN46 respectively, the sources of the forty-fourth NMOS tube MN44 and the forty-sixth NMOS tube MN46 are grounded, the thirtieth connection point AP30 is connected to the thirty-third connection point AP33 and connected to the twenty-ninth connection point AP29, the thirty-first connection point AP31 is connected to the thirty-second connection point AP32 and connected to the thirty-fourth connection point AP34 between the fifth inverter INV5 and the sixth inverter INV6, the gates of the thirty-seventh PMOS tube MP37 and the forty-sixth NMOS tube MN46 are connected to the output end of the sixth inverter INV6, and the output end of the sixth inverter INV6 forms the output end OUT5 of the clutter filtering module. ;

[0026] Further, the dead time generating module includes: a 39th PMOS tube MP39, a 40th PMOS tube MP40, a 41st PMOS tube MP41, a 42nd PMOS tube MP42, a 47th NMOS tube MN47, a 48th NMOS tube MN48, a 49th NMOS tube MN49, a 50th NMOS tube MN50, a 51st NMOS tube MN51, a 52nd NMOS tube MN52, a 7th inverter INV7, an 8th inverter INV8, a 1st buffer Buffer1, and a 2nd buffer Buffer2;The input end of the seventh inverter INV7 forms the input end IN6 of the dead time generating module externally, the output end of the seventh inverter INV7 is connected to the gate of the forty-seventh NMOS tube MN47 through the eighth inverter INV8, and the output end of the seventh inverter INV7 is connected to the gate of the forty-eighth NMOS tube MN48 in another way, the source of the thirty-ninth PMOS tube MP39, the fortieth PMOS tube MP40, the forty-first PMOS tube MP41, and the forty-second PMOS tube MP42 are connected to the internal power supply line, and the thirty-ninth PMOS tube MP39, the fortieth PMOS tube MP40, the forty-first PMOS tube MP41, and the forty-second PMOS tube MP42 are connected to the internal power supply line. The drains of the MOS tube MP41 and the forty-second PMOS tube MP42 are respectively connected to the drains of the forty-seventh NMOS tube MN47, the forty-eighth NMOS tube MN48, the fifty-first NMOS tube MN51, and the fifty-second NMOS tube MN52, the sources of the fifty-first NMOS tube MN51 and the fifty-second NMOS tube MN52 are respectively connected to the drains of the forty-ninth NMOS tube MN49 and the fiftieth NMOS tube MN50, the sources of the forty-seventh NMOS tube MN47, the forty-eighth NMOS tube MN48, the forty-ninth NMOS tube MN49, and the fiftieth NMOS tube MN50 are grounded, and the The gate of the 40th PMOS tube MP40 is connected to the seventh intersection CP7 between the drain of the 39th PMOS tube MP39 and the drain of the 47th NMOS tube MN47, the gate of the 39th PMOS tube MP39 is connected to the eighth intersection CP8 between the drain of the 40th PMOS tube MP40 and the drain of the 48th NMOS tube MN48, the gates of the 41st PMOS tube MP41 and the 51st NMOS tube MN51 are connected and connected to the seventh intersection CP7, the gates of the 42nd PMOS tube MP42 and the 52nd NMOS tube MN52 are connected and connected to the eighth intersection CP8, and the The gate of the 50th NMOS tube MN50 is connected to the ninth intersection CP9 between the drain of the 41st PMOS tube MP41 and the drain of the 51st NMOS tube MN51, the gate of the 49th NMOS tube MN49 is connected to the tenth intersection CP10 between the drain of the 42nd PMOS tube MP42 and the drain of the 52nd NMOS tube MN52, the ninth intersection CP9 forms the first output terminal OUTA6 of the dead time generating module through the first buffer Buffer1, and the tenth intersection CP10 forms the second output terminal OUTB6 of the dead time generating module through the second buffer Buffer2.

[0027] According to a second aspect of an embodiment of the present invention, an embodiment of the present application provides a signal transmission method in an isolation driving circuit, the method comprising:

[0028] The signal encoding module receives the first control signal and modulates it into a double oscillation signal;

[0029] The double oscillation signal is transmitted to the decoding side through the double isolation channel;

[0030] The signal decoding module receives the dual isolation channel signal and decodes it into a second control signal;

[0031] The clutter filtering module filters out the bit error pulse near the rising edge of the second control signal to obtain a third control signal;

[0032] The dead time generating module processes the third control signal to generate two fourth control signals with preset dead time.

[0033] Compared with the prior art, the signal transmission system and method in an isolated driving circuit provided by the embodiment of the present application adopts a fully differential structure to transmit signals with high common-mode transient suppression capability. The encoding side uses a frequency-jittering oscillation circuit to expand the signal spectrum and optimize the circuit EMI problem. The dual-bandpass characteristics of coarse frequency selection and precise frequency selection on the decoding side optimize the suppression of noise. Common-mode control, signal shaping, and positive feedback full-wave comparator greatly improve the decoding rate and reliability and reduce signal delay. The noise filtering module and the dead time generation module further ensure the correctness and integrity of the signal, and improve the safety factor of the circuit. Compared with the prior art, the embodiment of the present application has higher common-mode transient suppression and noise suppression capabilities, lower signal delay, and more sufficient reliability and safety. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to more clearly illustrate the implementation methods of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for the implementation methods or the description of the prior art. Obviously, the drawings in the following description are only exemplary, and for ordinary technicians in this field, other implementation drawings can be derived from the provided drawings without creative work.

[0035] The structures, proportions, sizes, etc. illustrated in this specification are only used to match the contents disclosed in the specification so as to facilitate understanding and reading by persons familiar with the technology. They are not used to limit the conditions under which the present invention can be implemented, and therefore have no substantial technical significance. Any structural modification, change in proportion or adjustment of size shall still fall within the scope of the technical contents disclosed in the present invention without affecting the effects and purposes that can be achieved by the present invention.

[0036] Figure 1A schematic diagram of the logical structure of a signal transmission system in an isolation drive circuit provided by an embodiment of the present invention;

[0037] Figure 2 A circuit diagram of a frequency jitter oscillation unit provided in an embodiment of the present invention;

[0038] Figure 3 A circuit diagram of a three-stage cascade differential positive feedback amplifier provided by an embodiment of the present invention;

[0039] Figure 4 A circuit diagram of a differential bandpass operational amplifier provided by an embodiment of the present invention;

[0040] Figure 5 A circuit diagram of a common mode control and signal shaping unit provided in an embodiment of the present invention;

[0041] Figure 6 A circuit diagram of a positive feedback full-wave comparison unit provided by an embodiment of the present invention;

[0042] Figure 7 A circuit diagram of a clutter filtering module provided in an embodiment of the present invention;

[0043] Figure 8 A circuit diagram of a dead time generating module provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0044] The following is a description of the implementation of the present invention by specific embodiments. People familiar with the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0045] In order to solve the above technical problems, Figure 1 As shown, an embodiment of the present application provides a signal transmission system in an isolation driving circuit, specifically comprising: a signal encoding module 1, a dual isolation channel 2, a signal decoding module 3, a clutter filtering module 4, and a dead time generating module 5.

[0046] Furthermore, the signal encoding module 1 is used to receive the first control signal and modulate it into a dual oscillation signal; the dual isolation channel 2 is used to transmit the dual oscillation signal to the decoding side; the signal decoding module 3 is used to receive the dual isolation channel signal and decode it into a second control signal; the noise filtering module 4 is used to filter out the error pulse near the rising edge of the second control signal to obtain a third control signal; the dead time generation module 5 is used to process the third control signal to generate two fourth control signals with preset dead times.

[0047] As described above, the signal encoding module 1 inputs a first control signal, which is a PWM control signal, serving as both a signal and a power supply. Figure 1 The signal encoding module 1 includes: a fast start unit 11, a frequency jitter oscillation unit 12, a voltage limiting output and undervoltage lockout unit 13, and an encoding side dual high-pass filter channel 14.

[0048] Furthermore, the fast start unit 11 is a fast start LDO (low dropout regulator), and the fast start unit 11 forms a signal input end externally, and the output end of the fast start unit 11 is connected to the input end of the frequency jittering oscillation unit 12 and the voltage limiting output and undervoltage lockout unit 13, and the output ends of the frequency jittering oscillation unit 12 and the voltage limiting output and undervoltage lockout unit 13 are respectively connected to the two input ends of the encoding side dual high-pass filter channel 14 through the AND gate circuit 15; the encoding side dual high-pass filter channel 14 includes: a first high-pass filter 141 and a second high-pass filter 142, the output ends of the frequency jittering oscillation unit 12 and the voltage limiting output and undervoltage lockout unit 13 are respectively connected to the first input end and the second input end of the AND gate circuit 15, and the first output end and the second output end of the AND gate circuit 15 are respectively connected to the input ends of the first high-pass filter 141 and the second high-pass filter 142 through the first inverter group 16 and the second inverter group 17.

[0049] Specifically, the fast start unit 11 is used to quickly power on and stabilize the voltage to power the internal sub-circuit when receiving the first control signal; the frequency jitter oscillation unit 12 is used to modulate the first control signal into a first oscillation signal that randomly changes within a preset frequency range; the voltage limiting output and undervoltage lockout unit 13 is used to output a high-level signal when the power-on voltage is greater than or equal to the first preset threshold or the undervoltage is greater than or equal to the second preset threshold.

[0050] In the embodiment of the present application, the frequency jitter oscillation unit is used to expand the spectrum and optimize the EMI characteristics of the signal. Figure 2 The frequency jitter oscillation unit 12 specifically includes: a random number generator 121 and a ring oscillator 122 .

[0051] The ring oscillator 122 includes: a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, a fourth PMOS transistor MP4, a first NMOS transistor MN1, a second NMOS transistor MN2, a third NMOS transistor MN3, and a fourth NMOS transistor MN4.

[0052] Specifically, the gates of the first PMOS transistor MP1 and the first NMOS transistor MN1, the drains of the first PMOS transistor MP1 and the first NMOS transistor MN1, the gates of the second PMOS transistor MP2 and the second NMOS transistor MN2, the drains of the second PMOS transistor MP2 and the second NMOS transistor MN2, the gates of the third PMOS transistor MP3 and the third NMOS transistor MN3, the drains of the third PMOS transistor MP3 and the third NMOS transistor MN3, the gates of the fourth PMOS transistor MP4 and the fourth NMOS transistor MN4, and the drains of the fourth PMOS transistor MP4 and the fourth NMOS transistor MN4 are connected to form a first connection point AP1, a second connection point AP2, a third connection point AP3, a fourth connection point AP4, a fifth connection point AP5, a sixth connection point AP6, a seventh connection point AP7, and an eighth connection point AP8. The second connection point AP2, the fourth connection point AP4, and the sixth connection point AP6 are connected to the third connection point AP3, the fifth connection point AP5, and the seventh connection point AP7, respectively. The first connection point AP1 is connected to the ninth connection point AP9 between the sixth connection point AP6 and the seventh connection point AP7, and the eighth connection point AP8 forms the output terminal OUT of the frequency-jittering oscillation unit. The sources of the first PMOS transistor MP1, the second PMOS transistor MP2, the third PMOS transistor MP3, and the fourth PMOS transistor MP4 are connected to the internal power supply line, and the sources of the first NMOS transistor MN1, the second NMOS transistor MN2, the third NMOS transistor MN3, and the fourth NMOS transistor MN4 are grounded.

[0053] In addition, the source ends of the first PMOS tube MP1, the second PMOS tube MP2, and the third PMOS tube MP3 are also provided with: a first resistor R1, a second resistor R2, and a third resistor R3. The sources of the first PMOS tube MP1, the second PMOS tube MP2, and the third PMOS tube MP3 are respectively connected to one end of the first resistor R1, the second resistor R2, and the third resistor R3, and the other ends of the first resistor R1, the second resistor R2, and the third resistor R3 and the source of the fourth PMOS tube MP4 are connected to the internal power supply line.

[0054] Each output terminal of the random number generator 121 is connected to the source grounding line of the first NMOS transistor MN1 via an NMOS transistor to form an access point, and a resistor is arranged between two adjacent access points.

[0055] like Figure 2As shown, taking the random number generator 121 having six output terminals as an example, the six output terminals are respectively: a first output terminal S1, a second output terminal S2, a third output terminal S3, a fourth output terminal S4, a fifth output terminal S5, and a sixth output terminal S6. In this way, the ring oscillator 122 also includes: a fifth NMOS transistor MN5, a sixth NMOS transistor MN6, a seventh NMOS transistor MN7, an eighth NMOS transistor MN8, a ninth NMOS transistor MN9, and a tenth NMOS transistor MN10. The first output terminal S1, the second output terminal S2, the third output terminal S3, the fourth output terminal S4, the fifth output terminal S5, and the sixth output terminal S6 are respectively connected to the gates of the fifth NMOS transistor MN5, the sixth NMOS transistor MN6, the seventh NMOS transistor MN7, the eighth NMOS transistor MN8, the ninth NMOS transistor MN9, and the tenth NMOS transistor MN10, and the sources of the fifth NMOS transistor MN5, the sixth NMOS transistor MN6, the seventh NMOS transistor MN7, the eighth NMOS transistor MN8, the ninth NMOS transistor MN9, and the tenth NMOS transistor MN10 are grounded.

[0056] The source end of the first NMOS transistor MN1 is provided with a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, and a ninth resistor R9. The fourth resistor R4, the fifth resistor R5, the sixth resistor R6, the seventh resistor R7, the eighth resistor R8, and the ninth resistor R9 are sequentially connected in series, the external end of the fourth resistor R4 is connected to the source of the first NMOS transistor MN1, and the external end of the ninth resistor R9 is grounded. In this way, a first access point BP1, a second access point BP2, a third access point BP3, a fourth access point BP4, a fifth access point BP5, and a sixth access point BP6 are formed between the fourth resistor R4 and the source of the first NMOS transistor MN1, between the fifth resistor R5 and the fourth resistor R4, between the sixth resistor R6 and the fifth resistor R5, between the seventh resistor R7 and the sixth resistor R6, between the eighth resistor R8 and the seventh resistor R7, and between the ninth resistor R9 and the eighth resistor R8, respectively, and the drains of the fifth NMOS transistor MN5, the sixth NMOS transistor MN6, the seventh NMOS transistor MN7, the eighth NMOS transistor MN8, the ninth NMOS transistor MN9, and the tenth NMOS transistor MN10 are connected to the first access point BP1, the second access point BP2, the third access point BP3, the fourth access point BP4, the fifth access point BP5, and the sixth access point BP6, respectively.

[0057] Similarly, the tenth resistor R10 and the eleventh resistor R11 are provided at one end of the source of the second NMOS tube MN2 and the third NMOS tube MN3, the sources of the second NMOS tube MN2 and the third NMOS tube MN3 are respectively connected to one end of the tenth resistor R10 and the eleventh resistor R11, the sources of the second NMOS tube MN2 and the third NMOS tube MN3 are respectively connected to one end of the tenth resistor R10 and the eleventh resistor R11, and the other ends of the tenth resistor R10 and the eleventh resistor R11 are grounded.

[0058] In addition, if Figure 1 As shown, the encoding side dual high-pass filter channel 14 includes: a first high-pass filter 141 and a second high-pass filter 142; the first oscillation signal and the high-level signal are transmitted together through the AND gate circuit 15, and the output end of the AND gate circuit 15 is connected to the input end of the first high-pass filter 141 and the second high-pass filter 142 through the first inverter group 16 and the second inverter group 17 respectively.

[0059] Further, the first high-pass filter 141 includes: a first capacitor C1 and a twelfth resistor R12. The second high-pass filter 142 includes: a second capacitor C2 and a thirteenth resistor R13. One end of the first capacitor C1 and the second capacitor C2 respectively form the input end of the first high-pass filter 141 and the second high-pass filter 142, and the other end of the first capacitor C1 and the second capacitor C2 respectively form the output end of the first high-pass filter 141 and the second high-pass filter 142, one end of the twelfth resistor R12 and the thirteenth resistor R13 are respectively connected to the other end of the first capacitor C1 and the second capacitor C2, and the other end of the twelfth resistor R12 and the thirteenth resistor R13 are grounded.

[0060] like Figure 1 As shown, the first inverter group 16 and the second inverter group 17 have different preset numbers of first inverters INV1 , the first inverter group 16 includes four first inverters INV1 , and the second inverter group 17 includes three first inverters INV1 .

[0061] In the embodiment of the present application, high-voltage isolation capacitors are used as isolation media for signal encoding modules and signal decoding modules to realize isolated transmission of signals. Specifically, dual isolation channels 2 include: a first capacitor HC1, a second capacitor HC2, a third capacitor HC3, and a fourth capacitor HC4. The first capacitor HC1, the second capacitor HC2, the third capacitor HC3, and the fourth capacitor HC4 are all high-voltage isolation capacitors, the first capacitor HC1 and the third capacitor HC3 are connected in series to form a first isolation channel 21, the second capacitor HC2 and the fourth capacitor HC4 are connected in series to form a second isolation channel 22, the first capacitor HC1 and the third capacitor HC3 are respectively formed to form the input and output of the first isolation channel 21, the second capacitor HC2 and the fourth capacitor HC4 are respectively formed to form the input and output of the second isolation channel 22, the input of the first isolation channel 21 is connected to the output of the first high-pass filter 141, and the input of the second isolation channel 22 is connected to the output of the second high-pass filter 22.

[0062] refer to Figure 1 The signal decoding module 3 includes: a rough frequency selection unit 31, a precise frequency selection unit 32, a common mode control and signal shaping unit 33, and a positive feedback full-wave comparison unit 34. The rough frequency selection unit 31 includes: a decoding side dual high-pass filter channel 311 and a three-stage cascade differential positive feedback amplifier 312; the decoding side dual high-pass filter channel 311 includes: a third high-pass filter 3111 and a fourth high-pass filter 3112; the precise frequency selection unit 32 includes: a differential bandpass amplifier 321.

[0063] Furthermore, the output end of the first isolation channel 21 is connected to the first input end INA1 of the three-stage cascade differential positive feedback amplifier 312 via the third high-pass filter 3111, the output end of the second isolation channel 22 is connected to the second input end INB1 of the three-stage cascade differential positive feedback amplifier 312 via the fourth high-pass filter 3112, the first output end OUTA1 and the second output end OUTB1 of the three-stage cascade differential positive feedback amplifier 312 are connected to the first input end INA2 and the second input end INB2 of the differential bandpass amplifier 321, respectively, the first output end OUTA2 and the second output end OUTB2 of the differential bandpass amplifier 321 are connected to the first input end INA2 and the second input end INB2 of the differential bandpass amplifier 321, respectively. The first input terminal INA3 and the second input terminal INB3 of the common mode control and signal shaping unit 33 are respectively connected to the first input terminal INA4 and the second input terminal INB4 of the positive feedback full-wave comparison unit 34, the output terminal OUT4 of the positive feedback full-wave comparison unit 34 is connected to the input terminal IN5 of the clutter filtering module 4, the output terminal OUT5 of the clutter filtering module 4 is connected to the input terminal IN6 of the dead time generating module 5, and the dead time generating module 5 forms a first output terminal OUTA6 and a second output terminal OUTB6 to the outside.

[0064] As described above, the dual isolation channel signals are sent to the three-stage cascade differential positive feedback amplifier 312 via the dual high-pass filter channel 311 on the decoding side to generate a differential signal; the differential signal is processed by the precise frequency selection unit 32 and the common mode control and signal shaping unit 33 in turn and then input into the positive feedback full-wave comparison unit 34, and the second control signal is obtained after decoding.

[0065] like Figure 1 As shown, the decoding side dual high-pass filter channel 311 also includes: a thirty-first PMOS transistor MP31 and a forty-second NMOS transistor MN42. Among them, the third high-pass filter 3111 includes: a third capacitor C3 and a fourteenth resistor R14; the fourth high-pass filter 3112 includes: a fourth capacitor C4 and a fifteenth resistor R15. One end of the third capacitor C3 and the fourth capacitor C4 form the input end of the third high-pass filter 3111 and the fourth high-pass filter 3112 respectively; the other end of the third capacitor C3 and the fourth capacitor C4 form the output end of the third high-pass filter 3111 and the fourth high-pass filter 3112 respectively. One end of the fourteenth resistor R12 and the thirteenth resistor R13 are respectively connected to the other end of the third capacitor C3 and the fourth capacitor C4, and the other end of the fourteenth resistor R14 and the fifteenth resistor R15 are connected to form a tenth connection point AP10; the source of the thirty-first PMOS tube MP31 is connected to the internal power supply line, the source of the forty-second NMOS tube MN42 is grounded, the gate and drain of the thirty-first PMOS tube MP31 are connected to the eleventh connection point AP11, the gate and drain of the forty-second NMOS tube MN42 are connected to the eleventh connection point AP11, and the tenth connection point AP10 is connected to the eleventh connection point AP11.

[0066] In the embodiment of the present application, as described above, the decoding side dual high-pass filter channel 311 includes a capacitor-resistor high-pass structure, and the voltage divider point formed by the diode-connected MOS tube is used as the signal common mode point. The common mode point can be arbitrarily adjusted through the width-to-length ratio of the MOS tube, and the interference caused by the ground to the common mode point can be shielded.

[0067] refer to Figure 3The three-stage cascade differential positive feedback amplifier 312 includes: a fifth PMOS tube MP5, a sixth PMOS tube MP6, a seventh PMOS tube MP7, an eighth PMOS tube MP8, a ninth PMOS tube MP9, a tenth PMOS tube MP10, an eleventh PMOS tube MP11, a twelfth PMOS tube MP12, a thirteenth PMOS tube MP13, a fourteenth PMOS tube MP14, a fifteenth PMOS tube MP15, a sixteenth PMOS tube MP16, an eleventh NMOS tube MN11, a twelfth NMOS tube MN12, a thirteenth NMOS tube MN13, a fourteenth NMOS tube MN14, a fifteenth NMOS tube MN15, a sixteenth NMOS tube MN16, a seventeenth NMOS tube MN17, an eighteenth NMOS tube MN18, a nineteenth NMOS tube MN19, a twentieth NMOS tube MN20, a fifth capacitor C5, a sixth capacitor C6, a seventh capacitor C7, an eighth capacitor C8, a ninth capacitor C9, and a tenth capacitor C10.

[0068] Specifically, the sources of the fifth PMOS tube MP5, the sixth PMOS tube MP6, the seventh PMOS tube MP7, the eighth PMOS tube MP8, the ninth PMOS tube MP9, the tenth PMOS tube MP10, the eleventh PMOS tube MP11, the twelfth PMOS tube MP12, the thirteenth PMOS tube MP13, the fourteenth PMOS tube MP14, the fifteenth PMOS tube MP15, and the sixteenth PMOS tube MP16 are connected to the internal power supply terminal line. The sources of the eleventh NMOS tube MN11, the twelfth NMOS tube MN12, the fifteenth NMOS tube MN15, and the eighteenth NMOS tube MN18 are grounded; the gates of the eleventh NMOS tube MN11, the twelfth NMOS tube MN12, the fifteenth NMOS tube MN15, and the eighteenth NMOS tube MN18 are connected, and the gate and drain of the eleventh NMOS tube MN11 are connected together and connected to the internal power supply terminal line. The drain of the twelfth NMOS tube MN12 is connected to the source of the thirteenth NMOS tube MN13 and the fourteenth NMOS tube MN14, the drain of the fifteenth NMOS tube MN15 is connected to the source of the sixteenth NMOS tube MN16 and the seventeenth NMOS tube MN17, the drain of the eighteenth NMOS tube MN18 is connected to the source of the nineteenth NMOS tube MN19 and the twentieth NMOS tube MN20, the gate of the thirteenth NMOS tube MN13 forms the first input terminal INA1 of the three-stage cascade differential positive feedback amplifier, and the gate of the fourteenth NMOS tube MN14 forms the second input terminal INB1 of the three-stage cascade differential positive feedback amplifier. The gates of the sixteenth NMOS tube MN16 and the seventeenth NMOS tube MN17 are connected to the source of the thirteenth NMOS tube MN13 and the fourteenth NMOS tube MN14, respectively, and the gates of the nineteenth NMOS tube MN19 and the twentieth NMOS tube MN20 are connected to the source of the sixteenth NMOS tube MN16 and the seventeenth NMOS tube MN17, respectively.The drains of the fifth PMOS tube MP5 and the sixth PMOS tube MP6 are connected to the drain of the thirteenth NMOS tube MN13 to form a first intersection CP1, the drains of the seventh PMOS tube MP7 and the eighth PMOS tube MP8 are connected to the drain of the fourteenth NMOS tube MN14 to form a second intersection CP2, the drains of the ninth PMOS tube MP9 and the tenth PMOS tube MP10 are connected to the drain of the sixteenth NMOS tube MN16 to form a third intersection CP3, the drains of the eleventh PMOS tube MP11 and the twelfth PMOS tube MP12 are connected to the drain of the seventeenth NMOS tube MN17 to form a fourth intersection CP4, the drains of the thirteenth PMOS tube MP13 and the tenth PMOS tube MP14 are connected to the drain of the seventeenth NMOS tube MN17 to form a fourth intersection CP5, and the drains of the thirteenth PMOS tube MP13 and the tenth PMOS tube MP15 are connected to the drain of the seventeenth NMOS tube MN18 to form a fourth intersection CP6. The drain of the fourteenth PMOS tube MP14 is connected to the drain of the nineteenth NMOS tube MN19 to form a fifth intersection CP5, the drains of the fifteenth PMOS tube MP15 and the sixteenth PMOS tube MP16 are connected to the drain of the twentieth NMOS tube MN20 to form a sixth intersection CP6, and the gates of the sixth PMOS tube MP6, the seventh PMOS tube MP7, the tenth PMOS tube MP10, the eleventh PMOS tube MP11, the fourteenth PMOS tube MP14, and the fifteenth PMOS tube MP15 are respectively connected to the second intersection CP2, the first intersection CP1, the fourth intersection CP4, the third intersection CP3, the sixth intersection CP6, and the fifth intersection CP5. The gate and drain of the fifth PMOS tube MP5 are connected, the gate and drain of the eighth PMOS tube MP8 are connected, the gate and drain of the ninth PMOS tube MP9 are connected, the gate and drain of the twelfth PMOS tube MP12 are connected, the gate and drain of the thirteenth PMOS tube MP13 are connected, and the gate and drain of the sixteenth PMOS tube MP16 are connected. The two ends of the fifth capacitor C5 are respectively connected to the source and gate of the fifth PMOS tube MP5, the two ends of the sixth capacitor C6 are respectively connected to the source and gate of the eighth PMOS tube MP8, the two ends of the seventh capacitor C7 are respectively connected to the source and gate of the ninth PMOS tube MP9, the two ends of the eighth capacitor C8 are respectively connected to the source and gate of the twelfth PMOS tube MP12, the two ends of the ninth capacitor C9 are respectively connected to the source and gate of the thirteenth PMOS tube MP13, the two ends of the tenth capacitor C10 are respectively connected to the source and gate of the sixteenth PMOS tube MP16, and the sources of the twentieth NMOS tube MN20 and the nineteenth NMOS tube MN19 respectively form the first output terminal OUTA1 and the second output terminal OUTB1 of the three-stage cascade differential positive feedback amplifier 312 to the outside.

[0069] As described above, in the embodiment of the present application, the circuit of the three-stage cascade differential positive feedback amplifier forms a three-pole amplifier, which decays rapidly at high frequencies to form a low-pass structure, and the load tube is connected in parallel with the capacitor, which accelerates the attenuation of the circuit gain at high frequencies, and the low-pass effect is more obvious.

[0070] refer to Figure 4 The differential bandpass operational amplifier 321 includes: a seventeenth PMOS transistor MP17, an eighteenth PMOS transistor MP18, a twenty-first NMOS transistor MN21, a twenty-second NMOS transistor MN22, a twenty-third NMOS transistor MN23, a twenty-fourth NMOS transistor MN24, an eleventh capacitor C11, a twelfth capacitor C12, a sixteenth resistor R16, and a seventeenth resistor R17.

[0071] Specifically, the sources of the seventeenth PMOS transistor MP17 and the eighteenth PMOS transistor MP18 are connected to the internal power supply terminal line, the sources of the twenty-first NMOS transistor MN21 and the twenty-second NMOS transistor MN22 are grounded, the gates of the twenty-first NMOS transistor MN21 and the twenty-second NMOS transistor MN22 are connected, the gate and drain of the twenty-first NMOS transistor MN21 are connected and connected to the internal power supply terminal line, the drain of the twenty-second NMOS transistor MN22 is connected to the sources of the twenty-third NMOS transistor MN23 and the twenty-fourth NMOS transistor MN24, the gate of the twenty-third NMOS transistor MN23 forms the first input terminal INA2 of the differential bandpass operational amplifier, and the gate of the twenty-fourth NMOS transistor MN24 forms the second input terminal INB2 of the differential bandpass operational amplifier. The drain of the seventeenth PMOS transistor MP17 is connected to the drain of the twenty-third NMOS transistor MN23 to form the twelfth connection point AP12, and the drain of the eighteenth PMOS transistor MP18 is connected to the drain of the twenty-fourth NMOS transistor MN24 to form the thirteenth connection point AP13. Two ends of the eleventh capacitor C11 are respectively connected to the source and gate of the seventeenth PMOS tube MP17, two ends of the sixteenth resistor R16 are respectively connected to the drain and gate of the seventeenth PMOS tube MP17, two ends of the twelfth capacitor C12 are respectively connected to the source and gate of the eighteenth PMOS tube MP8, two ends of the seventeenth resistor R17 are respectively connected to the drain and gate of the eighteenth PMOS tube MP18, and the thirteenth connection point AP13 and the twelfth connection point AP12 respectively form a first output terminal OUTA2 and a second output terminal OUTB2 of the differential bandpass operational amplifier to the outside.

[0072] As described above, the circuit of the differential bandpass op amp constitutes a precise frequency selection unit. The narrower bandpass characteristic further accurately selects the required frequency channel based on the above rough frequency selection, amplifies the signal frequency and suppresses high-frequency signals, thus better filtering out noise interference.

[0073] refer to Figure 5The common-mode control and signal shaping unit 33 includes: a nineteenth PMOS tube MP19, a twentieth PMOS tube MP20, a twenty-first PMOS tube MP21, a twenty-fifth NMOS tube MN25, a twenty-sixth NMOS tube MN26, a twenty-seventh NMOS tube MN27, a twenty-eighth NMOS tube MN28, a thirteenth capacitor C13, a fourteenth capacitor C14, an eighteenth resistor R18, a nineteenth resistor R19, a twentieth resistor R20, a twenty-first resistor R21, a twenty-second resistor R22, a twenty-third resistor R23, and an operational amplifier OPA.

[0074] Specifically, the source of the nineteenth PMOS tube MP19 is connected to the internal power supply line, the drain of the nineteenth PMOS tube MP19 is connected to the source of the twentieth PMOS tube MP20 and the twenty-first PMOS tube MP21, the sources of the twenty-fifth NMOS tube MN25 and the twenty-sixth NMOS tube MN26 are grounded, the gates of the twenty-fifth NMOS tube MN25 and the twenty-sixth NMOS tube MN26 are connected, the gate and drain of the twenty-fifth NMOS tube MN25 are connected to the internal power supply line together, and the drain of the twenty-sixth NMOS tube MN26 is connected to the source of the twenty-seventh NMOS tube MN27 and the twenty-eighth NMOS tube MN28. The gate of the twentieth PMOS transistor MP20 is connected to the gate of the twenty-seventh NMOS transistor MN27 to form a fourteenth connection point AP14, the drain of the twentieth PMOS transistor MP20 is connected to the drain of the twenty-seventh NMOS transistor MN27 to form a fifteenth connection point AP15, the gate of the twenty-first PMOS transistor MP21 is connected to the gate of the twenty-eighth NMOS transistor MN28 to form a sixteenth connection point AP16, the drain of the twenty-first PMOS transistor MP21 is connected to the drain of the twenty-eighth NMOS transistor MN28 to form a seventeenth connection point AP17, one end of the thirteenth capacitor C13 is connected to the fourteenth connection point AP14, the other end of the thirteenth capacitor C13 is connected to one end of the eighteenth resistor R18, and the other end of the eighteenth resistor R18 forms a common mode control and The first input terminal INA3 of the signal shaping unit 33, one end of the fourteenth capacitor C14 is connected to the sixteenth connection point AP16, the other end of the fourteenth capacitor C14 is connected to one end of the twenty-third resistor R23, the other end of the twenty-third resistor R23 forms the second input terminal INB3 of the common-mode control and signal shaping unit 33 to the outside, the two ends of the nineteenth resistor R19 are respectively connected to the fourteenth connection point AP14 and the fifteenth connection point AP15, the fifteenth connection point AP15 is connected to the seventeenth connection point AP17 via the twentieth resistor R20 and the twenty-first resistor R21 in sequence, the eighteenth connection point AP18 is formed between the twentieth resistor R20 and the twenty-first resistor R21, and the two ends of the twenty-second resistor R22 are respectively connected to the sixteenth connection point AP16 and the seventeenth connection point AP17. The first input terminal of the operational amplifier OPA is connected to the first preset reference level V1, the second input terminal of the operational amplifier OPA is connected to the eighteenth connection point AP18, the output terminal of the operational amplifier OPA is connected to the gate of the nineteenth PMOS tube MP19, and the drains of the twenty-eighth NMOS tube MN28 and the twenty-seventh NMOS tube MN27 respectively form the first output terminal OUTA3 and the second output terminal OUTB3 of the common-mode control and signal shaping unit 33.

[0075] As described above, in the circuit of the common mode control and signal shaping unit, a loop control is formed by the structure of an operational amplifier and a fixed reference voltage, and the common mode point of the signal is controlled near the fixed reference voltage, solving the drift problem of the common mode point of the signal under different conditions. The amplitude of the signal is controlled by the pull-up and pull-down currents of PMOS and NMOS flowing through the resistor, and different amplitudes can be achieved by changing the resistance value, and the highest amplitude is limited by the overdrive voltage and power supply of the PMOS and NMOS load tubes. The highest amplitude is the power supply voltage minus the overdrive voltage of PMOS, and the minimum amplitude is the overdrive voltage of NMOS, so that the subsequent stage can decode correctly.

[0076] refer to Figure 6 The positive feedback full-wave comparison unit 34 includes: a twenty-second PMOS tube MP22, a twenty-third PMOS tube MP23, a twenty-fourth PMOS tube MP24, a twenty-fifth PMOS tube MP25, a twenty-sixth PMOS tube MP26, a twenty-seventh PMOS tube MP27, a twenty-eighth PMOS tube MP28, a twenty-ninth PMOS tube MP29, a thirtieth PMOS tube MP30, a thirty-second PMOS tube MP32, a thirty-third PMOS tube MP33, a thirty-fourth PMOS tube MP34, a twenty-ninth NMOS tube MN29, a thirtieth NMOS tube MN 30, the thirty-first NMOS tube MN31, the thirty-second NMOS tube MN32, the thirty-third NMOS tube MN33, the thirty-fourth NMOS tube MN34, the thirty-fifth NMOS tube MN35, the thirty-sixth NMOS tube MN36, the thirty-seventh NMOS tube MN37, the thirty-eighth NMOS tube MN38, the thirty-ninth NMOS tube MN39, the fortieth NMOS tube MN40, the forty-first NMOS tube MN41, the twenty-fourth resistor R24, the twenty-fifth resistor R25, the twenty-sixth resistor R26, the twenty-seventh resistor R27, and the twenty-eighth resistor R28.

[0077] Further, the sources of the thirty-second PMOS tube MP32, the thirty-fourth PMOS tube MP34, the twenty-second PMOS tube MP22, the twenty-third PMOS tube MP23, the twenty-fifth PMOS tube MP25, the twenty-seventh PMOS tube MP27, and the twenty-ninth PMOS tube MP29 are connected to the internal power supply terminal line, the sources of the thirty-third PMOS tube MP33, the twenty-fourth PMOS tube MP24, the twenty-sixth PMOS tube MP26, the twenty-eighth PMOS tube MP28, and the thirtieth PMOS tube MP30 are connected to the drains of the thirty-fourth PMOS tube MP34, the twenty-third PMOS tube MP23, the twenty-fifth PMOS tube MP25, the twenty-seventh PMOS tube MP27, and the twenty-ninth PMOS tube MP29, respectively. The gates and drains of the OS tube MP32 and the twenty-second PMOS tube MP22 are connected to each other and are grounded; the gate of the thirty-fourth PMOS tube MP34 is connected to the drain of the thirty-third PMOS tube MP33 and is grounded; the gate of the thirty-second PMOS tube MP32 is connected to the gates of the thirty-third PMOS tube MP33, the twenty-fourth PMOS tube MP24, and the thirtieth PMOS tube MP30; the gate of the twenty-second PMOS tube MP22 is connected to the gates of the twenty-sixth PMOS tube MP26 and the twenty-eighth PMOS tube MP28; the gate of the thirty-fourth PMOS tube MP34 is connected to the gates of the twenty-third PMOS tube MP23 and the twenty-ninth PMOS tube MP29; and the gate of the twenty-fifth PMOS tube MP25 is connected to the gate of the twenty-seventh PMOS tube MP27.The gate of the twenty-fifth PMOS tube MP25 is connected to the drain of the twenty-sixth PMOS tube MP26 and is connected to the drains of the thirty-fourth NMOS tube MN34 and the thirty-fifth NMOS tube MN35. The sources of the thirty-first NMOS tube MN31, the thirty-second NMOS tube MN32 and the thirty-third NMOS tube MN33 are grounded. The drain of the thirty-first NMOS tube MN31 is connected to the source of the thirty-sixth NMOS tube MN36 to form a nineteenth connection point AP19. The drain of the thirty-second NMOS tube MN32 is connected to the source of the thirty-seventh NMOS tube MN37 to form a twentieth connection point AP20. The gate and drain of the thirty-first NMOS tube MN31 are connected. The drain of the thirty-second NMOS tube MN32 is connected to the source of the thirty-seventh NMOS tube MN37 to form a twentieth connection point AP20. The gate and the drain are connected, the gate and the drain of the thirty-third NMOS tube MN33 are connected, the nineteenth connection point AP19 and the twentieth connection point AP20 form the first input terminal INA4 and the second input terminal INB4 of the positive feedback full-wave comparison unit to the outside, the drains of the thirty-sixth NMOS tube MN36 and the thirty-seventh NMOS tube MN37 are respectively connected to the sources of the thirty-fourth NMOS tube MN34 and the thirty-fifth NMOS tube MN35, the gate of the thirty-fourth NMOS tube MN34 is connected to the gate of the thirty-fifth NMOS tube MN35 and form a twenty-first connection point AP21, the gate of the thirty-sixth NMOS tube MN36 is connected to the gate of the thirty-seventh NMOS tube MN37 and form a twenty-second connection point AP22. The source of the twenty-ninth NMOS tube MN29 is connected to the drain of the thirtieth NMOS tube MN30, the drain of the twenty-ninth NMOS tube MN29 is connected to one end of the twenty-fourth resistor R24 ​​to form a twenty-third connection point AP23, the other end of the twenty-fourth resistor R24 ​​is connected to the drain of the twenty-fourth PMOS tube MP24 to form a twenty-fourth connection point AP24, the source of the thirtieth NMOS tube MN30 is connected to one end of the twenty-fifth resistor R25 and the twenty-sixth resistor R26, the other ends of the twenty-fifth resistor R25 and the twenty-sixth resistor R26 are respectively connected to the sources of the thirty-sixth NMOS tube MN36 and the thirty-seventh NMOS tube MN37. The drain of the thirty-third NMOS tube MN33 is connected to the source of the thirty-ninth NMOS tube MN39 to form a twenty-fifth connection point AP25, the drain of the thirty-ninth NMOS tube MN39 is connected to the source of the thirty-eighth NMOS tube MN38, the drain of the thirty-eighth NMOS tube MN38 is connected to the drain of the twenty-eighth PMOS tube MP28 to form a twenty-sixth connection point AP26, and the twenty-sixth connection point AP26 forms the output end OUT4 of the positive feedback full-wave comparison unit to the outside.The gate of the 30th NMOS transistor MN30 is connected to the 23rd connection point AP23 and connected to the gate of the 39th NMOS transistor MN39. The gate of the 29th NMOS transistor MN29 is connected to the 24th connection point AP24 and connected to the gate of the 38th NMOS transistor MN38. The 25th connection point AP25 is connected to the source of the 41st NMOS transistor MN41 via the 28th resistor R28. The drain of the 41st NMOS transistor MN41 is connected to the source of the 40th NMOS transistor MN40. The drain of the 40th NMOS transistor MN40 is connected to the 24th connection point AP24 and connected to the gate of the 38th NMOS transistor MN38. One end of the seventeenth resistor R27 is connected to form a twenty-seventh connection point AP27, the other end of the twenty-seventh resistor R27 is connected to the drain of the thirtieth PMOS tube MP30 to form a twenty-eighth connection point AP28, the gate of the forty-first NMOS tube MN41 is connected to the twenty-seventh connection point AP27 and connected to the twenty-second connection point AP22, the gate of the fortieth NMOS tube MN40 is connected to the twenty-eighth connection point AP28 and connected to the twenty-first connection point AP21, and the drain and gate of the thirty-third NMOS tube MN33 are connected to the second preset reference level V2.

[0078] As described above, the circuit of the positive feedback full-wave comparison unit inputs the differential signal processed by the common-mode control and signal shaping unit into the same end of the comparator, and the other end is a fixed level. The cross-coupled structure forms a positive feedback structure for the input end, which can respond to the input of the signal more quickly. And through common-mode control, the common-mode voltage of the oscillation signal can be set slightly higher than the input fixed voltage of the positive feedback full-wave comparator, that is, when there is no oscillation signal, the comparator is set to ground and outputs a low level. When there is a signal, the differential oscillation signal alternately undershoots and overshoots. The overshoot signal cuts off the input tube, and the undershoot signal can increase the input tube branch current, and the input current on the other side of the comparator is reduced through cross-coupling bias, so that the comparator outputs a high level.

[0079] refer to Figure 7 The noise filtering module 4 includes: a thirty-fifth PMOS tube MP35, a thirty-sixth PMOS tube MP36, a thirty-seventh PMOS tube MP37, a thirty-eighth PMOS tube MP38, a forty-third NMOS tube MN43, a forty-fourth NMOS tube MN44, a forty-fifth NMOS tube MN45, a forty-sixth NMOS tube MN46, a second inverter INV2, a third inverter INV3, a fourth inverter INV4, a fifth inverter INV5, a sixth inverter INV6, a twenty-ninth resistor R29, a fifteenth capacitor C15, and a sixteenth capacitor C16.

[0080] The input end of the second inverter INV2 forms the input end IN5 of the noise filtering module 4 externally, the output end of the second inverter INV2 is connected to the input end of the sixth inverter INV6 via the third inverter INV3, the twenty-ninth resistor R29, and the fifth inverter INV5 in sequence, one end of the fifteenth capacitor C15 and the sixteenth capacitor C16 are connected to the twenty-ninth connection point AP29 between the twenty-ninth resistor R29 and the fifth inverter INV5, the other end of the fifteenth capacitor C15 is connected to the internal power supply line, and the other end of the sixteenth capacitor C16 is grounded; the output end of the second inverter INV2 is connected to the gates of the thirty-fifth PMOS tube MP35 and the forty-fourth NMOS tube MN44 via the fourth inverter INV4. The sources of the thirty-fifth PMOS tube MP35 and the thirty-seventh PMOS tube MP37 are connected to the internal power supply line, the drains of the thirty-fifth PMOS tube MP35 and the thirty-seventh PMOS tube MP37 are connected to the sources of the thirty-sixth PMOS tube MP36 and the thirty-eighth PMOS tube MP38 respectively, the drains of the thirty-sixth PMOS tube MP36 and the forty-third NMOS tube MN43 are connected to form a thirtieth connection point AP30, the gates of the thirty-sixth PMOS tube MP36 and the forty-third NMOS tube MN43 are connected to form a thirty-first connection point AP31, the drains of the thirty-eighth PMOS tube MP38 and the forty-fifth NMOS tube MN45 are connected to form a thirty-second connection point AP32, the gates of the thirty-eighth PMOS tube MP38 and the forty-fifth NMOS tube MN45 are connected to form a thirty-third connection point AP34. P33, the sources of the forty-third NMOS tube MN43 and the forty-fifth NMOS tube MN45 are connected to the drains of the forty-fourth NMOS tube MN44 and the forty-sixth NMOS tube MN46 respectively, the sources of the forty-fourth NMOS tube MN44 and the forty-sixth NMOS tube MN46 are grounded, the thirtieth connection point AP30 is connected to the thirty-third connection point AP33 and connected to the twenty-ninth connection point AP29, the thirty-first connection point AP31 is connected to the thirty-second connection point AP32 and connected to the thirty-fourth connection point AP34 between the fifth inverter INV5 and the sixth inverter INV6, the gates of the thirty-seventh PMOS tube MP37 and the forty-sixth NMOS tube MN46 are connected and connected to the output end of the sixth inverter INV6, and the output end of the sixth inverter INV6 forms the output end OUT5 of the noise filtering module 4 to the outside.

[0081] As described above, the circuit input of the clutter filtering module is the above-mentioned decoded signal. Through the dual-input reverse structure and the principle of slow power-on of the capacitor, the error pulse caused by the redundant oscillation signal caused by the voltage-limited output characteristics of the signal encoding side near the rising edge of the signal is filtered out to ensure the integrity of the decoded signal.

[0082] refer to Figure 8The dead time generating module 5 includes: a thirty-ninth PMOS tube MP39, a fortieth PMOS tube MP40, a forty-first PMOS tube MP41, a forty-second PMOS tube MP42, a forty-seventh NMOS tube MN47, a forty-eighth NMOS tube MN48, a forty-ninth NMOS tube MN49, a fiftieth NMOS tube MN50, a fifty-first NMOS tube MN51, a fifty-second NMOS tube MN52, a seventh inverter INV7, an eighth inverter INV8, a first buffer Buffer1, and a second buffer Buffer2.

[0083] Specifically, the input end of the seventh inverter INV7 forms the input end IN6 of the dead time generating module, the output end of the seventh inverter INV7 is connected to the gate of the forty-seventh NMOS tube MN47 via the eighth inverter INV8, and the output end of the seventh inverter INV7 is connected to the gate of the forty-eighth NMOS tube MN48. The sources of the thirty-ninth PMOS tube MP39, the fortieth PMOS tube MP40, the forty-first PMOS tube MP41 and the forty-second PMOS tube MP42 are connected to the internal power supply line, the drains of the thirty-ninth PMOS tube MP39, the fortieth PMOS tube MP40, the forty-first PMOS tube MP41 and the forty-second PMOS tube MP42 are respectively connected to the drains of the forty-seventh NMOS tube MN47, the forty-eighth NMOS tube MN48, the fifty-first NMOS tube MN51 and the fifty-second NMOS tube MN52, the sources of the fifty-first NMOS tube MN51 and the fifty-second NMOS tube MN52 are respectively connected to the drains of the forty-ninth NMOS tube MN49 and the fiftieth NMOS tube MN50, and the sources of the forty-seventh NMOS tube MN47, the forty-eighth NMOS tube MN48, the forty-ninth NMOS tube MN49 and the fiftieth NMOS tube MN50 are grounded. The gate of the 40th PMOS tube MP40 is connected to the seventh intersection CP7 between the drain of the 39th PMOS tube MP39 and the drain of the 47th NMOS tube MN47, the gate of the 39th PMOS tube MP39 is connected to the eighth intersection CP8 between the drain of the 40th PMOS tube MP40 and the drain of the 48th NMOS tube MN48, the gates of the 41st PMOS tube MP41 and the 51st NMOS tube MN51 are connected and connected to the seventh intersection CP7, the gates of the 42nd PMOS tube MP42 and the 52nd NMOS tube MN52 are connected and connected to the eighth intersection CP8, and the gates of the 52nd PMOS tube MP42 and the 52nd NMOS tube MN52 are connected and connected to the eighth intersection CP8. The gate of the fiftieth NMOS tube MN50 is connected to the ninth intersection CP9 between the drain of the forty-first PMOS tube MP41 and the drain of the fifty-first NMOS tube MN51, the gate of the forty-ninth NMOS tube MN49 is connected to the tenth intersection CP10 between the drain of the forty-second PMOS tube MP42 and the drain of the fifty-second NMOS tube MN52, the ninth intersection CP9 forms the first output terminal OUTA6 of the dead time generating module through the first buffer Buffer1, and the tenth intersection CP10 forms the second output terminal OUTB6 of the dead time generating module through the second buffer Buffer2.

[0084] As mentioned above, the circuit of the dead time generating unit is used to process the input square wave control signal, and utilizes the time difference caused by the different driving capabilities formed by the cross-coupling structure and the different width-to-length ratios of the MOS tubes to generate two control signals with a dead time of several nanoseconds, which are used to drive the upper bridge and lower bridge drive power tube structures respectively, avoiding damage to the circuit caused by cliff penetration, greatly improving the circuit safety.

[0085] Compared with the prior art, the signal transmission system in an isolation drive circuit provided by the embodiment of the present application adopts a fully differential structure to transmit signals with high common-mode transient suppression capability. The encoding side uses a frequency-jittering oscillation circuit to expand the signal spectrum and optimize the circuit EMI problem. The dual-bandpass characteristics of coarse frequency selection and precise frequency selection on the decoding side optimize the suppression of noise. Common-mode control, signal shaping, and positive feedback full-wave comparator greatly improve the decoding rate and reliability and reduce signal delay. The noise filtering module and the dead time generation module further ensure the correctness and integrity of the signal, and improve the safety factor of the circuit. Compared with the prior art, the embodiment of the present application has higher common-mode transient suppression and noise suppression capabilities, lower signal delay, and more sufficient reliability and safety.

[0086] Corresponding to the signal transmission method in the isolation drive circuit disclosed above, the embodiment of the present invention further discloses a signal transmission system in the isolation drive circuit. The following describes in detail the signal transmission system in the isolation drive circuit disclosed in the embodiment of the present invention in combination with the signal transmission method in the isolation drive circuit described above.

[0087] like Figure 1 As shown, the specific steps of a signal transmission method in an isolation driving circuit provided in an embodiment of the present application are described in detail below.

[0088] The signal encoding module 1 receives the first control signal and modulates it into a dual oscillation signal; the dual isolation channel 2 transmits the dual oscillation signal to the decoding side; the signal decoding module 3 receives the dual isolation channel signal and decodes it into a second control signal; the noise filtering module 4 filters out the error pulse near the rising edge of the second control signal to obtain a third control signal; the dead time generating module 5 processes the third control signal to generate two fourth control signals with preset dead times.

[0089] As mentioned above, reference Figure 1In the circuit of the dual high-pass filter channel on the decoding side, the third capacitor C3, the fourth capacitor C4, the fourteenth resistor R14, and the fifteenth resistor R15 are RC filter structures, the third capacitor C3 is connected to the fourteenth resistor R14, the fourth capacitor C4 is connected to the fifteenth resistor R15, the fourteenth resistor R14 is connected to the fifteenth resistor R15, the thirty-first PMOS tube MP31 and the forty-second NMOS tube MN42 are gate-drain short-circuited structures, the source end of the thirty-first PMOS tube MP31 is connected to the power supply, the source end of the forty-second NMOS tube MN42 is grounded, and the third The gate and drain of the eleventh PMOS tube MP31 and the forty-second NMOS tube MN42 are connected to form a current path, and the gate and drain of the two are connected to the midpoint of the fourteenth resistor R14 and the fifteenth resistor R15 as the common-mode oscillation point of the signal, and also as the input common-mode point of the three-stage cascade differential positive feedback amplifier circuit. The common-mode point can be arbitrarily adjusted by adjusting the width-to-length ratio of the thirty-first PMOS tube MP31 and the forty-second NMOS tube MN42, and the diode structure of the forty-second NMOS tube MN42 can be used to shield the interference of the common-mode point to the ground, thereby improving the stability of the signal.

[0090] refer to Figure 2 In the circuit of the frequency-jittering oscillation unit, the first PMOS tube MP1, the second PMOS tube MP2, the third PMOS tube MP3, the first NMOS tube MN1, the second NMOS tube MN2, and the third NMOS tube MN3 constitute a three-stage ring oscillation circuit, one end of the first resistor R1 is connected to the first PMOS tube MP1, and one end is connected to the power supply, one end of the second resistor R2 is connected to the second PMOS tube MP2, and one end is connected to the power supply, one end of the third resistor R3 is connected to the third PMOS tube MP3, and one end is connected to the power supply, one end of the tenth resistor R10 is connected to the second NMOS tube MN2, and one end is connected to the ground, one end of the eleventh resistor R11 is connected to the second NMOS tube MN2, and one end is connected to the ground, the upper end of the fourth resistor R4 is connected to the first NMOS tube MN1, the lower end of the ninth resistor R9 is grounded, the fourth resistor R4 to the ninth resistor R9 are connected in series and each is connected in parallel to an NMOS tube, and the NMOS tube is controlled by the random number generator circuit to control whether the corresponding resistor is connected to the circuit, thereby controlling the frequency of the ring oscillation circuit and completing the expansion of the spectrum.

[0091] refer to Figure 3In the circuit of the three-stage cascade differential positive feedback amplifier, the twelfth NMOS tube MN12, the thirteenth NMOS tube MN13, the fourteenth NMOS tube MN14, the fifth PMOS tube MP5, the sixth PMOS tube MP6, the seventh PMOS tube MP7, the eighth PMOS tube MP8, the fifth capacitor C5, and the sixth capacitor C6 are the first stage amplification, and the signal output by the dual high-pass filter channel 311 on the decoding side is input to the gate of the thirteenth NMOS tube MN13 and the fourteenth NMOS tube MN14, and the twelfth NMOS tube MN12 is used as an operational amplifier. The tail current supply of the thirteenth NMOS tube MN13 and the fourteenth NMOS tube MN14 is used as a differential input tube, the fifth PMOS tube MP5, the sixth PMOS tube MP6, the seventh PMOS tube MP7, and the eighth PMOS tube MP8 are used as load tubes, and the sixth PMOS tube MP6 and the seventh PMOS tube MP7 are cross-coupled, that is, the gate of the sixth PMOS tube MP6 is connected to the drain end of the seventh PMOS tube MP7, and the gate of the seventh PMOS tube MP7 is connected to the drain end of the sixth PMOS tube MP6. Through small signal analysis, its gain can be obtained as follows:

[0092]

[0093] The corresponding gain can be obtained by adjusting the ratio of the fifth PMOS tube MP5 and the sixth PMOS tube MP6; the fifth capacitor C5 is connected in parallel with the fifth PMOS tube MP5, and the sixth capacitor C6 is connected in parallel with the eighth PMOS tube MP8, which is used to accelerate the attenuation of the gain at high frequency and improve the low-pass performance. The second stage and the third stage are exactly the same as the first stage, the drain of the thirteenth NMOS tube MN13 is connected to the gate of the sixteenth NMOS tube MN16, the drain of the fourteenth NMOS tube MN14 is connected to the gate of the seventeenth NMOS tube MN17, the drain of the sixteenth NMOS tube MN16 is connected to the gate of the nineteenth NMOS tube MN19, the drain of the seventeenth NMOS tube MN17 is connected to the gate of the twentieth NMOS tube MN20, and the drains of the nineteenth NMOS tube MN19 and the twentieth NMOS tube MN20 serve as the first output terminal OUTA1 and the second output terminal OUTB1 of the three-stage cascade differential positive feedback amplifier 312.

[0094] refer to Figure 4 In the differential bandpass operational amplifier 321 circuit, the twenty-third NMOS transistor MN23 and the twenty-fourth NMOS transistor MN24 are used as differential input transistors, the seventeenth PMOS transistor MP17 and the eighteenth PMOS transistor MP18 are used as load transistors, R16 is connected to the gate-drain terminal of the seventeenth PMOS transistor MP17, the eleventh capacitor C11 is connected to the gate-source terminal of the seventeenth PMOS transistor MP17, the seventeenth resistor R17 is connected to the gate-drain terminal of the eighteenth PMOS transistor MP18, and the twelfth capacitor C12 is connected to the gate-source terminal of the eighteenth PMOS transistor MP18. By analyzing the small signal, its low-frequency gain is:

[0095]

[0096] The width-to-length ratio of the twenty-third NMOS tube MN23 and the seventeenth PMOS tube MP17 can be set to set the low-frequency gain; the small signal transfer function is:

[0097]

[0098] It can be seen that the circuit consists of one zero point and two poles. The sixteenth resistor R16 and the eleventh capacitor C11 can be set to place the zero point before the two poles to form a bandpass, and the double-pole gain decays faster and the bandpass characteristic is better.

[0099] refer to Figure 5In the circuit of the common-mode control and signal shaping unit 33, the output signals of the first output terminal OUTA2 and the second output terminal OUTB2 of the differential bandpass amplifier are input to the first input terminal INA3 and the second input terminal INB3 of the common-mode control and signal shaping unit 33; the eighteenth resistor R18, the thirteenth capacitor C13, the twenty-third resistor R23, and the fourteenth capacitor C14 are used as filtering components; the resonant frequency of the resistors and capacitors is set at the center point of the above-mentioned frequency band, and the signals outside the frequency band can be attenuated; the twenty-seventh NMOS tube MN27, the twenty-eighth NMOS tube MN28, the twentieth PMOS tube MP20, and the twenty-first PMOS tube MP21 are used as the inverting structure of the input oscillation signal; one end of the operational amplifier OPA is input as the first preset reference level V1, and the other end is the common mode point of the differential input signal; by adjusting the tail current, the nineteenth PMOS tube MP19 can control the common mode point to be close to the first preset reference level V1. When the oscillation signal of the first input terminal INA3 of the common-mode control and signal shaping unit 33 is undershooting, the oscillation signal of the second input terminal INB3 of the common-mode control and signal shaping unit 33 is overshooting. At this time, the oscillation signal of the first input terminal INA3 of the common-mode control and signal shaping unit 33 will control the twentieth PMOS tube MP20 to turn on, and the oscillation signal of the second input terminal INB3 of the common-mode control and signal shaping unit 33 will control the twenty-eighth NMOS tube MN28 to turn on. At this time, the twentieth PMOS tube MP20 and the twenty-eighth NMOS tube MN28 form a current path, and the current of the twentieth PMOS tube MP20 is provided by the nineteenth PMOS tube MP19, and the twenty-eighth NMOS tube MN28 is turned on. The current of the twenty-eighth NMOS tube MN28 is provided by the twenty-sixth NMOS tube MN26; when the common mode point is higher than the first preset reference level V1, the operational amplifier OPA outputs a high level, and the current is reduced through the nineteenth PMOS tube MP19. At this time, the pull-down current provided by the twenty-sixth NMOS tube MN26 is greater than the charging current provided by the nineteenth PMOS tube MP19, the common mode point drops, and the current flows through the nineteenth resistor R19, the twentieth resistor R20, the twenty-first resistor R21, and the twenty-second resistor R22 to provide an appropriate amplitude for the oscillation signal, so that the common mode point can be controlled near the first preset reference level V1 by adjusting the tail current of the nineteenth PMOS tube MP19.When the oscillation signal of the first input terminal INA3 of the common-mode control and signal shaping unit 33 is up-shooting, the oscillation signal of the second input terminal INB3 of the common-mode control and signal shaping unit 33 is down-shooting, the oscillation signal of the first input terminal INA3 of the common-mode control and signal shaping unit 33 will control the twenty-seventh NMOS transistor MN27 to turn on, and the oscillation signal of the second input terminal INB3 of the common-mode control and signal shaping unit 33 will control the twenty-first PMOS transistor MP21 to turn on. At this time, the twenty-first PMOS transistor MP21 and the twenty-seventh NMOS transistor MN27 form a current path, and the twenty-first PMOS transistor MP21 The current of the twenty-seventh NMOS tube MN27 is provided by the twenty-sixth NMOS tube MN26. When the common mode point is lower than the first preset reference level V1, the operational amplifier OPA outputs a low level, and the current is increased through the nineteenth PMOS tube MP19. At this time, the pull-down current provided by the twenty-sixth NMOS tube MN26 is greater than the charging current provided by the nineteenth PMOS tube MP19, the common mode point drops, and the current flows through the nineteenth resistor R19, the twentieth resistor R20, the twenty-first resistor R21, and the twenty-second resistor R22 to provide an appropriate amplitude for the oscillation signal.

[0100] refer to Figure 6In the positive feedback full-wave comparison unit circuit, the thirty-second PMOS tube MP32, the thirty-third PMOS tube MP33, and the thirty-fourth PMOS tube MP34 are used as current mirror input tubes, the thirty-second PMOS tube MP32 provides a bias voltage for the thirty-third PMOS tube MP33, the twenty-fourth PMOS tube MP24, and the thirtieth PMOS tube MP30, and the gates are connected, the thirty-fourth PMOS tube MP34 provides a bias voltage for the twenty-third PMOS tube MP23 and the twenty-ninth PMOS tube MP29, and the gates are connected, the twenty-second PMOS tube MP22, as a current mirror input tube, provides a bias voltage for the twenty-sixth PMOS tube MP26 and the twenty-eighth PMOS tube MP28, and the gates are connected, the twenty-fifth PMOS tube MP25 provides a bias voltage for the twenty-seventh PMOS tube MP27, and the gates are connected; the output signal of the first output terminal OUTA3 and the second output terminal OUTB3 of the above-mentioned common-mode control and signal shaping unit 33 The first input terminal INA4 and the second input terminal INB4 of the positive feedback full-wave comparison unit are input, and the twenty-third PMOS tube MP23 and the twenty-fourth PMOS tube MP24 act as current mirrors to generate current flowing into the self-bias structure where the twenty-fourth resistor R24, the twenty-ninth NMOS tube MN29 and the thirtieth NMOS tube MN30 are located, and generate a third voltage Vb3 and a fourth voltage Vb4 to provide a gate bias voltage for the input tubes where the thirty-eighth NMOS tube MN38 and the thirty-ninth NMOS tube MN39 are located, and since the source of the thirtieth NMOS tube MN30 is connected to the twenty-fifth resistor R25 and the twenty-sixth resistor R26, the twenty-fifth resistor R25 is the same as the twenty-sixth resistor R26 and is twice the twenty-eighth resistor R28, the current mirrored to the thirty-eighth NMOS tube MN38 and the thirty-ninth NMOS tube MN39 is slightly larger than the current of the circuit where the twenty-third PMOS tube MP23 and the twenty-fourth PMOS tube MP24 are located.The twenty-ninth PMOS tube MP29 and the thirtieth PMOS tube MP30 act as current mirrors to generate current flowing into the self-bias structure where the twenty-seventh resistor R27, the fortieth NMOS tube MN40, and the forty-first NMOS tube MN41 are located, and generate a first voltage Vb1 and a second voltage Vb2 to provide bias voltages for the input tubes where the thirty-fourth NMOS tube MN34, the thirty-fifth NMOS tube MN35, the thirty-sixth NMOS tube MN36, and the thirty-seventh NMOS tube MN37 are located, and because the source of the forty-first NMOS tube MN41 is connected to the twenty-eighth resistor R28, the current mirrored to the thirty-fourth NMOS tube MN34, the thirty-fifth NMOS tube MN35, the thirty-sixth NMOS tube MN36, and the thirty-seventh NMOS tube MN37 is slightly larger than the current of the structure where the twenty-ninth PMOS tube MP29 and the thirtieth PMOS tube MP30 are located; the thirty-fourth NMOS tube MN34, the thirty-fifth NMOS tube MN35, the thirty-sixth NMOS tube MN36, and the thirty-seventh NMOS tube MN37 are located. The input tube width-to-length ratio of the seventeenth NMOS tube MN37 is half of the input tube width-to-length ratio of the thirty-eighth NMOS tube MN38 and the thirty-ninth NMOS tube MN39. The width-to-length ratios of the twenty-ninth NMOS tube MN29, the thirtieth NMOS tube MN30, the fortieth NMOS tube MN40 and the forty-first NMOS tube MN41 are the same as the width-to-length ratios of the twenty-ninth PMOS tube MP29 and the thirtieth PMOS tube MP30. At this time, the twenty-fifth PMOS tube MP25 and the twenty-sixth PMOS tube MP26 are used as input tubes, the thirty-fourth NMOS tube MN34, the thirty-fifth NMOS tube MN35, the thirty-sixth NMOS tube MN36 and the thirty-seventh NMOS tube MN37 are used as load tubes to detect the current, and the current is mirrored to the twenty-seventh PMOS tube MP27 and the twenty-eighth PMOS tube MP28. The twenty-seventh PMOS tube MP27 and the twenty-eighth PMOS tube MP28 are input tubes, and the thirty-eighth NMOS tube MN38 and the thirty-ninth NMOS tube MN39 are load tubes. The thirty-first NMOS tube MN31, the thirty-second NMOS tube MN32, and the thirty-third NMOS tube MN33 are diode structures with gate and drain short-circuited, and can generate voltage according to current. The width-to-length ratio of the thirty-first NMOS tube MN31 and the thirty-second NMOS tube MN32 is half of the width-to-length ratio of the thirty-third NMOS tube MN33. Because the current flowing into the thirty-first NMOS tube MN31 and the thirty-second NMOS tube MN32 in static state is half of the current flowing into the thirty-third NMOS tube MN33, the common-mode voltages in static state are equal, and the voltage can be stabilized.The common-mode control and signal shaping current can flow into the 31st NMOS tube MN31 and the 32nd NMOS tube MN32 through the 20th PMOS tube MP20 and the 21st PMOS tube MP21 to raise the common-mode voltage, and can also draw out the current of the 31st NMOS tube MN31 and the 32nd NMOS tube MN32 through the 27th NMOS tube MN27 and the 28th NMOS tube MN28 to lower the common-mode voltage. When the input signals of the first input terminal INA4 and the second input terminal INB4 of the positive feedback full-wave comparison unit have no oscillation signal, the input is low level, and the common-mode voltage of the input terminal where the 31st NMOS tube MN31 and the 32nd NMOS tube MN32 are located is required. The level is higher than the common-mode level of the input end where the thirty-third NMOS tube MN33 is located. Since the first voltage Vb1 and the second voltage Vb2 remain unchanged, the currents of the twenty-fifth PMOS tube MP25, the twenty-sixth PMOS tube MP26, the twenty-seventh PMOS tube MP27 and the twenty-eighth PMOS tube MP28 will be reduced, and since the increase of the common-mode voltage will increase the third voltage Vb3 and the fourth voltage Vb4 of the bias voltage, that is, the gate voltages of the thirty-eighth NMOS tube MN38 and the thirty-ninth NMOS tube MN39 will be increased, the current will increase, the pull-down current of the node where the output end OUT4 of the positive feedback full-wave comparison unit is located is greater than the pull-up current, and the output end OUT4 of the positive feedback full-wave comparison unit outputs a low level. When there are oscillation signals at the first input terminal INA4 and the second input terminal INB4 of the positive feedback full-wave comparison unit, the up-rush oscillation signal will cut off the input tubes of the thirty-fourth NMOS tube MN34, the thirty-fifth NMOS tube MN35, the thirty-sixth NMOS tube MN36 and the thirty-seventh NMOS tube MN37, and the down-rush oscillation signal will pull down the sources of the thirty-fourth NMOS tube MN34, the thirty-fifth NMOS tube MN35, the thirty-sixth NMOS tube MN36 and the thirty-seventh NMOS tube MN37 while the gates remain unchanged, the currents of the twenty-fifth PMOS tube MP25, the twenty-sixth PMOS tube MP26, the twenty-seventh PMOS tube MP27 and the twenty-eighth PMOS tube MP28 increase, and the reduced third voltage Vb3 and fourth voltage Vb4 reduce the currents of the thirty-eighth NMOS tube MN38 and the thirty-ninth NMOS tube MN39, the pull-up current at the output terminal OUT4 of the positive feedback full-wave comparison unit is greater than the pull-down current, and the output terminal OUT4 of the positive feedback full-wave comparison unit outputs a high level.

[0101] refer to Figure 7In the circuit of the noise filtering module, the decoding signal outputted from the output terminal OUT4 of the positive feedback full-wave comparison unit is transmitted to the input terminal IN5 of the noise filtering module, and the thirty-fifth PMOS tube MP35, the thirty-sixth PMOS tube MP36, the forty-third NMOS tube MN43, and the forty-fourth NMOS tube MN44 constitute a first dual-input inverting structure, wherein the thirty-fifth PMOS tube MP35 is connected to the gate of the forty-fourth NMOS tube MN44, and the thirty-sixth PMOS tube MP36 is connected to the gate of the forty-third NMOS tube MN43; the thirty-seventh PMOS tube MP37, the thirty-eighth PMOS tube MP38, the forty-fifth NMOS tube MN45, and the forty-sixth NMOS tube MN46 constitute a second dual-input inverting structure, wherein the thirty-seventh PMOS tube MP37 is connected to the gate of the forty-sixth NMOS tube MN46, and the thirty-eighth PMOS tube MP38 is connected to the gate of the forty-fifth NMOS tube MN45. The above-mentioned dual-input inverting structure will only flip the signal when the two inputs are the same; after the input signal passes through the two-stage inverter, the 29th resistor R29 is used to charge and discharge the 15th capacitor C15 and the 16th capacitor C16 so that the voltage rises slowly, and then it is used as one end input of the two-input inverting structure, and the other end is the initial signal, so that the stray pulse can be filtered out. Reasonable setting of the 29th resistor R29, the 15th capacitor C15, and the 16th capacitor C16 can achieve different clutter filtering, and the 15th capacitor C15 and the 16th capacitor C16 have the same capacitance value, so that the rising edge and falling edge of the output signal of the output terminal OUT5 of the clutter filtering module have equal delay relative to the input signal of the input terminal IN5 of the clutter filtering module, thereby reducing pulse width distortion.

[0102] refer to Figure 8In the circuit of the dead time generation module, the signal outputted by the output terminal OUT5 of the clutter filtering module is transmitted to the input terminal IN6 of the dead time generation module, and then connected to the gate of the 48th NMOS tube MN48 through the 7th inverter INV7. The 7th inverter INV7 is also connected to the 8th inverter INV8, and then connected to the gate of the 47th NMOS tube MN47. The 47th NMOS tube MN47, the 48th NMOS tube MN48, the 39th PMOS tube MP39, and the 40th PMOS tube MP40 constitute a positive feedback level conversion, converting the power supply voltage from VL to VH. The 41st PMOS tube MP41 and the 51st NMOS tube MN51 constitute an inverting structure, wherein the drain end of the 41st PMOS tube MP41 is connected to the drain end of the 51st NMOS tube MN51, the source end of the 41st PMOS tube MP41 is connected to the power supply, the source end of the 51st NMOS tube MN51 is connected to the drain end of the 49th NMOS tube MN49, and the source end of the 49th NMOS tube MN49 is grounded. The 42nd PMOS tube MP42 and the 52nd NMOS tube MN52 form an inverting structure, wherein the drain end of the 42nd PMOS tube MP42 is connected to the drain end of the 52nd NMOS tube MN52, the source end of the 42nd PMOS tube MP42 is connected to the power supply, the source end of the 52nd NMOS tube MN52 is connected to the drain end of the 50th NMOS tube MN50, and the source end of the 50th NMOS tube MN50 is grounded. When the input signal of the input end IN6 of the dead time generation module is high level, the 47th NMOS tube MN47 is turned on, the 48th NMOS tube MN48 is turned off, the gate of the 41st PMOS tube MP41 is low level, and the gate of the 42nd PMOS tube MP42 is high level, at this time, the gate signal of the 50th NMOS tube MN50 rises and is driven by the first buffer Buffer1 to be output from the first output end OUTA6 of the dead time generation module. Since the forty-second PMOS tube MP42 is turned off, the gate signal of the forty-ninth NMOS tube MN49 is reduced and the fiftieth NMOS tube MN50 needs to be turned on first. The fiftieth NMOS tube MN50 is an inverse ratio tube and opens slowly. After opening, the gate of the forty-ninth NMOS tube MN49 is pulled down and output through the second output terminal OUTB6 of the dead time generating module. At this point, there is almost no delay between the rising edge of the second output terminal OUTB6 of the dead time generating module and the rising edge of the input signal of the input terminal IN6 of the dead time generating module, and there is a delay between the falling edge of the output signal of the first output terminal OUTA6 of the dead time generating module and the rising edge of the input signal of the input terminal IN6 of the dead time generating module.When the input signal of the input terminal IN6 of the dead time generation module is at a low level, similarly, there is almost no delay between the rising edge of the first output terminal OUTA6 of the dead time generation module and the falling edge of the input signal of the input terminal IN6 of the dead time generation module, and there is a delay between the falling edge of the output signal of the second output terminal OUTB6 of the dead time generation module and the falling edge of the input signal of the input terminal IN6 of the dead time generation module. The first output terminal OUTA6 and the second output terminal OUTB6 of the dead time generation module generate a fixed delayed dead time, and the delay difference of this dead time is generated by the difference in the width-to-length ratio (i.e., the difference in driving capability) of the forty-seventh NMOS tube MN47, the forty-eighth NMOS tube MN48, the forty-ninth NMOS tube MN49, and the fiftieth NMOS tube MN50, and is relatively stable under different processes and temperatures.

[0103] Compared with the prior art, the signal transmission method in an isolated driving circuit provided by the embodiment of the present application adopts a fully differential structure to transmit signals with high common-mode transient suppression capability. The encoding side uses a frequency-jittering oscillation circuit to expand the signal spectrum and optimize the circuit EMI problem. The dual-bandpass characteristics of coarse frequency selection and precise frequency selection on the decoding side optimize the suppression of noise. Common-mode control, signal shaping, and positive feedback full-wave comparator greatly improve the decoding rate and reliability and reduce signal delay. The noise filtering module and the dead time generation module further ensure the correctness and integrity of the signal, and improve the safety factor of the circuit. Compared with the prior art, the embodiment of the present application has higher common-mode transient suppression and noise suppression capabilities, lower signal delay, and more sufficient reliability and safety.

[0104] Although the present invention has been described in detail above by general description and specific embodiments, it is obvious to those skilled in the art that some modifications or improvements can be made to the present invention. Therefore, these modifications or improvements made without departing from the spirit of the present invention all belong to the scope of protection claimed by the present invention.

Claims

1. A signal transmission system in an isolation driving circuit, characterized in that: The system comprises: A signal encoding module, used for receiving the first control signal and modulating it into a double oscillation signal; Dual isolation channels for transmitting the dual oscillation signals to a decoding side; A signal decoding module, used for receiving the dual isolation channel signal and decoding it into a second control signal; A clutter filtering module, used for filtering out error pulses near the rising edge of the second control signal to obtain a third control signal; The dead time generating module is used to process the third control signal to generate two fourth control signals with preset dead time.

2. A signal transmission system in an isolation driving circuit as claimed in claim 1, characterized in that: The signal encoding module comprises: A fast start unit, used for quickly powering on and stabilizing the voltage to supply power to the internal sub-circuit upon receiving the first control signal; A frequency jitter oscillation unit, used for modulating the first control signal into a first oscillation signal that changes randomly within a preset frequency range; A voltage limiting output and undervoltage lockout unit, used to output a high level signal when the power-on voltage is greater than or equal to a first preset threshold or the undervoltage is greater than or equal to a second preset threshold; The encoding side dual high-pass filter channel comprises: a first high-pass filter and a second high-pass filter; the first oscillation signal and the high-level signal are transmitted together through an AND gate circuit, and the output end of the AND gate circuit is connected to the input end of the first high-pass filter and the input end of the second high-pass filter through a first inverter group and a second inverter group respectively; The first inverter group and the second inverter group have different preset numbers of first inverters INV1 , the first inverter group includes four first inverters INV1 , and the second inverter group includes three first inverters INV1 .

3. A signal transmission system in an isolation driving circuit as claimed in claim 2, characterized in that: The frequency-jittering oscillation unit includes: a random number generator and a ring oscillator, and the ring oscillator includes: a first PMOS tube MP1, a second PMOS tube MP2, a third PMOS tube MP3, a fourth PMOS tube MP4, a first NMOS tube MN1, a second NMOS tube MN2, a third NMOS tube MN3, and a fourth NMOS tube MN4; the gate of the first PMOS tube MP1 and the first NMOS tube MN1, the drain of the first PMOS tube MP1 and the first NMOS tube MN1, the gate of the second PMOS tube MP2 and the second NMOS tube MN2, the drain of the second PMOS tube MP2 and the second NMOS tube MN2, the gate of the third PMOS tube MP3 and the third NMOS tube MN3, the drain of the third PMOS tube MP3 and the third NMOS tube MN3, the gate of the fourth PMOS tube MP4 and the fourth NMOS tube MN4, and the drain of the fourth PMOS tube MP4 and the fourth NMOS tube MN4 are respectively connected to form a first connection point AP1, a second connection point AP2, and a third connection point AP4. The first connection point AP1 is connected to a ninth connection point AP9 between the sixth connection point AP6 and the seventh connection point AP7. The eighth connection point AP8 forms an output end OUT of the frequency-jittering oscillation unit. The sources of the first PMOS transistor MP1, the second PMOS transistor MP2, the third PMOS transistor MP3 and the fourth PMOS transistor MP4 are connected to the internal power supply line. The sources of the first NMOS transistor MN1, the second NMOS transistor MN2, the third NMOS transistor MN3 and the fourth NMOS transistor MN4 are grounded. The output ends of the random number generator are connected to the source grounding line of the first NMOS transistor MN1 through an NMOS transistor to form an access point. A resistor is arranged between two adjacent access points.

4. The signal transmission system in the isolation driving circuit according to claim 3, characterized in that: The signal decoding module includes: a coarse frequency selection unit, a precise frequency selection unit, a common mode control and signal shaping unit, and a positive feedback full-wave comparison unit; the coarse frequency selection unit includes: a dual high-pass filter channel on the decoding side and a three-stage cascade differential positive feedback amplifier; the precise frequency selection unit includes: a differential bandpass operational amplifier; the dual isolation channel signals are sent to the three-stage cascade differential positive feedback amplifier via the dual high-pass filter channel on the decoding side to generate a differential signal; the differential signal is processed by the precise frequency selection unit and the common mode control and signal shaping unit in turn and then input into the positive feedback full-wave comparison unit, and a second control signal is obtained after decoding.

5. A signal transmission system in an isolation driving circuit as claimed in claim 4, characterized in that: The decoding side dual high-pass filter channel includes: a third high-pass filter, a fourth high-pass filter, a thirty-first PMOS tube MP31 and a forty-second NMOS tube MN42; the third high-pass filter includes: a third capacitor C3 and a fourteenth resistor R14, the fourth high-pass filter includes: a fourth capacitor C4 and a fifteenth resistor R15, one end of the third capacitor C3 and the fourth capacitor C4 respectively form the input end of the third high-pass filter and the fourth high-pass filter, the other end of the third capacitor C3 and the fourth capacitor C4 respectively form the output end of the third high-pass filter and the fourth high-pass filter, the fourteenth resistor R12 One end of the thirteenth resistor R13 is respectively connected to the other end of the third capacitor C3 and the fourth capacitor C4, the other ends of the fourteenth resistor R14 and the fifteenth resistor R15 are connected to form a tenth connection point AP10; the source of the thirty-first PMOS tube MP31 is connected to the internal power supply line, the source of the forty-second NMOS tube MN42 is grounded, the gate and drain of the thirty-first PMOS tube MP31 are connected to the eleventh connection point AP11, the gate and drain of the forty-second NMOS tube MN42 are connected to the eleventh connection point AP11, and the tenth connection point AP10 is connected to the eleventh connection point AP11.

6. A signal transmission system in an isolation driving circuit as claimed in claim 5, characterized in that: The common mode control and signal shaping unit includes: a nineteenth PMOS tube MP19, a twentieth PMOS tube MP20, a twenty-first PMOS tube MP21, a twenty-fifth NMOS tube MN25, a twenty-sixth NMOS tube MN26, a twenty-seventh NMOS tube MN27, a twenty-eighth NMOS tube MN28, a thirteenth capacitor C13, a fourteenth capacitor C14, an eighteenth resistor R18, a nineteenth resistor R19, a twentieth resistor R20, a twenty-first resistor R21, a twenty-second resistor R22, a twenty-third resistor R23, and an operational amplifier OPA; the source of the nineteenth PMOS tube MP19 is connected to the internal power supply line, and the drain of the nineteenth PMOS tube MP19 is connected to the ...first The sources of the PMOS transistor MP20 and the twenty-first PMOS transistor MP21, the sources of the twenty-fifth NMOS transistor MN25 and the twenty-sixth NMOS transistor MN26 are grounded, the gates of the twenty-fifth NMOS transistor MN25 and the twenty-sixth NMOS transistor MN26 are connected, the gate and the drain of the twenty-fifth NMOS transistor MN25 are connected and connected to the internal power supply line, the drain of the twenty-sixth NMOS transistor MN26 is connected to the sources of the twenty-seventh NMOS transistor MN27 and the twenty-eighth NMOS transistor MN28, the gate of the 20th PMOS transistor MP20 is connected to the gate of the twenty-seventh NMOS transistor MN27 to form a fourteenth connection point AP14 , the drain of the 20th PMOS transistor MP20 is connected to the drain of the 27th NMOS transistor MN27 to form a 15th connection point AP15, the gate of the 21st PMOS transistor MP21 is connected to the gate of the 28th NMOS transistor MN28 to form a 16th connection point AP16, the drain of the 21st PMOS transistor MP21 is connected to the drain of the 28th NMOS transistor MN28 to form a 17th connection point AP17, one end of the 13th capacitor C13 is connected to the 14th connection point AP14, the other end of the 13th capacitor C13 is connected to one end of the 18th resistor R18, and the other end of the 18th resistor R18 forms the common mode control and signal shaping unit externally. The first input terminal INA3 of the common-mode control and signal shaping unit is connected to the first input terminal INA3 of the element, one end of the fourteenth capacitor C14 is connected to the sixteenth connection point AP16, the other end of the fourteenth capacitor C14 is connected to one end of the twenty-third resistor R23, the other end of the twenty-third resistor R23 forms the second input terminal INB3 of the common-mode control and signal shaping unit to the outside, the two ends of the nineteenth resistor R19 are respectively connected to the fourteenth connection point AP14 and the fifteenth connection point AP15, the fifteenth connection point AP15 is connected to the seventeenth connection point AP17 via the twentieth resistor R20 and the twenty-first resistor R21 in sequence, and the eighteenth connection point AP18 is formed between the twentieth resistor R20 and the twenty-first resistor R21,The two ends of the 22nd resistor R22 are respectively connected to the 16th connection point AP16 and the 17th connection point AP17, the first input end of the operational amplifier OPA is connected to the first preset reference level V1, the second input end of the operational amplifier OPA is connected to the 18th connection point AP18, the output end of the operational amplifier OPA is connected to the gate of the 19th PMOS tube MP19, and the drains of the 28th NMOS tube MN28 and the 27th NMOS tube MN27 respectively form the first output end OUTA3 and the second output end OUTB3 of the common mode control and signal shaping unit.

7. A signal transmission system in an isolation driving circuit as claimed in claim 6, characterized in that: The positive feedback full-wave comparison unit includes: a twenty-second PMOS tube MP22, a twenty-third PMOS tube MP23, a twenty-fourth PMOS tube MP24, a twenty-fifth PMOS tube MP25, a twenty-sixth PMOS tube MP26, a twenty-seventh PMOS tube MP27, a twenty-eighth PMOS tube MP28, a twenty-ninth PMOS tube MP29, a thirtieth PMOS tube MP30, a thirty-second PMOS tube MP32, a thirty-third PMOS tube MP33, a thirty-fourth PMOS tube MP34, a twenty-ninth NMOS tube MN29, a thirtieth NMOS tube MN30, a thirty-first NMOS tube MN31, a thirty-second NMOS tube MN32, and a thirty-third NMOS tube MN34. the S transistor MN33, the thirty-fourth NMOS transistor MN34, the thirty-fifth NMOS transistor MN35, the thirty-sixth NMOS transistor MN36, the thirty-seventh NMOS transistor MN37, the thirty-eighth NMOS transistor MN38, the thirty-ninth NMOS transistor MN39, the fortieth NMOS transistor MN40, the forty-first NMOS transistor MN41, the twenty-fourth resistor R24, the twenty-fifth resistor R25, the twenty-sixth resistor R26, the twenty-seventh resistor R27, the twenty-eighth resistor R28; the thirty-second PMOS transistor MP32, the thirty-fourth PMOS transistor MP34, the twenty-second PMOS transistor MP22, the twenty-third PMOS transistor MP23, the twenty-fifth PMOS transistor The sources of the thirty-third PMOS tube MP33, the twenty-fourth PMOS tube MP24, the twenty-sixth PMOS tube MP26, the twenty-eighth PMOS tube MP28, and the thirtieth PMOS tube MP30 are respectively connected to the drains of the thirty-fourth PMOS tube MP34, the twenty-third PMOS tube MP23, the twenty-fifth PMOS tube MP25, the twenty-seventh PMOS tube MP27, and the twenty-ninth PMOS tube MP29, and the thirty-second PMOS tube MP32, the twenty-second PMOS tube MP33, the twenty-fourth PMOS tube MP24, the twenty-sixth PMOS tube MP26, the twenty-eighth PMOS tube MP28, and the thirtieth PMOS tube MP30 are respectively connected to the drains of the thirty-fourth PMOS tube MP34, the twenty-third PMOS tube MP23, the twenty-fifth PMOS tube MP25, the twenty-seventh PMOS tube MP27, and the twenty-ninth PMOS tube MP29. The gate and drain of the S transistor MP22 are connected to the ground, the gate of the thirty-fourth PMOS transistor MP34 is connected to the drain of the thirty-third PMOS transistor MP33 and is grounded, the gate of the thirty-second PMOS transistor MP32 is connected to the gates of the thirty-third PMOS transistor MP33, the twenty-fourth PMOS transistor MP24, and the thirtieth PMOS transistor MP30, the gate of the twenty-second PMOS transistor MP22 is connected to the gates of the twenty-sixth PMOS transistor MP26 and the twenty-eighth PMOS transistor MP28, the gate of the thirty-fourth PMOS transistor MP34 is connected to the gates of the twenty-third PMOS transistor MP23 and the twenty-ninth PMOS transistor MP29,The gate of the twenty-fifth PMOS transistor MP25 is connected to the gate of the twenty-seventh PMOS transistor MP27, the gate of the twenty-fifth PMOS transistor MP25 is connected to the drain of the twenty-sixth PMOS transistor MP26 and connected to the drains of the thirty-fourth NMOS transistor MN34 and the thirty-fifth NMOS transistor MN35, the sources of the thirty-first NMOS transistor MN31, the thirty-second NMOS transistor MN32, and the thirty-third NMOS transistor MN33 are grounded, the drain of the thirty-first NMOS transistor MN31 is connected to the source of the thirty-sixth NMOS transistor MN36 and forms a nineteenth connection point AP19, the drain of the thirty-second NMOS transistor MN32 is connected to the drain of the thirty-third NMOS transistor MN33. The sources of the seventh NMOS tube MN37 are connected to form a twentieth connection point AP20, the gate and drain of the thirty-first NMOS tube MN31 are connected, the gate and drain of the thirty-second NMOS tube MN32 are connected, the gate and drain of the thirty-third NMOS tube MN33 are connected, the nineteenth connection point AP19 and the twentieth connection point AP20 form the first input terminal INA4 and the second input terminal INB4 of the positive feedback full-wave comparison unit, the drains of the thirty-sixth NMOS tube MN36 and the thirty-seventh NMOS tube MN37 are connected to the sources of the thirty-fourth NMOS tube MN34 and the thirty-fifth NMOS tube MN35, respectively, and the thirty-fourth NMOS tube MN The gate of the thirty-fifth NMOS tube MN34 is connected to the gate of the thirty-fifth NMOS tube MN35 to form a twenty-first connection point AP21, the gate of the thirty-sixth NMOS tube MN36 is connected to the gate of the thirty-seventh NMOS tube MN37 to form a twenty-second connection point AP22, the source of the twenty-ninth NMOS tube MN29 is connected to the drain of the thirtieth NMOS tube MN30, the drain of the twenty-ninth NMOS tube MN29 is connected to one end of the twenty-fourth resistor R24 ​​to form a twenty-third connection point AP23, the other end of the twenty-fourth resistor R24 ​​is connected to the drain of the twenty-fourth PMOS tube MP24 to form a twenty-fourth connection point AP24, the thirtieth NMOS tube MN3 The source of the third NMOS transistor MN30 is connected to one end of the twenty-fifth resistor R25 and the twenty-sixth resistor R26, the other ends of the twenty-fifth resistor R25 and the twenty-sixth resistor R26 are respectively connected to the sources of the thirty-sixth NMOS transistor MN36 and the thirty-seventh NMOS transistor MN37, the drain of the thirty-third NMOS transistor MN33 is connected to the source of the thirty-ninth NMOS transistor MN39 to form a twenty-fifth connection point AP25, the drain of the thirty-ninth NMOS transistor MN39 is connected to the source of the thirty-eighth NMOS transistor MN38, the drain of the thirty-eighth NMOS transistor MN38 is connected to the drain of the twenty-eighth PMOS transistor MP28 to form a twenty-sixth connection point AP26,The twenty-sixth connection point AP26 forms the output terminal OUT4 of the positive feedback full-wave comparison unit, the gate of the 30th NMOS tube MN30 is connected to the twenty-third connection point AP23 and connected to the gate of the thirty-ninth NMOS tube MN39, the gate of the twenty-ninth NMOS tube MN29 is connected to the twenty-fourth connection point AP24 and connected to the gate of the thirty-eighth NMOS tube MN38, the twenty-fifth connection point AP25 is connected to the source of the forty-first NMOS tube MN41 via the twenty-eighth resistor R28, the drain of the forty-first NMOS tube MN41 is connected to the source of the fortieth NMOS tube MN40, The drain of the 40th NMOS transistor MN40 is connected to one end of the 27th resistor R27 to form a 27th connection point AP27, the other end of the 27th resistor R27 is connected to the drain of the 30th PMOS transistor MP30 to form a 28th connection point AP28, the gate of the 41st NMOS transistor MN41 is connected to the 27th connection point AP27 and connected to the 22nd connection point AP22, the gate of the 40th NMOS transistor MN40 is connected to the 28th connection point AP28 and connected to the 21st connection point AP21, and the drain and gate of the 33rd NMOS transistor MN33 are connected to the second preset reference level V2.

8. The signal transmission system in the isolation driving circuit according to claim 7, characterized in that: The clutter filtering module includes: a thirty-fifth PMOS tube MP35, a thirty-sixth PMOS tube MP36, a thirty-seventh PMOS tube MP37, a thirty-eighth PMOS tube MP38, a forty-third NMOS tube MN43, a forty-fourth NMOS tube MN44, a forty-fifth NMOS tube MN45, a forty-sixth NMOS tube MN46, a second inverter INV2, a third inverter INV3, a fourth inverter INV4, a fifth inverter INV5, a sixth inverter INV6, a twenty-ninth resistor R29, a fifteenth capacitor C15, and a sixteenth capacitor C16; the second inverter The input end of INV2 forms the input end IN5 of the clutter filtering module externally, the output end of the second inverter INV2 is connected to the input end of the sixth inverter INV6 through the third inverter INV3, the twenty-ninth resistor R29, and the fifth inverter INV5 in sequence, one end of the fifteenth capacitor C15 and the sixteenth capacitor C16 are connected to the twenty-ninth connection point AP29 between the twenty-ninth resistor R29 and the fifth inverter INV5, the other end of the fifteenth capacitor C15 is connected to the internal power supply line, and the other end of the sixteenth capacitor C16 is grounded;The output end of the second inverter INV2 is connected to the gates of the thirty-fifth PMOS tube MP35 and the forty-fourth NMOS tube MN44 through the fourth inverter INV4. The sources of the thirty-fifth PMOS tube MP35 and the thirty-seventh PMOS tube MP37 are connected to the internal power supply line. The drains of the thirty-fifth PMOS tube MP35 and the thirty-seventh PMOS tube MP37 are connected to the sources of the thirty-sixth PMOS tube MP36 and the thirty-eighth PMOS tube MP38, respectively. The drains of the thirty-sixth PMOS tube MP36 and the forty-third NMOS tube MN43 are connected to form a thirtieth connection point AP30. The gates of the thirty-sixth PMOS tube MP36 and the forty-third NMOS tube MN43 are connected to form a thirty-first connection point AP31. The drains of the thirty-eighth PMOS tube MP38 and the forty-fifth NMOS tube MN45 are connected to form a thirty-second connection point AP32. The drains of the thirty-eighth PMOS tube MP38 and the forty-third NMOS tube MN43 are connected to form a thirty-first connection point AP33. The gates of the forty-fifth NMOS tube MN45 are connected to form a thirty-third connection point AP33, the sources of the forty-third NMOS tube MN43 and the forty-fifth NMOS tube MN45 are connected to the drains of the forty-fourth NMOS tube MN44 and the forty-sixth NMOS tube MN46 respectively, the sources of the forty-fourth NMOS tube MN44 and the forty-sixth NMOS tube MN46 are grounded, the thirtieth connection point AP30 is connected to the thirty-third connection point AP33 and connected to the twenty-ninth connection point AP29, the thirty-first connection point AP31 is connected to the thirty-second connection point AP32 and connected to the thirty-fourth connection point AP34 between the fifth inverter INV5 and the sixth inverter INV6, the gates of the thirty-seventh PMOS tube MP37 and the forty-sixth NMOS tube MN46 are connected to the output end of the sixth inverter INV6, and the output end of the sixth inverter INV6 forms the output end OUT5 of the clutter filtering module. ; 9. A signal transmission system in an isolation driving circuit as claimed in claim 8, characterized in that: The dead time generating module includes: a 39th PMOS tube MP39, a 40th PMOS tube MP40, a 41st PMOS tube MP41, a 42nd PMOS tube MP42, a 47th NMOS tube MN47, a 48th NMOS tube MN48, a 49th NMOS tube MN49, a 50th NMOS tube MN50, a 51st NMOS tube MN51, a 52nd NMOS tube MN52, a 7th inverter INV7, an 8th inverter INV8, a 1st buffer Buffer1, and a 2nd buffer Buffer2;The input end of the seventh inverter INV7 forms the input end IN6 of the dead time generating module externally, the output end of the seventh inverter INV7 is connected to the gate of the forty-seventh NMOS tube MN47 through the eighth inverter INV8, and the output end of the seventh inverter INV7 is connected to the gate of the forty-eighth NMOS tube MN48 in another way, the source of the thirty-ninth PMOS tube MP39, the fortieth PMOS tube MP40, the forty-first PMOS tube MP41, and the forty-second PMOS tube MP42 are connected to the internal power supply line, and the thirty-ninth PMOS tube MP39, the fortieth PMOS tube MP40, the forty-first PMOS tube MP41, and the forty-second PMOS tube MP42 are connected to the internal power supply line. The drains of the MOS tube MP41 and the forty-second PMOS tube MP42 are respectively connected to the drains of the forty-seventh NMOS tube MN47, the forty-eighth NMOS tube MN48, the fifty-first NMOS tube MN51, and the fifty-second NMOS tube MN52, the sources of the fifty-first NMOS tube MN51 and the fifty-second NMOS tube MN52 are respectively connected to the drains of the forty-ninth NMOS tube MN49 and the fiftieth NMOS tube MN50, the sources of the forty-seventh NMOS tube MN47, the forty-eighth NMOS tube MN48, the forty-ninth NMOS tube MN49, and the fiftieth NMOS tube MN50 are grounded, and the The gate of the 40th PMOS tube MP40 is connected to the seventh intersection CP7 between the drain of the 39th PMOS tube MP39 and the drain of the 47th NMOS tube MN47, the gate of the 39th PMOS tube MP39 is connected to the eighth intersection CP8 between the drain of the 40th PMOS tube MP40 and the drain of the 48th NMOS tube MN48, the gates of the 41st PMOS tube MP41 and the 51st NMOS tube MN51 are connected and connected to the seventh intersection CP7, the gates of the 42nd PMOS tube MP42 and the 52nd NMOS tube MN52 are connected and connected to the eighth intersection CP8, and the The gate of the 50th NMOS tube MN50 is connected to the ninth intersection CP9 between the drain of the 41st PMOS tube MP41 and the drain of the 51st NMOS tube MN51, the gate of the 49th NMOS tube MN49 is connected to the tenth intersection CP10 between the drain of the 42nd PMOS tube MP42 and the drain of the 52nd NMOS tube MN52, the ninth intersection CP9 forms the first output terminal OUTA6 of the dead time generating module through the first buffer Buffer1, and the tenth intersection CP10 forms the second output terminal OUTB6 of the dead time generating module through the second buffer Buffer2.

10. A signal transmission method in an isolation driving circuit, characterized in that: The method comprises: The signal encoding module receives the first control signal and modulates it into a double oscillation signal; The double oscillation signal is transmitted to the decoding side through the double isolation channel; The signal decoding module receives the dual isolation channel signal and decodes it into a second control signal; The clutter filtering module filters out the bit error pulse near the rising edge of the second control signal to obtain a third control signal; The dead time generating module processes the third control signal to generate two fourth control signals with preset dead time.

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