Memory device, manufacturing method of memory device and semiconductor device

Abstract

The invention provides a memory device and a manufacturing method thereof, and a semiconductor device, and the memory device comprises a substrate which comprises an insulating surface; a memory cell array including a plurality of memory cells disposed on the insulating surface, the plurality of memory cells being repeatedly arranged in a first horizontal direction, a second horizontal direction, and a vertical direction, the first horizontal direction intersecting the second horizontal direction; each memory cell comprises a transistor, the transistor comprises a gate insulating layer, a gate structure and an active layer parallel to the insulating surface, the gate structure comprises a gate main body part, the gate main body part comprises a first gate, the first gate extends along the side wall of the active layer, and the gate insulating layer is located between the first gate and the active layer; the bit line structure comprises a plurality of bit lines extending in the first horizontal direction, and the active layer comprises a source end connected to the common source electrode structure and a drain end connected to one bit line. The storage device is high in storage density and simple in preparation process.

Description

Technical Field

[0001] The present application belongs to the field of semiconductor technology, and in particular, relates to a storage device, a method for manufacturing a storage device, and a semiconductor device. Background Art

[0002] With the miniaturization of technology nodes, the storage unit of DRAM (Dynamic Random Access Memory) has gradually changed from a 1T1C (1Transistor 1Capacitor) structure to a 1T0C (1Transistor 0Capacitor) structure. The use of a capacitor-free structure reduces the size of the storage unit and improves the storage density.

[0003] In the prior art, DRAM memory cells are usually repeatedly arranged in space to form a three-dimensional stacked structure with high storage density. However, as the number of stacked layers of the three-dimensional stacked structure increases and the process nodes shrink, the difficulty of the manufacturing process gradually increases. Summary of the invention

[0004] The embodiments of the present application provide a storage device, which aims to at least solve the technical problem of the difficulty in the preparation process of a semiconductor device with a three-dimensional stacked structure.

[0005] The embodiment of the present application is implemented as follows: a storage device includes:

[0006] a substrate, including an insulating surface;

[0007] A memory cell array, the memory cell array comprising a plurality of memory cells disposed on the insulating surface, the plurality of memory cells being repeatedly arranged along a first horizontal direction, a second horizontal direction and a vertical direction, the first horizontal direction intersecting the second horizontal direction;

[0008] Each of the memory cells comprises a transistor, the transistor comprises an active layer, a gate insulating layer and a gate structure, the gate structure comprises a gate body portion, the gate body portion comprises a first gate, the active layer is parallel to the insulating surface, the first gate extends along a side wall of the active layer, and the gate insulating layer is located between the first gate and the active layer;

[0009] The storage device also includes a common source structure and a bit line structure, the bit line structure includes a plurality of bit lines, each of the bit lines extends along the first horizontal direction, the active layer includes a source terminal and a drain terminal, the source terminal is connected to the common source structure, and the drain terminal is connected to one of the bit lines.

[0010] The present application also provides a method for manufacturing a storage device, comprising the steps of:

[0011] providing a substrate;

[0012] Preparing a plurality of film layer pairs stacked along a vertical direction on the substrate, wherein the film layer pairs include a semiconductor material layer and a first insulating dielectric layer sequentially arranged along the vertical direction;

[0013] Etching the plurality of film layer pairs to form a plurality of first slits repeatedly arranged along a first horizontal direction and a second horizontal direction, wherein the first horizontal direction intersects with the second horizontal direction, and the first slits penetrate the plurality of film layer pairs along a vertical direction to form a second insulating dielectric layer filling the first slits, and in the second horizontal direction, the semiconductor material layer on one side of the first slit is formed into a bit line structure, wherein the bit line structure includes a plurality of bit lines, each of the bit lines extending along the first horizontal direction, and a common source structure is formed on a side of the first slit away from the bit line;

[0014] Etching the second insulating dielectric layer in the first gap to form a plurality of first grooves repeatedly arranged along the first horizontal direction and the second horizontal direction, wherein the first grooves penetrate the second insulating dielectric layer along the vertical direction, the first grooves correspond to the first gaps one by one, the two opposite side walls of the first groove in the first horizontal direction both expose the semiconductor material layer, and in the orthographic projection of the substrate, the two opposite side walls of the first groove in the second horizontal direction fall into the first groove;

[0015] forming a gate material layer on the entire sidewall of the first trench and a gate insulating material layer between the gate material layer and the surface of the semiconductor material layer exposed by the first trench, and filling a third insulating dielectric layer in the space surrounded by the gate material layer;

[0016] Etching the gate material layer to form a plurality of second grooves repeatedly arranged along the first horizontal direction and the second horizontal direction, wherein the second grooves penetrate the gate material layer, so that the gate material layer is formed into a first gate structure and a second gate structure spaced apart in the first horizontal direction;

[0017] A fourth insulating dielectric layer is filled in the second trench.

[0018] The present application also provides a semiconductor device, including:

[0019] substrate;

[0020] a transistor stack comprising a plurality of transistors stacked vertically on said substrate;

[0021] The transistor comprises an active layer and a gate electrode, the active layer extends in a horizontal direction, the gate electrode is located on a side wall of the active layer, and all gate electrodes in the transistor stack overlap in positive projection on the substrate;

[0022] The gate electrode includes an integrated gate body and a conductor part, wherein the gate body is arranged along the length direction of the active layer, the conductor part is located on the side of the gate body away from the active layer, and the conductor part is located at both ends of the gate body in the horizontal direction.

[0023] In the storage device of the embodiment of the present application, multiple DRAM storage cells of the 1T0C structure are repeatedly arranged along the first horizontal direction, the second horizontal direction and the vertical direction. The storage cell structure is simple, the storage density is high, the preparation process is simple, and the storage capacity can be improved by further increasing the number of stacking layers as needed. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 is a three-dimensional schematic diagram of a storage device according to an embodiment of the present application;

[0025] Figure 2 yes Figure 1 A schematic cross-sectional view of section C1 of the storage device shown;

[0026] Figure 3 is a schematic cross-sectional view of a transistor according to an embodiment of the present application in a first horizontal direction and a second horizontal direction;

[0027] Figure 4 is a cross-sectional schematic diagram of a transistor in another embodiment of the present application in a first horizontal direction and a second horizontal direction;

[0028] Figure 5 yes Figure 1 A schematic cross-sectional view of the storage device shown on section C2;

[0029] Figure 6 yes Figure 1 A schematic cross-sectional view of the storage device shown on section C3;

[0030] Figure 7 yes Figure 1 A schematic cross-sectional view of the storage device shown on section C4;

[0031] Figure 8 is a schematic diagram of the structure of a storage device according to an embodiment of the present application;

[0032] Fig. 9 is a cross-sectional schematic diagram of a storage device according to another embodiment of the present application in a first horizontal direction and a second horizontal direction;

[0033] Fig.10is a schematic flow chart of a method for manufacturing a storage device according to an embodiment of the present application;

[0034] Figures 11 to 19 is a schematic diagram of a process flow of a method for manufacturing a storage device according to an embodiment of the present application;

[0035] Fig. 20 Schematic diagram of the circuit connection of the storage unit according to the embodiment of the present application.

[0036] Description of main component symbols:

[0037] Memory device-1000; substrate-200; insulating surface-210; memory cell-100; active layer-1111; source terminal-11111; drain terminal-11112; channel region-11113; gate insulating layer-1112; gate structure-1113; gate body-1113A; first gate-11131; second gate-11132; conductor part-1113B; first conductor part-11133; second conductor part-11134; memory cell stack group-11A; first memory cell stack-111A; second memory cell stack-112A; common source-110; bit line structure-120; first insulating layer-130; second insulating layer-140; third insulating layer-150; insulating spacer-160;

[0038] Substrate-1A; film layer pair-1; semiconductor material layer-2; first insulating dielectric layer-3; first gap-4; second insulating dielectric layer-5; first trench-6; gate material layer-7; gate insulating material layer-8; third insulating dielectric layer-9; second insulating layer-9a; third insulating layer-9b; second trench-10; pre-trench-10A; first gate structure-11; second gate structure-12; fourth insulating dielectric layer / first insulating layer-13; third trench-14; conductive layer-15. DETAILED DESCRIPTION

[0039] In order to make the purpose, technical solutions and advantages of the present application clearer, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements with the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and should not be construed as limiting the present application. In addition, it should be understood that the specific embodiments described herein are only used to explain the present application and are not intended to limit the present application.

[0040] In the description of the present application, it should be understood that the orientation or positional relationship indicated in the description of the direction and positional relationship is based on the orientation or positional relationship shown in the accompanying drawings, which is only for the convenience of describing the present application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application.

[0041] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0042] The disclosure below provides many different embodiments or examples to realize the different structures of the present application. In order to simplify the disclosure of the present application, the parts and settings of specific examples are described below. Of course, they are only examples, and the purpose is not to limit the present application. In addition, the present application can repeat reference numbers and / or reference letters in different examples, and this repetition is for the purpose of simplification and clarity, which itself does not indicate the relationship between the various embodiments and / or settings discussed. In addition, the various specific processes and material examples provided by the present application, but those of ordinary skill in the art can appreciate the application of other processes and / or the use of other materials.

[0043] In the embodiments of the present application, the technical concept "layer" refers to a material portion including an area with a thickness. A layer may extend over the entire lower structure or upper structure, or may have a range smaller than the lower structure or upper structure. In addition, a layer may be an area of ​​a uniform or non-uniform continuous structure whose thickness is less than the thickness of the continuous structure.

[0044] For example, a layer may be located between the top surface and the bottom surface of the continuous structure or between any pair of horizontal planes at the top surface and the bottom surface of the continuous structure. The layer may extend horizontally, vertically and / or along a tapered surface. The substrate may be a layer, may include one or more layers therein, and / or may have one or more layers thereon, above it and / or below it. The layer may include multiple layers. For example, an interconnect layer may include one or more conductors and a contact layer (wherein interconnects and / or via contacts are formed) and one or more dielectric layers.

[0045] In the embodiments of the present application, the technical concept of “vertical / vertically” should be understood as perpendicular to the lateral surface of the substrate, and the technical concept of “parallel / parallel” should be understood as parallel to the lateral surface of the substrate.

[0046] Specifically, "perpendicular" means approximately perpendicular, for example, the angle formed by two straight lines is greater than 80° and less than 100°, and therefore, the angle is greater than 85° and less than 95°. In addition, "parallel" means approximately parallel or almost parallel, for example, the angle formed by two straight lines is greater than 10° and less than 10°, and therefore, the angle is greater than 5° and less than 5°.

[0047] The technical concept of "A and B are arranged in the same layer" in the embodiment of the present application means that A and B are formed simultaneously through the same patterning process. The technical concept of "the orthographic projection of B is within the range of the orthographic projection of A" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0048] The technical concept of the embodiment of the present application that "A and B are an integrated structure" may refer to the absence of obvious boundary interfaces such as obvious faults or gaps in the microstructure. Generally, a film layer patterned to form a connection on a film layer is an integrated structure. For example, A and B use the same material to form a film layer and simultaneously form a structure with a connection relationship through the same patterning process.

[0049] See also Figures 1 to 7 , the storage device 1000 of the embodiment of the present application includes:

[0050] A substrate 200 including an insulating surface 210;

[0051] A memory cell array, the memory cell array comprising a plurality of memory cells 100 disposed on an insulating surface 210, the plurality of memory cells 100 being repeatedly arranged along a first horizontal direction, a second horizontal direction and a vertical direction, the first horizontal direction intersecting the second horizontal direction;

[0052] Each memory cell 100 includes a transistor, the transistor includes an active layer 1111, a gate insulating layer 1112 and a gate structure 1113, the gate structure 1113 includes a gate body 1113A, the gate body 1113A includes a first gate 11131, the active layer 1111 is parallel to the insulating surface 210, the first gate 11131 extends along the sidewall of the active layer 1111, and the gate insulating layer 1112 is located between the gate structure 1113 and the active layer 1111;

[0053] The storage device 1000 also includes a common source 110 and a bit line structure 120, the bit line structure 120 includes a plurality of bit lines, each bit line extends along a first horizontal direction, the active layer 1111 includes a source terminal 11111 and a drain terminal 11112, the source terminal 11111 is connected to the common source 110, and the drain terminal 11112 is connected to a bit line.

[0054] Specifically, the substrate 200 may include a semiconductor substrate 200 and an insulating layer located on a side of the semiconductor substrate 200 close to the memory cell array. The surface of the insulating layer away from the semiconductor substrate 200 is formed as an insulating surface 210 of the substrate 200, and the memory cell 100 is insulated and spaced from the semiconductor substrate 200 by the insulating layer.

[0055] The substrate 200 may include a semiconductor material, for example, at least one of silicon (e.g., single crystal silicon Si), silicon germanium (SiGe), germanium (Ge), gallium arsenide (GaAs), indium phosphide (InP), and silicon carbide (SiC). For example, the semiconductor substrate 200 may be a single crystal silicon substrate 200, and optionally, the semiconductor substrate 200 includes a logic circuit.

[0056] In one embodiment, the insulating layer may include an insulating material commonly used in the art, such as silicon dioxide (SiO 2 ), silicon nitride (SiNx), and the like.

[0057] In one embodiment, the substrate 200 may be a single-layer structure, for example, a single-layer structure made of at least one of silicon, germanium, gallium arsenide, and the like.

[0058] In another embodiment, the substrate 200 may also be a multilayer structure, for example, a composite substrate 200 including a stack of silicon and silicon germanium, a stack of silicon and silicon carbide, silicon on insulator, germanium on insulator, or silicon germanium on insulator.

[0059] In other embodiments, the substrate 200 is an insulating substrate, and its upper surface is the insulating surface 210. The insulating substrate can be made of non-conductive materials such as glass, plastic, or sapphire wafer. Alternatively, the substrate 200 can also be silicon dioxide (SiO2), silicon nitride (SiN x ) and other insulating dielectric materials.

[0060] It can be understood that the first horizontal direction and the second horizontal direction are parallel to the substrate, and the vertical direction is perpendicular to the substrate. Figure 1 In the illustrated embodiment, the first horizontal direction is the Y-axis direction, the second horizontal direction is the X-axis direction, and the vertical direction is the Z-axis direction. It can be understood that the first horizontal direction, the second horizontal direction and the vertical direction can intersect. Preferably, the first horizontal direction is perpendicular to the second horizontal direction. Preferably, as Figure 1 In the illustrated embodiment, the X-axis direction is perpendicular to the Y-axis direction, and both the X-axis direction and the Y-axis direction are perpendicular to the Z-axis direction.

[0061] In the storage device 1000 of the embodiment of the present application, multiple storage cells 100 are repeatedly arranged along the first horizontal direction, the second horizontal direction and the vertical direction to form a storage cell array. The storage cell 100 has a simple structure, a high storage density, and a simple preparation process, and the storage capacity can be improved by further increasing the number of stacking layers as needed.

[0062] In the embodiment of the present application, the storage device 1000 may be regarded as comprising a plurality of storage device layers stacked in a vertical direction, wherein in each storage device layer, a plurality of storage cells 100 are repeatedly arranged along a first horizontal direction and a second horizontal direction, thereby forming an array arrangement, such as Figure 2 It can be understood that the array arrangement in the memory device layer is the same.

[0063] It is worth noting that “repeatedly arranged” indicates that the memory cell array is a 3D stacked structure, and the multiple memory cells 100 therein may not have exactly the same structure, that is, the structures of the multiple memory cells 100 may be the same or different.

[0064] For example, Figure 1 As shown, the functional structures of two adjacent memory cells 100 in the X direction are symmetrical about the common source 110, that is, they are not completely repeated in space; for example, the sizes, materials, component structures, etc. of any two memory cells 100 can be the same or different; for example, the extension directions of the active layers 1111 of any two memory cells 100 can be the same or different. However, this is not limited to this, and it depends on the specific situation.

[0065] Figure 1 Only a storage device 1000 formed by 3D stacking of several storage units 100 is shown. It can be understood that the storage device 1000 may include any number of storage device layers, and the storage device layers may include any number of storage units 100. The storage units 100 may be arbitrarily distributed and extended along the first horizontal direction, the second horizontal direction and the vertical direction to meet different storage requirements.

[0066] In the embodiment of the present application, the memory device 1000 may be a DRAM memory device, and its basic memory cell 100 is a DRAM memory cell of a 1T0C structure, that is, each memory cell 100 includes a transistor, that is, a single transistor may be the smallest memory cell 100 in the memory device 1000, such as Figure 3 and Figure 4 shown.

[0067] In the memory cell 100, the active layer 1111 is parallel to the insulating surface 210. For example, the active layer 1111 extends along the second horizontal direction, but is not limited thereto. For example, in other embodiments, the active layer 1111 may extend along a third horizontal direction intersecting both the first horizontal direction and the second horizontal direction. Alternatively, in another embodiment, the active layer 1111 may be bent, depending on the specific circumstances.

[0068] In the memory cell 100, the gate structure 1113 includes a gate body 1113A, the gate body 1113A includes a first gate 11131, and the first gate 11131 extends along the side wall of the active layer 1111. It can be understood that the gate body 1113A is the portion of the gate structure 1113 that can control the active layer 1111, that is, the gate body 1113A is the portion of the gate structure 1113 that extends along the active layer 1111. The active layer 1111 includes a top surface, a bottom surface, and two side walls located between the top surface and the bottom surface. The first gate 11131 extends along the side wall of the active layer 1111 parallel to the substrate 200. The first gate 11131 is substantially perpendicular to the substrate 200. On the orthographic projection of the substrate 200, the first gate 11131 is located on one side of the active layer 1111.

[0069] In the embodiment of the present application, the source terminal 11111 of the memory cell 100 is connected to the common source structure. The common source structure can be connected to a fixed potential, such as grounding. Thus, a fixed potential can be provided for the source terminal 11111 of the DRAM memory cell 100 of the 1T0C structure.

[0070] In one embodiment, the material of the common source structure may be the same as or different from the material of the active layer 1111. For example, the material of the common source structure may be a conductive material such as polysilicon, doped polysilicon or metal (eg, tungsten or titanium nitride).

[0071] like Figure 1 , 2 , 5 and Figure 6 As shown, the common source structure includes at least one common source 110 .

[0072] The common source structure includes at least one common source 110 vertically arranged on the substrate 200 , and the common source 110 also extends along the first horizontal direction. The common source 110 is connected to multiple source terminals 11111 adjacent in the vertical direction, and the source terminals 11111 adjacent in the first horizontal direction are connected to the same common source 110 .

[0073] like Figure 5As shown, the common source 110 can penetrate all the storage device layers in the vertical direction, for example, can vertically penetrate each layer of the multi-layer storage device layers from top to bottom; transistors adjacent to each other in the vertical direction in different layers of storage device layers can be connected to the same common source 110 accordingly.

[0074] like Figure 2 As shown, in the same memory device layer, the memory cells 100 are arranged in a column along the first horizontal direction. Since the common source 110 extends along the first horizontal direction, each memory cell 100 in the same column of transistors can be connected to the same common source 110 .

[0075] Furthermore, the two columns of memory cells 100 adjacent to the common source 110 in the second horizontal direction are symmetrically arranged about the common source 110 in terms of functional structure and are both connected to the same common source 110 , that is, the two columns of memory cells 100 adjacent to each other in the second horizontal direction can share the common source 110 .

[0076] Thus, the common source 110 can be formed as a plate-like structure extending in a plane formed in the vertical direction and the first horizontal direction. Thus, the common source 110 can be formed by etching a larger groove and filling the groove with a conductive material, which can reduce the difficulty of the preparation process and has lower impedance.

[0077] like Figure 8 As shown, the common source structure may include a plurality of common sources 110 , and the plurality of common sources 110 are arranged along the second horizontal direction.

[0078] However, the present application is not limited to this. In other embodiments not shown in the figure, the common source structure includes a plurality of common sources 110 vertically arranged on the substrate 200, and the common source 110 is connected to a plurality of source terminals 11111 adjacent in the vertical direction, and the source terminals 11111 adjacent in the first horizontal direction are connected to different common sources 110, that is, the common source 110 is formed as a columnar vertical conductor that passes through at least two adjacent storage device layers. In this case, the common source 110 is regarded as a vertical contact, and a plurality of vertical contacts are vertically stacked to form a common source structure.

[0079] Alternatively, the common source structure may include multiple common sources 110 extending along a first horizontal direction, each common source 110 corresponds to a storage device layer, adjacent source terminals 11111 in the first horizontal direction are connected to the same common source 110, and adjacent source terminals 11111 in the vertical direction are connected to different common sources 110, that is, the common source 110 can be formed as a linear horizontal conductor extending along the first horizontal direction, and multiple common sources 110 can be stacked in the vertical direction to reduce the horizontal area of ​​the common source structure.

[0080] The present application does not make any specific limitation on the common source structure, and it can be specifically configured according to specific needs.

[0081] like Figure 1 , 2 as well as Figure 8 As shown, the memory device 1000 includes a bit line structure, the bit line structure includes a plurality of bit lines, the bit lines extend along a first horizontal direction, and the drain terminal 11112 of the memory cell 100 is connected to the bit lines. In the embodiment of the present application, a specified memory cell 100 in the memory cell array can be selected by cross-positioning the gate structure 1113 and the bit lines.

[0082] The number of bit lines included in each memory device layer may be multiple. The multiple bit lines included in each memory device layer may be arranged at intervals along the second horizontal direction. In the same memory device layer, the memory cells 100 are arranged in a column along the first horizontal direction, the bit lines extend along the first horizontal direction, and each memory cell 100 in the same column of transistors may be connected to the same bit line.

[0083] Furthermore, if Figure 2 , Figure 8 As shown, in the memory device layer, two columns of memory cells 100 adjacent to the bit line in the second horizontal direction are symmetrically arranged about the bit line in terms of functional structure and are both connected to the same bit line, that is, the two columns of memory cells 100 adjacent to each other in the second horizontal direction can share the bit line.

[0084] In one embodiment, the material of the bit line may be the same as or different from the material of the common source 110 and the active layer 1111 .

[0085] By way of example, the material of the bit line may be polysilicon, doped polysilicon, or metal (eg, tungsten, titanium nitride, etc.), as long as it is conductive to achieve electrical connection with the source of the transistor.

[0086] Exemplarily, the bit line and the active layer 1111 in the transistor may be made of the same material, and the two may be connected as one.

[0087] In one embodiment, the material of the bit line and the material of the active layer 1111 can be the same, and the bit line and the active layer 1111 in the same memory device layer can be provided by the same semiconductor material layer 2, that is, the two can be respectively part of the same semiconductor material layer 2 and formed as one. The semiconductor material layer 2 can be made of N-type polysilicon or P-type polysilicon, for example, it can be made of N-type polysilicon.

[0088] Optionally, the doping concentration of the bit line may be higher than that of the active layer 1111 .

[0089] In the embodiments of the present application, Figure 1 , Figures 5 to 7 As shown, the memory device 1000 may further include an insulating spacer 160 , and the insulating spacer 160 is used to electrically isolate the active layers 1111 and the bit lines of the transistors of adjacent layers stacked in a vertical direction.

[0090] In one embodiment, the material of the insulating spacer layer 160 may be the same as or different from the material of the gate insulating layer 1112. For example, the material of the insulating spacer layer 160 may be SiO2, SiN x Or insulating materials such as TEOS (tetraethoxysilane) or low dielectric constant materials.

[0091] In the embodiment of the present application, the gate main body 1113A also includes a second gate 11132, which extends along the side wall of the active layer 1111. In the orthographic projection of the substrate 200, the first gate 11131 and the second gate 11132 are located on both sides of the active layer 1111 and extend along the side wall of the active layer 1111.

[0092] like Figures 2 to 7 As shown, the transistor in the memory cell 110 is a dual-gate transistor, and the two gates are respectively a first gate 11131 and a second gate 11132 .

[0093] The first gate 11131 and the second gate 11132 of the gate structure 1113 in the transistor are relatively arranged on both sides of the active layer 1111, which can improve the control ability of the gate in the transistor over the channel. In particular, for the storage unit of the 1T0C structure, it is more conducive to achieving full depletion of the channel region.

[0094] In the embodiment of the present application, the material of the gate structure 1113 may include a conductive material such as metal (e.g., tungsten or titanium nitride), wherein the materials of the first gate 11131 and the second gate 11132 may be the same or different. Preferably, the materials of the first gate 11131 and the second gate 11132 are the same.

[0095] Furthermore, the shapes and widths of the first gate 11131 and the second gate 11132 may be the same or different, and may be completely opposite or only partially opposite. Preferably, the first gate 11131, the second gate 11132 and the active layer 1111 all extend along the second horizontal direction.

[0096] like Figure 1 , Figure 2 as well as Figure 7As shown, a plurality of memory cells 100 adjacent in the vertical direction form a memory cell stack. In the plurality of memory cells 100 in the memory cell stack, the active layer 1111, the gate insulating layer 1112, and the gate structure 1113 overlap in their orthographic projections on the substrate 200, and the overlapping portions of the gate structure 1113 in the orthographic projections on the substrate 200 are correspondingly connected.

[0097] As an embodiment of the present application, two adjacent storage units 100 stacked in the vertical direction have the same structure and are prepared or patterned simultaneously, so that the orthographic projections of the structures in the upper and lower storage units 100 on the substrate 200 overlap.

[0098] It can be understood that since the adjacent memory cells 100 in the vertical direction are located at different depths, there are certain process errors between the two during the preparation process, so the overlap includes complete overlap and approximate overlap.

[0099] It can be understood that the overlapping parts of the gate structure 1113 in the orthographic projection of the substrate 200 are correspondingly connected, that is, the gate structure 1113 includes a gate main body 1113A and other parts. If the gate main body 1113A overlaps in the orthographic projection of the substrate 200, the gate main body 1113A is connected, and if other parts overlap in the orthographic projection of the substrate 200, the other parts are connected. The gate main body 1113A includes a first gate 11131 and a second gate 11132. If the first gate 11131 and the second gate 11132 overlap respectively in the orthographic projection of the substrate 200, the first gate 11131 and the second gate 11132 are respectively connected.

[0100] like Figure 2 , Figure 7 As shown, a plurality of memory cells 100 adjacent in the vertical direction form a memory cell stack. In the plurality of memory cells 100 in the memory cell stack, the orthographic projections of the gate structures 1113 on the substrate 200 overlap respectively. The plurality of memory cell stacks include a first memory cell stack 111A and a second memory cell stack 112A. The first memory cell stack 111A and the second memory cell stack 112A are stacked adjacent in the first horizontal direction to form a memory cell stack group 11A.

[0101] In a memory cell stack group 11A, the first gate 11131 of the first memory cell stack 111A is arranged opposite to the first gate 11131 of the second memory cell stack 112A, and the gate structure 1113 also includes a conductor portion 1113B, and the conductor portion 1113B includes a first conductor portion 11133 formed as a whole with the first gate 11131. On the orthographic projection of the substrate 200, the first conductor portion 11133 is located on the side of the first gate 11131 away from the active layer 1111, and the first conductor portion 11133 is located at the horizontal ends of the first gate 11131.

[0102] It should be noted that the present embodiment does not specifically limit whether the orthographic projections of the active layer 1111 and the gate insulating layer 1112 on the substrate 200 overlap.

[0103] like Figure 2 , Figure 7 As shown, the memory device 1000 includes a plurality of memory cell stacks horizontally distributed on a substrate 200 , wherein at least two memory cell stacks are adjacent to each other in a first horizontal direction, namely a first memory cell stack 111A and a second memory cell stack 112A.

[0104] The first memory cell stack 111A and the second memory cell stack 112A are adjacent to each other in a first horizontal direction to form a memory cell stack group 11A, that is, there is no other memory cell stack between the first memory cell stack 111A and the second memory cell stack 112A.

[0105] The first gate 11131 of the first memory cell stack 111A is arranged opposite to the first gate 11131 of the second memory cell stack 112A, that is, the first gate 11131 of the first memory cell stack 111A and the second memory cell stack 112A is located between the active layers 1111 of the first memory cell stack 111A and the second memory cell stack 112A.

[0106] See also Figure 2 , further, in the memory cell 100: the gate structure 1113 further includes a conductor portion 1113B, the conductor portion 1113B includes a first conductor portion 11133 formed integrally with the first gate 11131, and in the orthographic projection of the substrate 200, the first conductor portion 11133 is located on the side of the first gate 11131 away from the active layer 1111, and the first conductor portion 11133 is located at both horizontal ends of the first gate 11131. However, it is not limited thereto, in some embodiments not shown, the first conductor portion 11133 is located at one end of the first gate 11131.

[0107] Specifically, the first gate 11131 in the embodiment of the present application is substantially in a "C" shape, such as Figure 2As shown, the first gate 11131 extends along the active layer 1111 , and the first conductor portion 11133 extends from two ends of the first gate 11131 away from the active layer 1111 along a first horizontal direction.

[0108] It should be noted that the present application does not limit the angle between the first gate 11131 and the first conductor portion 11133, which may be an acute angle, an obtuse angle, a right angle, etc. The angles between different first gates 11131 and first conductor portions 11133 may be the same or different. In some embodiments, the first gate 11131 and the first conductor portion 11133 may be connected in a circular arc transition. Moreover, the present application embodiment does not specifically limit whether the gate structure 1113 includes the second gate 11132.

[0109] In some embodiments, Figure 1 , Figure 2 As shown, the memory cell stack groups 11A are repeatedly arranged in the first horizontal direction. The embodiment of the present application does not specifically limit whether the gate structure 1113 includes the second gate 11132 .

[0110] Please continue reading Figure 2 In some embodiments, the gate body also includes a second gate 11132, and the second gate 11132 is the same as the above, and will not be described again. The conductor portion 1113B also includes a second conductor portion 11134 formed as a whole with the second gate 11132. In the orthographic projection of the substrate 200, the second conductor portion 11134 is located on the side of the second gate 11132 away from the active layer 1111, and the second conductor portion 11134 is located at both horizontal ends of the second gate 11132. However, it is not limited to this. In some embodiments not shown in the figure, the second conductor portion 11134 is located at one end of the second gate 11132.

[0111] Specifically, the second gate 11132 in the embodiment of the present application is substantially in a "C" shape, such as Figure 2 In the illustrated embodiment, the second gate 11132 extends along the active layer 1111 , and the second conductor portion 11134 extends from two ends of the second gate 11132 away from the active layer 1111 along a first horizontal direction.

[0112] It should be noted that the present application does not limit the angle between the second gate 11131 and the second conductor portion 11134. The angle may be an acute angle, an obtuse angle, a right angle, etc. The angles between different second gates 11132 and second conductor portions 11134 may be the same or different. In some embodiments, the second gate 11132 and the second conductor portion 11134 may be connected by a circular arc transition.

[0113] The memory cell stacking group 11A is repeatedly arranged in the first horizontal direction, and when the gate structure 1113 includes a second gate 11132 and a second conductor portion 11134 connected to the second gate 11132, a gate electrode arranged oppositely and in a "C" shape is formed between every two memory cell stacks arranged adjacently in the first horizontal direction. It can be understood that the above-mentioned gate electrode is an integral body formed by the first gate 11131 and the first conductor portion 11133, or an integral body formed by the second conductor portion 11134 and the second gate 11132; for the second gate 11132, that is, between every two memory cell stacking groups 11A arranged adjacently in the first horizontal direction, the second gate 11132 is arranged oppositely.

[0114] Please continue reading Figure 2 and Fig. 9 Furthermore, between at least one group of adjacent gate structures 1113 of the first memory cell stack 111A and the second memory cell stack 112A, a first insulating layer 130, a second insulating layer 140 and a third insulating layer 150 are sequentially formed in a direction from the gate structure 1113 of the first memory cell stack 111A to the gate structure 1113 of the second memory cell stack 112A.

[0115] Among them, the first insulating layer 130 and the third insulating layer 150 are made of the same material, and the first insulating layer 130 and the third insulating layer 150 respectively contact the gate main body 1113A of the first memory cell stack 111A and the second memory cell stack 112A, and the second insulating layer 140 is arranged between the conductor parts 1113B of the adjacent first memory cell stack 111A and the second memory cell stack 112A, and contacts the conductor parts 1113B of the first memory cell stack 111A and the second memory cell stack 112A.

[0116] A spacing region is included between the active layers 1111 of the group of adjacent first memory cell stacks 111A and second memory cell stacks 112A. For the first memory cell stack 111A and the second memory cell stack 112A, both have at least a portion of a gate structure 1113 located in the spacing region. The at least portion of the gate structure 1113 includes at least a portion of a gate body portion 1113A and at least a portion of a conductor portion 1113B, and the portions of the gate structure 1113 located in the spacing region are relatively arranged.

[0117] For example, Figure 2As shown, the memory cell 100 includes a first gate 11131, and a spacer region is included between the active layers 1111 of a group of adjacent first memory cell stacks 111A and second memory cell stacks 112A. For the first memory cell stack 111A and the second memory cell stack 112A, the first gate 11131 is disposed in the spacer region, and the gate structure 1113 includes a first conductor portion 11131. In the spacer region:

[0118] The first insulating layer 130 and the third insulating layer 150 can be prepared in the same layer and made of the same material. The first insulating layer 130 and the third insulating layer 150 contact the gate main body 1113A, that is, the first insulating layer 130 and the third insulating layer 150 contact the first gate 11131 of the first memory cell stack 111A and the second memory cell stack 112A, respectively; the second insulating layer 140 is arranged between adjacent first conductor portions 11133 and contacts the first conductor portions 11133, that is, the second insulating layer 140 isolates the first conductor portions 11133 located in the spacing area.

[0119] However, the present application is not limited thereto. In some embodiments, the memory cell 100 further includes a second gate 11132. The second gate 11132 and the second conductor portion 11134 are located in the spacing region. In the spacing region:

[0120] The first insulating layer 130 and the third insulating layer 150 can be prepared in the same layer and made of the same material. The first insulating layer 130 and the third insulating layer 150 contact the gate main body 1113A, that is, the first insulating layer 130 and the third insulating layer 150 contact the second gate 11132 of the first memory cell stack 111A and the second memory cell stack 112A, respectively; the second insulating layer 140 is arranged between adjacent second conductor portions 11134 and contacts the second conductor portions 11134, that is, the second insulating layer 140 isolates the second conductor portions 11134 located in the spacing area.

[0121] like Figure 2 In the illustrated embodiment, in a pair of memory cell stacks adjacent to each other in the first horizontal direction, namely, the first memory cell stack 111A and the second memory cell stack 112A, a portion of the gate structure 1113 located in a spacing region may be prepared from the same material layer. For example, after a cylindrical conductive film layer extending in a vertical direction is formed in the spacing region, a vertical gap is formed to cut and separate the conductive film layer.

[0122] The cutting and separation can be performed by etching. Before etching, an insulating material is filled in the hollow part of the tubular conductive film layer, and then an etching process is performed to form a vertical gap. The gap separates the conductive film layer into two parts spaced apart from each other, respectively forming the first gate 11131 and the first conductor part 11133, or the second gate 11132 and the second conductor part 11134 in the group of adjacent first storage cell stacks 111A and second storage cell stacks 112A. The remaining insulating material contacts the gate main body 1113A of the first storage cell stack 111A and the second storage cell stack 112A, respectively, to form a first insulating layer 130 and a second insulating layer 160. The conductor parts 1113B of the first storage cell stack 111A and the second storage cell stack 112A are opposite to each other with a vertical gap between them. The vertical gap exposes the opposite conductor parts 1113B. The first insulating layer 130 and the third insulating layer 150 can be completely separated or partially separated by the vertical gap (such as Fig. 9 As shown), the second insulating layer 140 fills the vertical gap and contacts the conductor portion 1113B.

[0123] The first insulating layer 130 and the third insulating layer 150 isolate the gate body portions 1113A of two adjacent memory cells 100 in the first horizontal direction, and the second insulating layer 140 isolates the conductor portions 1113B of two adjacent memory cells 100 in the first horizontal direction.

[0124] The first insulating layer 130 and the third insulating layer 150 can be formed in one process, so the two can use the same insulating material, such as SiO2, SiN x or TEOS and other insulating materials. The materials of the first insulating layer 130 and the third insulating layer 150 may be the same as or different from the materials of the gate insulating layer 1112 and the insulating spacer layer 160, which is not specifically limited in this application. The material of the second insulating layer 140 may be the same as or different from the materials of the first insulating layer 130 and the third insulating layer 150.

[0125] In some embodiments, the first insulating layer 130 and the third insulating layer 150 may be a single-layer or multi-layer structure, and the second insulating layer 140 may be a single-layer or multi-layer structure, which is not specifically limited in the present application.

[0126] Furthermore, the first insulating layer 130 and the third insulating layer 150 may be completely or partially separated by the vertical gap. Specifically, on the orthographic projection of the substrate 200: the first insulating layer 130 and the third insulating layer 150 are separately disposed on both sides of the second insulating layer 140 ( Figure 2 ); or, the first insulating layer 130 and the third insulating layer 150 are partially connected ( Fig. 9 ).

[0127] like Fig. 9As shown, the above-mentioned gap may also be formed only between two opposite conductor parts 1113B (two first conductor parts 11133 or two second conductor parts 11134) in two adjacent storage cells 100 in the second horizontal direction, that is, the gap only cuts off the gate structure 1113 originally connected in two adjacent storage cells 100 in the first horizontal direction and partially extends into the insulating material, that is, the first insulating layer 130 is partially connected to the third insulating layer 150.

[0128] It can be understood that even if the first insulating layer 130 is partially connected to the third insulating layer 150, in the direction from the gate structure 1113 of the first memory cell stack 111A to the gate structure 1113 of the second memory cell stack 112A, the first insulating layer 130, the second insulating layer 140 and the third insulating layer 150 are also arranged in sequence between the gate structures 1113 of the group of adjacent first memory cell stacks 111A and second memory cell stacks 112A.

[0129] Furthermore, between the gate structures 1113 of the group (i.e., at least one group) of adjacent first memory cell stacks 111A and second memory cell stacks 112A, on the orthographic projection of the substrate 200, the first insulating layer 130 is formed in the area surrounded by the gate body 1113A, the conductor portion 1113B and the second insulating layer 140 of the first memory cell stack 111A, and the edge of the first insulating layer 130 extending along the conductor portion 1113B of the first memory cell stack 111A is also adjacent to the second insulating layer 140, and the third insulating layer 150 is formed in the area surrounded by the gate body 1113A, the conductor portion 1113B and the second insulating layer 140 of the second memory cell stack 112A, and the edge of the third insulating layer 150 extending along the conductor portion 1113B of the second memory cell stack 112A is also adjacent to the second insulating layer 150.

[0130] See also Fig.16 , etching to form vertical gaps to cut off the separated conductive film, the etching may include a first step of anisotropic etching, and a second step of wet etching.

[0131] In the first step, anisotropic etching is performed to form a pre-groove 10A, and the pre-groove 10A penetrates the insulating material filled in the hollow part of the conductive film and the tubular conductive film layer. The pre-groove 10A has basically cut off and separated the conductive film, and at the same time, the insulating material filled in the hollow part of the tubular conductive film layer is patterned into the first insulating layer 130 and the third insulating layer 150.

[0132] The first insulating layer 130 is formed in the space surrounded by the pre-groove 10A and the conductive film on the side of the first memory cell stack 111A, wherein the portion of the conductive film extending along the active layer 1111 of the first memory cell stack 111A is formed as the gate body 1113A of the first memory cell stack 111A, the first insulating layer 130 is away from the end surface of the gate body 1113A of the first memory cell stack 111A, and the conductive film on the side of the first memory cell stack 111A is away from the end surface of its gate body 1113A to form a continuous surface, and the continuous surface is exposed to the pre-groove 10A.

[0133] Similarly, a third insulating layer 150 is formed in a space surrounded by the pre-groove 10A and the conductive film on the side of the second memory cell stack 112A, wherein a portion of the conductive film extending along the active layer 1111 of the second memory cell stack 112A is formed as a gate body 1113A of the second memory cell stack 112A, and the third insulating layer 150 is away from an end face of the gate body 1113A of the second memory cell stack 112A, and the conductive film on the side of the second memory cell stack 112A is away from an end face of its gate body 1113A to form a continuous surface, and the continuous surface is exposed to the pre-groove 10A.

[0134] In order to completely cut off the separation conductive film and avoid short circuit between the conductor parts 1113B of the adjacent first memory cell stack 111A and the second memory cell stack 112A, a second wet etching step is performed to selectively etch the conductive film exposed by the pre-groove 10A to form the gate structure 1113 of the first memory cell stack 111A and the second memory cell stack 112A.

[0135] Compared with the previous continuous surface, the end surface of the conductive film exposed by the pre-groove 10A "retres" due to wet etching, so that the surface of the first insulating layer 130 and the third insulating layer 150 that originally contacted the conductive film is exposed, and the pre-groove 10A is extended to form a gap for filling the second insulating layer 140, and the exposed surface is formed to contact the second insulating layer 140, such as Fig.16 shown.

[0136] Thus, on the orthographic projection of the substrate 200 , the edge of the first insulating layer 130 extending along the conductor portion 1113B of the first memory cell stack 111A is also adjacent to the second insulating layer 140 , and the edge of the third insulating layer 150 extending along the conductor portion 1113B of the second memory cell stack 112B is also adjacent to the second insulating layer 140 .

[0137] It should be noted that the second insulating layer 140 may be an insulating material layer or an air gap having an insulating function, and the present application does not specifically limit the composition of the second insulating layer 140. Figure 2As shown, the second insulating layer 140 separates the first insulating layer 130 and the third insulating layer 150 as a whole, so that the size of the gap where the second insulating layer 140 is located is larger, which can reduce the difficulty of the process.

[0138] Furthermore, the second insulating layer 140 includes a low dielectric constant (Low K) material, that is, the second insulating layer 140 can be made of a material with a dielectric constant lower than 3.9, which is beneficial to reducing the parasitic capacitance between transistors, including reducing the coupling between the gate structures 1113 of two adjacent memory cells 100 in the first horizontal direction.

[0139] In particular, in the present embodiment, the gate structure 1113 of two adjacent memory cells 100 in the first horizontal direction includes a conductor portion 1113B, and the distance between the closest conductor portions 1113B in the two adjacent memory cells 100 in the first horizontal direction is smaller than that between the closest gate body portions 1113A. Therefore, the material selected for designing the second insulating layer 140 includes a low dielectric constant material, which can more significantly reduce the coupling effect between the gate structures 1113 of two adjacent memory cells 100 in the first horizontal direction.

[0140] Furthermore, based on the above technical solution, the transistor in the embodiment of the present application can be a junctionless field effect transistor, so there is no need to pattern the source and drain of the transistor, which can simplify the process flow and save production costs.

[0141] In the embodiment of the present application, the active layer 1111 is parallel to the insulating surface 210, that is, the active layer 1111 is perpendicular to the vertical direction, and its material includes polysilicon, preferably, its material includes N-type doped polysilicon. However, it is not limited thereto, and the specific material of the active layer 1111 can be set according to actual needs.

[0142] Furthermore, in the embodiment of the present application, the transistor is a junctionless transistor, that is, the active layer 1111 further includes a channel region 11113 located between the source terminal 11111 and the drain terminal 11112, and the source terminal 11111, the drain terminal 11112, and the channel region 11113 have the same conductivity type. In the memory cell 100, the channel region 11113 is arranged corresponding to the first gate 11131 and the second gate 11132, that is, the channel region 11113 is located between the first gate 11131 and the second gate 11132, and the width of the channel region 11113 in the direction from the first gate 11131 to the second gate 11132 is less than 40nm.

[0143] It should be noted that, for the active layer 1111 made of polysilicon or N-type doped polysilicon, the width of the channel region is less than 40 nm, and for the active layer 1111 made of other than polysilicon, the width of the channel region 11113 may have different ranges.

[0144] Among them, the width of the channel region 11113 in the direction from the first gate 11131 to the second gate 11132 refers to the distance between the two side surfaces of the channel region 11113 in the first horizontal direction. By making the width of the channel region 11113 in the direction from the first gate 11131 to the second gate 11132 less than 40nm, the transistor can become a storage cell 100 with a 1T0C structure, and the storage cell 100 can be read and written.

[0145] For example, for the memory cell 100 including a junctionless transistor and an active layer 1111 material including N-type doped polysilicon, a method for read and write operations is proposed, see Fig. 20 , methods include:

[0146] A negative voltage is applied to the gate structure 1113, and a positive voltage is applied to the drain terminal through the bit line BL. Holes accumulate in the channel region, and the threshold voltage of the transistor is reduced, completing the "write 1" operation; a positive voltage is applied to the gate structure 1113, and a negative voltage is applied to the drain terminal through the bit line BL. Carrier recombination occurs in the channel region, and the threshold voltage of the transistor is restored, completing the "write 0" operation; when a read voltage is applied to the gate structure 1113, due to the difference in threshold voltage caused by the write operation, drain currents of different sizes are generated, so that the "0" and "1" states can be distinguished in the read operation.

[0147] For example, the width of the channel region 11113 may be 30 nm, 20 nm or 10 nm, etc. In addition, the cross-sectional shape of the channel region 11113 perpendicular to the second horizontal direction may be a circular, square, rectangular, hexagonal or octagonal geometric shape, which is not specifically limited in this application.

[0148] The gate insulating layer 1112 is disposed between the gate structure 1113 of the transistor and the active layer 1111 (channel region 11113), and its material may include SiO2 or a high dielectric constant material, etc., which is not specifically limited in this application. For example, the material of the active layer 1111 contains silicon, such as polysilicon, N-type or P-type doped polysilicon, etc., and the gate insulating layer 1112 can be formed by oxidizing the surface containing the above silicon-containing material, and the unoxidized silicon-containing material layer forms the active layer 1111, so that the gate insulating layer 1112 is only formed at the sidewalls of the active layer 1111, and the width of the channel region 11113 can also be smaller than at least one of the source terminal 11111 and the drain terminal 11112, but it is not limited thereto.

[0149] like Figure 7 As shown, in some embodiments, an insulating material layer may be deposited on the surface of the active layer 1111 to form a gate insulating layer 1112 , so that the gate insulating layers 1112 of multiple memory cells 100 may be formed into an integrated structure.

[0150] Furthermore, as an embodiment of the present application, in the gate structure 1113:

[0151] The first gate 11131 and the second gate 11132 are electrically connected to achieve synchronous control of the first gate 11131 and the second gate 11132 in the gate structure 1113; and / or

[0152] The first gate 11131 and the second gate 11132 are controlled independently of each other, that is, the first gate 11131 and the second gate 11132 are electrically connected to the external circuit respectively, so as to realize different control over the gate structure 1113, thereby improving the charge retention capability of the DRAM memory cell 100 with a 1T0C structure; and / or

[0153] The first gate 11131 and the second gate 11132 are controlled independently of each other, and the first gate 11131 and the second gate 11132 do not completely overlap on opposite surfaces, that is, in the storage unit 100, the projections of the first gate 11131 and the second gate 11132 on the active layer 1111 do not completely overlap, which can improve the charge retention capability of the DRAM storage unit 100 with a 1T0C structure.

[0154] The first gate 11131 and the second gate 11132 are electrically connected, and a conductive connection structure can be set at the top and / or bottom of the first gate 11131 and the second gate 11132 to achieve electrical connection between the two, but is not limited to this. It can be determined according to the circumstances as long as the two are electrically connected.

[0155] The first gate 11131 and the second gate 11132 do not completely overlap on opposite surfaces. For example, the length of the first gate 11131 is greater than or equal to the length of the second gate 11132, or the projections of the first gate 11131 and the second gate 11132 on the active layer 1111 are staggered in the horizontal direction. This application does not make any specific limitation.

[0156] In the storage device 1000 of the embodiment of the present application, multiple DRAM storage cells 100 with 1T0C structures are repeatedly arranged along the first horizontal direction, the second horizontal direction and the vertical direction. The storage cell 100 has a simple structure and a high storage density, and the storage capacity can be improved by further increasing the number of stacked layers as needed. The transistor can be a junctionless field effect transistor, and there is no need to perform patterned ion implantation on the active layer 1111, thereby reducing the process difficulty and saving production costs. In the transistor of the storage cell 100, the first gate 11131 and the second gate 11132 of the gate structure 1113 are horizontally arranged on both sides of the active layer 1111, which can improve the control of the gate over the channel in the transistor.

[0157] The present application also provides a method for manufacturing the storage device 1000, which is used to manufacture the storage device 1000 in the above embodiment. Fig.10 , a method for manufacturing the storage device 1000 includes:

[0158] Please combine Fig.11 , step S100: providing a substrate 1A;

[0159] In some embodiments, the substrate 1A may be the substrate 200. For details about the substrate 1A, please refer to the description of the substrate 200 in the above embodiment of the storage device 1000, which will not be described in detail here. However, the present invention is not limited thereto. In other embodiments, the substrate may also be a temporary substrate.

[0160] Please continue reading Fig.11 , step S200: preparing a plurality of film layer pairs 1 stacked along a vertical direction on a substrate 1A, wherein the film layer pairs 1 include a semiconductor material layer 2 and a first insulating dielectric layer 3 sequentially arranged along the vertical direction.

[0161] A plurality of film layer pairs 1 are stacked in a vertical direction to form a stacked structure, that is, the stacked structure includes first insulating medium layers 3 and semiconductor material layers 2 alternately stacked in the vertical direction.

[0162] The semiconductor material layer 2 and the first insulating dielectric layer 3 may be formed by thin film deposition methods such as chemical vapor deposition (CVD), atomic layer deposition (ALD), and physical vapor deposition (PVD).

[0163] It can be understood that any suitable material and deposition process can be used to form the first insulating dielectric layer 3 and the semiconductor material layer 2 .

[0164] The material of the semiconductor material layer 2 may be a material containing silicon, such as N-type polysilicon and other semiconductor materials, but is not limited thereto. Oxide semiconductor materials and the like may also be used for the semiconductor material layer 2, depending on the specific circumstances.

[0165] Taking oxide semiconductor as an example, the semiconductor material layer 2 may be an indium gallium zinc oxide (IGZO) layer. It should be noted that the material of the metal oxide may also be ITO, IWO, ZnO x 、InO x 、In2O3、InWO、SnO2、TiO x 、InSnO x 、Zn x Oy N z Mg x Zn y O z 、In x Zn y O z 、In x Ga y Zn z O a 、Zr x In y Zn z O a , Hf x In y Zn z O a Sn x In y Zn z O a 、Al x Sn y In z Zn a O d 、Si x In y Zn z O a 、Zn x Sn y O z 、Al x Zn y Sn z O a , Ga x Zn y Sn z O a 、Zr x Zn y Sn z O a , InGaSiO and other materials, the specific selection can be made according to the actual situation.

[0166] In one example, the material of the first insulating dielectric layer 3 may be an insulating material, such as but not limited to SiO2, or SiN x .

[0167] In one embodiment, the stacked structure may be a stacked structure of SiO2 layer (first insulating dielectric layer 3) / N-type polysilicon layer (semiconductor material layer 2).

[0168] Please combine Fig.12 and Fig.13, step S300: etching a plurality of film layer pairs 1 to form a plurality of first slits 4 repeatedly arranged along a first horizontal direction and a second horizontal direction, the first horizontal direction intersects the second horizontal direction, the first slits 4 penetrate the plurality of film layer pairs 1 along a vertical direction, forming a second insulating dielectric layer 5 to fill the first slits 4, in the second horizontal direction, the semiconductor material layer 2 on one side of the first slit 4 is formed into a bit line structure 120, the bit line structure 120 includes a plurality of bit lines, each bit line extends along the first horizontal direction, and a common source structure is formed on the side of the first slit 4 away from the bit line structure 120.

[0169] The first horizontal direction and the second horizontal direction are the same as those in the previous text and will not be described in detail.

[0170] In the embodiment of the present application, the stacked structure formed by the plurality of film layers 1 may be patterned to form a first slit 4 that penetrates the stacked structure in a vertical direction, that is, the first slit 4 vertically penetrates each semiconductor material layer 2 and the first insulating dielectric layer 3. For example, an anisotropic etching process (for example, a dry etching process such as an ion etching process or a reactive ion etching process, or a wet etching process or an etching process combining dry etching and wet etching) may be used to etch downward from the top semiconductor material layer 2 in a direction perpendicular to the substrate 1A to form a first slit 4, and there are a plurality of first slits 4, and the plurality of first slits 4 are repeatedly arranged along the first horizontal direction and the second horizontal direction, that is, the plurality of first slits 4 are distributed in an array in the stacked structure. Fig.12 As shown, a plurality of first slits 4 are arranged in rows along a first horizontal direction, and two adjacent rows of first slits 4 in a second horizontal direction are symmetrically distributed.

[0171] like Fig.12 As shown, the semiconductor material layer 2 between adjacent first slits 4 in the first horizontal direction is used to prepare the active layer 1111, and in the second horizontal direction, the semiconductor material layer 2 on one side of the first slit 4 is formed into a bit line structure.

[0172] It can be understood that the end of the semiconductor material layer 2 used to prepare the active layer 1111 connected to the bit line structure is used to form a drain terminal, and the end of the semiconductor material layer 2 used to prepare the active layer 1111 away from the bit line connected thereto is used to form a source terminal, and the source terminal is used to connect to the common source structure.

[0173] The manufacturing method of the memory device 1000 further includes the step of preparing a common source structure. Optionally, the common source is formed on a side of the first gap 4 away from the bit line structure. It can be understood that the common source structure is electrically connected to the source terminal.

[0174] Afterwards, see Fig.13, a second insulating dielectric layer 5 is filled in the first gap 4, and the material of the second insulating dielectric layer 5 can be the same as or different from the material of the first insulating dielectric layer 3. For example, the material of the second insulating dielectric layer 5 can also be SiO2.

[0175] Please combine Fig.14 , step S400: etching the second insulating dielectric layer 5 in the first gap 4 to form a plurality of first grooves 6 repeatedly arranged along the first horizontal direction and the second horizontal direction, the first grooves 6 penetrate the second insulating dielectric layer 5 along the vertical direction, the first grooves 6 correspond to the first gaps 4 one by one, the two opposite side walls of the first groove 6 in the first horizontal direction both expose the semiconductor material layer 2, and on the orthographic projection of the substrate 1A, the opposite side walls of the first groove 6 in the second horizontal direction fall into the first groove 4.

[0176] Specifically, the first trench 6 penetrates the second insulating dielectric layer 5 in the vertical direction and is located in each first slit 4. The first trench 6 exposes the semiconductor material layer 2 and the first insulating dielectric layer 3 between two adjacent first trenches 6 in the first horizontal direction, and can be two opposite side walls of the first trench 6 in the first horizontal direction, which overlap with the side walls of the first slit 4 in the orthographic projection on the substrate 1A. It can be understood that the semiconductor material layer 2 between two adjacent first trenches 6 in the first horizontal direction is used to form the channel region 11113.

[0177] On the orthographic projection of the substrate 1A, the sidewalls of the first trench 6 on both sides in the second horizontal direction fall into the first trench 4. It can be understood that there is a second insulating dielectric layer 5 between the first trench 6 and the bit line structure, and a second insulating dielectric layer 5 is also formed between the first trench 6 and the common source structure to be formed. The second insulating dielectric layer 5 can expose the channel region of the active layer 1111 and cover the source terminal and the drain terminal.

[0178] In the subsequent steps, the first trench 6 is used to prepare the gate structure 1113 , so that the length of the gate structure 1113 subsequently formed in the first trench 6 can be controlled by controlling the size of the first trench 6 , that is, the length of the gate body extending horizontally along the active layer 1111 .

[0179] In the embodiment of the present application, the etching process may be dry etching, wet etching, or an etching process combining dry etching and wet etching.

[0180] Please combine Fig.15 and Fig.16 , step S500: forming a gate material layer 7 on the entire sidewall of the first trench 6 , and a gate insulating material layer 8 between the gate material layer 7 and the surface of the semiconductor material layer 2 exposed by the first trench 6 , and filling a third insulating dielectric layer 9 in the first trench 6 .

[0181] It can be understood that filling the third insulating dielectric layer 9 in the first trench 6 means filling the third insulating dielectric layer 9 in the space surrounded by the gate material layer 7 .

[0182] The gate material layer 7 is used to form a gate structure 1113 , and the gate insulating material layer 8 is used to form a gate insulating layer 1112 .

[0183] The gate insulating material layer 8 is formed at least on the surface of the semiconductor material layer 2 exposed by the first trench 6. Fig.15 In one embodiment, the semiconductor material layer 2 includes silicon, such as N-type doped polysilicon, and the gate insulating material layer 8 is obtained by oxidizing the semiconductor material layer 2. The remaining semiconductor material layer 2 is formed into a channel region 11113, so that the gate insulating material layer 8 is only formed on the surface of the active layer exposed by the first trench 6, as shown in FIG. Figure 4 , Fig.15 As shown. Further, since the semiconductor material layer 2 consumes a certain thickness, the width of the channel region 11113 formed later can be made smaller than the source terminal 11111 and the drain terminal 11112 (not shown); in another embodiment, the gate insulating layer material 8 is deposited on the entire sidewall of the first trench 6, and the formed memory cell 100 can be as shown. Figure 3 shown.

[0184] Optionally, the gate material layer 7 is disposed on the entire sidewall of the first trench 6, such as in a vertical cylindrical shape, but not limited thereto. In some embodiments, the gate material layer 7 may be a plurality of rings stacked vertically and spaced apart from each other, depending on the specific situation. The preparation process may be a deposition process commonly used in the art.

[0185] Furthermore, the preparation method of the gate material layer 7 may include: depositing a conductor layer on the entire inner wall of the first trench 6, and removing the portion of the conductor layer located at the bottom of the first trench 6. Removing the portion of the conductor layer located at the bottom of the first trench 6 may be achieved by anisotropic etching.

[0186] The third insulating dielectric layer 9 may be formed by deposition, that is, after forming the gate material layer 7 on the entire sidewall of the first trench 6 , an insulating material is deposited in the remaining first trench 6 surrounded by the gate material layer 7 to form the third insulating dielectric layer 9 .

[0187] The material of the third insulating dielectric layer 9 can be the same as or different from the material of the first insulating dielectric layer 3 and the material of the second insulating dielectric layer 5. Preferably, the material of the third insulating dielectric layer 9 is the same as the material of the first insulating dielectric layer 3 and the material of the second insulating dielectric layer 5, that is, the material of the third insulating dielectric layer 9 can also be SiO2 or SiN x .

[0188] In addition, the material of the conductor layer can be the same as or different from the material of the semiconductor material layer 2. As an embodiment of the present application, the material of the conductor layer is different from the material of the semiconductor material layer 2. The conductor layer can be tungsten (W), titanium nitride (TiN), etc.

[0189] Please combine Fig.16 , step S600: etching the gate material layer 7 to form a plurality of second trenches 10 repeatedly arranged along the first horizontal direction and the second horizontal direction, the second trenches 10 penetrate the gate material layer 7, so that the gate material layer 7 is formed into a first gate structure 11 and a second gate structure 12 spaced apart in the first horizontal direction.

[0190] The etching method at least includes anisotropic etching. In order to reduce the difficulty of the etching process, preferably, in the process of etching the gate material layer 7 to form the second groove 10, a portion of the third insulating dielectric layer 9 is also etched, that is, the second groove 10 also penetrates the third insulating dielectric layer 9, that is, the second groove cuts the third insulating dielectric layer 9 into a partially connected second insulating layer and a third insulating layer.

[0191] Preferably, the second trench 10 cuts off the third insulating dielectric layer 9 to form a second insulating layer and a third insulating layer separated from each other.

[0192] Preferably, during the process of etching the gate material layer 7 to form the second trench 10 , a portion of the second insulating dielectric layer 5 is also etched, that is, the second trench 10 also penetrates the second insulating dielectric layer 5 , which can further reduce the difficulty of the etching process.

[0193] In the embodiment of the present application, the second groove 10 extends along the second horizontal direction and penetrates the gate material layer 7 in the vertical direction. It can be understood that the second groove 10 cuts the gate material layer 7 into two opposite parts in the first horizontal direction, so that the gate material layer 7 is formed into a first gate structure 11 and a second gate structure 12 separated in the first horizontal direction.

[0194] It can be understood that the first gate structure 11 and the second gate structure 12 belong to two adjacent memory cells in the first horizontal direction respectively.

[0195] After the etching is completed, the remaining third insulating dielectric layer 9 is located in the space enclosed by the second trench 10 and the first gate structure 11 and the second gate structure 12, respectively, to form a second insulating layer and a third insulating layer. That is, during the process of etching to prepare the second trench, the third insulating dielectric layer 9 covers and protects the portion of the first gate structure 11 and the second gate structure 12 extending along the surface of the semiconductor material layer 2 exposed by the first trench 6.

[0196] It is understood that etching to form holes or grooves that penetrate the stacked structure usually adopts anisotropic etching, such as dry etching. As the number of stacked layers in the stacked structure increases, the hole or groove that needs to be formed has a larger aspect ratio, and the etching process becomes more difficult. As shown in the embodiment of the present application, when the second groove 10 has a high aspect ratio, there is a risk that the anisotropic dry etching cannot completely cut off the gate material layer 7, and the first gate structure 11 and the second gate structure 12 may be short-circuited, resulting in a decrease in yield.

[0197] To this end, etching the gate material layer 7 in step S600 may be implemented through step S610.

[0198] Step S610: Anisotropically etch the gate material layer 7 located on the two side walls opposite to each other in the second horizontal direction of the first groove 6 to form a pre-groove 10A, the pre-groove 10A penetrates the gate material layer 7, and the pre-groove 10A does not expose the gate material layer 7 located on the two side walls opposite to each other in the first horizontal direction of the first groove, and wet-etch the gate material layer 7 exposed by the pre-groove 10A to form a first gate structure 11 and a second gate structure 12.

[0199] The pre-groove 10A has basically cut the gate material layer 7 into two opposite parts in the first horizontal direction, and then a wet etching step is performed to ensure that the gate material layer 7 is formed into a first gate structure 11 and a second gate structure 12 spaced apart in the first horizontal direction, thereby reducing the risk of short circuit and reducing the difficulty of the etching process. However, it is not limited to this, and the process for etching the gate material layer 7 exposed by the pre-groove 10A to form the first gate structure 11 and the second gate structure 12 can be other isotropic etching processes commonly used in the art, depending on the specific situation.

[0200] The gate material layer 7 is anisotropically etched on the two side walls of the first trench 6 opposite to each other in the second horizontal direction to form a pre-groove 10A, and the pre-groove 10A does not expose the gate material layer 7 on the two side walls of the first trench opposite to each other in the first horizontal direction, that is, the pre-groove 10A overlaps with both opposite sides of the gate material layer 7 in the second horizontal direction on the orthographic projection of the substrate 1A, and is spaced from both opposite sides of the gate material layer 7 in the first horizontal direction. Therefore, when wet etching is performed, the etchant can only contact the end of the gate material layer 7 exposed by the pre-groove 10A.

[0201] Preferably, the pre-groove 10A also penetrates the third insulating dielectric layer 9 , and the wet etching selectively etches the gate material layer 7 without etching the third insulating dielectric layer 9 .

[0202] Specifically, various anisotropic etchings are performed to form a pre-groove 10A, which penetrates the gate material layer 7 and the third insulating dielectric layer 9. The pre-groove 10A has basically cut off and separated the gate material layer 7, and at the same time, the third insulating dielectric layer 9 filled in the hollow portion of the cylindrical gate material layer 7 is patterned into a second insulating layer and a third insulating layer.

[0203] The second insulating layer and the third insulating layer are respectively formed in the space surrounded by the pre-groove 10A and the gate material layer 7 which is basically cut and separated into two parts, wherein the portion of the gate material layer 7 extending along the first slit 4 on both sides opposite to each other in the first horizontal direction forms the gate body, and the end surfaces of the second insulating layer and the third insulating layer away from the gate body in contact with them form a continuous surface with the end surface of the gate material layer 7 away from the gate body, and the continuous surface is exposed to the pre-groove 10A, such as Fig.16 shown.

[0204] In order to completely cut off the separation gate material layer 7 and avoid short circuit between the first gate structure 11 and the second gate structure 12 , a second wet etching step is performed to selectively etch the gate material layer 7 exposed by the pre-groove 10A to form the first gate structure 11 and the second gate structure 12 .

[0205] Compared with the previous continuous surface, the end surface of the gate material layer 7 exposed by the pre-groove 10A "retres" due to wet etching, so that the surface of the second insulating layer and the third insulating layer that originally contacted the gate material layer 7 is exposed, and the pre-groove 10A is expanded to form a second gap 10, such as Fig.16 shown.

[0206] Preferably, the wet etching does not etch the first gate structure 11 and the second gate structure 12, which extend along the surface of the semiconductor material layer 2 exposed by the first trench 6. Specifically, the extent to which the gate material layer 7 is wet-etched can be achieved by controlling the wet etching time. Thus, the risk of short circuit is reduced without affecting the gate length.

[0207] Therefore, please combine Figure 2 , Fig.14 and Fig.19 The first gate structure 11 and the second gate structure 12 both include a portion extending along the surface of the semiconductor material layer 2 exposed by the first groove 6, that is, both include a gate main body 1113A, and a portion located on the side of the gate main body 1113A away from the active layer 1111, that is, the conductor portion 1113B, and the conductor portion 1113B is located at the horizontal ends of the gate main body 1113A.

[0208] Thus, the semiconductor material layer 2 located between two adjacent first trenches 4 in the first horizontal direction is formed as an active layer 1111, and the portion of the gate insulating material layer 8 located between the gate structure 1113 and the active layer 1111 is formed as a gate insulating layer 1112. The active layer 1111, the gate insulating layer 1112 and the gate structure 1113 form a memory cell 100 of the memory device 1000, and one end of the active layer 1111 is connected to the bit line, and the other end is connected to the common source structure 120. It can be understood that the gate structure 1113 is one of the first gate structure 11 and the second gate structure 12 described above, and the first gate structure 11 and the second gate structure 12 belong to two memory cells 100 respectively.

[0209] Please combine Fig.17 , step S700 : filling the second trench 10 with a fourth insulating dielectric layer 13 .

[0210] The fourth insulating dielectric layer 13 is formed as a first insulating layer.

[0211] It should be noted that the first insulating layer is the second insulating layer 140 (eg, Figure 2 The fourth insulating dielectric layer 13 insulates and isolates the gate structures 1113 of transistors that are adjacent to each other in the first horizontal direction.

[0212] It should be noted that the fourth insulating dielectric layer 13 used to form the first insulating layer may be an insulating material layer or an air gap, and the present application does not specifically limit the composition of the fourth insulating dielectric layer 13 and the first insulating layer.

[0213] Furthermore, the material of the fourth insulating dielectric layer 13 includes a low dielectric constant material.

[0214] Exemplarily, the fourth insulating dielectric layer 13 may be made of a material with a dielectric constant lower than 3.9, thereby facilitating reduction of parasitic capacitance between transistors.

[0215] The material of the fourth insulating dielectric layer 13 may be the same as or different from the material of the first insulating dielectric layer 3 to the third insulating dielectric layer 9. Furthermore, the material of the fourth insulating dielectric layer 13 is different from the material of the first insulating dielectric layer 3 to the third insulating dielectric layer 9.

[0216] In the embodiment of the present application, the material of the third insulating dielectric layer 9 can be SiO2 or SiN x , and the material of the fourth insulating dielectric layer 13 is a low dielectric constant material.

[0217] Thus, the second insulating layer, the first insulating layer and the third insulating layer are disposed between two adjacent gate main bodies in the first horizontal direction.

[0218] It should be noted that the second insulating layer here is the first insulating layer 130 in the embodiment of the storage device 1000, and the third insulating layer is the third insulating layer 150 in the embodiment of the storage device 1000. It can be understood that the second insulating layer and the third insulating layer are formed after the third insulating dielectric layer 9 is patterned.

[0219] Furthermore, as an embodiment of the present application, two surfaces of two first grooves 6 adjacent to each other in the first horizontal direction do not completely overlap with each other.

[0220] It can be understood that two first trenches 6 adjacent in the first horizontal direction can be used to form a gate structure 1113 in the same transistor, and the gate structure 1113 includes a first gate 11131 and a second gate 11132. Therefore, the two opposite surfaces of the two first trenches 6 adjacent in the first horizontal direction do not completely overlap, and thus the first gate 11131 and the second gate 11132 that do not completely overlap on the opposite surfaces can be formed. The memory cell 100 includes a transistor, and the transistor includes the first gate 11131 and the second gate 11132 that are opposite and do not completely overlap, which is the same as the above-mentioned embodiment and will not be repeated.

[0221] In some embodiments, a method of forming a common source structure includes:

[0222] Step S310 : forming a common source 110 , wherein the common source 110 includes a plurality of vertical contacts.

[0223] The embodiment in which the common source 110 includes a vertical contact is the same as that in the above-mentioned embodiment of the storage device 1000 and will not be described in detail here.

[0224] In a preferred embodiment of the present application, the common source 110 is a plate-like structure, which extends along the first horizontal direction, that is, extends parallel to the bit line structure 120. The common source 110 penetrates the stacked structure in the vertical direction and is connected to each semiconductor material layer 2.

[0225] On the basis of the above, the method for forming a common source structure includes: etching multiple film layer pairs 1 to form multiple third gaps repeatedly arranged in the second horizontal direction, the third gaps extend along the first horizontal direction and penetrate the multiple film layer pairs 1 in the vertical direction, and the conductive material is filled in the third gaps to form a common source 110, and the common source 110 is connected to the adjacent semiconductor material layers 2 in the vertical direction, or the common source 110 is connected to each semiconductor material layer 2.

[0226] Specifically, see Fig.18 , Fig.19As shown, the semiconductor material layer 2 and the fourth insulating dielectric layer 13 are etched to form a third trench 14, which extends along the first horizontal direction and penetrates the semiconductor material layer 2 and the fourth insulating dielectric layer 13. A conductive layer 15 is filled in the third trench 14 to form a common source 110.

[0227] The embodiment in which the common source 110 includes a plate-shaped structure is the same as that in the above-mentioned embodiment of the storage device 1000 , and will not be described in detail here.

[0228] It is worth mentioning that although the content of the manufacturing method of the storage device in this embodiment is described in the order of method steps, in the specific implementation, the order of some method steps can be changed. For example, the preparation step of the common source structure can be performed after step S200 and before any step. It can be implemented according to specific needs.

[0229] In one embodiment, the method for forming the common source structure includes: forming a bit line structure 120 and a common source 110 respectively on the semiconductor material layer 2 located on both sides of the first gap 4 in the second horizontal direction.

[0230] The embodiment in which the common source 110 includes a horizontal wiring extending along the first direction is the same as above and will not be described in detail.

[0231] The method for manufacturing the storage device of the embodiment of the present application not only has the beneficial effects of the embodiment of the storage device 1000 described above, but also can reduce the risk of short circuit without affecting the gate length, thereby significantly improving the yield of the storage device 1000.

[0232] Although the present application proposes a 3D 1T0C DRAM storage device in the previous embodiment, the above storage device has a C-shaped gate electrode, which can reduce the risk of short circuit. However, for a semiconductor device in which a repeating unit includes a 3D stack with a horizontal channel and a vertical gate, a C-type gate can be prepared to reduce short circuit. Therefore, the present application also proposes an embodiment of the semiconductor device as described below.

[0233] The semiconductor device of the embodiment of the present application includes: a substrate; a transistor stack, including a plurality of transistors stacked vertically on the substrate; the transistor includes an active layer and a gate electrode, the active layer extends in a horizontal direction, the gate electrode is located on the side wall of the active layer, all gate electrodes in a transistor stack overlap in the positive projection of the substrate, the gate electrode includes an integral gate body portion and a conductor portion, the gate body portion is arranged along the length direction of the active layer, the conductor portion is located on the side of the gate body portion away from the active layer, and the conductor portion is located at both ends of the gate body portion in the horizontal direction.

[0234] Among them, the structures such as the gate body, conductor part, gate electrode and transistor stack can be similar to the gate body, conductor part, gate structure and storage unit stack containing only one transistor in the above-mentioned storage device embodiment, and will not be repeated here.

[0235] In some embodiments not shown, the conductor portion may be located at one end of the gate body portion in the horizontal direction.

[0236] In the semiconductor device of the embodiment of the present application, the transistor included in the repeating unit can be a JFET or a MOSFET, without specific limitation. However, it should be noted that when the transistor is a MOSFET, the transistor also includes a gate insulating layer, and the gate insulating layer is located between the gate body and the active layer. It can be understood that the repeating unit can also include other structures besides the transistor described in the above embodiment.

[0237] In an embodiment of the present application, there are multiple transistor stacks, and the multiple transistor stacks are horizontally distributed on the substrate. In the horizontal direction perpendicular to the extension direction of the gate body, the gate electrodes of two adjacent transistor stacks are arranged opposite to each other.

[0238] It can be understood that the gate electrodes of two adjacent transistor stacks are arranged opposite to each other, that is, the gate electrodes of the two transistor stacks are located between the active layers of the two transistor stacks and are arranged face to face, including the gate body part and the conductor part facing each other.

[0239] Exemplarily, the extension direction of the active layer and the gate body is the second horizontal direction, and the horizontal direction perpendicular to the extension direction of the gate body is the first horizontal direction, that is, the gate electrodes of two adjacent transistor stacks are relatively arranged in the first horizontal direction.

[0240] In an embodiment of the present application, in adjacent transistor stacks, relatively arranged gate electrodes are in a "C" shape, and forming the gate electrode of the transistor stack into a "C" shape can be specifically implemented by a method including step S610 of the above-mentioned method for manufacturing the storage device, that is, etching to form a pre-groove so that the gate material layer prepared as a whole for forming the gate electrode of the adjacent transistor stack is basically disconnected, and then wet etching is performed to form mutually disconnected gate electrodes of the adjacent transistor stacks. This is the same as the previous text and will not be repeated. Therefore, while ensuring cutting off and reducing the risk of short circuit, the gate length is not affected.

[0241] Furthermore, in an embodiment of the present application, the semiconductor device includes a first insulating layer, a second insulating layer and a third insulating layer. In a horizontal direction extending perpendicular to the gate main body, the first insulating layer, the second insulating layer and the third insulating layer are sequentially arranged between the gate electrodes of two adjacent transistor stacks. The first insulating layer and the third insulating layer are made of the same material and respectively contact the gate main bodies of the two adjacent transistor stacks. The second insulating layer is arranged between the conductive parts of the two adjacent transistor stacks and contacts the conductor parts of the two adjacent transistor stacks.

[0242] Specifically, the first insulating layer and the third insulating layer isolate the gate body parts of two transistor stacks adjacent to each other in the first horizontal direction (i.e., the horizontal direction perpendicular to the extension direction of the gate body), and the second insulating layer isolates the conductor parts of two transistor stacks adjacent to each other in the first horizontal direction. The first insulating layer and the third insulating layer can be formed in one process, so the same insulating material can be used for both, such as SiO2, SiN x Or insulating materials such as TEOS.

[0243] Furthermore, since the gate electrode can be prepared in step S610 of the manufacturing method of the storage device, between the gate electrodes of two adjacent transistor stacks, on the orthographic projection of the substrate: the first insulating layer and the third insulating layer are respectively formed in the area surrounded by the gate electrodes of the two adjacent memory cell stacks and the second insulating layer, the edge of the first insulating layer extending along the conductor portion in contact with the first insulating layer is also adjacent to the second insulating layer, and the edge of the third insulating layer extending along the conductor portion in contact with the first insulating layer is also adjacent to the second insulating layer.

[0244] The material of the second insulating layer can be the same as or different from the materials of the first insulating layer and the third insulating layer. Since the second insulating layer and the first insulating layer and the third insulating layer are formed in different processes, preferably, the material of the second insulating layer is different from the materials of the first insulating layer and the third insulating layer.

[0245] It should be noted that the structure, materials and functions of the first insulating layer, the second insulating layer and the third insulating layer mentioned in the context of the embodiment of the semiconductor device are basically the same as the structure, materials and functions of the first insulating layer, the second insulating layer and the third insulating layer mentioned in the embodiment of the above-mentioned storage device. For other contents of the first insulating layer, the second insulating layer and the third insulating layer not mentioned in the embodiment of the semiconductor device, reference can be made to the corresponding contents of the first insulating layer, the second insulating layer and the third insulating layer in the embodiment of the above-mentioned storage device, and no further description will be made here.

[0246] Furthermore, in an embodiment of the present application, the first insulating layer and the third insulating layer are separately arranged on both sides of the second insulating layer; or, the first insulating layer and the third insulating layer are partially connected.

[0247] There is a certain area between adjacent transistor stacks, and the spacing area includes the gate electrode of the transistor. The part of the gate electrode located in the spacing area can be prepared from the same material layer. For example, after a cylindrical conductive film layer extending in the vertical direction is formed in the spacing area, a vertical gap is formed to cut and separate the conductive film layer.

[0248] Among them, the cutting and separation can be carried out by etching. Before etching, the hollow part of the tubular conductive film layer is filled with insulating material, and then the etching process is performed to form a vertical gap. The above gap separates the conductive film layer into two parts spaced apart from each other, which respectively form a gate main body part and a conductor part of adjacent transistor stacks. The remaining insulating material forms a first insulating layer and a second insulating layer respectively. The conductor parts of the two transistor stacks are opposite to each other, and the vertical gap exposes the opposite conductor parts. The first insulating layer and the third insulating layer can be completely or partially separated by the vertical gap. The second insulating layer is filled in the vertical gap and contacts the conductor part.

[0249] Exemplarily, the above-mentioned gap may also be formed only between two opposite conductor parts in two adjacent transistor stacks in the second horizontal direction, that is, the gap only cuts off the gate electrodes originally connected in the two adjacent transistor stacks in the second horizontal direction and partially extends into the insulating material, that is, the first insulating layer is partially connected to the third insulating layer.

[0250] In a preferred embodiment, the second insulating layer separates the first insulating layer and the third insulating layer as a whole, so that the size of the gap is larger, which can reduce the difficulty of the process.

[0251] Furthermore, in the embodiment of the present application, the second insulating layer includes a low dielectric constant (Low K) material.

[0252] That is, the second insulating layer may be made of a material with a dielectric constant lower than 3.9, which is beneficial to reducing the parasitic capacitance between transistors, including reducing the coupling between gate electrodes of two transistors adjacent to each other in the horizontal direction.

[0253] In particular, in the embodiment of the present application, the gate electrodes of two adjacent transistors in the horizontal direction include a conductor portion, and the distance between the closest conductor portions in the two adjacent transistors in the horizontal direction is smaller than that between the closest gate main portions. Therefore, the material selected for designing the second insulating layer includes a low dielectric constant material, which can more obviously reduce the coupling effect between the gate electrodes of the two adjacent transistors in the horizontal direction, thereby avoiding crosstalk caused by the conductor portions of the two adjacent transistors being too close.

[0254] Furthermore, in the embodiment of the present application, the overlapping parts of the gate electrodes in the orthographic projection of the substrate are connected to each other.

[0255] That is to say, the gate electrodes in the transistor stack are prepared as an integrated structure, that is, the gate electrodes of each transistor in the transistor stack are connected together as an integrated structure, and the gate electrodes are prepared and formed in one process. In this way, all transistors stacked in the vertical direction can be controlled by "one" vertically arranged gate electrode, which can simplify the manufacturing process of the semiconductor device and reduce manufacturing costs.

[0256] In the semiconductor device of the embodiment of the present application, multiple transistors are stacked vertically to form a transistor stack, the transistor has a horizontal channel and a vertical gate, and the gates of adjacent transistor stacks can be prepared simultaneously to reduce manufacturing costs; the vertical gate includes a gate body portion extending horizontally along the active layer, and a conductor portion located at both horizontal ends of the gate body portion, and the conductor portion is horizontally located on the side of the gate body portion away from the active layer, which can reduce the risk of short circuit between vertical gates without affecting the gate length.

[0257] In the description of this specification, the description with reference to the terms "Example 1", "Example 2", etc. means that the specific features, structures, materials or characteristics described in conjunction with the implementation or example are included in at least one implementation or example of the present application. In this specification, the schematic representation of the above terms does not necessarily refer to the same implementation or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more implementations or examples in a suitable manner.

[0258] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present application should be included in the protection scope of the present application.

Claims

1. A storage device, characterized in that: include: a substrate, including an insulating surface; A memory cell array, the memory cell array comprising a plurality of memory cells disposed on the insulating surface, the plurality of memory cells being repeatedly arranged along a first horizontal direction, a second horizontal direction and a vertical direction, the first horizontal direction intersecting the second horizontal direction; Each of the memory cells comprises a transistor, the transistor comprises an active layer, a gate insulating layer and a gate structure, the gate structure comprises a gate body portion, the gate body portion comprises a first gate, the active layer is parallel to the insulating surface, the first gate extends along a side wall of the active layer, and the gate insulating layer is located between the first gate and the active layer; The storage device also includes a common source structure and a bit line structure, the bit line structure includes a plurality of bit lines, each of the bit lines extends along the first horizontal direction, the active layer includes a source terminal and a drain terminal, the source terminal is connected to the common source structure, and the drain terminal is connected to one of the bit lines.

2. The storage device according to claim 1, characterized in that The gate body also includes a second gate extending along a side wall of the active layer. On an orthographic projection of the substrate, the first gate and the second gate are disposed on opposite sides of the active layer.

3. The storage device according to claim 1, characterized in that: The plurality of memory cells adjacent to each other in the vertical direction form a memory cell stack. In the plurality of memory cells in the memory cell stack, the active layer, the gate insulating layer, and the gate structure overlap in the orthographic projection of the substrate, respectively, and the overlapping parts of the gate structure in the orthographic projection of the substrate are connected correspondingly.

4. The storage device according to claim 1, characterized in that: A plurality of the memory cells adjacent to each other in the vertical direction form a memory cell stack, wherein the gate structures in the memory cell stack overlap with each other in their orthographic projections on the substrate; The plurality of memory cell stacks include a first memory cell stack and a second memory cell stack, wherein the first memory cell stack and the second memory cell stack are adjacent to each other in a first horizontal direction to form a memory cell stack group, and in one of the memory cell stack groups, the first gate of the first memory cell stack is arranged opposite to the first gate of the second memory cell stack; The gate structure also includes a conductor portion, which includes a first conductor portion formed integrally with the first gate. On the orthographic projection of the substrate, the first conductor portion is located on a side of the first gate away from the active layer, and the first conductor portion is located at both horizontal ends of the first gate.

5. The storage device according to claim 4, characterized in that: The storage unit stack groups are repeatedly arranged in the first horizontal direction.

6. The storage device according to claim 5, characterized in that: The gate body portion includes a second gate extending along a side wall of the active layer, and on an orthographic projection of the substrate, the first gate and the second gate are disposed on two sides of the active layer opposite to each other; The conductor portion further includes a second conductor portion formed integrally with the second gate, and on the orthographic projection of the substrate, the second conductor portion is located on a side of the second gate away from the active layer, and the second conductor portion is located at two horizontal ends of the second gate; The second gates are arranged opposite to each other between two adjacent memory cell stacking groups in the first horizontal direction.

7. The storage device according to any one of claims 4 to 6, characterized in that: Between the gate structures of at least one group of adjacent first memory cell stacks and second memory cell stacks, a first insulating layer, a second insulating layer and a third insulating layer are sequentially formed in a direction from the gate structure of the first memory cell stack to the gate structure of the second memory cell stack, and the first insulating layer and the third insulating layer are made of the same material; The first insulating layer and the third insulating layer contact the gate main body parts of the first memory cell stack and the second memory cell stack respectively, and the second insulating layer is arranged between the relative conductive parts in the first memory cell stack and the second memory cell stack and contacts the conductor parts of the first memory cell stack and the second memory cell stack.

8. The storage device according to claim 7, characterized in that: Between the gate structures of the at least one group of adjacent first memory cell stacks and second memory cell stacks, on an orthographic projection of the substrate: The first insulating layer is formed in a region surrounded by the gate body portion, the conductor portion and the second insulating layer of the first memory cell stack, and the edge of the first insulating layer extending along the conductor portion of the first memory cell stack is also adjacent to the second insulating layer; The third insulating layer is formed in a region surrounded by the gate body, the conductor part and the second insulating layer of the second memory cell stack, and the edge of the third insulating layer extending along the conductor part of the second memory cell stack is also adjacent to the second insulating layer.

9. The storage device according to claim 7, characterized in that: On the orthographic projection of the substrate: The first insulating layer and the third insulating layer are separately arranged on both sides of the second insulating layer; or the first insulating layer and the third insulating layer are partially connected.

10. The storage device according to claim 7, characterized in that: The second insulating layer includes a low dielectric constant material.

11. The storage device according to claim 2 or 6, characterized in that: The transistor is a junctionless transistor, the material of the active layer includes N-type doped polysilicon, the active layer also includes a channel region located between the source terminal and the drain portion, and in the storage unit, the channel region is located between the first gate and the second gate, and the width of the channel region in the direction from the first gate to the second gate is less than 40nm.

12. The storage device according to claim 2 or 6, characterized in that: In the gate structure: The first gate and the second gate are electrically connected; and / or The first gate and the second gate are controlled independently of each other; and / or The first gate and the second gate are controlled independently of each other, and the first gate and the second gate do not completely overlap on opposite surfaces.

13. The storage device according to claim 1, characterized in that: The common source structure includes at least one common source vertically arranged on the substrate, and the common source also extends along the first horizontal direction. The common source is connected to the source ends of multiple active layers adjacent in the vertical direction, and the source ends of the active layers adjacent in the first horizontal direction are connected to the same common source.

14. The storage device according to any one of claims 1 to 6, 8, 9, 10, and 13, characterized in that: The transistor is a junctionless transistor.

15. A method for manufacturing a storage device, characterized in that: Includes steps: providing a substrate; Preparing a plurality of film layer pairs stacked along a vertical direction on the substrate, wherein the film layer pairs include a semiconductor material layer and a first insulating dielectric layer sequentially arranged along the vertical direction; Etching the plurality of film layer pairs to form a plurality of first slits repeatedly arranged along a first horizontal direction and a second horizontal direction, wherein the first horizontal direction intersects with the second horizontal direction, and the first slits penetrate the plurality of film layer pairs along a vertical direction to form a second insulating dielectric layer filling the first slits, and in the second horizontal direction, the semiconductor material layer on one side of the first slit is formed into a bit line structure, wherein the bit line structure includes a plurality of bit lines, each of the bit lines extending along the first horizontal direction, and a common source structure is formed on a side of the first slit away from the bit line; Etching the second insulating dielectric layer in the first gap to form a plurality of first grooves repeatedly arranged along the first horizontal direction and the second horizontal direction, wherein the first grooves penetrate the second insulating dielectric layer along the vertical direction, the first grooves correspond to the first gaps one by one, the two opposite side walls of the first groove in the first horizontal direction both expose the semiconductor material layer, and in the orthographic projection of the substrate, the two opposite side walls of the first groove in the second horizontal direction fall into the first groove; forming a gate material layer on the entire sidewall of the first trench and a gate insulating material layer between the gate material layer and the surface of the semiconductor material layer exposed by the first trench, and filling a third insulating dielectric layer in the space surrounded by the gate material layer; Etching the gate material layer to form a plurality of second grooves repeatedly arranged along the first horizontal direction and the second horizontal direction, wherein the second grooves penetrate the gate material layer, so that the gate material layer is formed into a first gate structure and a second gate structure spaced apart in the first horizontal direction; A fourth insulating dielectric layer is filled in the second trench.

16. The method for manufacturing a storage device according to claim 15, characterized in that: The etching of the gate material layer to form a plurality of second grooves repeatedly arranged along the first horizontal direction and the second horizontal direction, wherein the second grooves penetrate the gate material layer, so that the gate material layer is formed into a first gate structure and a second gate structure spaced apart in the first horizontal direction, comprises: Anisotropically etching portions of the gate material layer located on opposite side walls of the first trench in the second horizontal direction to form pre-grooves, wherein the pre-grooves penetrate the gate material layer and do not expose portions of the gate material layer located on opposite side walls of the first trench in the first horizontal direction; The gate material layer exposed by the pre-groove is wet-etched to form the second groove.

17. The method for manufacturing a storage device according to claim 16, wherein: The step of anisotropically etching the gate material layer on the side walls of the first groove opposite to each other in the second horizontal direction to form a pre-groove also includes etching the third insulating layer, and the pre-groove also enables the third insulating medium layer to be formed into a second insulating layer and a third insulating layer at least partially separated in the first horizontal direction.

18. The method for manufacturing a storage device according to claim 15, wherein: The gate material layer formed on the entire sidewall of the first trench includes: depositing a conductor layer on the entire inner wall of the first trench, and removing a portion of the conductor layer located at the bottom of the first trench.

19. The method for manufacturing a storage device according to claim 15, wherein: The method for preparing the gate insulating material layer comprises deposition; or The semiconductor material layer comprises polysilicon, and the preparation method of the gate insulating material layer comprises thermally oxidizing the semiconductor material layer.

20. The method for manufacturing a storage device according to claim 15, wherein: The material of the fourth insulating dielectric layer includes a low dielectric constant material, and / or The material of the third insulating medium layer is different from the material of the fourth insulating medium layer.

21. The method for manufacturing a storage device according to claim 15, wherein: Two surfaces of two first grooves adjacent to each other in the first horizontal direction that are opposite to each other in the first horizontal direction do not completely overlap.

22. The method for manufacturing a storage device according to claim 15, wherein: The forming of the common source structure comprises the following steps: Etching the semiconductor material layer to form a third trench extending along the first horizontal direction, wherein the third trench penetrates the entire semiconductor material layer, and filling the third trench with a conductive layer to form a common source structure; In the second horizontal direction, the common source structure and the bit line structure are respectively located on two sides of the first gap.

23. A semiconductor device, characterized in that: include: substrate; a transistor stack comprising a plurality of transistors stacked vertically on said substrate; The transistor comprises an active layer and a gate electrode, the active layer extends in a horizontal direction, the gate electrode is located on a side wall of the active layer, and all gate electrodes in the transistor stack overlap in positive projection on the substrate; The gate electrode includes an integrated gate body and a conductor part, wherein the gate body is arranged along the length direction of the active layer, the conductor part is located on the side of the gate body away from the active layer, and the conductor part is located at both ends of the gate body in the horizontal direction.

24. The semiconductor device according to claim 23, wherein: The transistor stack is multiple, and the multiple transistor stacks are horizontally distributed on the substrate; In a horizontal direction perpendicular to an extending direction of the gate body portion, the gate electrodes of two adjacent transistor stacks are arranged opposite to each other.

25. The semiconductor device according to claim 24, wherein: The semiconductor device comprises a first insulating layer, a second insulating layer and a third insulating layer; In a horizontal direction extending perpendicular to the gate main body, the first insulating layer, the second insulating layer and the third insulating layer are sequentially arranged between the gate electrodes of the two adjacent transistor stacks, the first insulating layer and the third insulating layer are made of the same material and respectively contact the gate main bodies of the two transistor stacks, and the second insulating layer is arranged between the conductive parts of the two adjacent transistor stacks and contacts the conductive parts of the two adjacent transistor stacks.

26. The semiconductor device according to claim 25, wherein: Between the gate structures of the two adjacent transistor stacks, on the orthographic projection of the substrate: The first insulating layer and the third insulating layer are respectively formed in the area surrounded by the gate electrodes of the two adjacent memory cell stacks and the second insulating layer, the first insulating layer is also adjacent to the second insulating layer along the edge extending from the conductor part in contact with it, and the third insulating layer is also adjacent to the second insulating layer along the edge extending from the conductor part in contact with it.

27. The semiconductor device according to claim 25, wherein: On the orthographic projection of the substrate: the first insulating layer and the third insulating layer are separately arranged on both sides of the second insulating layer; or the first insulating layer and the third insulating layer are partially connected.

28. The semiconductor device according to claim 25, wherein: The second insulating layer includes a low dielectric constant material.

29. The semiconductor device according to claim 23, wherein: The transistor further comprises a gate insulating layer, wherein the gate insulating layer is located between the gate body and the active layer; and / or The overlapping parts of the gate electrodes in the orthographic projection of the substrate are connected to each other accordingly.

Images