Junction barrier Schottky diode and preparation method thereof

Abstract

The invention provides a junction barrier Schottky diode and a preparation method thereof. The junction barrier Schottky diode comprises a drift layer located on one side of a semiconductor substrate layer; the plurality of grooves are arranged in the drift layer along a first direction, and the first direction is parallel to the surface of the semiconductor substrate layer; the first P-type doped region is positioned in the drift layer on one side of the groove along the first direction and in the drift layer on one side of the groove facing the semiconductor substrate layer; the anode layers are located on the inner walls of the grooves, the surfaces of the sides, deviating from the semiconductor substrate layer, of the first P-type doped regions and the surfaces of the sides, deviating from the semiconductor substrate layer, of the drift layers between the adjacent grooves; wherein the first P-type doped region surrounds the anode layer on the side wall of one side of the groove in the first direction and a part of the anode layer on the bottom wall of the groove, and the first P-type doped region exposes the anode layer on the side wall of the other side of the groove in the first direction and the other part of the anode layer on the bottom wall of the groove. And the anti-surge capability and the integration level of the junction barrier Schottky diode are both improved.

Description

Technical Field

[0001] The invention relates to the technical field of semiconductors, and in particular to a junction barrier Schottky diode and a preparation method thereof. Background Art

[0002] Common power semiconductor structures include power diodes, vertical metal oxide semiconductor field effect transistors or insulated gate bipolar transistors. Among them, power diodes are one of the most commonly used electronic components and the most basic component unit of power electronic circuits. Its unidirectional conductivity can be used for circuit rectification, clamping and freewheeling. In the peripheral circuit, the diode mainly plays an anti-reverse role to prevent the current from backflowing and causing device damage. Traditional power diodes mainly include Schottky power diodes (SBDs) and PN junction power diodes. Compared with PN junction power diodes, Schottky power diodes use metal and semiconductor contact (gold-semiconductor contact) to form a metal semiconductor junction, which makes its forward turn-on voltage smaller. Moreover, Schottky power diodes are unipolar majority carrier conduction mechanisms. Its reverse recovery time is ideally zero, and there is no accumulation of excess minority carriers. Schottky power diodes have the characteristics of low on-state voltage drop, good switching characteristics, and small reverse recovery current. However, the reverse blocking characteristics of Schottky power diodes are very poor, and the leakage current is large under high temperature and reverse high voltage. PN junction power diodes have good reverse blocking characteristics, but the forward conduction voltage drop is higher than that of Schottky power diodes, and the reverse recovery time is long, the recovery current is large, and the energy consumption is large. The junction barrier Schottky diode (JBS) combines the Schottky power diode (SBD) with the PN junction power diode. By introducing the P-type region, the surface electric field of the Schottky contact area can be shielded, and higher reverse breakdown characteristics and forward surge performance can be achieved. Summary of the invention

[0003] The technical problem to be solved by the present invention is how to improve both the surge resistance and the integration of the junction barrier Schottky diode.

[0004] In order to solve the above technical problems, the present invention provides a junction barrier Schottky diode, comprising: a semiconductor substrate layer; a drift layer located on one side of the semiconductor substrate layer; a plurality of grooves arranged along a first direction in the drift layer, wherein the first direction is parallel to the surface of the semiconductor substrate layer; a first P-type doping region located in the drift layer on one side of the groove along the first direction and in the drift layer on the side of the groove facing the semiconductor substrate layer; an anode layer located on the inner wall of the groove, the surface of the first P-type doping region facing away from the semiconductor substrate layer, and the surface of the drift layer between adjacent grooves facing away from the semiconductor substrate layer; wherein the first P-type doping region surrounds the anode layer on the side wall of the groove on one side along the first direction and a portion of the anode layer on the bottom wall of the groove, and the first P-type doping region exposes the anode layer on the side wall of the groove on the other side along the first direction and another portion of the anode layer on the bottom wall of the groove.

[0005] Optionally, a dimension of the groove along a direction perpendicular to the semiconductor substrate layer is 0.5 micrometer to 3 micrometers.

[0006] Optionally, a dimension of the drift layer located between adjacent grooves and at a side of the first P-type doping region along the first direction is 0.5 micrometer to 2 micrometers.

[0007] Optionally, in a first direction, a size of a portion of the first P-type doped region located on a side of the groove facing the semiconductor substrate layer is a first size; in a direction perpendicular to the semiconductor substrate layer, a size of a portion of the first P-type doped region located on a side of the groove along the first direction is a second size, and the second size is larger than the first size.

[0008] Optionally, the second size is 1.2 to 2 times the first size.

[0009] Optionally, it also includes: a second P-type doping region located in the drift layer, the doping concentration of the second P-type doping region is less than the doping concentration of the first P-type doping region; wherein the second P-type doping region is located on the side of the first P-type doping region facing the semiconductor substrate layer and is in contact with the first P-type doping region; or, the second P-type doping region is located on the side of the groove away from the first P-type doping region along the first direction and on the side of the groove facing the semiconductor substrate layer, the second P-type doping region and the first P-type doping region respectively surround the anode layer in different areas of the bottom wall of the groove, the second P-type doping region is in contact with the first P-type doping region, and the distance from the second P-type doping region to the surface of the drift layer away from the semiconductor substrate layer is greater than zero.

[0010] Optionally, it also includes: a current extension zone, located in the drift layer, the distance from the current extension zone to the surface of the drift layer facing away from the semiconductor substrate layer is greater than zero, and the doping concentration of the current extension zone is greater than the doping concentration of the drift layer; wherein the first P-type doping region and the groove also extend into the current extension zone, and the current extension zone is provided between adjacent first P-type doping regions.

[0011] The present application also provides a method for preparing a junction barrier Schottky diode, comprising: forming a drift layer on one side of a semiconductor substrate layer; forming a plurality of grooves arranged along a first direction, wherein the grooves extend from a surface of the drift layer on a side away from the semiconductor substrate layer to a portion of the drift layer, and the first direction is parallel to the surface of the semiconductor substrate layer; forming a first P-type doping region in the drift layer on one side of the grooves along the first direction and in the drift layer on a side of the grooves facing the semiconductor substrate layer; forming an anode layer on an inner wall of the groove, a surface of the first P-type doping region on a side away from the semiconductor substrate layer, and a surface of the drift layer between adjacent grooves on a side away from the semiconductor substrate layer; wherein the first P-type doping region surrounds the anode layer on a side wall of the groove on one side along the first direction and a portion of the anode layer on a bottom wall of the groove, and the first P-type doping region exposes the anode layer on a side wall of the groove on the other side along the first direction and another portion of the anode layer on the bottom wall of the groove.

[0012] Optionally, the process of forming the first P-type doping region includes an ion implantation process.

[0013] Optionally, it also includes: before forming the anode layer, forming a second P-type doping region in the drift layer, the doping concentration of the second P-type doping region is less than the doping concentration of the first P-type doping region; wherein the second P-type doping region is located on the side of the first P-type doping region facing the semiconductor substrate layer and is in contact with the first P-type doping region; or, the second P-type doping region is located on the side of the groove away from the first P-type doping region along the first direction and on the side of the groove facing the semiconductor substrate layer, the second P-type doping region and the first P-type doping region respectively surround the anode layer in different areas of the bottom wall of the groove, the second P-type doping region is in contact with the first P-type doping region, and the distance from the second P-type doping region to the surface of the drift layer away from the semiconductor substrate layer is greater than zero.

[0014] Optionally, it also includes: forming a current extension zone in the drift layer, the distance from the current extension zone to the surface of the drift layer facing away from the semiconductor substrate layer is greater than zero, and the doping concentration of the current extension zone is greater than the doping concentration of the drift layer; after forming the groove, the groove also extends to the current extension zone; after forming the first P-type doping region, the first P-type doping region also extends into the current extension zone, and the current extension zone is provided between adjacent first P-type doping regions.

[0015] The technical solution of this application has the following technical effects:

[0016] The junction barrier Schottky diode provided by the technical solution of the present invention has a groove, and based on the existence of the groove, the depth of the surface of the side of the first P-type doping region facing the semiconductor substrate layer is deeper, so that the first P-type doping region located on the side of the groove along the first direction is larger in size in the direction perpendicular to the semiconductor substrate layer, thus increasing the contact area between the first P-type doping region and the drift layer. During the surge process, more surge current and surge voltage are applied to the junction of the first P-type doping region and the drift layer, promoting the opening of the PN junction formed by the first P-type doping region and the drift layer, so that the holes in the first P-type doping region diffuse into the drift layer, and the electrons in the drift layer diffuse into the first P-type doping region, generating conductivity modulation, limiting the further increase of voltage during the surge process, limiting the increase of power consumption, reducing the probability of failure of the junction barrier Schottky diode, and improving the surge resistance. Secondly, since the first P-type doping region located on the side of the groove along the first direction is larger in size in the direction perpendicular to the semiconductor substrate layer, and does not affect the size of the first P-type doping region located on the side of the groove facing the semiconductor substrate layer in the first direction, the overall area of ​​the junction barrier Schottky diode can be kept unchanged, and the integration is high. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0018] Figure 1 It is a schematic diagram of the structure of a junction barrier Schottky diode in the related art;

[0019] Figure 2 This is a schematic diagram of the structure of a junction barrier Schottky diode in one embodiment of the present application;

[0020] Figure 3 This is a schematic diagram of the structure of a junction barrier Schottky diode in another embodiment of the present application;

[0021] Figure 4 This is a schematic structural diagram of a junction barrier Schottky diode in another embodiment of the present application;

[0022] Figure 5 This is a schematic structural diagram of a junction barrier Schottky diode in another embodiment of the present application;

[0023] Figure 6 This is a schematic structural diagram of a junction barrier Schottky diode in another embodiment of the present application;

[0024] Figures 7 to 9 This is a structural diagram of the preparation process of a junction barrier Schottky diode in one embodiment of the present application;

[0025] Figure 10 to Figure 11 A structural diagram of a preparation process of a junction barrier Schottky diode provided in another embodiment of the present application;

[0026] Figure 12 to Figure 13 A structural diagram of a preparation process of a junction barrier Schottky diode provided in another embodiment of the present application;

[0027] Figures 14 to 17 A structural diagram of a preparation process of a junction barrier Schottky diode provided in another embodiment of the present application;

[0028] Figure 18 to Figure 19 A structural diagram of the preparation process of a junction barrier Schottky diode provided in another embodiment of the present application. DETAILED DESCRIPTION

[0029] Related art junction barrier Schottky diode, refer to Figure 1 , including: a semiconductor substrate layer 10; a drift layer 11 located on one side of the semiconductor substrate layer 10; a plurality of P-type doped layers F arranged along a first direction X in the drift layer 11, wherein the first direction X is parallel to the surface of the semiconductor substrate layer 10; an anode layer 14, located on a side surface of the P-type doped layer F away from the semiconductor substrate layer 10 and between the adjacent P-type doped layer F on a side surface of the drift layer 11 away from the semiconductor substrate layer 10.

[0030] Figure 1In the embodiment, the width of a portion of the P-type doped layer 13b along the first direction X is greater than the width of another portion of the P-type doped layer 13a along the first direction X, so that the contact area between the P-type doped layer 13b and the drift layer 11 is larger. During the surge process, more surge current and surge voltage are applied to the junction between the P-type doped layer and the drift layer 11, which promotes the opening of the PN junction formed by the P-type doped layer 13b and the drift layer 11, so that the holes in the P-type doped layer 13b diffuse into the drift layer, and the electrons in the drift layer 11 diffuse into the P-type doped layer 13b, resulting in conductivity modulation, limiting the further increase of voltage during the surge process, limiting the increase of power consumption, reducing the probability of failure of the junction barrier Schottky diode, and improving the surge resistance.

[0031] However, since the width of the P-type doped layer 13 b along the first direction X increases, the overall area of ​​the junction barrier Schottky diode increases, and the integration level decreases.

[0032] On this basis, the present application provides a junction barrier Schottky diode and a preparation method thereof, which improves both the surge resistance and the integration of the junction barrier Schottky diode.

[0033] The technical solution of the present invention will be described clearly and completely below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0034] In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first", "second", and "third" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.

[0035] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, it can also be the internal connection of two components, it can be a wireless connection, or it can be a wired connection. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0036] In addition, the technical features involved in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0037] An embodiment of the present application provides a junction barrier Schottky diode, referring to Figure 2 ,include:

[0038] Semiconductor substrate layer 100;

[0039] A drift layer 110 located on one side of the semiconductor substrate layer 100;

[0040] A plurality of grooves 120 arranged along a first direction X in the drift layer 110 , wherein the first direction X is parallel to a surface of the semiconductor substrate layer 100 ;

[0041] A first P-type doping region 130 is located in the drift layer 110 on one side of the groove 120 along the first direction X and in the drift layer 110 on a side of the groove 120 facing the semiconductor substrate layer 100;

[0042] an anode layer 140, located on the inner wall of the groove 120, the surface of the first P-type doping region 130 facing away from the semiconductor substrate layer 100, and the surface of the drift layer 110 between adjacent grooves 120 facing away from the semiconductor substrate layer 100;

[0043] Among them, the first P-type doping region 130 surrounds the anode layer 140 on the side wall of the groove 120 on one side along the first direction X and a portion of the anode layer 140 on the bottom wall of the groove 120, and the first P-type doping region 130 exposes the anode layer 140 on the side wall of the groove 120 on the other side along the first direction X and another portion of the anode layer 140 on the bottom wall of the groove 120.

[0044] In the present embodiment, due to the provision of the groove 120, based on the existence of the groove 120, the depth of the surface of the side of the first P-type doping region 130 facing the semiconductor substrate layer 100 is deeper, so that the first P-type doping region 130 located on the side of the groove 120 along the first direction X is larger in size in the direction perpendicular to the semiconductor substrate layer 100, thereby increasing the contact area between the first P-type doping region 130 and the drift layer 110. During the surge process, more surge current and surge voltage are applied to the junction of the first P-type doping region 130 and the drift layer 110, which promotes the opening of the PN junction formed by the first P-type doping region 130 and the drift layer 110, so that the holes in the first P-type doping region 130 diffuse into the drift layer 110, and the electrons in the drift layer 110 diffuse into the first P-type doping region 130, thereby generating conductivity modulation, limiting the further increase of voltage during the surge process, limiting the increase of power consumption, reducing the probability of failure of the junction barrier Schottky diode, and improving the surge resistance. Secondly, since the first P-type doped region 130 located on the side of the groove 120 along the first direction X is larger in size in the direction perpendicular to the semiconductor substrate layer 100, it does not affect the size of the first P-type doped region 130 located on the side of the groove 120 facing the semiconductor substrate layer 100 in the first direction X, so the overall area of ​​the junction barrier Schottky diode can be kept unchanged and the integration is higher.

[0045] The first P-type doping region 130 contacts the anode layer 140 on one side wall of the groove 120 along the first direction X and a portion of the anode layer 140 on the bottom wall of the groove 120 .

[0046] The first P-type doping region 130 exposes the anode layer 140 of the side wall of the groove 120 on the other side along the first direction X and another part of the anode layer 140 of the bottom wall of the groove 120, which means that the first P-type doping region 130 does not surround the anode layer 140 of the side wall of the groove 120 on the other side along the first direction X and another part of the anode layer 140 of the bottom wall of the groove 120, and the first P-type doping region 130 does not contact the anode layer 140 of the side wall of the groove 120 on the other side along the first direction X and does not contact the other part of the anode layer 140 of the bottom wall of the groove 120.

[0047] Preferably, the size of the portion of the anode layer 140 of the first P-type doping region 130 surrounding a portion of the bottom wall of the groove 120 in the first direction X is greater than 1 / 2 of the size of the groove 120 in the first direction X. This increases the reverse blocking capability.

[0048] In this embodiment, the new generation of SiC-based semiconductor power devices represented by SiC have higher reverse withstand voltage, lower forward conduction loss, faster switching frequency and stronger environmental tolerance compared to Si-based semiconductor power devices, and are therefore considered to be a new hope in the field of power conversion. It should be noted that in this embodiment, the semiconductor substrate layer 100 is silicon carbide (SiC) doped with conductive ions. In one embodiment, the conductive ions in the semiconductor substrate layer 100 are N-type ions. In other embodiments, there is no restriction on the conductivity type of the semiconductor substrate layer 100.

[0049] In one embodiment, the conductivity type of the drift layer 110 is the same as the conductivity type of the semiconductor substrate layer 100, and the doping concentration of the drift layer 110 is less than the doping concentration of the semiconductor substrate layer 100. In one embodiment, the material of the drift layer 110 is silicon carbide doped with N-type conductive ions. The N-type conductive ions may be phosphorus ions or nitrogen ions.

[0050] The conductivity type of the first P-type doping region 130 is opposite to the conductivity type of the drift layer 110 . Exemplarily, the conductivity type of the drift layer 110 is N-type, and the conductivity type of the first P-type doping region 130 is P-type.

[0051] If the size of the groove 120 along the direction perpendicular to the semiconductor substrate layer 100 is too large, the difficulty of the process implementation increases, the cost increases, the spacing distance between the groove 120 and the semiconductor substrate layer 100 becomes smaller, and the area of ​​the forward conduction current of the semiconductor power device decreases, which is not conducive to the reduction of the forward conduction resistance. If the size of the groove 120 along the direction perpendicular to the semiconductor substrate layer 100 is too small, the degree of increase in the size of the first P-type doping region 130 in the direction perpendicular to the semiconductor substrate layer 100 is limited, and the degree of improvement in the surge resistance is limited. Therefore, in one embodiment, the size of the groove 120 along the direction perpendicular to the semiconductor substrate layer 100 is 0.5 microns to 3 microns, for example, 0.5 microns, 1 micron, 1.5 microns, 2 microns, 2.5 microns or 3 microns.

[0052] If the size of the drift layer 100 located between the adjacent grooves 120 and on the side of the first P-type doping region 130 along the first direction X is too small, the forward conduction performance is affected; if the size of the drift layer 100 located between the adjacent grooves 120 and on the side of the first P-type doping region 130 along the first direction X is too large, the pinch-off performance during the reverse withstand voltage process is affected. Therefore, in one embodiment, the size of the drift layer 100 located between the adjacent grooves 120 and on the side of the first P-type doping region 130 along the first direction X is 0.5 micrometers to 2 micrometers, such as 0.5 micrometers, 1 micrometer, 1.5 micrometers or 2 micrometers.

[0053] In one embodiment, in the first direction X, the size of the portion of the first P-type doping region 130 located on the side of the groove 120 facing the semiconductor substrate layer 100 is a first size; in the direction perpendicular to the semiconductor substrate layer 100, the size of the portion of the first P-type doping region 130 located on the side of the groove 120 along the first direction X is a second size, and the second size is greater than the first size. Preferably, the second size is 1.2 to 2 times the first size, for example, 1.2 times, 1.5 times, 1.8 times or 2 times.

[0054] Another embodiment of the present application further provides a junction barrier Schottky diode, referring to Figure 3 The junction barrier Schottky diode of this embodiment is Figure 2 The difference between the junction barrier Schottky diode in the embodiment is that the junction barrier Schottky diode also includes: a second P-type doping region 150 located in the drift layer 110; wherein, the second P-type doping region 150 is located on the side of the first P-type doping region 130 facing the semiconductor substrate layer 110 and is in contact with the first P-type doping region 130, and the doping concentration of the second P-type doping region 150 is less than the doping concentration of the first P-type doping region 130.

[0055] Since the second P-type doping region 150 is provided, the overall structure composed of the first P-type doping region 130 and the second P-type doping region 150 and the PN junction of the drift layer 110 move the electric field peak toward the semiconductor substrate layer 100 , thereby enhancing the protection of the area near the inner wall of the groove 120 .

[0056] Preferably, the doping concentration of the first P-type doping region 130 is 1E18 atom / cm 3 ~1E19atom / cm 3 The doping concentration of the second P-type doping region 150 is 3E16atom / cm 3 ~1E17atom / cm 3 .

[0057] Another embodiment of the present application further provides a junction barrier Schottky diode, referring to Figure 4 The junction barrier Schottky diode of this embodiment is Figure 2The difference between the junction barrier Schottky diode in the embodiment is that the junction barrier Schottky diode also includes: a second P-type doping region 151 located in the drift layer 110; wherein the second P-type doping region 151 is located on the side of the groove 120 away from the first P-type doping region 130 along the first direction X and on the side of the groove 120 toward the semiconductor substrate layer 100, the second P-type doping region 130 and the first P-type doping region 130 respectively surround the anode layer 140 in different areas of the bottom wall of the groove 120, the second P-type doping region 151 is in contact with the first P-type doping region 130, the distance from the second P-type doping region 151 to the surface of the drift layer 110 away from the semiconductor substrate layer 100 is greater than zero, and the doping concentration of the second P-type doping region 151 is less than the doping concentration of the first P-type doping region 130.

[0058] The doping concentration of the second P-type doping region 151 is relatively low, so that when no voltage is applied, the degree of depletion of the drift layer 110 between the second P-type doping region 151 of the anode layer surrounding the inner wall of one groove 120 and the first P-type doping region 130 of the anode layer surrounding the inner wall of an adjacent groove 120 is reduced, which is beneficial to the reduction of the forward on-resistance. When no voltage is applied, the drift layer 110 between the second P-type doping region 151 of the anode layer surrounding the inner wall of one groove 120 and the first P-type doping region 130 of the anode layer surrounding the inner wall of an adjacent groove 120 is prevented from being pinched off.

[0059] Preferably, the doping concentration of the first P-type doping region 130 is 1E18 atom / cm 3 ~1E19atom / cm 3 The doping concentration of the second P-type doping region 151 is 3E16atom / cm 3 ~1E17atom / cm 3 .

[0060] Another embodiment of the present application further provides a junction barrier Schottky diode, referring to Figure 5 The junction barrier Schottky diode of this embodiment is Figure 4The difference between the junction barrier Schottky diode in the embodiment is that the junction barrier Schottky diode also includes: a current extension region 160, which is located in the drift layer 110, and the distance between the current extension region 160 and the surface of the drift layer 110 on the side away from the semiconductor substrate layer 100 is greater than zero, and the doping concentration of the current extension region 160 is greater than the doping concentration of the drift layer 110. Among them, the first P-type doping region 130 and the groove 120 also extend into the current extension region 160, and there is a current extension region 160 between adjacent first P-type doping regions 130. The second P-type doping region 151 also extends into the current extension region 160. For any two adjacent grooves 120, there is a current extension region 160 between the second P-type doping region 151 of the anode layer 140 surrounding the inner wall of one groove 120 and the first P-type doping region 130 of the anode layer 140 including the inner wall of another groove 120.

[0061] Another embodiment of the present application further provides a junction barrier Schottky diode, referring to Figure 6 The junction barrier Schottky diode of this embodiment is Figure 3 The difference between the junction barrier Schottky diode in the embodiment is that the junction barrier Schottky diode also includes: a current extension region 160, which is located in the drift layer 110, and the distance between the current extension region 160 and the surface of the drift layer 110 on the side away from the semiconductor substrate layer 100 is greater than zero, and the doping concentration of the current extension region 160 is greater than the doping concentration of the drift layer 110. Among them, the first P-type doping region 130 and the groove 120 also extend into the current extension region 160, and there is a current extension region 160 between adjacent first P-type doping regions 130. There is a current extension region 160 between adjacent second P-type doping regions 150.

[0062] Another embodiment of the present application also provides a method for preparing a junction barrier Schottky diode, referring to Figures 7 to 9 The preparation process of the junction barrier Schottky diode of this embodiment is introduced in detail.

[0063] refer to Figure 7 A drift layer 110 is formed on one side of the semiconductor substrate layer 100; a plurality of grooves 120 are formed along a first direction X, wherein the grooves 120 extend from a surface of the drift layer 110 that is away from the semiconductor substrate layer 100 to a portion of the drift layer 110, and the first direction X is parallel to the surface of the semiconductor substrate layer 100.

[0064] In one embodiment, the process of forming the groove 120 is an etching process.

[0065] refer to Figure 8 A first P-type doping region 130 is formed in the drift layer 110 on one side of the groove 120 along the first direction X and in the drift layer 110 on the side of the groove 120 facing the semiconductor substrate layer 100 .

[0066] The process of forming the first P-type doping region 130 includes an ion implantation process.

[0067] refer to Fig. 9 An anode layer 140 is formed on the inner wall of the groove 120 , the surface of the first P-type doping region 130 facing away from the semiconductor substrate layer 100 , and the surface of the drift layer 110 between adjacent grooves 120 facing away from the semiconductor substrate layer 100 .

[0068] Among them, the first P-type doping region 130 surrounds the anode layer 140 on the side wall of the groove 120 on one side along the first direction X and a portion of the anode layer 140 on the bottom wall of the groove 120, and the first P-type doping region 130 exposes the anode layer 140 on the side wall of the groove 120 on the other side along the first direction X and another portion of the anode layer 140 on the bottom wall of the groove 120.

[0069] Another embodiment of the present application also provides a method for preparing a junction barrier Schottky diode, referring to Figure 10 to Figure 11 The preparation process of the junction barrier Schottky diode of this embodiment is introduced in detail.

[0070] refer to Fig.10 , Fig.10 For Figure 8 Based on the schematic diagram, a second P-type doping region 150 is formed in the drift layer 110; the second P-type doping region 150 is located on the side of the first P-type doping region 130 facing the semiconductor substrate layer 100 and is in contact with the first P-type doping region 130, and the doping concentration of the second P-type doping region 150 is less than the doping concentration of the first P-type doping region 130.

[0071] The process of forming the second P-type doping region 150 includes an ion implantation process.

[0072] refer to Fig.11 An anode layer 140 is formed on the inner wall of the groove 120 , the surface of the first P-type doping region 130 facing away from the semiconductor substrate layer 100 , and the surface of the drift layer 110 between adjacent grooves 120 facing away from the semiconductor substrate layer 100 .

[0073] Another embodiment of the present application also provides a method for preparing a junction barrier Schottky diode, referring to Figure 12 to Figure 13 The preparation process of the junction barrier Schottky diode of this embodiment is introduced in detail.

[0074] refer to Fig.12 , Fig.12 For Figure 8Based on the schematic diagram, a second P-type doping region 151 is formed in the drift layer 110; the second P-type doping region 151 is located on the side of the groove 120 away from the first P-type doping region 130 along the first direction X and on the side of the groove 120 toward the semiconductor substrate layer 100, the second P-type doping region 130 and the first P-type doping region 130 respectively surround the anode layer 140 in different areas of the bottom wall of the groove 120, the second P-type doping region 151 is in contact with the first P-type doping region 130, the distance from the second P-type doping region 151 to the surface of the drift layer 110 away from the semiconductor substrate layer 100 is greater than zero, and the doping concentration of the second P-type doping region 151 is less than the doping concentration of the first P-type doping region 130.

[0075] The process of forming the second P-type doping region 151 includes an ion implantation process.

[0076] refer to Fig.13 An anode layer 140 is formed on the inner wall of the groove 120 , the surface of the first P-type doping region 130 facing away from the semiconductor substrate layer 100 , and the surface of the drift layer 110 between adjacent grooves 120 facing away from the semiconductor substrate layer 100 .

[0077] Another embodiment of the present application also provides a method for preparing a junction barrier Schottky diode, referring to Figures 14 to 17 The preparation process of the junction barrier Schottky diode of this embodiment is introduced in detail.

[0078] refer to Fig.14 , a drift layer 110 is formed on one side of the semiconductor substrate layer 100; a current extension region 160 is formed in the drift layer, the distance from the current extension region 160 to the surface of the drift layer 110 on the side away from the semiconductor substrate layer 100 is greater than zero, and the doping concentration of the current extension region 160 is greater than the doping concentration of the drift layer 110.

[0079] The process of forming the current extension region 160 includes an ion implantation process.

[0080] refer to Fig.15 , forming a plurality of grooves 120 arranged along a first direction X, wherein the grooves 120 extend from a surface of the drift layer 110 facing away from the semiconductor substrate layer 100 to a portion of the drift layer 110 , and the first direction X is parallel to the surface of the semiconductor substrate layer 100 .

[0081] In one embodiment, the process of forming the groove 120 is an etching process.

[0082] After the groove is formed, the groove also extends to the current extension region.

[0083] refer to Fig.16A first P-type doping region 130 is formed in the drift layer 110 on one side of the groove 120 along the first direction X and in the drift layer 110 on the side of the groove 120 facing the semiconductor substrate layer 100 .

[0084] The process of forming the first P-type doping region 130 includes an ion implantation process.

[0085] After the first P-type doping regions 130 are formed, the first P-type doping regions 130 further extend into the current extension region, and a current extension region 160 is provided between adjacent first P-type doping regions 130 .

[0086] In this embodiment, it also includes: forming a second P-type doping region 151 in the drift layer 110; the second P-type doping region 151 is located on the side of the groove 120 away from the first P-type doping region 130 along the first direction X and on the side of the groove 120 facing the semiconductor substrate layer 100, the second P-type doping region 130 and the first P-type doping region 130 respectively surround the anode layer 140 in different areas of the bottom wall of the groove 120, the second P-type doping region 151 is in contact with the first P-type doping region 130, the distance from the second P-type doping region 151 to the surface of the drift layer 110 away from the semiconductor substrate layer 100 is greater than zero, and the doping concentration of the second P-type doping region 151 is less than the doping concentration of the first P-type doping region 130. It should be noted that in other embodiments, the second P-type doping region may not be formed.

[0087] refer to Fig.17 An anode layer 140 is formed on the inner wall of the groove 120 , the surface of the first P-type doping region 130 facing away from the semiconductor substrate layer 100 , and the surface of the drift layer 110 between adjacent grooves 120 facing away from the semiconductor substrate layer 100 .

[0088] The second P-type doping region 151 also extends into the current extension region 160. For any two adjacent grooves 120, a current extension region 160 is provided between the second P-type doping region 151 of the anode layer 140 surrounding the inner wall of one groove 120 and the first P-type doping region 130 of the anode layer 140 including the inner wall of the other groove 120.

[0089] Another embodiment of the present application also provides a method for preparing a junction barrier Schottky diode, referring to Figure 18 to Figure 19 The preparation process of the junction barrier Schottky diode of this embodiment is introduced in detail.

[0090] refer to Fig.18 , Fig.18 for Fig.15 Based on the schematic diagram of FIG. 1 , a first P-type doping region 130 is formed in the drift layer 110 on one side of the groove 120 along the first direction X and in the drift layer 110 on the side of the groove 120 facing the semiconductor substrate layer 100 .

[0091] The process of forming the first P-type doping region 130 includes an ion implantation process.

[0092] After the first P-type doping regions 130 are formed, the first P-type doping regions 130 further extend into the current extension region 160 , and a current extension region 160 is provided between adjacent first P-type doping regions 130 .

[0093] In this embodiment, the second P-type doping region 150 is formed in the drift layer 110. The second P-type doping region 150 is located on the side of the first P-type doping region 130 facing the semiconductor substrate layer 100 and is in contact with the first P-type doping region 130. The doping concentration of the second P-type doping region 150 is less than the doping concentration of the first P-type doping region 130. A current extension region 160 is provided between adjacent second P-type doping regions 150.

[0094] It should be noted that in other embodiments, the second P-type doping region 150 may not be formed.

[0095] refer to Fig.19 An anode layer 140 is formed on the inner wall of the groove 120 , the surface of the first P-type doping region 130 facing away from the semiconductor substrate layer 100 , and the surface of the drift layer 110 between adjacent grooves 120 facing away from the semiconductor substrate layer 100 .

[0096] Obviously, the above embodiments are merely examples for the purpose of clear explanation, and are not intended to limit the implementation methods. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived therefrom are still within the scope of protection of the invention.

Claims

1. A junction barrier Schottky diode, characterized in that: include: Semiconductor substrate layer; a drift layer located on one side of the semiconductor substrate layer; a plurality of grooves arranged in a first direction in the drift layer, wherein the first direction is parallel to a surface of the semiconductor substrate layer; A first P-type doping region is located in the drift layer on one side of the groove along the first direction and in the drift layer on a side of the groove facing the semiconductor substrate layer; an anode layer, located on the inner wall of the groove, the surface of the first P-type doping region facing away from the semiconductor substrate layer, and the surface of the drift layer between adjacent grooves facing away from the semiconductor substrate layer; Among them, the first P-type doping region surrounds the anode layer on the side wall of the groove on one side along the first direction and a portion of the anode layer on the bottom wall of the groove, and the first P-type doping region exposes the anode layer on the side wall of the groove on the other side along the first direction and another portion of the anode layer on the bottom wall of the groove.

2. The junction barrier Schottky diode according to claim 1, characterized in that: The size of the groove along a direction perpendicular to the semiconductor substrate layer is 0.5 micrometer to 3 micrometers.

3. The junction barrier Schottky diode according to claim 1, characterized in that: The drift layer located between adjacent grooves and at the side of the first P-type doping region has a size along the first direction of 0.5 micrometers to 2 micrometers.

4. The junction barrier Schottky diode according to claim 1, characterized in that: In a first direction, a size of a portion of the first P-type doping region located on a side of the groove facing the semiconductor substrate layer is a first size; in a direction perpendicular to the semiconductor substrate layer, a size of a portion of the first P-type doping region located on a side of the groove along the first direction is a second size, and the second size is greater than the first size; Preferably, the second size is 1.2 to 2 times the first size.

5. The junction barrier Schottky diode according to claim 1, characterized in that: Also includes: a second P-type doping region located in the drift layer, wherein the doping concentration of the second P-type doping region is less than the doping concentration of the first P-type doping region; Wherein, the second P-type doping region is located on a side of the first P-type doping region facing the semiconductor substrate layer and is in contact with the first P-type doping region; or, the second P-type doping region is located on a side of the groove along the first direction away from the first P-type doping region and on a side of the groove facing the semiconductor substrate layer, the second P-type doping region and the first P-type doping region respectively surround the anode layer in different areas of the bottom wall of the groove, the second P-type doping region is in contact with the first P-type doping region, and the distance from the second P-type doping region to the surface of the drift layer away from the semiconductor substrate layer is greater than zero.

6. The junction barrier Schottky diode according to claim 1, characterized in that: Also includes: a current extension region, located in the drift layer, wherein a distance between the current extension region and a surface of the drift layer facing away from the semiconductor substrate layer is greater than zero, and a doping concentration of the current extension region is greater than a doping concentration of the drift layer; The first P-type doping region and the groove further extend into the current extension region, and the current extension region is provided between adjacent first P-type doping regions.

7. A method for preparing a junction barrier Schottky diode, characterized in that: include: forming a drift layer on one side of the semiconductor substrate layer; forming a plurality of grooves arranged along a first direction, wherein the grooves extend from a surface of the drift layer facing away from the semiconductor substrate layer to a portion of the drift layer, and the first direction is parallel to a surface of the semiconductor substrate layer; forming a first P-type doping region in the drift layer on one side of the groove along the first direction and in the drift layer on a side of the groove facing the semiconductor substrate layer; An anode layer is formed on the inner wall of the groove, the surface of the first P-type doping region facing away from the semiconductor substrate layer, and the surface of the drift layer between adjacent grooves facing away from the semiconductor substrate layer; Among them, the first P-type doping region surrounds the anode layer on the side wall of the groove on one side along the first direction and a portion of the anode layer on the bottom wall of the groove, and the first P-type doping region exposes the anode layer on the side wall of the groove on the other side along the first direction and another portion of the anode layer on the bottom wall of the groove.

8. The method for preparing a junction barrier Schottky diode according to claim 7, characterized in that: The process of forming the first P-type doping region includes an ion implantation process.

9. The method for preparing a junction barrier Schottky diode according to claim 7, characterized in that: Also includes: Before forming the anode layer, forming a second P-type doping region in the drift layer, wherein the doping concentration of the second P-type doping region is less than the doping concentration of the first P-type doping region; Wherein, the second P-type doping region is located on a side of the first P-type doping region facing the semiconductor substrate layer and is in contact with the first P-type doping region; or, the second P-type doping region is located on a side of the groove along the first direction away from the first P-type doping region and on a side of the groove facing the semiconductor substrate layer, the second P-type doping region and the first P-type doping region respectively surround the anode layer in different areas of the bottom wall of the groove, the second P-type doping region is in contact with the first P-type doping region, and the distance from the second P-type doping region to the surface of the drift layer away from the semiconductor substrate layer is greater than zero.

10. The method for preparing a junction barrier Schottky diode according to claim 7, characterized in that: Also includes: forming a current extension region in the drift layer, wherein the distance between the current extension region and the surface of the drift layer facing away from the semiconductor substrate layer is greater than zero, and the doping concentration of the current extension region is greater than the doping concentration of the drift layer; After forming the groove, the groove further extends to the current extension region; After the first P-type doping region is formed, the first P-type doping region further extends into the current extension region, and the current extension region is provided between adjacent first P-type doping regions.

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