Matrix operation device based on flexible RRAM storage and calculation array

Abstract

The invention relates to a matrix operation device based on a flexible RRAM storage and calculation array, belongs to the technical field of integrated circuits, and solves the problem that the area of the storage and calculation array cannot be reduced under the condition that the precision is not influenced in the prior art. According to the device, a flexible RRAM memory array outputs accumulated current of each column of memory units to a multiplexer MUX according to multi-row input; the multiplexer MUX selects one column of accumulated current from each column of storage and calculation unit and sends the accumulated current to the analog-to-digital converter ADC; the analog-to-digital converter ADC converts the received accumulated current into a digital signal and sends the digital signal to the subtractor; the popcount module receives the multi-line input, obtains the number of 1 in the multi-line input, and outputs the number to the multiplier; the multiplier multiplies the number of 1 by a fixed value beta and sends a product result to the subtracter; and the subtracter subtracts the product result from the digital signal to obtain a multiplication and addition result of the matrix. A small-area storage and calculation array high-precision storage and calculation function is realized, the energy efficiency is further improved, and the method is applied to a flexible calculation chip to make electronic skin.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a matrix operation device based on a flexible RRAM storage and operation array. Background Art

[0002] The current trend of artificial intelligence perception research is to make machines more human-like, and electronic skin can give intelligent robots tactile perception functions, which is expected to bring great changes to robotics technology. The development direction of electronic skin for tactile perception is to integrate sensing, storage and computing to build a sense-storage-computation integrated architecture, solve the power consumption bottleneck of data handling in the von Neumann architecture, and combine with sensing to improve overall efficiency. The traditional von Neumann architecture is subject to the "storage wall bottleneck", with high power consumption and slow speed, while in-memory computing technology can achieve a more efficient computing system and reduce computing power consumption. Since a large number of multiplication and addition convolution operations are the core components of deep learning algorithms, in-memory computing and in-memory logic are very suitable for deep neural network applications of artificial intelligence and big data technologies based on AI. The BNN (Binarized Neural Networks) algorithm can reduce memory usage, power consumption and area overhead, and improve computing speed while maintaining a certain computing accuracy, which is very suitable for edge computing. As a new type of non-volatile storage, RRAM (Resistive Random Access Memory) has been considered as the new device most likely to break through the limitations of traditional devices due to its simple structure, high integration, and low power consumption. It is used in in-memory computing.

[0003] Although there have been many achievements in the design of flexible pressure sensors, flexible computing chips are still in the exploratory stage, which is also needed to create truly flexible electronic skin. In-memory computing chips based on RRAM currently use XNOR operations based on 2T2R (2 RRAMs and 2 MOS transistors to form a memory computing unit) to implement BNN algorithms. Therefore, in order to further improve energy efficiency and apply flexible computing chips to create electronic skin, a matrix computing device based on a flexible memory computing array with a 1T1R structure of flexible RRAM and IGZO TFT is urgently needed. Summary of the invention

[0004] In view of the above analysis, an embodiment of the present invention aims to provide a matrix operation device based on a flexible RRAM storage and computing array, so as to solve the problem in the prior art that the storage and computing array is large in size and cannot be applied to electronic skin.

[0005] On the one hand, an embodiment of the present invention provides a matrix operation device based on a flexible RRAM storage and computing array, the device comprising: a flexible RRAM storage and computing array, a multiplexer MUX, an analog-to-digital converter ADC, a popcount module, a multiplier and a subtractor;

[0006] The flexible RRAM storage and computing array outputs the accumulated current of each column of storage and computing units to the multiplexer MUX according to the multiple row inputs;

[0007] The multiplexer MUX selects one column from each column of storage and calculation units, and sends the accumulated current of the column of storage and calculation units to the analog-to-digital converter ADC;

[0008] The analog-to-digital converter ADC converts the accumulated current output by the RRAM storage array into a digital signal and sends it to the subtractor;

[0009] The popcount module receives multiple lines of input and obtains the number of 1s in the multiple lines of input, and outputs the number of 1s to the multiplier;

[0010] The multiplier multiplies the number of 1s by a fixed value β and sends the product to the subtractor;

[0011] The subtractor subtracts the product result from the digital signal to obtain the matrix multiplication and addition result.

[0012] Furthermore, the flexible RRAM storage and computing array comprises n×m storage and computing units;

[0013] The word lines WL of each row of storage and calculation units are connected in sequence, the source lines SL of each column of storage and calculation units are connected in sequence, and the bit lines BL of each column of storage and calculation units are connected in sequence, and the bit lines BL are used to output the calculation results of the storage and calculation units in this column;

[0014] Each of the storage and computing units has a 1T1R structure, including a transistor and a memristor.

[0015] Further, the transistor is an indium gallium zinc oxide thin film transistor IGZO TFT, and the memristor is RRAM;

[0016] The gate of the indium gallium zinc oxide thin film transistor IGZO TFT is connected to the word line WL of the storage unit, the drain is connected to the bit line BL of the storage unit, the source is connected to one end of the memristor RRAM, and the other end of the RRAM is connected to the source line SL of the storage unit.

[0017] Furthermore, the working modes of the flexible RRAM storage and computing array include a write weight mode and an inference working mode.

[0018] Furthermore, in the write weight working mode, the connection voltages of the word line WL, the bit line BL and the source line SL are controlled to change the resistance state of the memristor RRAM, thereby achieving weight writing.

[0019] Further, when the word line WL is connected to a high level, the bit line BL is connected to a write voltage Vw, and the source line SL is grounded, the conductance state of the memristor RRAM is a low resistance state LRS, and its weight is assigned to β+1;

[0020] When the word line WL is connected to a high level, the bit line BL is grounded, and the source line SL is connected to a write voltage Vw, the conductance state of the memristor RRAM is a high resistance state HRS, and its weight is assigned to β-1;

[0021] When the word line WL is connected to a low level, it indicates that the memristor RRAM is not selected, and the resistance state of the memristor RRAM remains unchanged.

[0022] Furthermore, the write weight mode adopts a half voltage method, the write voltage Vw is greater than the threshold voltage of the memristor RRAM, and the half write voltage Vw is less than the threshold voltage of the memristor RRAM to ensure that the state of the unselected memristor RRAM remains unchanged.

[0023] Furthermore, in the inference working mode, the bit line BL is connected to the read voltage Vr and the source line SL is grounded. The input of the storage unit is determined according to whether the bit line WL is connected to a high level or a low level. The current value output by the storage unit is taken as the product of the input of the storage unit and the weight of the memristor RRAM. The currents output by each storage unit in each column of storage units are combined in the bit line corresponding to the storage unit in the column, so that the bit line output is the sum of the products of each unit in the column of storage units.

[0024] Furthermore, when the word line WL is connected to a high level and the resistance state of the memristor RRAM is a high resistance state HRS, the input of the storage unit is 1 and the output is a low current I L , low current I L The value of is β-1;

[0025] When the word line WL is connected to a high level and the resistance state of the memristor RRAM is a low resistance state LRS, the input of the storage unit is 1 and the output current I H , high current I H The value of is β+1;

[0026] When the word line WL is connected to a low level, the indium gallium zinc oxide thin film transistor IGZO TFT is disconnected, the storage unit is not connected, the input of the storage unit is 0, and the output current of the storage unit is 0.

[0027] Furthermore, the β>1.

[0028] Compared with the prior art, the present invention can achieve at least one of the following beneficial effects:

[0029] 1. This application uses a flexible RRAM storage and computing array with a 1T1R unit structure. The indium gallium zinc oxide thin-film transistor IGZO TFT and memristor in the 1T1R unit structure are both flexible structures of RRAM. Compared with the traditional 2T2R structure, this application reduces the storage and computing array area by half without affecting the calculation accuracy, further improving energy efficiency. Its flexible characteristics are more suitable for application in creating electronic skin.

[0030] 2. The design of peripheral circuits such as analog-to-digital converter ADC, popcount module, multiplier and subtractor improves the calculation accuracy of the matrix operation.

[0031] In the present invention, the above-mentioned technical solutions can also be combined with each other to achieve more preferred combination solutions. Other features and advantages of the present invention will be described in the subsequent description, and some advantages can become obvious from the description, or can be understood by practicing the present invention. The purpose and other advantages of the present invention can be realized and obtained through the contents particularly pointed out in the description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The drawings are only for the purpose of illustrating particular embodiments and are not to be considered limiting of the present invention. Like reference symbols denote like components throughout the drawings.

[0033] Figure 1 The circuit structure diagram of the flexible RRAM storage and computing array;

[0034] Figure 2 A calculation coding table for the RRAM storage array based on the 1T1R structure;

[0035] Figure 3 The overall circuit block diagram of the RRAM storage and computing array. DETAILED DESCRIPTION

[0036] The preferred embodiments of the present invention are described in detail below in conjunction with the accompanying drawings, wherein the accompanying drawings constitute a part of this application and are used together with the embodiments of the present invention to illustrate the principles of the present invention, but are not used to limit the scope of the present invention.

[0037] A specific embodiment of the present invention discloses a matrix operation device based on a flexible RRAM storage array, such as Figure 1 The device comprises: a flexible RRAM storage and computing array, a multiplexer MUX, an analog-to-digital converter ADC, a popcount module, a multiplier and a subtractor;

[0038] The flexible RRAM storage and computing array outputs the accumulated current of each column of storage and computing units to the multiplexer MUX according to the multiple row inputs;

[0039] The multiplexer MUX selects one column from each column of storage and calculation units, and sends the accumulated current of the column of storage and calculation units to the analog-to-digital converter ADC;

[0040] The analog-to-digital converter ADC converts the accumulated current output by the RRAM storage array into a digital signal and sends it to the subtractor;

[0041] The popcount module receives multiple lines of input and obtains the number of 1s in the multiple lines of input, and outputs the number of 1s to the multiplier;

[0042] The multiplier multiplies the number of 1s by a fixed value β and sends the product to the subtractor;

[0043] The subtractor subtracts the product result from the digital signal to obtain the matrix multiplication and addition result.

[0044] Specifically, the function of the multiplier is to multiply the input by a fixed β value, where the β value is determined by the performance of the RRAM storage array.

[0045] Exemplarily, when the matrix multiplication is [1,0,1,0,1]*[+1,+1,-1,-1,-1], that is, multiple rows of input are [1,0,1,0,1], the weight of a column of the RRAM storage array is [+1,+1,-1,-1,-1], the multiplication and addition result is -1, and the corresponding multiple rows of input of the RRAM storage array are 10101. The resistance states of the input corresponding RRAM units are β+1, β+1, β-1, β-1, β-1, respectively. Then, the accumulated current output by the RRAM storage array in this column is input to the multiplexer, and the multiplexer selects the accumulated current of the column of the storage array to be output to the analog-to-digital converter ADC. After analog-to-digital conversion, a current digital signal of 3β-1 is output to the subtractor. The popcount module output is 3, the multiplier output is 3β, and the subtractor output is -1. It can be seen that this scheme is completely consistent with the original multiplication and addition result.

[0046] Furthermore, the flexible RRAM storage and computing array comprises n×m storage and computing units;

[0047] The word lines WL of each row of storage and calculation units are connected in sequence, the source lines SL of each column of storage and calculation units are connected in sequence, and the bit lines BL of each column of storage and calculation units are connected in sequence, and the bit lines BL are used to output the calculation results of the storage and calculation units in this column;

[0048] Each of the storage and computing units has a 1T1R structure, including a transistor and a memristor.

[0049] Further, the transistor is an indium gallium zinc oxide thin film transistor IGZO TFT, and the memristor is RRAM;

[0050] The gate of the indium gallium zinc oxide thin film transistor IGZO TFT is connected to the word line WL of the storage unit, the drain is connected to the bit line BL of the storage unit, the source is connected to one end of the memristor RRAM, and the other end of the RRAM is connected to the source line SL of the storage unit.

[0051] Furthermore, the working modes of the flexible RRAM storage and computing array include a write weight mode and an inference working mode.

[0052] Specifically, when the bit line BL or the source line SL is connected to the write voltage Vw, the working mode of the flexible RRAM storage array is the write weight mode, and when the bit line BL is connected to the read voltage Vr, the working mode of the flexible RRAM storage array is the inference working mode.

[0053] Specifically, the input voltages of the word lines, bit lines and source lines connected to the array are controlled by the peripheral FPGA, that is, the word line WL is connected to a high level or a low level to control the on and off of the transistor, thereby selecting whether the current storage unit is enabled; when the word line WL is connected to a high level, the transistor is turned on, that is, the storage unit is enabled; when the word line WL is connected to a low level, the transistor is not turned on, that is, the storage unit is not enabled.

[0054] Furthermore, in the write weight working mode, the connection voltages of the word line WL, the bit line BL and the source line SL are controlled to change the resistance state of the memristor RRAM, thereby achieving weight writing.

[0055] Further, when the word line WL is connected to a high level, the bit line BL is connected to a write voltage Vw, and the source line SL is grounded, the conductance state of the memristor RRAM is a low resistance state LRS, and its weight is assigned to β+1;

[0056] When the word line WL is connected to a high level, the bit line BL is grounded, and the source line SL is connected to a write voltage Vw, the conductance state of the memristor RRAM is a high resistance state HRS, and its weight is assigned to β-1;

[0057] When the word line WL is connected to a low level, it indicates that the memristor RRAM is not selected, and the resistance state of the memristor RRAM remains unchanged.

[0058] In the write weight mode, the high and low resistance states of the RRAM are set by controlling the write voltage Vw of the storage and calculation unit and the on and off of the transistor, thereby completing the deployment of the weight in the RRAM array; the output of the source line SL and the bit line BL is grounded or connected to the write voltage, and the word line WL controls the on and off of the transistor to control the weight writing of the RRAM in the storage and calculation unit. For example, when the word line WL <0> When the source line SL is connected to the ground terminal and the bit line BL is connected to the write voltage, the RRAM is programmed to a low resistance state.

[0059] Specifically, in the write weight mode and the inference working mode, because the memristor RRAM is a non-volatile device, after the write weight mode completes the resistance state setting of the RRAM, the resistance state of the memristor RRAM is fixed and will not change unless a new programming voltage is applied to the word line WL, the bit line BL and the source line SL.

[0060] Furthermore, the write weight mode adopts a half voltage method, the write voltage Vw is greater than the threshold voltage of the memristor RRAM, and the half write voltage Vw is less than the threshold voltage of the memristor RRAM to ensure that the state of the unselected memristor RRAM remains unchanged.

[0061] Furthermore, in the inference working mode, the bit line BL is connected to the read voltage Vr and the source line SL is grounded. The input of the storage unit is determined according to whether the bit line WL is connected to a high level or a low level. The current value output by the storage unit is taken as the product of the input of the storage unit and the weight of the memristor RRAM. The currents output by each storage unit in each column of storage units are combined in the bit line corresponding to the storage unit in the column, so that the bit line output is the sum of the products of each unit in the column of storage units.

[0062] Further, such as Figure 2 As shown in FIG. 1 , when the word line WL is connected to a high level and the resistance state of the memristor RRAM is a high resistance state HRS, the input of the storage unit is 1 and the output is a low current I L , low current I L The value of is β-1;

[0063] When the word line WL is connected to a high level and the resistance state of the memristor RRAM is a low resistance state LRS, the input of the storage unit is 1 and the output current I H , high current I H The value of is β+1;

[0064] When the word line WL is connected to a low level, the indium gallium zinc oxide thin film transistor IGZO TFT is disconnected, the storage unit is not connected, the input of the storage unit is 0, and the output current of the storage unit is 0.

[0065] In the inference working mode, the entire RRAM array can realize the calculation function of multiplication and addition; the on and off of the TFT transistor is controlled by the word line WL to realize the input: when the word line WL is connected to a high level, the TFT transistor is turned on, that is, the storage unit is selected, indicating that the input is 1; when the word line WL is connected to a low level, the transistor is turned off, that is, the unit is not connected, indicating that the input is 0. The source line SL is connected to the ground, and the bit line BL is connected to the read voltage Vr to obtain the corresponding accumulated current, which is the multiplication and addition result. RRAM represents the weight distribution through the high and low resistance states after programming. When a bit line BL of the RRAM array is selected, a current I will be generated according to different high resistance states or low resistance states. H or I LFor example, when the word line WL <0> When the RRAM is in a high impedance state, the storage unit generates a reference current I L , which means that the calculation result of the unit is β-1 (β>1), and so on for the calculation of a whole column of storage and calculation units. The accumulated current obtained at the output bit line BL is the multiplication and addition result of a column of storage and calculation units. In this way, only one TFT transistor and one RRAM can be used as a storage and calculation unit to form a storage and calculation array.

[0066] This solution reduces the area of ​​the storage and computing array by half without affecting the calculation accuracy, and can improve the energy efficiency of the overall computing chip by combining with peripheral circuits. In addition, this solution uses flexible IGZO TFT and flexible RRAM as basic devices to construct a completely flexible storage and computing array. Combined with peripheral circuits, a matrix operation device based on a flexible RRAM storage and computing array is constructed, which provides a good foundation for the subsequent manufacture of complete electronic skin. Based on the RRAM storage and computing array, a binary multiplication and accumulation calculation method is provided, which provides a good foundation for the subsequent hardware circuit implementation of intelligent algorithms.

[0067] Furthermore, the β>1.

[0068] Specifically, the present application is equivalent to a deformed binary calculation. The input of the word line WL is to control whether the transistor is turned on or not. In the write weight mode, the high resistance state and low resistance state of the memristor RRAM are determined by controlling the voltage connected to the bit line BL and the source line SL. Since the high resistance state and the low resistance state are actually positive values, the low resistance state and the high resistance state are encoded as β+1 and β-1 respectively. In the inference working mode, the output also changes accordingly, and the output is also a binary high current and low current.

[0069] Furthermore, the size of the flexible RRAM storage and computing array is 64*64, and the total capacity is 4Kb.

[0070] Compared with the prior art, the matrix operation device based on the flexible RRAM storage and calculation array provided in this embodiment uses a flexible RRAM storage and calculation array with a 1T1R unit structure. The indium gallium zinc oxide thin film transistor IGZO TFT and the memristor in the 1T1R unit structure are both flexible structures. Compared with the traditional 2T2R structure, this application reduces the storage and calculation array area by half without affecting the calculation accuracy. It further improves energy efficiency by combining with peripheral circuits. Its flexible characteristics are more suitable for creating electronic skin. The design of peripheral circuits such as analog-to-digital converter ADC, popcount module, multiplier and subtractor improves the calculation accuracy of the matrix operation; this application provides a binary multiplication and accumulation calculation method based on the RRAM storage and calculation array, which provides a good foundation for the subsequent hardware circuit implementation of intelligent algorithms.

[0071] Those skilled in the art will appreciate that all or part of the processes of the above-mentioned embodiments can be implemented by instructing related hardware through a computer program, and the program can be stored in a computer-readable storage medium, wherein the computer-readable storage medium is a disk, an optical disk, a read-only storage memory, or a random access memory, etc.

[0072] The above description is only a preferred specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by any technician familiar with the technical field within the technical scope disclosed by the present invention should be covered within the protection scope of the present invention.

Claims

1. A matrix operation device based on a flexible RRAM storage and computing array, characterized in that: The device comprises: a flexible RRAM storage array, a multiplexer mux, an analog-to-digital converter ADC, a popcount module, a multiplier and a subtractor; The flexible RRAM storage and computing array outputs the accumulated current of each column of storage and computing units to the multiplexer MUX according to the multiple row inputs; The multiplexer MUX selects one column from each column of storage and calculation units, and sends the accumulated current of the column of storage and calculation units to the analog-to-digital converter ADC; The analog-to-digital converter ADC converts the accumulated current output by the RRAM storage array into a digital signal and sends it to the subtractor; The popcount module receives multiple lines of input and obtains the number of 1s in the multiple lines of input, and outputs the number of 1s to the multiplier; The multiplier multiplies the number of 1s by a fixed value β and sends the product to the subtractor; The subtractor subtracts the product result from the digital signal to obtain the matrix multiplication and addition result.

2. A matrix operation device based on a flexible RRAM storage and computing array according to claim 1, characterized in that: The flexible RRAM storage and computing array contains n×m storage and computing units; The word lines WL of each row of storage and calculation units are connected in sequence, the source lines SL of each column of storage and calculation units are connected in sequence, and the bit lines BL of each column of storage and calculation units are connected in sequence, and the bit lines BL are used to output the calculation results of the storage and calculation units in this column; Each of the storage and computing units has a 1T1R structure, including a transistor and a memristor.

3. A matrix operation device based on a flexible RRAM storage and computing array according to claim 2, characterized in that: The transistor is an indium gallium zinc oxide thin film transistor IGZO TFT, and the memristor is RRAM; The gate of the indium gallium zinc oxide thin film transistor IGZO TFT is connected to the word line WL of the storage unit, the drain is connected to the bit line BL of the storage unit, the source is connected to one end of the memristor RRAM, and the other end of the RRAM is connected to the source line SL of the storage unit.

4. A matrix operation device based on a flexible RRAM storage and computing array according to claim 3, characterized in that: The working modes of the flexible RRAM storage and computing array include a write weight mode and an inference working mode.

5. A matrix operation device based on a flexible RRAM storage and computing array according to claim 4, characterized in that: In the write weight working mode, the connection voltage of the word line WL, the bit line BL and the source line SL is controlled to change the resistance state of the memristor RRAM, thereby achieving weight writing.

6. A matrix operation device based on a flexible RRAM storage and computing array according to claim 5, characterized in that: When the word line WL is connected to a high level, the bit line BL is connected to a write voltage Vw, and the source line SL is grounded, the conductance state of the memristor RRAM is a low resistance state LRS, and its weight is assigned to β+1; When the word line WL is connected to a high level, the bit line BL is grounded, and the source line SL is connected to a write voltage Vw, the conductance state of the memristor RRAM is a high resistance state HRS, and its weight is assigned to β-1; When the word line WL is connected to a low level, it indicates that the memristor RRAM is not selected, and the resistance state of the memristor RRAM remains unchanged.

7. A matrix operation device based on a flexible RRAM storage and computing array according to claim 6, characterized in that: The write weight mode adopts a half voltage method, the write voltage Vw is greater than the threshold voltage of the memristor RRAM, and the half write voltage Vw is less than the threshold voltage of the memristor RRAM to ensure that the state of the unselected memristor RRAM remains unchanged.

8. The matrix operation device based on the flexible RRAM storage and computing array according to claim 7, characterized in that: In the inference working mode, the bit line BL is connected to the read voltage Vr and the source line SL is grounded. The input of the storage unit is determined according to whether the bit line WL is connected to a high level or a low level. The current value output by the storage unit is taken as the product of the input of the storage unit and the weight of the memristor RRAM. The currents output by each storage unit in each column of storage units are combined in the bit line corresponding to the storage unit in the column, so that the bit line output is the sum of the products of each unit in the column of storage units.

9. A matrix operation device based on a flexible RRAM storage and computing array according to claim 8, characterized in that: When the word line WL is connected to a high level and the resistance state of the memristor RRAM is a high resistance state HRS, the input of the storage unit is 1 and the output is a low current I L , low current I L The value of is β-1; When the word line WL is connected to a high level and the resistance state of the memristor RRAM is a low resistance state LRS, the input of the storage unit is 1 and the output current I H , high current I H The value of is β+1; When the word line WL is connected to a low level, the indium gallium zinc oxide thin film transistor IGZO TFT is disconnected, the storage unit is not connected, the input of the storage unit is 0, and the output current of the storage unit is 0.

10. The matrix operation device based on the flexible RRAM storage and computing array according to claim 9, characterized in that: The β>1.

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