Photovoltaic cell and preparation method thereof

Abstract

The invention discloses a preparation method of a photovoltaic cell. The preparation method comprises the following steps: providing a semiconductor substrate layer; forming a textured structure at least on the first surface of the semiconductor substrate layer; forming a first metal seed layer on the first surface side of the semiconductor substrate layer; forming a second metal seed layer on the second surface side of the semiconductor substrate layer; forming a first patterned grid line mask layer; the first graphical grid line mask layer is provided with a plurality of first electrode grooves; and forming a second patterned grid line mask layer, the second graphical grid line mask layer is provided with a plurality of second electrode grooves; wherein the difference between the top width and the bottom width of at least the first electrode groove is between 0 mu m and 3 mu m; forming a first conductive structure; and a second conductive structure; and removing the first patterned grid line mask layer, the second patterned grid line mask layer, a part of the first metal seed layer which is not covered by the first conductive structure and a part of the second metal seed layer which is not covered by the second conductive structure. The invention also provides a photovoltaic cell.

Description

Technical Field

[0001] The present application relates to the field of batteries, and in particular, to a photovoltaic cell and a method for preparing the photovoltaic cell. Background Art

[0002] The photovoltaic industry is an important part of the new energy industry. From developed countries to developing countries, investment in the photovoltaic industry is sweeping the world.

[0003] Heterojunction (HJT, HeteroJunction with intrinsic Thin-layer) batteries have high conversion efficiency, great expansion potential, simple process and clear cost reduction route, which conforms to the law of development of the photovoltaic industry and is the most promising next-generation battery technology. However, high cost is one of the key factors restricting the large-scale industrialization of HJT batteries. Its silver paste cost accounts for more than 40% of the total cost of HJT batteries, which is the main factor in the high cost of HJT. In the process of HJT industrialization, metallization cost reduction is the most urgent task at present. In order to reduce the cost of heterojunction batteries, a technical means currently used includes using copper instead of silver paste to electroplate the grid lines of heterojunction batteries.

[0004] However, the copper grid lines obtained by the electroplating process have poor adhesion and even grid line falling off (ie, grid detachment). Therefore, how to improve the adhesion of the copper grid lines has become a technical problem to be solved in the art. Summary of the invention

[0005] The present application aims to solve one of the technical problems in the related art to a certain extent. To this end, the present application provides a method for preparing a photovoltaic cell and a photovoltaic cell obtained by using the preparation method.

[0006] As a first aspect of the present application, a method for preparing a photovoltaic cell is provided, comprising: providing a semiconductor substrate layer, wherein the semiconductor substrate layer has a first surface and a second surface opposite to each other; wherein the method further comprises:

[0007] forming a velvet structure at least on the first surface of the semiconductor substrate layer;

[0008] forming a first metal seed layer on the first surface side of the semiconductor substrate layer;

[0009] forming a second metal seed layer on the second surface side of the semiconductor substrate layer;

[0010] A first patterned gate line mask layer is formed on the side of the first metal seed layer away from the semiconductor substrate layer by using a photolithography process; the first patterned gate line mask layer has a plurality of first electrode grooves penetrating the first metal seed layer in a thickness direction; and a second patterned gate line mask layer is formed on the side of the second metal seed layer away from the semiconductor substrate layer by using a photolithography process; the second patterned gate line mask layer has a plurality of second electrode grooves penetrating the first metal seed layer in a thickness direction; wherein at least the difference between the top width and the bottom width of the first electrode groove is between 0 μm and 3 μm;

[0011] forming a first conductive structure filling the first electrode groove; and forming a second conductive structure filling the second electrode groove;

[0012] The first patterned gate line mask layer, the second patterned gate line mask layer, the portion of the first metal seed layer not covered by the first conductive structure, and the portion of the second metal seed layer not covered by the second conductive structure are removed; wherein the first conductive structure and the retained portion of the first metal seed layer together constitute a first gate line; and the second conductive structure and the retained portion of the second metal seed layer together constitute a second gate line.

[0013] Optionally, forming a velvet structure at least on the first surface of the semiconductor substrate layer comprises:

[0014] Using a first type of texturing liquid to chemically etch the first surface to form a first type of pyramid structure on the first surface;

[0015] The second surface is chemically etched by using a second type of texturing liquid to form a second type of pyramid structure on the second surface; wherein,

[0016] The height of the first type pyramid structure includes: 1 μm to 1.5 μm;

[0017] The side length of the base of the first type pyramid structure includes: 1 μm to 1.7 μm;

[0018] The height of the second type pyramid structure includes: 1.6 μm to 1.8 μm;

[0019] The side length of the base of the second type pyramid structure includes: 1.6μm to 2μm.

[0020] Optionally, forming a velvet structure at least on the first surface of the semiconductor substrate layer comprises:

[0021] The first surface and the second surface are chemically etched by using a first type of texturing liquid to form a first type of pyramid structure on both the first surface and the second surface; wherein,

[0022] The height of the first type pyramid structure includes: 1 μm to 1.5 μm;

[0023] The side length of the base of the first type pyramid structure includes: 1 μm to 1.7 μm.

[0024] Optionally, the first type of texturing liquid includes:

[0025] 1.5wt% to 1.7wt% of an alkaline solvent; and 1.5wt% to 3wt% of a texturing active agent.

[0026] Optionally, the second type of texturing liquid includes:

[0027] 2wt% to 4wt% of alkaline solvent by mass; and 3wt% to 5wt% of texturing active agent by mass.

[0028] Optionally, a first patterned gate line mask layer is formed on a side of the first metal seed layer away from the semiconductor substrate layer by using a photolithography process; and a second patterned gate line mask layer is formed on a side of the second metal seed layer away from the semiconductor substrate layer by using a photolithography process, comprising:

[0029] Using photosensitive materials, a first initial gate line mask layer is formed on a side of the first metal seed layer away from the semiconductor substrate layer; and a second initial gate line mask layer is formed on a side of the second metal seed layer away from the semiconductor substrate layer;

[0030] Expose the first initial gate line mask layer and the second initial gate line mask layer through a mask plate respectively, wherein the ultraviolet exposure dose when at least one of the first initial gate line mask layer and the second initial gate line mask layer is exposed is between 40 mJ and 50 mJ;

[0031] The first initial gate line mask layer and the second initial gate line mask layer after exposure are developed to obtain a first patterned gate line mask layer and a second patterned gate line mask layer respectively.

[0032] Optionally, after forming the textured structure and before forming the first metal seed layer and the second metal seed layer, the method further includes:

[0033] forming a first functional layer on the first surface side of the semiconductor substrate layer; and forming a second functional layer on the second surface side of the semiconductor substrate layer;

[0034] forming a first transparent conductive layer on a side of the first functional layer away from the semiconductor substrate layer; and forming a second transparent conductive layer on a side of the second functional layer away from the semiconductor substrate layer;

[0035] The step of forming a first metal seed layer on the first surface side of the semiconductor substrate layer and the step of forming a second metal seed layer on the second surface side of the semiconductor substrate layer include:

[0036] The first metal seed layer is formed on a side of the first transparent conductive layer away from the first functional layer; and the second metal seed layer is formed on a side of the second transparent conductive layer away from the second functional layer.

[0037] Optionally, the metal seed layer includes at least one of a copper seed layer, a nickel seed layer and a titanium seed layer.

[0038] Optionally, the first functional layer includes: a first intrinsic semiconductor layer and a first doped semiconductor layer, wherein the first intrinsic semiconductor layer is formed on a first surface of the semiconductor substrate layer, and the first doped semiconductor layer is formed on a surface of the first intrinsic semiconductor layer away from the semiconductor substrate layer;

[0039] The second functional layer includes: a second intrinsic semiconductor layer and a second doped semiconductor layer, wherein the second intrinsic semiconductor layer is formed on the second surface of the semiconductor substrate layer, and the second doped semiconductor layer is formed on the surface of the second intrinsic semiconductor layer away from the semiconductor substrate layer.

[0040] As a second aspect of the present application, a photovoltaic cell is provided, wherein the photovoltaic cell is prepared by the method for preparing the photovoltaic cell described in the first aspect of the present application.

[0041] The inventor of the present application has found that one of the reasons for the gate line to be off is that the gate line groove of the gate line mask pattern presents a "wide at the top and narrow at the bottom" structure, which leads to a reduction in the contact area between the bottom of the gate line obtained by filling the gate line groove and the relevant film layer, and the gate line adhesion is poor. In the battery preparation method provided by the present application, the difference between the top width of the gate line groove and the bottom width of the gate line groove is limited to between 0μm and 3μm, so as to ensure that the difference between the top width and the bottom width of the gate line prepared in the subsequent steps is small, and the gate line width is more uniform, so as to improve the adhesion of the gate line (especially the bottom), thereby avoiding off-grid, and then improving the yield of the heterojunction battery finally prepared.

[0042] These features and advantages of the present application will be disclosed in detail in the following specific embodiments and drawings. The best embodiments or means of the present application will be described in detail in conjunction with the drawings, but they are not intended to limit the technical solutions of the present application. In addition, there are multiple features, elements, and components that appear in each of the following texts and drawings, and different symbols or numbers are marked for convenience, but they all represent components with the same or similar structures or functions. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] The present application will be further described below in conjunction with the accompanying drawings:

[0044] Figure 1 A schematic diagram of a structure of gate line preparation provided in some embodiments of the present application;

[0045] Figure 2 yes Figure 1 (b) is an enlarged schematic diagram of the area A in Figure;

[0046] Figure 3 yes Figure 1 (c) is an enlarged schematic diagram of the area A in Figure;

[0047] Figure 4 yes Figure 1 (d) is an enlarged schematic diagram of area A in Figure 1;

[0048] Figure 5 A schematic diagram of a process for preparing a photovoltaic cell provided in some embodiments of the present application;

[0049] Figure 6 is a flowchart of step S120 provided in some embodiments of the present application;

[0050] Figure 7 is a structural schematic diagram of a structure obtained after executing step S110 provided in some embodiments of the present application;

[0051] Figure 8 is a structural diagram of a structure obtained after executing step S120 provided in some embodiments of the present application;

[0052] Fig. 9 is a structural schematic diagram of another structure obtained after executing step S120 provided in some embodiments of the present application;

[0053] Fig.10 is a schematic structural diagram of a structure obtained after executing step S140 provided in some embodiments of the present application;

[0054] Fig.11 and Fig.12 is a schematic diagram of a structure obtained after executing step S150 provided in some embodiments of the present application; wherein, Fig.11 is a structural diagram of a structure obtained after executing step S152 provided in some embodiments of the present application; Fig.12 is a schematic structural diagram of a structure obtained after executing step S153 provided in some embodiments of the present application;

[0055] Fig.13 yes Fig.12A magnified schematic diagram of the middle B area;

[0056] Fig.14 is a structural diagram of a structure obtained after executing step S160 provided in some embodiments of the present application;

[0057] Fig.15 and Fig.16 is a structural diagram of a structure obtained after executing step S170 provided in some embodiments of the present application;

[0058] Fig.17 is a structural diagram of another structure obtained after executing step S170 provided in some embodiments of the present application;

[0059] Fig.18 is a flowchart of step S150 provided in some embodiments of the present application;

[0060] Fig.19 is a scanned image at the gate line in Example 1;

[0061] Fig. 20 is a scanned image at the gate line in Example 2;

[0062] Fig.21 is a scanned image at the gate line in Example 3;

[0063] Fig. 22 This is a scanned image at the gate line in Example 4.

[0064] Reference numerals:

[0065] 00-semiconductor substrate; 10-semiconductor substrate layer; 20-metal seed layer; 21-first metal seed layer; 22-second metal seed layer; 30-initial mask layer; 30'-patterned mask layer; 31-first initial gate line mask layer; 32-second initial gate line mask layer; 31'-first patterned gate line mask layer; 32'-second patterned gate line mask layer; 40-conductive structure; 41-first conductive structure; 42-second conductive structure; 51-first functional layer; 52-second functional layer; 61-first transparent conductive layer; 62-second transparent conductive layer; M0-gate line; M1-first gate line; M2-second gate line; H0-electrode groove; H1-first electrode groove; H2-second electrode groove; E1-first type pyramid structure; E2-second type pyramid structure. DETAILED DESCRIPTION

[0066] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements with the same or similar functions. The embodiments based on the embodiments are intended to be used to explain the present application and cannot be understood as limiting the present application.

[0067] References to "one embodiment" or "an example" or "an example" in this specification mean that a particular feature, structure, or characteristic described in conjunction with the embodiment itself may be included in at least one embodiment disclosed in the present application. The appearance of the phrase "in one embodiment" in various places in the specification does not necessarily refer to the same embodiment.

[0068] In the related art, the gate line is usually obtained by electroplating copper, and the electroplating copper process includes: seed layer preparation, patterning, metallization, post-processing and other links.

[0069] Accordingly, the graphical steps include:

[0070] forming an initial mask layer on the semiconductor substrate layer using a photoresist;

[0071] The initial mask layer is exposed and developed to obtain a grid line pattern in the target area.

[0072] Since the negative dry film has strong photosensitivity, the negative dry film can be used to make the mask layer. During exposure, the exposure light makes the negative dry film covering the target exposure area sensitive to light and solidified, and further through development, the uncured negative dry film covering the non-target exposure area is removed, thereby obtaining a preset shape of the grid line pattern. Because a velvet structure (i.e., a pyramid structure) is formed on the semiconductor substrate layer, it has a weak reflection effect on the exposure light, which will cause the part of the negative dry film covering the non-target exposure area to be abnormally solidified, and then cannot react with the developer in the subsequent development step. In this way, after the mask layer is exposed and developed, there will be residues formed by the negative dry film that has not been removed in the non-target exposure area (for the convenience of description, it is referred to as "residual feet"). The residue of the negative dry film will further cause the line width morphology of the grid line pattern to be distorted (for example, the aforementioned "wide at the top and narrow at the bottom" inverted trapezoidal structure).

[0073] The following Figure 1-Figure 4 How to form gate lines on the semiconductor substrate layer 10 in some embodiments of the present application is schematically described:

[0074] Providing a semiconductor substrate 00;

[0075] A metal seed layer 20 is formed on one side of the semiconductor substrate 00 (see Figure 1 (a) in the above;

[0076] An initial mask layer 30 is formed on the surface of the metal seed layer 20 (see Figure 1 (b) in the above);

[0077] The initial mask layer 30 is patterned to obtain a patterned mask layer 30', on which the patterned mask layer 30' is formed an electrode groove H0 penetrating the patterned mask layer 30 along the thickness direction (see FIG. Figure 1 (c) in the above);

[0078] A conductive structure 40 is formed in the electrode groove H0 (see Figure 1 (d) in the above);

[0079] The metal seed layer 20 is etched using the patterned mask layer 30' as a mask to obtain a gate line M0, wherein the gate line M0 includes a portion of the seed layer 20 and a conductive structure 40 (see Figure 1 (e) in the figure.

[0080] It should be pointed out that if Figure 2 As shown, a velvet structure (i.e., a pyramid structure) is formed on the surface of the semiconductor substrate 00, and the metal seed layer 20 is conformally covered on the velvet structure. Under normal circumstances, after exposure and development, the A1 area is exposed, while the A2 area should not be exposed. However, due to the reflection of light by the velvet structure, part of the exposure light applied to the edge of the A1 area is reflected into the A2 area.

[0081] like Figure 3 As shown, after development, the bottom width of the formed electrode groove is w1, and the top width is w2. However, due to the irradiation of reflected light in the A2 area, part of the initial mask layer 30 in the A2 area cannot be removed by the developer, resulting in that after development, the width w1 of the bottom of the electrode groove is smaller than the top width w2 of the electrode groove (i.e., an inverted trapezoidal morphology of "wide at the top and narrow at the bottom").

[0082] like Figure 4 As shown, the conductive structure 40 finally filled in the electrode groove also presents an inverted trapezoidal structure, and the contact area between the bottom and the seed layer 20 is greatly reduced. The gate line M0 in this morphology has poor adhesion and is easy to be decoupled.

[0083] In view of this, as one aspect of the present application, a method for preparing a battery is provided, such as Figure 5 As shown, the battery preparation method includes:

[0084] In step S110, a semiconductor substrate layer is provided, wherein the semiconductor substrate layer includes a first surface and a second surface;

[0085] In step S120, a textured structure is formed at least on the first surface of the semiconductor substrate layer;

[0086] In step S130, a first metal seed layer is formed on the first surface side of the semiconductor substrate layer;

[0087] In step S140, a second metal seed layer is formed on the second surface side of the semiconductor substrate layer;

[0088] In step S150, a first patterned gate line mask layer is formed on the side of the first metal seed layer away from the semiconductor substrate layer by using a photolithography process; the first patterned gate line mask layer has a plurality of first electrode grooves penetrating the first metal seed layer in a thickness direction; and a second patterned gate line mask layer is formed on the side of the second metal seed layer away from the semiconductor substrate layer by using a photolithography process; the second patterned gate line mask layer has a plurality of second electrode grooves penetrating the first metal seed layer in a thickness direction; wherein at least the difference between the top width and the bottom width of the first electrode groove is between 0 μm and 3 μm;

[0089] In step S160, a first conductive structure filling the first electrode groove is formed; and a second conductive structure filling the second electrode groove is formed;

[0090] In step S170, the first patterned gate line mask layer, the second patterned gate line mask layer, the portion of the first metal seed layer not covered by the first conductive structure, and the portion of the second metal seed layer not covered by the second conductive structure are removed; wherein the first conductive structure and the retained portion of the first metal seed layer together constitute a first gate line; and the second conductive structure and the retained portion of the second metal seed layer together constitute a second gate line.

[0091] As described above, one of the reasons for gate detachment is that the gate line groove of the gate line mask pattern presents a "wide at the top and narrow at the bottom" structure. In the battery preparation method provided in the present application, at least the difference between the top width of the first electrode groove and the bottom width of the first electrode groove is limited to between 0μm and 3μm, thereby ensuring that in the metal graphic layer prepared in the subsequent steps, at least the difference between the top width of the first conductive structure and the bottom width of the first conductive structure is small, and at least the width of the first gate line is uniform, thereby at least reducing the probability of gate detachment of the first gate line and improving the yield of the heterojunction battery finally prepared.

[0092] Although the two opposite surfaces of the semiconductor substrate layer are respectively referred to as the first surface and the second surface, in the embodiment of the present application, the first surface and the second surface are only used to distinguish different surfaces of the semiconductor substrate layer, rather than to provide a limitation.

[0093] In step S120 , the textured structure may be formed only on the first surface of the semiconductor substrate layer, or may be formed on both the first surface and the second surface of the semiconductor substrate layer.

[0094] In the embodiments of the present application, there is no special limitation on the "velvet structure". The velvet structure can be obtained by using a single crystal velvet method. Specifically, the semiconductor substrate layer is anisotropically etched using an alkali solution within a certain concentration range to obtain the velvet structure. Since the 111 lattice is anisotropically etched, the velvet structure obtained by this process often has a "pyramid" appearance.

[0095] In addition, the velvet structure can also be obtained by using a polycrystalline acid velvet method. For example, a mixed acid of hydrofluoric acid and nitric acid can be used to etch the semiconductor substrate layer. The velvet structure obtained in this way is a wormhole-like velvet.

[0096] Of course, the embodiments of the present application are not limited thereto, and the texture structure may also be obtained by using a variety of processes such as electrochemical texturing, reactive ion etching texturing, laser texturing, and mask texturing.

[0097] After the textured structure is formed on the surface of the semiconductor substrate layer, the light trapping effect of the semiconductor substrate layer can be improved.

[0098] The top of the first electrode groove refers to the portion of the first electrode groove away from the semiconductor substrate layer, and the bottom of the first electrode groove refers to the portion of the first electrode groove close to the semiconductor substrate layer.

[0099] The “at least the difference between the top width and the bottom width of the first electrode groove is between 0 μm and 3 μm” in step S150 may include the following situations:

[0100] 1. The difference between the top width and the bottom width of the first electrode groove is between 0 μm and 3 μm, and no requirement is imposed on the width of the second electrode groove;

[0101] 2. The difference between the top width and the bottom width of the first electrode groove is between 0 μm and 3 μm, and the difference between the top width and the bottom width of the second electrode groove is also between 0 μm and 3 μm.

[0102] In an embodiment in which the difference between the top width and the bottom width of the first electrode groove is between 0 μm and 3 μm, and the difference between the top width and the bottom width of the second electrode groove is also between 0 μm and 3 μm, the widths of the first gate line and the second gate line are relatively uniform, thereby reducing the probability of the first gate line and the second gate line being decoupled and improving the yield of the heterojunction battery finally produced.

[0103] In the present application, there is no special limitation on how to ensure that the difference between the top width of the first electrode groove and the bottom width of the first electrode groove is between 0μm and 3μm. As described above, the reason for the residual photoresist in the electrode groove is that the velvet structure has a weak reflective effect on the exposure light used in the exposure process. Therefore, reducing the size of the protrusions (such as the pyramid structure) in the velvet structure located on the first surface of the semiconductor substrate layer can reduce the reflective effect of the velvet structure on the exposure light to a certain extent, thereby reducing or even eliminating the amount of photoresist irradiated by the reflected light at the bottom of the first electrode groove, and ultimately reducing the residual foot at the bottom of the first electrode groove after development, so that the difference between the top width of the first electrode groove and the bottom width of the electrode groove is between 0μm and 3μm.

[0104] In the embodiment where the suede structure includes a plurality of protrusions, reducing the height of the protrusions can reduce the light reflection effect of the suede structure. As an optional embodiment, the height of the protrusions can be between 1 μm and 1.5 μm.

[0105] In addition to reducing the height of the protrusion, reducing the cross-sectional area of ​​the protrusion can also reduce the light reflection effect of the velvet structure. Accordingly, the side length of the bottom surface of the protrusion can be between 1 μm and 1.5 μm.

[0106] As described above, the protrusions of the velvet structure can be a pyramid structure. In the specific embodiment provided in the present application, the height of the pyramid structure is between 1 μm and 1.5 μm, and the size of the base (rectangle) of the pyramid structure (i.e., the side length of the rectangle) is between 1 μm and 1.7 μm.

[0107] In this application, there is no special limitation on how to obtain a velvet structure that meets the above-mentioned size requirements. As an optional implementation, Figure 6 As shown, a velvet structure is formed at least on the first surface of the semiconductor substrate layer, including:

[0108] In step S121, a first type of texturing liquid is used to chemically etch the first surface to form a first type of pyramid structure on the first surface;

[0109] In step S122, a second type of texturing liquid is used to chemically etch the second surface to form a second type of pyramid structure on the second surface.

[0110] The height of the first type pyramid structure is 1 μm to 1.5 μm; the side length of the base of the first type pyramid structure is 1 μm to 1.7 μm.

[0111] Wherein, the height of the second type pyramid structure is 1.6 μm to 1.8 μm; the side length of the base of the second type pyramid structure is 1.6 μm to 2 μm.

[0112] The size of the first type of pyramid structure is smaller than that of the second type of pyramid structure. Generally speaking, the first pyramid structure is a "small velvet" pyramid structure.

[0113] In the embodiment of the present application, the order of step S121 and step S122 is not particularly limited. When executing step S121, a mask layer can be set on the second side of the semiconductor substrate layer, and the mask layer can be peeled off after step S121 is completed; similarly, when executing step S122, a mask layer can be set on the first side of the semiconductor substrate layer, and the mask layer can be peeled off after step S122 is completed.

[0114] In the above embodiment, the velvet structure of the first surface of the semiconductor substrate layer is different from the velvet structure of the second surface of the semiconductor substrate layer. As another optional embodiment, a velvet structure including a plurality of small pyramid structures can be formed on both the first surface and the second surface of the semiconductor layer. That is, the velvet structure is formed at least on the first surface of the semiconductor substrate layer, including:

[0115] The first surface and the second surface are chemically etched by using a first type of texturing liquid to form a first type of pyramid structure on both the first surface and the second surface; wherein,

[0116] The height of the first type pyramid structure includes: 1 μm to 1.5 μm;

[0117] The side length of the base of the first type pyramid structure includes: 1 μm to 1.7 μm.

[0118] As an optional implementation manner, the first type of texturing liquid includes: 1.5wt% to 1.7wt% of an alkaline solvent by weight; and 1.5wt% to 3wt% of a texturing additive by weight.

[0119] In an embodiment of the present application, by relatively reducing the concentration of the alkaline solvent in the first texturing solution, the corrosion rate of the semiconductor substrate (for example, a silicon substrate) in the 111 crystal direction in the alkaline solution can be reduced, thereby reducing the side length of the pyramid-shaped base and the height of the protrusion.

[0120] As an optional implementation, the second type of texturing liquid comprises: 2wt% to 4wt% of an alkaline solvent by weight; and 3wt% to 5wt% of a texturing additive by weight.

[0121] As an optional embodiment, the alkaline solvent may be NaOH and / or KOH.

[0122] In the above specific implementation, the specific process parameters of the texturing treatment are not particularly limited. Optionally, the temperature of the texturing treatment is 40° C.-80° C., and the time of the texturing treatment is 630s-810s.

[0123] In the texturing step, the texturing additive can inhibit the rate of alkaline corrosion, and pyramid-shaped protrusions that meet size requirements can be formed by increasing the concentration of the texturing additive in the texturing liquid.

[0124] In this embodiment, the specific composition of the texturing additive is not particularly limited. For example, the texturing additive can be an alcohol additive or an alcohol-free additive.

[0125] In the above specific implementation, the temperature of the texturing treatment may be 40° C.-80° C., and the time of the texturing treatment may be 630s-810s.

[0126] Figure 7 and Figure 8 Shown in the figure are schematic diagrams of the steps of forming a first type pyramid structure on the first surface and a second type pyramid structure on the second surface:

[0127] Providing a semiconductor substrate layer 10, the semiconductor substrate layer 10 having a first surface and a second surface opposite to each other;

[0128] A first type pyramid structure E1 is formed on the first surface of the semiconductor substrate layer 10, and a second type pyramid structure E2 is formed on the second surface; wherein, the height h1 of the first type pyramid structure E1 includes: 1μm~1.5μm; the base side length a1 of the first type pyramid structure E1 includes: 1μm~1.7μm; the height h2 of the second type pyramid structure E2 includes: 1.6μm~1.8μm; the base side length a2 of the second type pyramid structure E2 includes: 1.6μm~2μm.

[0129] For example, the first type pyramid structure E1 and the second type pyramid structure E2 may be formed by plasma etching or chemical etching.

[0130] For example, the first type of pyramid structure E1 can be prepared by using the first type of texturing liquid, wherein the first type of texturing liquid includes: 1.5wt% to 1.7wt% of alkaline solvent; and 1.5wt% to 3wt% of texturing additive.

[0131] For example, the second type of texturing liquid mentioned above can be used to prepare the second type of pyramid structure E2, wherein the second type of texturing liquid includes: 2wt% to 4wt% of alkaline solvent by mass; and 3wt% to 5wt% of texturing additive by mass.

[0132] Fig. 9 What is shown in FIG. 1 is a process of forming a textured structure having a first type of pyramid E1 on both the first surface and the second surface.

[0133] For example, the first type of pyramid structure E1 can be prepared by using the first type of texturing liquid, wherein the first type of texturing liquid includes: 1.5wt% to 1.7wt% of alkaline solvent and 1.5wt% to 3wt% of texturing additive.

[0134] Fig.10 The process shown in FIG. 1 is to form a first metal seed layer 21 on a first surface side of the semiconductor substrate layer 10 and to form a second metal seed layer 22 on a second surface side of the semiconductor substrate layer 10 .

[0135] For example, the first metal seed layer 21 is selected from at least one of a copper seed layer, a nickel seed layer, and a titanium seed layer.

[0136] For example, the second metal seed layer 22 is selected from at least one of a copper seed layer, a nickel seed layer, and a titanium seed layer.

[0137] Therefore, compared with traditional photovoltaic cells with electrodes made of silver paste, the photovoltaic cells prepared by the preparation method provided in the present application not only have lower costs, but also have higher yields and service life.

[0138] Figures 11 to 13 What is shown in FIG. 1 is a process of preparing the first patterned gate line mask layer 31 and the second patterned gate line mask layer 32 .

[0139] Specifically, a photosensitive material may be used to form a first initial gate line mask layer 31 on the side of the first metal seed layer 21 away from the semiconductor substrate layer 10; and a second initial gate line mask layer 32 may be formed on the side of the second metal seed layer 22 away from the semiconductor substrate layer 10;

[0140] Then, the first initial gate line mask layer 31 and the second initial gate line mask layer 32 are respectively subjected to exposure processing through a mask plate;

[0141] Finally, the first initial gate line mask layer 31 and the second initial gate line mask layer 32 after exposure are developed to obtain a first patterned gate line mask layer 31 ′ and a second patterned gate line mask layer 32 ′ respectively.

[0142] Among them, the first patterned gate line mask layer 31 has multiple first electrode grooves H1 penetrating itself in the thickness direction; the second patterned gate line mask layer 32 has multiple second electrode grooves H2 penetrating itself in the thickness direction; wherein, at least the difference between the top width w3 and the bottom width w4 of the first electrode groove H1 is between 0μm and 3μm.

[0143] Fig.14 What is shown in FIG. 4 is a process of forming the first conductive structure 41 and the second conductive structure 42 .

[0144] Specifically, a plating process may be first used to form a conductive material that fills the first electrode groove H1 and the second electrode groove H2, and then a polishing process may be used to remove excess conductive material to obtain a first conductive structure 41 in the first electrode groove H1 and a second conductive structure 42 in the second electrode groove H2.

[0145] Figure 15 to Figure 16 What is shown in FIG. 1 is a process of forming the first gate line M1 and the second gate line M2 .

[0146] Specifically, the first patterned gate line mask layer 31' and the second patterned gate line mask layer 32' may be removed by wet etching or dry etching; and the first conductive structure 41 and the second conductive structure 42 are used as masks to etch away the first metal seed layer 21 and the second metal seed layer 22 that are not covered by the first conductive structure 41 and the second conductive structure 42. Thus, the first conductive structure 41 and the retained portion of the first metal seed layer 21 together constitute the first gate line M1; the second conductive structure 42 and the retained portion of the second metal seed layer 22 together constitute the second gate line M2.

[0147] In the present application, in addition to changing the size of the velvet structure, the exposure dose in step S150 may be reduced to ensure that at least the difference between the top width of the first electrode groove and the bottom width of the first electrode groove is between 0 μm and 3 μm.

[0148] Specifically, Fig.17 As shown, a first patterned gate line mask layer is formed on the side of the first metal seed layer away from the semiconductor substrate layer by using a photolithography process; and a second patterned gate line mask layer is formed on the side of the second metal seed layer away from the semiconductor substrate layer by using a photolithography process, including:

[0149] In step S151, a first initial gate line mask layer is formed on a side of the first metal seed layer away from the semiconductor substrate layer using a photosensitive material; and a second initial gate line mask layer is formed on a side of the second metal seed layer away from the semiconductor substrate layer;

[0150] In step S152, the first initial gate line mask layer and the second initial gate line mask layer are respectively exposed through a mask plate, wherein the ultraviolet exposure dose when at least one of the first initial gate line mask layer and the second initial gate line mask layer is exposed is between 40 mJ and 50 mJ;

[0151] In step S153, the first initial gate line mask layer and the second initial gate line mask layer after exposure are developed to obtain a first patterned gate line mask layer and a second patterned gate line mask layer respectively.

[0152] In some related technologies, the exposure dose when forming the gate line mask pattern can be between 80mJ and 100mJ. By reducing the exposure dose to between 40mJ and 50mJ, the intensity of light reflected on the sidewall of the electrode groove is reduced, thereby reducing the residual foot caused at the bottom of the electrode groove during subsequent development.

[0153] In step S152, the ultraviolet exposure dose when at least one of the first initial gate line mask layer and the second initial gate line mask layer is exposed is between 40 mJ and 50 mJ, which may include two implementations:

[0154] In a first embodiment, when exposing one of the first initial gate line mask layer and the second initial gate line mask layer, the ultraviolet exposure dose is controlled to be between 40 mJ and 50 mJ;

[0155] In a second embodiment, the ultraviolet exposure dose when exposing the first initial gate line mask layer and the second initial gate line mask layer is controlled to be between 40 mJ and 50 mJ.

[0156] In the above embodiment, the size of the velvet structure does not need to be reduced. That is, for the velvet structure including a plurality of second-type pyramid structures, the height of the second-type pyramid structure can be between 1.6 μm and 1.8 μm. Furthermore, the side length of the base of the second-type pyramid structure is between 1.6 μm and 2 μm.

[0157] See also Fig.18 In the embodiment of the present application, the photovoltaic cell further includes a functional layer. That is, after forming the velvet structure and before forming the first metal seed layer and the second metal seed layer, the method further includes:

[0158] A first functional layer 51 is formed on the first surface side of the semiconductor substrate layer 10; and a second functional layer 52 is formed on the second surface side of the semiconductor substrate layer 10;

[0159] A first transparent conductive layer 61 is formed on a side of the first functional layer 51 away from the semiconductor substrate layer 10 ; and a second transparent conductive layer 62 is formed on a side of the second functional layer 52 away from the semiconductor substrate layer 10 ;

[0160] Accordingly, the step of forming the first metal seed layer 21 on the first surface side of the semiconductor substrate layer 10 and the step of forming the second metal seed layer 22 on the second surface side of the semiconductor substrate layer 10 include:

[0161] The first metal seed layer 21 is formed on a side of the first transparent conductive layer 61 away from the first functional layer 51 ; and the second metal seed layer 22 is formed on a side of the second transparent conductive layer 62 away from the second functional layer 52 .

[0162] In the embodiments of the present application, there is no special limitation on the order of forming the first functional layer and the second functional layer; there is no special limitation on the order of forming the first transparent conductive layer and the second transparent conductive layer; there is no special limitation on the order of forming the first metal seed layer and the second metal seed layer.

[0163] As an optional embodiment, the first functional layer includes: a first intrinsic semiconductor layer and a first doped semiconductor layer, wherein the first intrinsic semiconductor layer is formed on the first surface of the semiconductor substrate layer, and the first doped semiconductor layer is formed on the surface of the first intrinsic semiconductor layer away from the semiconductor substrate layer.

[0164] As an optional embodiment, the second functional layer includes: a second intrinsic semiconductor layer, and a second doped semiconductor layer, wherein the second intrinsic semiconductor layer is formed on the second surface of the semiconductor substrate layer, and the second doped semiconductor layer is formed on the surface of the second intrinsic semiconductor layer away from the semiconductor substrate layer.

[0165] As a second aspect of the present application, a photovoltaic cell is provided, wherein the photovoltaic cell is prepared by the preparation method provided in the first aspect of the present application.

[0166] As described above, the photovoltaic cell manufactured by the above method has a uniform grid line width, is not prone to grid detachment, and has a high yield.

[0167] In the present application, the specific structure of the semiconductor substrate layer is not particularly limited. As an optional implementation, the semiconductor substrate layer can be a silicon-based substrate such as single crystal silicon, polycrystalline silicon, etc.

[0168] As an optional embodiment, the photovoltaic cell may be a heterojunction cell. Fig.18 As shown, the photovoltaic cell may include:

[0169] Semiconductor substrate layer 10,;

[0170] A first functional layer 51 disposed on a first surface of the semiconductor substrate layer 10, and a second functional layer 52 disposed on a second surface of the semiconductor substrate 10;

[0171] A first transparent conductive layer 61 disposed on the side of the first functional layer 51 away from the semiconductor substrate 10, and a second transparent conductive layer 62 disposed on the side of the second functional layer 52 away from the semiconductor substrate 10;

[0172] A first gate line 61 disposed on a side of the first transparent conductive layer 61 away from the first functional layer 51;

[0173] The second gate line 62 is disposed on a side of the second transparent conductive layer 62 away from the first functional layer 52 .

[0174] As an optional embodiment, the first functional layer 51 may include a first intrinsic semiconductor layer and a first doped semiconductor layer, wherein the first intrinsic semiconductor layer is formed on the first surface of the semiconductor layer 10 , and the first doped semiconductor layer is formed on a side of the first intrinsic semiconductor layer away from the semiconductor layer 10 .

[0175] As an optional embodiment, the second functional layer 52 may include a second intrinsic semiconductor layer and a second doped semiconductor layer, wherein the second intrinsic semiconductor layer is formed on the second surface of the semiconductor layer 10 and the second doped semiconductor layer is formed on a side of the second intrinsic semiconductor layer away from the semiconductor layer 10 .

[0176] As described above, the first gate line M1 may include a first conductive structure 41, and a portion of the first metal seed layer 21 disposed between the first conductive structure 41 and the first transparent conductive layer 61; as described above, the second gate line M2 may include a second conductive structure 42, and a portion of the second metal seed layer disposed between the second conductive structure 42 and the second transparent conductive layer 62.

[0177] Example

[0178] Example 1

[0179] A method for preparing a photovoltaic cell, comprising:

[0180] Providing a semiconductor substrate layer made of single crystal silicon, the semiconductor substrate layer comprising a first surface and a second surface opposite to each other;

[0181] Immersing the semiconductor substrate layer in a texturing liquid for texturing, wherein the texturing liquid is an aqueous solution, and the components of the texturing liquid include: 1.5wt% of NaOH and 3wt% of a texturing additive by mass percentage, the duration of this step is 630s, and the temperature of the texturing liquid is 40°C;

[0182] forming a first intrinsic semiconductor layer, a first doped semiconductor layer, and a first transparent conductive layer on the textured structure on the first surface;

[0183] forming a second intrinsic semiconductor layer, a second doped semiconductor layer, and a second transparent conductive layer on the textured structure on the second surface;

[0184] On the first transparent conductive layer, a first metal seed layer is formed by an epitaxial growth process, wherein the material of the first metal seed layer is copper;

[0185] On the second transparent conductive layer, forming a second metal seed layer by an epitaxial growth process, wherein the material of the second metal seed layer is copper;

[0186] forming a first photosensitive material mask layer on the first metal seed layer, and forming a second photosensitive material mask layer on the second metal seed layer;

[0187] The first photosensitive material mask layer and the second photosensitive material mask layer are exposed respectively, and the ultraviolet exposure dose is 100 mJ;

[0188] Developing the exposed first photosensitive material mask layer and the second photosensitive material mask layer with a developer to obtain a corresponding patterned gate line mask layer;

[0189] Patterning the first metal seed layer and the second metal seed layer according to the patterned gate line mask layer to form a plurality of first electrode grooves on the first metal seed layer and to form a plurality of second electrode grooves on the second metal seed layer;

[0190] Filling the first electrode groove with a first conductive structure and the second electrode groove with a second conductive structure by electroplating;

[0191] The patterned gate line mask layer is removed.

[0192] Example 2

[0193] A heterojunction battery is manufactured using the battery preparation method provided in Example 1, with the difference that the components of the texturing solution include: 3wt% NaOH and 2wt% texturing additive by mass, the duration of this step is 810s, the temperature of the texturing solution is 80°C, and the ultraviolet exposure dose is 40mJ.

[0194] Example 3

[0195] A heterojunction battery was manufactured using the battery preparation method provided in Example 1, except that the texturing solution contained 4 wt % of NaOH and 5 wt % of a texturing additive, and the ultraviolet exposure dose was 80 mJ.

[0196] Example 4

[0197] A heterojunction battery was made using the battery preparation method provided in Example 1, except that the components of the solution preparation included: 2 wt% NaOH and 3 wt% texturing additive, the duration of this step was 800 s, and the ultraviolet exposure dose was 60 mJ.

[0198] Test Case

[0199] 1. Determine the reflectivity of pyramid velvet surfaces of different sizes through simulation.

[0200]

[0201] From the simulation results, it can be known that when the size of the pyramid satisfies "the height of the pyramid structure is between 1 μm and 1.5 μm, and the side length of the base (rectangle) of the pyramid structure is between 1 μm and 1.7 μm", the reflectivity is low.

[0202] 2. Sample the structures obtained in Examples 1 to 4 and take scanning electron microscope images of the grid lines.

[0203] from Fig.19 It can be seen that the top width of the gate line obtained in Example 1 is about 19.37 μm, and the bottom width of the gate line is about 17.06 μm;

[0204] from Fig. 20 It can be seen that the top width of the gate line obtained in Example 2 is about 17.70 μm, and the bottom width of the gate line is about 16.06 μm;

[0205] from Fig.21 It can be seen that the top width of the gate line obtained in Example 3 is about 15.59 μm, and the bottom width of the gate line is about 13.06 μm;

[0206] from Fig. 22 It can be seen that the top width of the gate line obtained in Example 4 is about 19.01 μm, and the bottom width of the gate line is about 15.73 μm.

[0207] The above are only specific embodiments of the present application, but the protection scope of the present application is not limited thereto. Those skilled in the art should understand that the present application includes but is not limited to the contents described in the drawings and the above specific embodiments. Any modification that does not deviate from the functional and structural principles of the present application will be included in the scope of the claims.

Claims

1. A method for preparing a photovoltaic cell, comprising: A semiconductor substrate layer is provided, wherein the semiconductor substrate layer has a first surface and a second surface opposite to each other; wherein the method further comprises: forming a velvet structure at least on the first surface of the semiconductor substrate layer; forming a first metal seed layer on the first surface side of the semiconductor substrate layer; forming a second metal non-metal seed layer on the second surface side of the semiconductor substrate layer; A first patterned gate line mask layer is formed on the side of the first metal seed layer away from the semiconductor substrate layer by using a photolithography process; the first patterned gate line mask layer has a plurality of first electrode grooves penetrating the first metal seed layer in a thickness direction; and a second patterned gate line mask layer is formed on the side of the second metal seed layer away from the semiconductor substrate layer by using a photolithography process; the second patterned gate line mask layer has a plurality of second electrode grooves penetrating the first metal seed layer in a thickness direction; wherein at least the difference between the top width and the bottom width of the first electrode groove is between 0 μm and 3 μm; forming a first conductive structure filling the first electrode groove; and forming a second conductive structure filling the second electrode groove; The first patterned gate line mask layer, the second patterned gate line mask layer, the portion of the first metal seed layer not covered by the first conductive structure, and the portion of the second metal seed layer not covered by the second conductive structure are removed; wherein the first conductive structure and the retained portion of the first metal seed layer together constitute a first gate line; and the second conductive structure and the retained portion of the second metal seed layer together constitute a second gate line.

2. The method for preparing a photovoltaic cell according to claim 1, characterized in that: Forming a velvet structure at least on the first surface of the semiconductor substrate layer, comprising: Using a first type of texturing liquid to chemically etch the first surface to form a first type of pyramid structure on the first surface; The second surface is chemically etched by using a second type of texturing liquid to form a second type of pyramid structure on the second surface; wherein, The height of the first type pyramid structure includes: 1 μm to 1.5 μm; The side length of the base of the first type pyramid structure includes: 1 μm to 1.7 μm; The height of the second type pyramid structure includes: 1.6 μm to 1.8 μm; The side length of the base of the second type pyramid structure includes: 1.6μm to 2μm.

3. The method for preparing a photovoltaic cell according to claim 1, characterized in that: Forming a velvet structure at least on the first surface of the semiconductor substrate layer, comprising: The first surface and the second surface are chemically etched by using a first type of texturing liquid to form a first type of pyramid structure on both the first surface and the second surface; wherein, The height of the first type pyramid structure includes: 1 μm to 1.5 μm; The side length of the base of the first type pyramid structure includes: 1 μm to 1.7 μm.

4. The method for preparing a photovoltaic cell according to claim 2 or 3, characterized in that: The first type of texturing liquid comprises: 1.5wt% to 1.7wt% of an alkaline solvent; and 1.5wt% to 3wt% of a texturing active agent.

5. The method for preparing a photovoltaic cell according to claim 3, characterized in that: The second type of texturing liquid comprises: 2wt% to 4wt% of alkaline solvent by mass; and 3wt% to 5wt% of texturing active agent by mass.

6. The method for preparing a photovoltaic cell according to any one of claims 1 to 3, characterized in that: Forming a first patterned gate line mask layer on a side of the first metal seed layer away from the semiconductor substrate layer by using a photolithography process; And, forming a second patterned gate line mask layer on a side of the second metal seed layer away from the semiconductor substrate layer by using a photolithography process, comprising: Using photosensitive materials, a first initial gate line mask layer is formed on a side of the first metal seed layer away from the semiconductor substrate layer; and a second initial gate line mask layer is formed on a side of the second metal seed layer away from the semiconductor substrate layer; Expose the first initial gate line mask layer and the second initial gate line mask layer through a mask plate respectively, wherein the ultraviolet exposure dose when at least one of the first initial gate line mask layer and the second initial gate line mask layer is exposed is between 40 mJ and 50 mJ; The first initial gate line mask layer and the second initial gate line mask layer after exposure are developed to obtain a first patterned gate line mask layer and a second patterned gate line mask layer respectively.

7. The method for preparing a photovoltaic cell according to claim 1, characterized in that: After forming the textured structure and before forming the first metal seed layer and the second metal seed layer, the method further includes: forming a first functional layer on the first surface side of the semiconductor substrate layer; and forming a second functional layer on the second surface side of the semiconductor substrate layer; forming a first transparent conductive layer on a side of the first functional layer away from the semiconductor substrate layer; and forming a second transparent conductive layer on a side of the second functional layer away from the semiconductor substrate layer; The step of forming a first metal seed layer on the first surface side of the semiconductor substrate layer and the step of forming a second metal seed layer on the second surface side of the semiconductor substrate layer include: The first metal seed layer is formed on a side of the first transparent conductive layer away from the first functional layer; and the second metal seed layer is formed on a side of the second transparent conductive layer away from the second functional layer.

8. The method for preparing a photovoltaic cell according to any one of claims 1 to 7, characterized in that: The metal seed layer includes at least one of a copper seed layer, a nickel seed layer and a titanium seed layer.

9. The method for preparing a photovoltaic cell according to claim 8, characterized in that: The first functional layer comprises: a first intrinsic semiconductor layer and a first doped semiconductor layer, wherein the first intrinsic semiconductor layer is formed on a first surface of the semiconductor substrate layer, and the first doped semiconductor layer is formed on a surface of the first intrinsic semiconductor layer away from the semiconductor substrate layer; The second functional layer includes: a second intrinsic semiconductor layer and a second doped semiconductor layer, wherein the second intrinsic semiconductor layer is formed on the second surface of the semiconductor substrate layer, and the second doped semiconductor layer is formed on the surface of the second intrinsic semiconductor layer away from the semiconductor substrate layer.

10. A photovoltaic cell, characterized in that: The photovoltaic cell is prepared by the method for preparing a photovoltaic cell according to any one of claims 1 to 9.

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