Neural network test system based on electronic synaptic array

Abstract

The invention discloses a neural network test system based on an electronic synapse array, which comprises a control system, an array test circuit board and an electronic synapse array, and is characterized in that the control system is an SoC development board comprising an ARM module and an FPGA module, and array test and in-memory calculation programs can be written in a reconfigurable manner; the array test circuit board comprises an analog-to-digital / digital-to-analog conversion module and a multiplexer module, and is connected with the electronic synapse array through a pin header; the electronic synapse array is of an m-row and n-column array structure formed by a plurality of non-volatile and multi-state artificial electronic synapse devices through a cross process, and is connected with a word line WL driver and a bit line BL driver of the array test circuit board through pin headers, and synapses receive input signals from the array test circuit board. And the storage state of the synaptic device of the corresponding unit is reflected by the read-out signal. The system is high in read-write precision, and the flexibility of testing the electronic synaptic array is improved.

Description

Technical Field

[0001] The invention relates to the technical field of semiconductors and integrated circuits, and in particular to a neural network testing system based on an electronic synapse array. Background Art

[0002] With the rapid development of emerging technologies such as big data, artificial intelligence, and the Internet of Things, the demand for data-centric real-time and intelligent computing is growing, but traditional von Neumann computing systems are increasingly unable to meet the explosive growth in computing power. This is because under the von Neumann architecture, the data processing unit and the storage unit are separated, and the delay and energy consumption caused by the reciprocating transmission of data lead to problems such as slow speed and high power consumption, and these problems are more prominent when processing complex information. In contrast, the human brain, a parallel structured neural network system composed of neurons and synapses, can process a large amount of complex information with extremely low power consumption (about 20W). Therefore, imitating the human brain, researchers have started the study of integrated computing that integrates computing units and storage units, proposed a variety of artificial electronic synaptic devices, and explored neural network in-memory computing systems based on these devices, showing application potential such as fast speed and low power consumption. Among them, emerging memristive electronic synaptic devices, including ferroelectric tunnel junctions, ferroelectric field-effect transistors, and resistive random access memories based on oxygen vacancies or metal ion migration, have demonstrated more significant advantages in terms of energy consumption and integration than electronic synapses constructed using traditional CMOS (Complementary Metal Oxide Semiconductor) devices.

[0003] However, the research on the emerging electronic synaptic memristor devices still focuses on the performance of unit devices, while the research on the neural network constructed by them is mainly based on simulation. The preparation of a cross array composed of multiple synaptic devices and the realization of neural network calculations at the hardware level have gradually attracted attention. Related research and development urgently need to build a test system for electronic synaptic arrays and their neural network calculations, so as to accurately read and erase the resistance values ​​of electronic synapses in specified rows and columns in the array, and combine the connected system on chip (System on Chip, SoC) containing ARM (Advanced RISC (Reduced Instruction Set Computer) Machines) modules and FPGA (Field Programmable Gate Array) modules to build different neural network structures, and realize the performance test of the neural network computing system constructed by the synaptic array, which is of great significance to the research and development in related fields. Summary of the invention

[0004] The purpose of the present invention is to provide a neural network testing system based on an electronic synapse array, which gives full play to the programmable characteristics of the FPGA part of the SoC development board, can apply positive pulses or negative pulses to selected devices of the electronic synapse array through an array test circuit board, has high reading and writing accuracy, and improves the flexibility of testing the electronic synapse array.

[0005] The objective of the present invention is achieved through the following technical solutions:

[0006] A neural network test system based on an electronic synapse array, the system comprising a control system, an array test circuit board and an electronic synapse array, wherein:

[0007] The control system is specifically a SoC development board including an ARM module and an FPGA module, which can reconfigurably write array test and in-memory computing programs and exchange data with a computer and an array test circuit board;

[0008] The control system is connected to the array test circuit board and communicates with the internal integrated circuit IIC protocol through the FPGA middle layer board interface;

[0009] The array test circuit board comprises an analog-to-digital / digital-to-analog conversion module and a multiplexer MUX module, which are connected to the electronic synapse array via a pin header;

[0010] The array test circuit board receives the command of the control system, and is used to select specific units or rows and columns in the electronic synapse array, and perform high-precision voltage writing and current reading operations on the selected units; or provide multiple different voltage inputs to different rows of a column at the same time, and multiple current results are output at the same time;

[0011] The array test circuit board uses word lines WL and bit lines BL to control row and column signals of the electronic synapse array, and can select a designated unit of the electronic synapse array to switch between reading and writing;

[0012] The electronic synapse array is composed of a plurality of non-volatile, polymorphic artificial electronic synapse devices, which are connected to the word line WL driver and the bit line BL driver of the array test circuit board through a pin arrangement. The synapse receives an input signal from the array test circuit board, and the storage state of the corresponding unit synapse device is reflected by the readout signal.

[0013] Among them, the electronic synapse array is configured as a conductance matrix, the conductance value corresponds to the synaptic weight in the neural network, and the input voltage and output current correspond to the input and output in the neural network respectively; thereby mapping the multiplication and addition convolution operations of the convolution layer and the fully connected layer in the neural network to the operation of inputting different voltages and reading parallel currents of the electronic synapse array.

[0014] It can be seen from the technical solution provided by the present invention that the system gives full play to the programmable characteristics of the FPGA part of the SoC development board, and can apply positive pulses or negative pulses to selected devices of the electronic synapse array through the array test circuit board, with high reading and writing accuracy, thereby improving the flexibility of testing the electronic synapse array. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative work.

[0016] Figure 1 A schematic diagram of a neural network testing system based on an electronic synapse array provided in an embodiment of the present invention;

[0017] Figure 2 This is a schematic diagram of the principle of the biological neural synapse according to an embodiment of the present invention;

[0018] Figure 3 An architecture diagram of an electronic synapse array control system provided by an embodiment of the present invention;

[0019] Figure 4 A circuit schematic diagram of an array test circuit board according to an embodiment of the present invention;

[0020] Figure 5 This is a schematic diagram of the result of the electronic synapse array implementing the vector inner product described in Example 1 of the present invention;

[0021] Figure 6 This is a schematic diagram of the error distribution of the electronic synapse array implementing the vector inner product described in Example 1 of the present invention;

[0022] Figure 7 This is a schematic diagram of the result of image convolution operation performed by the electronic synapse array described in Example 2 of the present invention;

[0023] Figure 8 This is a schematic diagram of the structure of a small convolutional neural network provided in Example 3 of the present invention;

[0024] Fig. 9 Schematic diagram of the results of implementing small convolutional neural network reasoning using the electronic synapse array provided in Example 3 of the present invention. DETAILED DESCRIPTION

[0025] The following is a clear and complete description of the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments, which does not constitute a limitation of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0026] like Figure 1 The figure shows a schematic flow chart of a neural network test system based on an electronic synapse array provided by an embodiment of the present invention, wherein the system includes a control system, an array test circuit board and an electronic synapse array, wherein:

[0027] The control system is specifically a SoC development board including an ARM module and an FPGA module, which can reconfigurably write array test and calculation programs and exchange data with a computer (Personal Computer, PC) and an array test circuit board;

[0028] The control system is connected to the array test circuit board through an FPGA Mezzanine Card (FMC) interface and communicates using an Inter-Integrated Circuit (IIC) protocol;

[0029] The array test circuit board comprises an analog to digital / digital to analog converter (ADC / DAC) module and a multiplexer (MUX) module, which are connected to the electronic synapse array via a pin row;

[0030] The array test circuit board receives the command of the control system, and is used to select specific units or rows and columns in the electronic synapse array, and perform high-precision voltage writing and current reading operations on the selected units; or provide multiple different voltage inputs to different rows of a column at the same time, and output multiple current results at the same time; the pulse width and amplitude of the input voltage are set according to the device characteristics, and can be set to positive voltage or negative voltage; wherein the array test circuit board uses word lines WL (WordLine) and bit lines BL (Bit Line) to control the row and column signals of the electronic synapse array, and can select the specified unit of the electronic synapse array to switch between reading and writing;

[0031] The electronic synapse array is composed of a plurality of non-volatile, polymorphic artificial electronic synapse devices, which are formed into an array structure of m rows and n columns through a crossbar process, and are connected to the WL driver and BL driver of the array test circuit board through a pin header. The synapse receives an input signal from the array test circuit board, and the storage state of the corresponding unit synapse device is reflected by the readout signal;

[0032] The electronic synapse array is configured as a conductance matrix, the conductance value corresponds to the synaptic weight in the neural network, and the input voltage and output current correspond to the input and output in the neural network respectively; thereby mapping the multiplication and addition convolution operations of the convolutional layer (Convolutional Layer) and the fully-connected layer (Fully-Connected Layer) in the neural network to the operation of inputting different voltages and reading parallel currents of the electronic synapse array.

[0033] like Figure 2 The figure shows a schematic diagram of the principle of the biological neural synapse described in the embodiment of the present invention. The postsynaptic neuron is stimulated by several presynaptic neurons and integrates these signals until a certain threshold is reached to produce a response. The weight of the biological synapse connecting the pre- and post-neurons can be adjusted to affect the transmission of the above-mentioned stimulation signals and realize functions such as learning and recognition. The researchers imitated the structure of biological neural synapses to construct artificial electronic synaptic devices to achieve efficient and low-power in-memory computing. The device has the characteristics of non-volatility, polymorphism, programmability, and low energy consumption. In a specific implementation, the artificial electronic synaptic device may include a ferroelectric tunnel junction, a ferroelectric field effect transistor, a resistive memory based on oxygen vacancies or metal ion migration, a phase change memory, or a magnetic tunnel junction.

[0034] like Figure 3 The figure shows the architecture diagram of the electronic synapse array control system provided by the embodiment of the present invention. The control system is composed of a SoC development board and a PC. The ARM module of the SoC development board is used as a multi-interface processing system (PS), and the computer uses a universal asynchronous receiver / transmitter (UART) protocol to communicate. The program can be burned into the SoC development board and communicate with the SoC development board. The array storage information and processing results obtained by the interaction between the SoC development board and the array test circuit board are returned to the computer for monitoring by researchers. Researchers can dynamically write different bitstream files on the computer's Vitis platform and burn them into the SoC development board to achieve short-cycle program development and testing.

[0035] The Advanced eXtensible Interface (AXI) is used as the bus protocol for communication between the ARM module and the FPGA module, where:

[0036] The ARM module communicates with a general-purpose input / output (GPIO), an interrupt control module, a digital-to-analog conversion control module, and an analog-to-digital conversion control module of the array test circuit board through a bus interconnect (AXI Interconnect);

[0037] The universal input / output module is used to control the MUX module in the array test circuit board, and controls the rows and columns of the array test circuit board to access the active channel, the inactive channel or the ground by setting the values ​​of the word line write WL_WR, the bit line write BL_WR and the bit line read BL_RD;

[0038] The digital-to-analog conversion control module and the analog-to-digital conversion control module are used to control the read and write operations of the electronic synapse array, set the initial and final values ​​of the input voltage and pulse width of each row of the digital-to-analog conversion module; receive the output value of each column of the analog-to-digital conversion module and return it to the SoC development board and the computer.

[0039] like Figure 4 The circuit schematic diagram of the array test circuit board according to the embodiment of the present invention is shown. The intersections of multiple artificial synaptic devices constitute an electronic synaptic array of at most 10×10, which is connected to the corresponding nodes WL and BL of the array test circuit board through pins; the conductance value of the electronic synaptic device located in the i-th row and j-th column is marked as G i,j ; Applying a read voltage pulse to the array test circuit board can obtain the conductivity value of the device at the specified position; applying a write voltage pulse can adjust the conductivity value, thereby realizing non-volatile storage of the electronic synapse array. In a specific implementation, the digital-to-analog conversion module DAC of the array test circuit board converts the discrete DAC code into an analog voltage input, which reaches the specified row of the array through a potentiometer (RP) and a row selection, and the device current reaches the analog-to-digital conversion module ADC after a column selection, and the analog voltage is read out in a discrete ADC code, thereby reflecting the current of the corresponding column, wherein:

[0040] The row selection is a two-way selector. When the selector is set to "0", the row is connected to the active channel of the word line WL; when the selector is set to "1", the row is connected to the inactive channel of the word line WL;

[0041] The column selection is a three-way selector. When the selector is set to "0", the column is connected to the inactive channel of the bit line BL; when the selector is set to "1", the column is grounded; when the selector is set to "2", the column is connected to the bit line BL channel of the corresponding sequence number;

[0042] The purpose of adopting active and inactive channel design is: when erasing a single device in a specified row or column, the electronic synaptic device is operated by connecting one row to the active channel to apply a write voltage V, one column to ground, and the remaining rows and columns to the inactive channel to apply V / 2 or V / 3, thereby reducing the impact of crosstalk in the array circuit;

[0043] The column current is read by transimpedance amplification. Under the premise that the column select is set to "2", the column current is first connected to the operational amplifier (OPA) and then through the feedback resistor R F The current is converted into voltage and read by the analog-to-digital conversion module ADC after passing through a low-pass filter (LPF). The current value is determined by the ADC reading value and the feedback resistor R F The ratio is obtained;

[0044] Therefore, the relationship between the semaphores is:

[0045] I j =Σ i G ij ×V i (1)

[0046] V j (ADC) = R F ×I j (2)

[0047] Among them, I j is the column current of the j-th bit line; G ij is the conductance of the electronic synaptic device at the intersection of the i-th row and the j-th column in the array; V i is the row voltage of the i-th row word line; V j (ADC) is the voltage value read by the ADC corresponding to the j-th column bit line; R F is the feedback resistor used by the transimpedance amplifier circuit corresponding to the j-th column bit line.

[0048] In the specific implementation, the clock frequency is set in the ARM module, and three different clock frequencies are generated through the clock multiplication (Clocking Wizard), which are used as the bus frequency, DAC frequency and ADC frequency respectively. Specifically, in this embodiment, they are 100 MHz, 48 MHz and 24 MHz.

[0049] The unit device of the electronic synapse array performs conductivity control by inputting a write voltage pulse, and the current conductivity state of the device is measured by inputting a read voltage pulse and reading the output current.

[0050] In addition, the indicators of the array test circuit board include:

[0051] The voltage pulse width provided by the digital-to-analog conversion module DAC is at least 500ns, and the maximum amplitude of each pulse voltage is ±10V; the voltage accuracy is better than 10mV; the maximum current that each channel can provide is 60mA;

[0052] The accuracy of voltage reading is better than 1mV; the accuracy of current reading is better than 1nA; the upper limit of single-channel reading current is 3.3mA; the feedback resistor R F When taking 1kΩ and 1MΩ, read the mA current and μA current respectively.

[0053] It is worth noting that the contents not described in detail in the embodiments of the present invention belong to the prior art known to professional and technical personnel in the field.

[0054] To verify the capabilities of the synaptic array test, the following specific examples are tested:

[0055] Example 1. This example tests an electronic synapse array constructed by a ferroelectric tunnel junction (FTJ), and uses it to implement the inner product calculation of two vectors (each containing 9 components). The 9 components of one vector are the conductance values ​​of 9 FTJ synapses in a column in the FTJ synapse array, which are written as different set values ​​through the circuit board. The 9 components of the other vector are represented by different read voltages applied by 9 channels, and a total of 84 different read voltage vectors are generated for testing.

[0056] Specifically, in the test circuit board of this embodiment, in view of the transport characteristics of FTJ (selecting the linear volt-ampere characteristic region in the low-voltage region), the amplitude range of the read voltage applied to each row is set to be between -0.1V and +0.1V; the division value of the DAC of this test board is 1.22mV, so the voltage range corresponds to the DAC encoding range of 8110 (corresponding to the voltage amplitude of -100.04mV) to 8274 (corresponding to the voltage amplitude of 100.04mV). 9 random integers ranging from 8110 to 8274 are generated in the SoC development board, and their amplitudes are assigned to the DACs of the 9 channels of the array test circuit board, thereby generating a read voltage pulse on the corresponding WL (for example, when the DAC encoding is 8205, the corresponding voltage amplitude is 15.86mV); 9 read voltages are simultaneously applied to 9 FTJ synapses in one column of the FTJ synapse array; the current on the BL corresponding to the FTJ synapse in this column is read by the corresponding ADC and converted into ADC encoding.

[0057] The array test circuit board then returns the ADC code collected on the BL to the SoC development board and the computer, and the measured current value is converted by the above formula (2). The measured current value and the theoretical current value calculated by Ohm's law and Kirchhoff's law are used as the vertical axis and horizontal axis respectively, as shown in Figure 5 FIG. 1 is a schematic diagram showing the results of the electronic synapse array implementing the vector inner product described in Example 1 of the present invention. The results of 84 sets of vector inner products are compared and the relative standard error is calculated. Figure 6 The figure shows a schematic diagram of the error distribution of the electronic synapse array implementing the vector inner product described in Example 1 of the present invention.

[0058] from Figure 5 , Figure 6 It can be seen that under the control of this system, the electronic synapse array completes the vector inner product operation, and the standard deviation of the relative error is only 2.24%, indicating that the vector inner product operation performed by the electronic synapse array has high accuracy.

[0059] Example 2: The synaptic array is applied to image processing. The specific task is to perform gradient operation on the input grayscale image to achieve edge extraction or sharpening of the image.

[0060] like Figure 7 FIG. 1 is a schematic diagram showing the result of image convolution operation performed by the electronic synapse array described in Example 2 of the present invention. Three image processing operators are selected, of which the first two are 2×2 Roberts operators in the 45° direction and the 135° direction (corresponding to the two diagonals of the image). Figure 7 The three operators are marked as Roberts (+) and Roberts (-) respectively, and the third one is a 3×3 sharpening operator. These operators process the grayscale image as follows:

[0061] In terms of storage form, a grayscale image is composed of a pixel matrix, and the grayscale value of each pixel is an integer between 0 and 255; the matrix operator is slid on the pixel matrix, and for each pixel, the pixel block containing the current pixel and the same size as the operator is multiplied and added with the operator, that is, each grayscale value in the pixel block is multiplied with the matrix element at the corresponding position of the operator and then summed.

[0062] When the synaptic array is used to process this task, since the operator involves negative numbers and the device conductance value can only be positive numbers, this embodiment adopts a translation and scaling mapping method to map the matrix element value range of the operator to the variation range of the device conductance value, and completes the translation operation by adding a bias column. The specific mapping method is as follows:

[0063]

[0064] Among them, W and G are the matrix element of the operator and the device conductivity value after mapping, respectively. The value range of W is from -W max To W max The symmetric range of G is the minimum conductance value G of the device. min and the maximum conductance G max between.

[0065] In this mapping method, the voltage result read by the ADC should be transformed as follows:

[0066] V j ′=V j (ADC)×2-V bias (ADC) (4)

[0067] Among them, V j (ADC) is the same as that described in formula (2), and is the voltage value read by the ADC corresponding to the j-th column bit line; V bias (ADC) is the voltage value read by the bias column, which is obtained by passing the same row voltage through a column with a fixed conductivity value of G min +G max The voltage value read after the conductivity is j 'Multiply by the coefficient W max / (G max -G min ) is the final result of the operation.

[0068] Based on the above solution, a program is written on the Vitis platform to control the synaptic array constructed by FTJ to perform image processing with storage and computing. The processing results of the three operators are as follows: Figure 7 As shown in the figure, it can be seen that for the input grayscale image with diamond pattern, the two Roberts operators correctly output the diagonal edges in the directions of 45° and 135°, and the sharpening operator correctly outputs the sharpening result of the image.

[0069] Example 3: After the electronic synapse array and its control and test system described in this application are built, the synapse array is applied to a convolutional neural network. The specific task is to achieve ten-class recognition of numbers 0 to 9 through the reasoning operation of the convolutional neural network, such as Figure 8 The diagram is a schematic diagram of the structure of a small convolutional neural network provided in Example 3 of the present invention. The operations performed by each layer of the network are as follows:

[0070] The first part is a downsampling process, which reduces the original size of 28×28 to 15×15 through pooling operation; followed by two convolutional layers, which transform the size of the feature map to 7×7 and 3×3 respectively; followed by a flattening layer and two fully connected layers: 10 feature maps of size 3×3 are flattened into a one-dimensional vector of 90×1, and the size of the two fully connected layers is 90×10×10. The second fully connected layer outputs a 10×1 vector, and the classification of the input image is determined according to the maximum value in the vector, realizing the task of classifying images of the MNIST (Modified National Institute of Standards and Technology) handwritten digit dataset from 0 to 90 points.

[0071] Based on the network structure described above, a convolutional neural network program is written on the Vitis platform to complete the following functions: first, the device conductance is adjusted to the target conductance corresponding to the convolution kernel weight, and then the array test circuit board is ordered to generate a row voltage pulse corresponding to the convolution input. According to the scheme described in the embodiment of the present invention, the result of the convolution operation is obtained and combined with other parts of the network, and finally the recognition result of the input digital image is given on the computer.

[0072] The first layer of convolution operations is implemented on the synaptic array built in this example, and the remaining layers are calculated by the FPGA module based on the device conductance data.

[0073] Run the program to identify all images in the MNIST dataset, and then Fig. 9 The figure shows the result of implementing the small convolutional neural network reasoning using the electronic synapse array provided in Example 3 of the present invention, where the horizontal axis and the vertical axis represent the predicted value (Predicted Label) and the true value (True Label), respectively. The statistical accuracy of recognizing 10,000 test images is 92.53%; while the recognition accuracy of the same LeNet network using floating-point operations on the CPU is 93.87%. Therefore, the reasoning results of the convolutional neural network using in-memory calculations in this embodiment are relatively accurate.

[0074] It is worth noting that, according to calculations, the in-memory calculation method of this embodiment significantly reduces power consumption and significantly improves energy efficiency compared to the method of performing floating-point operations in the CPU.

[0075] In summary, based on the test system of the embodiment of the present invention, researchers can obtain the test data of the synaptic array and the neural network calculation results on the computer in a simple and intuitive manner, and can reduce the test cycle of the synaptic array through dynamic repeated programming, which is helpful to explore the potential of electronic synaptic devices to realize neural network intelligent computing at the hardware level, accelerate the development of electronic synaptic devices and their arrays that meet the requirements of artificial intelligence computing in the Internet of Things, and provide strong support for the research of brain-like devices and artificial intelligence.

[0076] In addition, a person skilled in the art can understand that all or part of the steps in the above-mentioned embodiment method can be implemented by instructing related hardware through a program, and the corresponding program can be stored in a computer-readable storage medium. The above-mentioned storage medium can be a read-only memory, a disk or an optical disk, etc.

[0077] The above is only a preferred specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by any technician familiar with the technical field within the technical scope disclosed in the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims. The information disclosed in the background technology section of this article is only intended to deepen the understanding of the overall background technology of the present invention, and should not be regarded as an admission or in any form that the information constitutes prior art known to those skilled in the art.

Claims

1. A neural network testing system based on an electronic synapse array, characterized in that: The system comprises a control system, an array test circuit board and an electronic synapse array, wherein: The control system is specifically a SoC development board including an ARM module and an FPGA module, which can reconfigurably write array test and in-memory computing programs and exchange data with a computer and an array test circuit board; The control system is connected to the array test circuit board and communicates with the internal integrated circuit IIC protocol through the FPGA middle layer board interface; The array test circuit board comprises an analog-to-digital / digital-to-analog conversion module and a multiplexer MUX module, which are connected to the electronic synapse array via a pin header; The array test circuit board receives the command of the control system, and is used to select specific units or rows and columns in the electronic synapse array, and perform high-precision voltage writing and current reading operations on the selected units; or provide multiple different voltage inputs to different rows of a column at the same time, and multiple current results are output at the same time; The array test circuit board uses word lines WL and bit lines BL to control row and column signals of the electronic synapse array, and can select a designated unit of the electronic synapse array to switch between reading and writing; The electronic synapse array is composed of a plurality of non-volatile, polymorphic artificial electronic synapse devices, which are connected to the word line WL driver and the bit line BL driver of the array test circuit board through a pin arrangement. The synapse receives an input signal from the array test circuit board, and the storage state of the corresponding unit synapse device is reflected by the readout signal. Among them, the electronic synapse array is configured as a conductance matrix, the conductance value corresponds to the synaptic weight in the neural network, and the input voltage and output current correspond to the input and output in the neural network respectively; thereby mapping the multiplication and addition convolution operations of the convolution layer and the fully connected layer in the neural network to the operation of inputting different voltages and reading parallel currents of the electronic synapse array.

2. The neural network testing system based on electronic synapse array according to claim 1, characterized in that: The computer and the ARM module communicate using the Universal Asynchronous Receiver / Transmitter (UART) protocol, which can burn the program into the SoC development board and communicate with the SoC development board. The array storage information and processing results obtained by the interaction between the SoC development board and the array test circuit board are returned to the computer for researchers to monitor.

3. The neural network testing system based on electronic synapse array according to claim 1, characterized in that: The ARM module and the FPGA module use an advanced extensible interface as a bus protocol for communication, where: The ARM module communicates with the general input / output module, the interrupt control module, the digital-to-analog conversion control module, and the analog-to-digital conversion control module of the array test circuit board through bus interconnection; The general input / output module is used to control the MUX module in the array test circuit board, and controls the rows and columns of the array test circuit board to access the activation channel, the inactivation channel or the ground by setting the values ​​of the word line write WL_WR, the bit line write BL_WR and the bit line read BL_RD; The digital-to-analog conversion control module and the analog-to-digital conversion control module are used to control the read and write operations of the electronic synapse array, set the initial and final values ​​of the input voltage and pulse width of each row of the digital-to-analog conversion module; receive the output value of each column of the analog-to-digital conversion module and return it to the SoC development board and the computer.

4. The neural network testing system based on electronic synapse array according to claim 1, characterized in that: The digital-to-analog conversion module DAC of the array test circuit board converts the discrete DAC code into an analog voltage input, which reaches the specified row of the array through the potentiometer and the row strobe. The device current reaches the analog-to-digital conversion module ADC after the column strobe, and the analog voltage is read out in the discrete ADC code, thereby reflecting the current of the corresponding column, wherein: The row selection is a two-way selector. When the selector is set to "0", the row is connected to the active channel of the corresponding number of the word line WL; when the selector is set to "1", the row is connected to the inactive channel of the word line WL; The column selection is a three-way selector. When the selector is set to "0", the column is connected to the inactive channel of the bit line BL; when the selector is set to "1", the column is grounded; when the selector is set to "2", the column is connected to the bit line BL channel of the corresponding sequence number; The purpose of adopting active and inactive channel design is: when erasing a single device in a specified row or column, the electronic synaptic device is operated by connecting one row to the active channel to apply a write voltage V, one column to ground, and the remaining rows and columns to the inactive channel to apply V / 2 or V / 3, thereby reducing the impact of crosstalk in the array circuit; The column current is read by transimpedance amplification. When the column select is set to "2", the column current is first connected to the operational amplifier OPA and then to the feedback resistor R F Converted into voltage, it is read by the analog-to-digital conversion module ADC after passing through the low-pass filter LPF. The current value is determined by the ADC reading value and the feedback resistor R F The ratio is obtained; Therefore, the relationship between the semaphores is: I j =∑ i G ij ×V i (1) V j (ADC)=R F ×I j (2) Among them, I j is the column current of the j-th bit line; G ij is the conductance of the electronic synaptic device at the intersection of the i-th row and the j-th column in the array; V i is the row voltage of the i-th row word line; V j (ADC) is the voltage value read by the ADC corresponding to the j-th column bit line; R F is the feedback resistor used by the transimpedance amplifier circuit corresponding to the j-th column bit line.

5. The neural network testing system based on electronic synapse array according to claim 1, characterized in that: The clock frequency is set in the ARM module, and three different clock frequencies are generated by clock multiplication, which are used as bus frequency, DAC frequency and ADC frequency respectively.

6. The neural network testing system based on electronic synapse array according to claim 1, characterized in that: The unit device of the electronic synapse array performs conductivity control by inputting a write voltage pulse, and the current conductivity state of the device is measured by inputting a read voltage pulse and reading the output current.

7. The neural network testing system based on electronic synapse array according to claim 1, characterized in that: The indicators of the array test circuit board include: The voltage pulse width provided by the digital-to-analog conversion module DAC is at least 500ns, and the maximum amplitude of each pulse voltage is ±10V; the voltage accuracy is better than 10mV; the maximum current that each channel can provide is 60mA; The accuracy of voltage reading is better than 1mV; the accuracy of current reading is better than 1nA; the upper limit of single-channel reading current is 3.3mA; the feedback resistor R F Take 1kΩ and 1MΩ, and read the mA current and μA current respectively.

8. The neural network testing system based on electronic synapse array according to claim 1, characterized in that: The artificial electronic synaptic device includes a ferroelectric tunnel junction, a ferroelectric field effect transistor, a resistive memory based on oxygen vacancies or metal ion migration, a phase change memory or a magnetic tunnel junction.

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