Pixel array circuit and micro-display integrated circuit

Abstract

The invention discloses a pixel array circuit and a micro-display integrated circuit, and the pixel array circuit comprises a plurality of main pixel circuits and sub-pixel circuits which are arranged in a crossed manner. The main light-emitting control unit of each main pixel circuit generates a main current driving signal according to a pixel circuit driving voltage signal input by the switch storage unit so as to drive a corresponding light-emitting device; each sub-pixel circuit comprises a light-emitting device and N sub light-emitting control units electrically connected with the light-emitting device; the N sub light-emitting control units in each sub pixel circuit are respectively connected with the switch storage units in the N main pixel circuits, and the N sub light-emitting control units of each sub pixel circuit are configured to respectively generate N sub current driving signals under the control of sampling voltage input by the switch storage units in the N connected main pixel circuits, and the N sub-current driving signals jointly drive the corresponding light-emitting device. More pixel circuits are integrated in the same chip area, the resolution ratio is high, the power is low, and the luminance consistency is high.

Description

Technical Field

[0001] The present invention belongs to the field of micro-display technology, and relates to a high-resolution display circuit, and in particular to a pixel array circuit, a micro-display integrated circuit and a display chip. Background Art

[0002] Silicon-based microdisplay technology is an emerging display technology that cleverly combines semiconductor CMOS technology with display technology. It can achieve high-resolution display in a tiny space, and is used to meet the near-eye display requirements of new electronic technologies such as augmented reality / virtual reality / fused reality. This display has completed the drive circuit and light-emitting display materials on a single-crystal silicon CMOS substrate, and then amplifies the image information through a suitable optical engine system. It is not only used in a wide range of fields such as military applications, aerospace, automotive assisted driving, industrial electronics, etc., but has also begun to be applied to consumer electronics in recent years.

[0003] At present, micro display technologies mainly include high temperature polysilicon liquid crystal display technology (HTPS-LCD), silicon-based reflective liquid crystal display technology (LCOS), silicon-based OLED display technology (Micro OLED) and silicon-based LED display technology (Micro LED). Among them, OLED display technology has many advantages such as low power consumption, high color gamut, high contrast and fast response speed. Micro OLED micro display chip is an active organic light-emitting diode display device made by combining CMOS process and OLED technology and using single crystal silicon as active driver chip.

[0004] Currently common display devices include active light-emitting devices (OLED, LED, etc.) and passive light-emitting devices (LCOS, DMD, etc.). Active light-emitting devices such as OLED and LED have the advantages of low power consumption, high contrast, high brightness and fast response speed. Therefore, they are more suitable for application in technologies such as AR, VR and projection products.

[0005] Usually micro display chips consist of a certain number of row / column arrays of single pixel circuits, such as Figure 1 As shown, a certain resolution is achieved by sharing row / column data signals. The actual resolution is the product of the number of row and column pixel circuits. Figure 2 An existing pixel driving circuit is provided. Usually, each pixel circuit includes a switch MOSFET (NM1) for receiving row / column information of an image. A voltage storage unit (C1) completes the storage of a voltage signal after sampling by NM1. A light emitting control unit (PM1) converts the voltage value stored in the voltage storage unit into a current to drive a light emitting device (D1) to work. Within a certain current range, the display brightness of the light emitting device is proportional to the current.

[0006] In recent years, with the continuous development of display products such as AR, VR and projection products, micro-display chips are required to achieve higher resolution and lower power consumption in a smaller area, that is, more pixel circuits can be integrated in the same chip area. Since each pixel unit circuit in the existing pixel circuit contains a switch and a voltage memory, especially the voltage memory occupies more chip resources. If the voltage memory uses a MOS tube to form a capacitor, it will directly occupy the pixel area; if the voltage memory uses a MIM (metal layer-dielectric layer-metal layer) capacitor, since it is placed above the MOS tube, it does not occupy the placement area of ​​the MOS tube, but it will occupy the resources of the metal routing layer, which will also increase the resource consumption of the chip (such as more metal layers are needed to connect the signals in the pixel area, etc.), so it becomes difficult to integrate more pixel circuits in the same chip area. Summary of the invention

[0007] The technical problem to be solved by the present invention is that the pixel circuits in the existing display circuits all use MOS tubes and voltage memories, which occupy a large area of ​​the pixel circuits, especially the voltage memory occupies more chip resources. Too many MOS tubes and voltage memories make it difficult to integrate more pixel circuits under the same chip area, and it is difficult to further improve the resolution; on the other hand, the logical operation and driving of the chip circuit generate more power consumption, which cannot meet the requirements for the micro display chip.

[0008] In order to solve the above problems, the technical solution adopted by the present invention is: a pixel array circuit, comprising a plurality of cross-arranged main pixel circuits and sub-pixel circuits;

[0009] Each main pixel circuit includes a switch storage unit, a main light emitting control unit connected to the switch storage unit, and a light emitting device; the switch storage unit is configured to perform voltage sampling and storage on the image data signal, and input the sampled voltage to the main light emitting control unit, and the main light emitting control unit is configured to generate a main current driving signal under the control of the sampled voltage input by the switch storage unit to drive the corresponding light emitting device;

[0010] Each sub-pixel circuit includes a light-emitting device and N sub-light-emitting control units electrically connected to the light-emitting device; the N sub-light-emitting control units in each sub-pixel circuit are respectively connected to the switch storage units in the N main pixel circuits, and the N sub-light-emitting control units in each sub-pixel circuit are configured to generate N sub-current drive signals respectively under the control of the sampling voltage input by the switch storage units in the connected N main pixel circuits, and the N sub-current drive signals jointly drive the corresponding light-emitting devices.

[0011] As a preferred solution of the present invention, the magnitude of the current driving signal generated by each sub-light emitting control unit of the sub-pixel circuit is configured to be no higher than 1 / N of the magnitude of the current driving signal generated by the main light emitting control unit in the main pixel circuit connected thereto.

[0012] As a preferred solution of the present invention, each sub-light-emitting control unit in each sub-pixel circuit is composed of N third MOS tubes with the same specifications and parameters connected in series and the gates of the N third MOS tubes are connected, and the main light-emitting control unit in each main pixel circuit is composed of a second MOS tube with the same specifications and parameters as the third MOS tube, so as to achieve the goal that under the control of the sampling voltage input by the switch storage unit of a main pixel circuit, the current driving signal size ratio generated by the sub-light-emitting control unit connected to the switch storage unit and the main light-emitting control unit is configured to be 1:N.

[0013] As a preferred solution of the present invention, each sub-pixel circuit includes a light-emitting device and two sub-light-emitting control units electrically connected to the light-emitting device, each sub-light-emitting control unit in each sub-pixel circuit is composed of two third MOS tubes with the same specifications and parameters connected in series and the gates of the two third MOS tubes are connected, and the main light-emitting control unit in each main pixel circuit is composed of a second MOS tube with the same specifications and parameters as the third MOS tube, so as to achieve the goal that under the control of the sampling voltage input by the switch storage unit of a main pixel circuit, the current driving signal size ratio generated by the sub-light-emitting control unit connected to the switch storage unit and the main light-emitting control unit is configured to be 1:2.

[0014] As a preferred solution of the present invention, the switch storage unit includes a data writing unit and a voltage storage unit, the data writing unit is composed of a first MOS tube, and the voltage storage unit is composed of a voltage capacitor; the gate of the first MOS tube is used to receive a scanning signal, the first electrode of the first MOS tube is used to receive an image data signal, the second electrode of the first MOS tube is used to perform voltage sampling on the image data signal according to the scanning signal, and is connected to the voltage storage unit, and the voltage storage unit is used to store the sampling voltage and input the sampling voltage to the control end of the main light-emitting control unit and the control end of the sub-light-emitting control unit connected thereto. This structure is simple, easy to control, and the area of ​​the main pixel circuit is relatively large.

[0015] As a preferred solution of the present invention, the switch storage unit includes a data writing unit and a voltage storage unit, the data writing unit is composed of two N-type MOS tubes, and the voltage storage unit is composed of two inverters, the input end of the first inverter is connected to the output end of the second inverter, and the input end of the second inverter is connected to the output end of the first inverter; each inverter is composed of a P-type MOS tube and an N-type MOS tube connected in series, and the control ends of the two inverters are respectively connected to the two N-type MOS tubes of the data writing unit, and the control end of each inverter is connected to the phase connection point in the other inverter, and the control end of one of the inverters is connected to the control end of the main light-emitting control unit and the sub-light-emitting control unit, replacing the capacitor to store the sampling voltage.

[0016] As a preferred solution of the present invention, the sub-pixel circuits are distributed in the left-right direction or the up-down direction of the main pixel circuit.

[0017] A micro display integrated circuit comprises the above-mentioned pixel array circuit and a data storage driving unit, wherein the data storage driving unit is electrically connected to a switch storage unit in a main pixel circuit, and is used to receive image row / column information data and perform analytical operations on the data, and to generate and output a pixel circuit driving voltage signal to the switch storage unit.

[0018] As a preferred solution of the present invention, the data storage driving unit includes a column signal storage driving unit, a row signal storage driving unit and a data processing unit. After receiving the image data outside the chip, the data processing unit performs compression, analysis, reorganization and other conventional technical algorithm processing, and then parses the original graphic image data into row signals and column signals corresponding to the pixel array circuit, and sends them to the row signal storage driving unit and the column signal storage driving unit respectively. After the row signal storage driving unit and the column signal storage driving unit perform storage and analysis operations on the received row signals, they are output to the switch storage units of the corresponding rows of the pixel array circuit through the scan lines and data lines respectively.

[0019] Compared with the prior art, the present invention has the following beneficial effects:

[0020] 1. The switch storage unit of the present invention includes a voltage storage unit. The circuit area of ​​the pixel circuit occupied by the switch storage unit is much larger than the area occupied by the light-emitting control unit and the light-emitting device. The sub-pixel circuit reuses the switch storage unit of the main pixel circuit, which can reduce the number of switch storage units in the pixel array circuit. Even when the number of sub-light-emitting control units in the sub-pixel circuit is increased, the reduction in the number of switch storage units will greatly reduce the area of ​​the entire pixel array circuit. Fewer row and column signal lines will also reduce the area of ​​the entire pixel array circuit, that is, more pixel circuits can be integrated within the same chip area, thereby improving the resolution of the pixel array circuit.

[0021] 2. The sub-pixel circuit of the present invention reuses the switch storage unit of the main pixel circuit. When the number of pixels in the entire pixel array circuit is the same, the pixel array circuit of the present invention reduces the number of switch storage units, reduces the number of row and column drivers and the number of row and column signal line wiring requirements, and significantly reduces the logical operation amount of the data storage drive unit and the output amount of the drive signal, thereby reducing the power consumption of the data storage drive unit and achieving a reduction in the power consumption of the micro-display integrated circuit.

[0022] 3. In the present invention, a sub-pixel circuit reuses the switch storage unit of the main pixel circuit, and the sub-light-emitting control units in the sub-pixel circuit are all controlled by the reused switch storage unit. The light-emitting devices of the sub-pixel circuit are jointly acted upon by N driving currents, which may lead to poor consistency in the light-emitting brightness of the pixel array circuit. Therefore, under the control of the sampling voltage input by the switch storage unit of a main pixel circuit, the current driving signals respectively generated by the sub-light-emitting control unit and the main light-emitting control unit connected to the switch storage unit are configured to have a size ratio of 1:N, so as to ensure that the light-emitting brightness of the light-emitting device of the sub-pixel circuit is between the light-emitting brightness of all the main pixel circuits connected thereto, thereby ensuring that the pixel array circuit has a high light-emitting brightness consistency. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions and advantages in the embodiments of the present invention or the prior art, the drawings required for use in the embodiments or the prior art descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0024] Figure 1 It is a structural schematic diagram of an existing pixel array circuit;

[0025] Figure 2 is a circuit structure diagram of an existing single pixel circuit;

[0026] Figure 3 is a first structural diagram of a pixel array circuit in the present invention;

[0027] Figure 4 A partial diagram of a first structural diagram of a pixel array circuit in the present invention;

[0028] Figure 5 A first circuit diagram corresponding to the first pixel array circuit structure diagram of the present invention;

[0029] Figure 6 A second circuit diagram corresponding to the first pixel array circuit structure diagram of the present invention;

[0030] Figure 7The second circuit corresponding to the first pixel array circuit structure diagram of the present invention corresponds to the pulse modulation control timing diagram;

[0031] Figure 8 is a second structural diagram of the pixel array circuit in the present invention;

[0032] Fig. 9 A circuit diagram corresponding to the second pixel array circuit structure diagram in the present invention;

[0033] Fig.10 It is a structural diagram of the micro display integrated circuit of the present invention.

[0034] In the figure, there are a data storage driving unit 101, a switch storage unit 102, a main light emitting control unit 103 and a sub-light emitting control unit 104. DETAILED DESCRIPTION

[0035] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments.

[0036] In the following, the terms "second", "first", "third", etc. are used only for convenience of description and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, a feature defined as "second", "first", "third", etc. may explicitly or implicitly include one or more of the feature. In the description of this application, unless otherwise specified, "plurality" means two or more.

[0037] In addition, in the embodiments of the present application, directional terms such as "up", "down", "left" and "right" may be defined including but not limited to the orientation relative to the schematic placement of the components in the drawings. It should be understood that these directional terms may be relative concepts, which are used for relative description and clarification, and may change accordingly according to changes in the orientation of the components in the drawings.

[0038] In the embodiments of the present application, unless otherwise clearly specified or limited, the term "connection" should be understood in a broad sense.

[0039] For example, "connection" can be a fixed connection or a detachable connection, a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium. In addition, the term "coupled" can be a direct electrical connection or an indirect electrical connection through an intermediate medium. The term "contact" can be a direct contact or an indirect contact through an intermediate medium.

[0040] The terms "coupling" and "coupling" involved in the embodiments of the present application should be understood in a broad sense. For example, they may refer to a direct physical connection, or an indirect connection achieved through electronic devices, such as a connection achieved through resistors, inductors, capacitors or other electronic devices.

[0041] like Figure 1 The existing pixel array circuit is formed by arranging multiple pixel circuits in a matrix manner. Each pixel circuit is connected to the power supply terminal ELVDD and the common terminal ELVSS, so that the pixel circuit obtains power. At the same time, each pixel circuit is coupled to the row driver and the column driver. Under the action of the row driver voltage signal ROW_W and the column driver voltage signal COL_W, the pixel circuit can realize light emission control. Multiple pixel circuits share row / column data signals to realize a certain resolution of the pixel array circuit. The actual resolution size is the product of the number of row and column pixel circuits (MxN). The more row and column pixel circuits integrated per unit chip area, the higher the resolution.

[0042] The pixel circuits in the existing pixel array circuits all include a switch storage unit, a light-emitting control unit and a light-emitting device. The switch storage unit provides a driving voltage signal to the light-emitting control unit. The light-emitting control unit generates a current driving signal under the control of the driving voltage signal. The current driving signal flows through the light-emitting device, thereby driving the light-emitting device to emit light.

[0043] The light emitting device generally adopts a light emitting diode (LED for short), and an OLED may also be adopted. Active light emitting devices such as OLED and LED have the advantages of low power consumption, high contrast, high brightness and fast response speed.

[0044] A pixel circuit may contain one light-emitting diode or multiple light-emitting diodes. For example, the pixel written in some display screen design plans is: 2R1G1B, which means that the smallest imaging unit of the display screen is composed of 2 red light-emitting tubes, 1 green light-emitting tube, and 1 blue light-emitting diode (in the display screen industry, red, green, and blue light-emitting diodes are usually replaced by their English letters, R, G, and B).

[0045] The core part of the light-emitting diode is a wafer composed of a P-type semiconductor and an N-type semiconductor. There is a transition layer between the P-type semiconductor and the N-type semiconductor, which is called a PN junction. In the PN junction of some semiconductor materials, when the injected minority carriers recombine with the majority carriers, the excess energy will be released in the form of light, thereby directly converting electrical energy into light energy. When a reverse voltage is applied to the PN junction, it is difficult for minority carriers to be injected, so no light is emitted. When a forward voltage is applied to the light-emitting diode, the holes injected from the P region into the N region and the electrons injected from the N region into the P region recombine with the electrons in the N region and the holes in the P region within a few microns near the PN junction of the light-emitting diode, respectively, to produce spontaneously radiated fluorescence. The energy states of electrons and holes in different semiconductor materials are different. When electrons and holes recombine, the amount of energy released is different. The more energy released, the shorter the wavelength of the emitted light. Commonly used are light-emitting diodes that emit red, green or yellow light.

[0046] When it is in the forward working state (i.e., a forward voltage is applied to both ends), when the current flows from the LED anode to the cathode, the semiconductor crystal emits light of different colors from ultraviolet to infrared. The intensity of the LED light is positively correlated with the size of the driving current, that is, the greater the driving current, the higher the light intensity emitted by the LED.

[0047] like Figure 2 The switch storage unit of the existing pixel circuit includes a MOS tube NM1 and a capacitor C1. The gate of the MOS tube NM1 is connected to the row driving voltage signal ROW_W, the source of the MOS tube NM1 is connected to the driving voltage signal COL_W, the drain of the MOS tube NM1 is connected to one end of the capacitor C1, and the other end of the capacitor C1 is connected to the common end ELVSS. Under the action of the row driving voltage signal ROW_W and the column driving voltage signal COL_W, the MOS tube NM1 of each pixel circuit is in a conducting state in the data writing stage, so as to receive the image data signal according to the scanning signal and perform voltage sampling on the image data signal. The capacitor C1 stores the voltage sampled by the MOS tube NM1. The light emitting control unit PM1 generates a current driving signal under the control of the sampling voltage input by the switch storage unit to drive the light emitting device D1 to work. The light emitting device D1 is an LED.

[0048] Since MOS tubes and capacitors occupy more resources of the pixel circuit, especially capacitors occupy more chip resources, the large number of MOS tubes and capacitors makes it difficult to integrate more pixel circuits in the same chip area, and the resolution is difficult to further improve; on the other hand, since all pixel circuits on M rows and N columns need to be controlled by the data storage driving unit, the data storage driving unit needs to perform logical operations on the control voltages required by all pixel circuits to generate control voltages and output them to each pixel circuit, which causes the logical operations and driving of the chip circuit to generate more power consumption, and cannot meet the low power consumption requirements of the micro display chip.

[0049] Embodiment 1, based on this, refer to Figure 3 and Figure 4 This embodiment provides a pixel array circuit, including a plurality of main pixel circuits and sub-pixel circuits arranged crosswise; each main pixel circuit includes a switch storage unit 102, a main light-emitting control unit 103 connected to the switch storage unit 102, and a light-emitting device, and each sub-pixel circuit includes a light-emitting device and two sub-light-emitting control units 104 electrically connected to the light-emitting device; the main pixel circuits and the sub-pixel circuits are crosswise arranged to form a pixel array circuit with M rows and N columns.

[0050] The main pixel circuit and the sub-pixel circuit are arranged crosswise in the form of: a sub-pixel circuit is disposed adjacent to each main pixel circuit on the left and right, and a main pixel circuit is disposed adjacent to each sub-pixel circuit on the left and right.

[0051] In this embodiment, specifically, each main pixel circuit includes a switch storage unit 102, a main light emitting control unit 103 connected to the switch storage unit 102, and a light emitting device; the switch storage unit 102 is configured to perform voltage sampling and storage on the image data signal, and input the sampled voltage to the main light emitting control unit 103, and the main light emitting control unit 103 is configured to generate a main current driving signal to drive the corresponding light emitting device under the control of the sampled voltage input by the switch storage unit 102. The output end of the main light emitting control unit 103 is connected to the positive electrode of the light emitting device, the input end of the main light emitting control unit 103 is connected to the power supply, and the negative electrode of the light emitting device is connected to the common end; the switch storage unit 102 is respectively connected to the scan line and the data line.

[0052] The main pixel circuit may include a data writing stage during a display frame operation. When the main pixel circuit operates in the data writing stage, the data line may be used to transmit an image data signal. The switch storage unit 102 obtains a scan signal through the scan line, and samples and stores the voltage of the image data signal on the data line according to the scan signal, and writes it to the control end of the main light emitting control unit 103.

[0053] The main pixel circuit may also include a light-emitting stage during the operation of a display frame. When the main pixel circuit operates in the light-emitting stage, the control end of the main light-emitting control unit 103 generates a main current drive signal under the control of the written sampling voltage to drive the corresponding light-emitting device.

[0054] The light emitting device in the embodiment of the present invention adopts a light emitting diode (LED for short), and may also adopt an OLED. Active light emitting devices such as OLED and LED have the advantages of low power consumption, high contrast, high brightness and fast response speed.

[0055] A pixel circuit may contain one light-emitting diode or multiple light-emitting diodes. For example, the pixel written in some display screen design plans is: 2R1G1B, which means that the smallest imaging unit of the display screen is composed of 2 red light-emitting tubes, 1 green light-emitting tube, and 1 blue light-emitting diode (in the display screen industry, red, green, and blue light-emitting diodes are usually replaced by their English letters, R, G, and B).

[0056] In one embodiment of the present invention, Figure 5 This is a partial circuit diagram of the pixel array circuit of this embodiment, the switch storage unit includes a data writing unit and a voltage storage unit, the data writing unit is composed of a first MOS tube, and the voltage storage unit is composed of a capacitor. The main light emitting control unit in each main pixel circuit is composed of a second MOS tube.

[0057] In this embodiment, the full name of MOS transistor is metal oxide semiconductor field effect transistor. It is a field effect transistor based on metal-oxide-semiconductor structure, mainly composed of metal gate, oxide insulating layer (usually silicon dioxide SiO2) and semiconductor layer (usually silicon Si). MOS transistor changes the electric field on the surface or inside of the semiconductor by controlling the gate voltage, thereby controlling the current between the source and the drain. It has excellent switching performance, high frequency characteristics and low power consumption advantages.

[0058] The MOS transistor in this embodiment is a component including at least a gate, a drain and a source. In this example, the first electrode of the MOS transistor can be a drain, the second electrode can be a source, or the first electrode can be a source, and the second electrode can be a drain. In the case of using transistors with opposite polarities or the current direction changes during circuit operation, the functions of the "source" and "drain" are sometimes interchanged. In this embodiment, the gates of all transistors can be used as control electrodes, and the first electrode and the second electrode can be interchanged as needed.

[0059] The gate of the first MOS tube is connected to the scan line ROW_WM for receiving a scan signal; the first electrode of the first MOS tube is connected to the data line for receiving an image data signal; when the scan signal voltage is at a high level, the first MOS tube is turned on to perform voltage sampling on the image data signal; the second electrode of the first MOS tube is connected to the positive electrode of the capacitor; the second electrode of the first MOS tube writes the sampling voltage into the capacitor; the negative electrode of the capacitor is connected to the common terminal ELVSS; the capacitor is used to store the sampling voltage and input the sampling voltage into the gate of a second MOS tube of a main light-emitting control unit.

[0060] When the main pixel circuit operates in the data writing stage, the gate of the first MOS tube obtains the scanning signal through the scanning line, and samples the voltage of the image data signal on the data line according to the scanning signal. The sampling voltage is stored by the capacitor, and the switch storage unit inputs the sampling voltage to the gate of the second MOS tube of the main light-emitting control unit 103.

[0061] The operation process of the main pixel circuit in a display frame may include a light-emitting stage. When the pixel circuit operates in the light-emitting stage, the gate of the second MOS tube of the main light-emitting control unit 103 generates a main current drive signal under the control of the input sampling voltage to drive the corresponding light-emitting device.

[0062] The current flowing through the light emitting device is I = k*(Vgs-Vth) 2 , where k is a parameter, k = 1 / 2u n C ox (W / L),u n is the electron mobility, C ox is the gate oxide capacitance, W is the width of the MOS tube, L is the length of the MOS tube, Vgs is the voltage difference between the gate voltage Vg and the source voltage Vs of the MOS tube, that is, the gate-source voltage; Vth is the threshold voltage of the MOS tube. In the light-emitting stage, when the second MOS tube is turned on based on the sampling voltage, the main light-emitting control unit can turn on the path of the light-emitting device, which generates current and lights up the light-emitting device. At this time, I = k*(Vgs-Vth) 2

[0063] =k*(Vdata-Vs-Vth) 2 Therefore, the sampling voltage Vdata can affect the current flowing through the light-emitting device, and further affect the display brightness of the light-emitting device. Within a certain current range, the brightness of the light-emitting device is proportional to the magnitude of the driving current flowing through it.

[0064] Each sub-pixel circuit includes a light-emitting device and two sub-light-emitting control units 104 electrically connected to the light-emitting device; the two sub-light-emitting control units 104 in each sub-pixel circuit are respectively connected to the switch storage units 102 in the two main pixel circuits, and the two sub-light-emitting control units 104 in each sub-pixel circuit are configured to generate two sub-current drive signals respectively under the control of the sampling voltage input by the switch storage units 102 in the two connected main pixel circuits, and the two sub-current drive signals jointly drive the corresponding light-emitting device.

[0065] The output end of the sub-light emitting control unit 104 is connected to the positive electrode of the light emitting device, the input end of the sub-light emitting control unit 104 is connected to the power supply ELVDD, and the negative electrode of the light emitting device is connected to the common end ELVSS.

[0066] The sub-pixel circuit may include a data writing phase during a display frame operation, and the data writing phase of the sub-pixel circuit is performed synchronously with the data writing phase of the two main pixel circuits connected thereto. Assuming that the two main pixel circuits are a first main pixel circuit and a second main pixel circuit, the switch storage unit 102 of the first main pixel circuit is connected to the first sub-light-emitting control unit of the sub-pixel circuit, and the switch storage unit 102 of the second main pixel circuit is connected to the second sub-light-emitting control unit of the sub-pixel circuit. The switch storage unit 102 of the first main pixel circuit obtains a scan signal through the scan line ROW_WM, and samples and stores the voltage of the image data signal on the data line COL_WN according to the scan signal, and writes it to the control end of the first sub-light-emitting control unit of the sub-pixel circuit. The switch storage unit 102 of the second main pixel circuit obtains a scan signal through the scan line ROW_WM, and samples and stores the voltage of the image data signal on the data line COL_WN+1 according to the high-level scan signal, and writes it to the control end of the second sub-light-emitting control unit of the sub-pixel circuit.

[0067] The sub-pixel circuit may also include a light-emitting stage during the operation of a display frame. When the sub-pixel circuit operates in the light-emitting stage, the control end of the first sub-light-emitting control unit of the sub-pixel circuit generates a first current drive signal under the control of the written sampling voltage, and the control end of the second sub-light-emitting control unit of the sub-pixel circuit generates a second current drive signal under the control of the written sampling voltage. The first current drive signal and the second current drive signal flow through the corresponding light-emitting device together to drive the light-emitting device to emit light. The corresponding light-emitting device generally adopts a light-emitting diode, which can be a single light-emitting diode or multiple light-emitting diodes. In this embodiment, the display light-emitting device adopts a light-emitting diode, and its light-emitting brightness is proportional to the sum of the first current drive signal and the second current drive signal flowing through.

[0068] Since the image data signals sampled by the switch storage unit of the first main pixel circuit and the switch storage unit of the second main pixel circuit come from different data lines during the data writing phase of the sub-pixel circuit, the sampling voltages of the control terminals of the first sub-light emitting control unit and the second sub-light emitting control unit written in the sub-pixel circuit are different. According to the current I=k*(Vgs-Vth) flowing through the light emitting device, 2 =k*(Vdata-Vs-Vth) 2 , where k is a parameter, k = 1 / 2u n C ox (W / L),u n is the electron mobility, C ox is the gate oxide capacitance, W is the width of the MOS tube, L is the length of the MOS tube, Vgs is the voltage difference between the gate voltage Vg and the source voltage Vs of the MOS tube, that is, the gate-source voltage; Vth is the threshold voltage of the MOS tube, and Vdata is the sampling voltage, which is input to the gate of the MOS tube to generate the gate voltage Vg. The size of the first current drive signal generated by the first sub-light-emitting control unit and the size of the second current drive signal generated by the second sub-light-emitting control unit depend on the sampling voltage Vdata written to their control terminals, respectively. Therefore, the size of the first current drive signal and the second current drive signal can be different or the same. In order to ensure the consistency of the light-emitting brightness of the light-emitting device of the pixel array circuit, the size of the first current drive signal and the second current drive signal must be reasonably set according to the actual situation.

[0069] The consistency of the luminous brightness of the light-emitting device of the pixel array circuit in this embodiment determines the display quality of the pixel array circuit. The higher the consistency, the higher the display quality; otherwise, the display quality is low. In order to make the luminous brightness of the pixel array circuit highly consistent, it is necessary to ensure that the luminous brightness of the sub-pixel circuit is between the luminous brightness of the first pixel circuit and the second pixel circuit connected thereto during the luminescence process, and the current driving signal generated by each sub-luminescence control unit of the sub-pixel circuit is configured to be no higher than 1 / 2 of the current driving signal generated by the main luminescence control unit in the main pixel circuit connected thereto. Assuming that it is higher than half of the current driving signal generated by the main luminescence control unit, it may happen that the current driving signal flowing through the light-emitting device in the sub-pixel circuit is greater than the main current driving signal of the first pixel circuit and the second pixel circuit connected thereto, and the luminous brightness of the sub-pixel circuit is higher than the luminous brightness of the first pixel circuit and the second pixel circuit, resulting in poor image display effect of the pixel array circuit.

[0070] Assuming that the main light-emitting control unit of the first main pixel circuit generates 1 unit driving current to drive the corresponding light-emitting device, and the main light-emitting control unit of the second main pixel circuit generates 1.2 unit driving current to drive the corresponding light-emitting device, then, when the sub-pixel circuits share the sampling voltage stored in the switch storage unit of the adjacent main pixel circuit, the current driving signal size generated by a sub-light-emitting control unit inside the sub-pixel circuit is not higher than 0.5 unit driving current, and the current driving signal size generated by the other sub-light-emitting control unit is not higher than 0.6 unit driving current, and the sum of the current driving signal sizes generated by the two sub-light-emitting units should be between 1 unit driving current and 1.2 unit driving currents. The pixel array circuit has a better image display effect. Therefore, preferably, the current driving signal size generated by each sub-light-emitting control unit of the sub-pixel circuit is configured to be equal to 1 / 2 of the current driving signal size generated by the main light-emitting control unit in the main pixel circuit connected thereto.

[0071] In one embodiment of the present invention, if each sub-light emitting control unit of the sub-pixel circuit is composed of a MOS tube, the chip resources occupied by the sub-pixel circuit will be greatly reduced. According to the current I flowing through the light emitting device = k*(Vgs-Vth) 2 =k*(Vdata-Vs-Vth) 2 , by changing the width and length of the MOS tube, the k value of the MOS tube is reduced, k is a parameter, k = 1 / 2u n C ox (W / L),u n is the electron mobility, C ox is the gate oxide capacitance, W is the width of the MOS tube, L is the length of the MOS tube, u n C ox It is related to the process and the designer cannot change it in general. By changing the k value, the current driving signal size ratio generated by the sub-light-emitting control unit and the main light-emitting control unit connected to the switch storage unit is configured to be 1:2 under the control of the sampling voltage input by the switch storage unit of a main pixel circuit. However, this implementation scheme also has a major defect, so that in actual chip design, the parameters of the MOS tube will not be easily changed to change the branch current. The specific reasons are as follows:

[0072] Changing the width and length of the MOS tube of the sub-light-emitting control unit of the sub-pixel circuit will cause the length and width of the MOS tube of the main light-emitting control unit of the main pixel circuit shared by the left and right connections to be inconsistent, which will lead to inconsistency in the width and length deviation rate of the MOS tubes of the main light-emitting control unit and the sub-light-emitting control unit under the same integrated circuit manufacturing process. For example, assuming that the width of the MOS tube of the sub-light-emitting control unit is 1um and is changed to 0.5um, when the manufacturing process error is 0.1um, the deviation rate of the width of the changed MOS tube increases from 10% to 20%. It should be noted that the increase in the deviation rate of the MOS tube parameters has a very obvious impact on the current generated by the MOS tube, thereby causing the current bias and deviation of the MOS tubes flowing through the main light-emitting control unit and the sub-light-emitting control unit to be inconsistent, and the light-emitting consistency of the light-emitting devices of the main pixel circuit and the sub-pixel circuit cannot be guaranteed.

[0073] Therefore, in a more preferred technical solution of this embodiment, reference Figure 5 , each sub-light-emitting control unit in each sub-pixel circuit is formed by two third MOS tubes with the same specifications and parameters connected in series, and the gates of the two third MOS tubes are connected, and the gates of the two third MOS tubes are connected to the output end of the switch storage unit of the main pixel circuit. In each sub-light-emitting control unit, the source of the first third MOS tube is connected to ELVDD, and the drain thereof is connected to the source of the second third MOS tube, the drain of the second third MOS tube is connected to the positive electrode of the light-emitting device, and the negative electrode of the light-emitting device is connected to ELVSS. The main light-emitting control unit in each main pixel circuit adopts a second MOS tube with the same specifications and parameters as the third MOS tube. Under the control of the sampling voltage input by the switch storage unit of a main pixel circuit, the current driving signal size ratio generated by the sub-light-emitting control unit connected to the switch storage unit and the main light-emitting control unit is configured to be 1:2, so as to ensure the light-emitting consistency of the light-emitting devices of the main pixel circuit and the sub-pixel circuit. By sharing the switch storage unit of two main pixel circuits through the gate of a sub-light emitting control unit of a sub-pixel circuit, the switch storage unit in the sub-pixel circuit is omitted while ensuring the consistency of light emission, thereby reducing the chip resources occupied by the sub-pixel circuit and increasing the number of pixel circuits integrated per unit chip area, thereby improving the resolution.

[0074] The sub-pixel circuit may include a data writing phase during a display frame operation. The data writing phase of the sub-pixel circuit is performed synchronously with the data writing phase of the two main pixel circuits connected thereto. Assuming that the two main pixel circuits are the first main pixel circuit and the second main pixel circuit, the switch storage unit 102 of the first main pixel circuit is connected to the gate of the third MOS tube in the first sub-light-emitting control unit of the sub-pixel circuit, and the switch storage unit 102 of the second main pixel circuit is connected to the gate of the third MOS tube in the second sub-light-emitting control unit of the sub-pixel circuit. The switch storage unit 102 of the first main pixel circuit obtains a scan signal through the scan line ROW_WM. When the scan signal is at a high level, the switch storage unit 102 is turned on, and then the image data signal on the data line COL_WN is sampled and stored in voltage, and written to the gate of the third MOS tube in the first sub-light-emitting control unit of the sub-pixel circuit. The switch storage unit 102 of the second main pixel circuit obtains a scan signal through the scan line ROW_WM, and samples and stores the image data signal on the data line COL_WN+1 in voltage according to the scan signal, and writes it to the gate of the third MOS tube in the second sub-light-emitting control unit of the sub-pixel circuit.

[0075] The sub-pixel circuit also includes a light-emitting stage during the operation of a display frame. When the sub-pixel circuit operates in the light-emitting stage, the gate of the third MOS tube in the first sub-light-emitting control unit of the sub-pixel circuit generates a first current drive signal under the control of the written sampling voltage, and the magnitude of the first current drive signal is half of the main current drive signal in the main pixel circuit sharing the sampling signal. The gate of the third MOS tube in the second sub-light-emitting control unit of the sub-pixel circuit generates a second current drive signal under the control of the written sampling voltage, and the magnitude of the second current drive signal is half of the main current drive signal in the main pixel circuit sharing the sampling signal. The first current drive signal and the second current drive signal flow through the corresponding light-emitting device together to drive the light-emitting device to emit light. The sum of the current values ​​of the first current drive signal and the second current drive signal is between the current values ​​of the main current drive signals in the two main pixel circuits connected thereto, so as to achieve the pixel array circuit light emitting brightness consistency meeting the requirements.

[0076] In order to achieve higher consistency of luminous brightness of the pixel array circuit, in the present embodiment, preferably, the type and parameters of the first MOS tubes in all main pixel circuits are the same, and the type and parameters of the voltage memory in all main pixel circuits are the same. The main light-emitting control units in all main pixel circuits use the same type and parameters of the second MOS tube, the gate of the second MOS tube is connected to the voltage memory, the second electrode of the second MOS tube is connected to ELVDD, the second electrode of the second MOS tube is connected to the corresponding positive electrode of the light-emitting device, and the negative electrode of the light-emitting device is connected to ELVSS. The specifications and parameters of the MOS tubes are the same, and the deviation rate of the MOS tube parameters is the same. When the environment in which the pixel array circuit is located changes, the impact of the environment on the MOS tube is consistent, and the current bias and deviation value of the MOS tubes flowing through the main light-emitting control unit and the sub-light-emitting control unit are consistent, thereby ensuring the consistency of the light emission of the light-emitting devices of the main pixel circuit and the sub-pixel circuit, and improving the light emission quality of the pixel array circuit.

[0077] In this embodiment, reference Figure 4 The main pixel circuit adopts the existing display circuit architecture, that is, it includes a switch storage unit 102. The switch storage unit 102 provides the pixel circuit driving voltage signal SV1 to the sub-light emitting control units of the adjacent sub-pixel circuits respectively, and also provides the pixel circuit driving voltage signal SV1 to the main light emitting control unit of its own main pixel circuit. The sub-light emitting control units of the adjacent sub-pixel circuits on the left and right receive the pixel circuit driving voltage signals SV2 and SV3 stored in the switch storage unit of the adjacent main pixel circuit. The two sub-light emitting control units of the left sub-pixel circuit respectively convert the pixel circuit driving voltage signal SV2 and the pixel circuit driving voltage signal SV1 into two driving currents to drive the light-emitting device together.

[0078] It can be seen that compared with the existing pixel array circuit, the sub-pixel circuit of the present invention has fewer switch storage units. When the number of pixels in the entire pixel array circuit is the same, the present invention can save about half of the switch storage units, reduce the number of row and column drivers and the row and column signal line wiring requirements, and significantly reduce the logical operation amount of the data storage drive unit and the output amount of the drive signal, thereby reducing the power consumption of the data storage drive unit and achieving a reduction in the power consumption of the micro display integrated circuit.

[0079] At the same time, the switch storage unit of the present invention includes a voltage storage device, and the circuit area of ​​the pixel circuit occupied by the switch storage unit is much larger than the area occupied by the light-emitting control unit and the light-emitting device. Therefore, even when the number of sub-light-emitting control units of the sub-pixel circuit is increased, the reduction in the number of switch storage units will greatly reduce the area of ​​the entire pixel array circuit. Fewer row and column signal lines will also reduce the area of ​​the entire pixel array circuit, that is, more pixel circuits can be integrated within the same chip area, thereby improving the resolution of the pixel array circuit.

[0080] In this embodiment, the main pixel circuit and the sub-pixel circuit may be arranged in a cross-arrangement form: each main pixel circuit is adjacent to a sub-pixel circuit above and below, and each sub-pixel circuit is adjacent to a main pixel circuit above and below. The change in the arrangement of the pixel circuits does not change the technical principle of the present invention. When describing the embodiment, the technical solution of the present invention should be explained according to the orientation in the embodiment.

[0081] In the above embodiment, the main pixel circuit adopts the existing display circuit architecture, that is, the switch storage unit 102 included therein adopts a MOS tube and a capacitor. If other voltage memory technology solutions can be used to replace the capacitor and reduce the chip resources occupied by the switch storage unit, more pixel circuits can be integrated within the same chip area, thereby improving the resolution of the pixel array circuit.

[0082] Therefore, in a preferred embodiment, reference is made to Figure 6 The switch storage unit includes a data writing unit and a voltage storage unit. The data writing unit is composed of two N-type MOS tubes NMN and NMBN. The voltage storage unit is composed of two inverters. The input end of the first inverter is connected to the output end of the second inverter, and the input end of the second inverter is connected to the output end of the first inverter. Each inverter is composed of a P-type MOS tube and an N-type MOS tube connected in series. The control ends of the two inverters are respectively connected to the two N-type MOS tubes of the data writing unit. The control end of each inverter is connected to the phase connection point in the other inverter, and the control end of one of the inverters is connected to the control ends of the main light-emitting control unit and the sub-light-emitting control unit.

[0083] Specifically, refer to Figure 6In the main pixel circuit on the left, the source of the N-type MOS tube NMN is connected to the data line COL_WN, the gate thereof is connected to the scan line ROW_WM, the drain thereof is connected to the gates of the P-type MOS tube PM1N and the N-type MOS tube NM1N, the drain of the P-type MOS tube PM1N is connected to the drain of the N-type MOS tube NM1N, the source of the P-type MOS tube PM1N is connected to the scan line ROW_WM, the source of the N-type MOS tube NM1N is connected to ELVSS; the drain of the N-type MOS tube NMBN is connected to the data line -COL_WN, the data signal of the data line is opposite to the data signal of the above-mentioned data line COL_WN, and the gate of the N-type MOS tube NMBN is connected to the scan line RO W_WM, the source of the N-type MOS tube NMBN is connected to the gates of the P-type MOS tube PM2N and the N-type MOS tube NM2N, the drain of the P-type MOS tube PM2N is connected to the drain of the N-type MOS tube NM2N, the source of the P-type MOS tube PM2N is connected to the scan line ROW_WM, the source of the N-type MOS tube NM2N is connected to ELVSS, the gate of the P-type MOS tube PM2N is connected to the drain of the P-type MOS tube PM1N, the gate of the P-type MOS tube PM1N is connected to the drain of the P-type MOS tube PM12N, and the gate of the P-type MOS tube PM2N is connected to the control end of the main light-emitting control unit and the control end of the sub-light-emitting control unit as the output end of the switch storage unit. Figure 6 The structure of the main pixel circuit on the right side of the middle is consistent with the structure of the main pixel circuit on the left side.

[0084] In this embodiment, the pixel circuit adopts a digital pulse width modulation driving mode, and the brightness control of the light-emitting device is realized by controlling the length of time that the light-emitting control unit is turned on; the data writing unit in the switch storage unit of the main pixel circuit is composed of two MOS tubes NMN and NMBN, and the two MOS tubes respectively receive a pair of opposite level data signals sent by the data storage driving unit. The storage unit in the switch storage unit is connected end to end by two inverters to form a digital level latch unit. When the row drive signal ROWM is at a high level, the two MOS tubes NMN and NMBN are turned on, and the level latch unit completes the latching of the column drive signal COLWN, the main light-emitting control unit is turned on, and the light-emitting device works. The luminous intensity of the light-emitting device is determined by the length of time that the main light-emitting control unit is turned on. Figure 7 , the digital level latches the low level signal of COLWN and turns on the main light-emitting control unit. The pulse width period of the light-emitting time T2 is longer than the pulse width period of the light-emitting time T1, and the light-emitting device has a greater light intensity at the time length T2.

[0085] The data writing unit in the switch storage unit in the present embodiment is composed of two MOS tubes NMN and NMBN, and respectively receives a pair of opposite data signals sent by the data storage driving unit. The voltage storage in the switch storage unit is connected end to end by two inverters to realize the storage function of the image data signal. The technical solution of the switch storage unit in the present embodiment can replace the traditional solution, realize the replacement of capacitors, and reduce the chip resources occupied by the switch storage unit. More pixel circuits can be integrated in the same chip area, thereby improving the resolution of the pixel array circuit.

[0086] Example 2, Reference Figure 8 - Fig. 9 This embodiment provides a pixel array circuit, including a plurality of cross-arranged main pixel circuits and sub-pixel circuits; each main pixel circuit includes a switch storage unit 102, a main light-emitting control unit 103 connected to the switch storage unit 102, and a light-emitting device, and each sub-pixel circuit includes a light-emitting device and four sub-light-emitting control units 104 electrically connected to the light-emitting device.

[0087] The main pixel circuit and the sub-pixel circuit are arranged crosswise in the left and right directions of the same row, and form an M×N pixel array circuit. The main pixel circuit and the sub-pixel circuit are arranged crosswise in the form of: in the same row, each main pixel circuit is adjacent to a sub-pixel circuit on the left and right, and each sub-pixel circuit is adjacent to a main pixel circuit on the left and right.

[0088] In this embodiment, the switch storage unit 102 is configured to perform voltage sampling and storage on the image data signal, and input the sampled voltage to the main light-emitting control unit 103, and the main light-emitting control unit 103 is configured to generate a main current drive signal to drive the corresponding light-emitting device under the control of the sampled voltage input by the switch storage unit 102. The output end of the main light-emitting control unit 103 is connected to the positive electrode of the light-emitting device, the input end of the main light-emitting control unit 103 is connected to the power supply, and the negative electrode of the light-emitting device is connected to the common end; the switch storage unit 102 is respectively connected to the scan line and the data line.

[0089] The main pixel circuit may include a data writing stage during a display frame operation. When the main pixel circuit operates in the data writing stage, the data line may be used to transmit an image data signal. The switch storage unit 102 obtains a scan signal through the scan line, and samples and stores the voltage of the image data signal on the data line according to the scan signal, and writes it to the control end of the main light emitting control unit 103.

[0090] The main pixel circuit may also include a light-emitting stage during the operation of a display frame. When the main pixel circuit operates in the light-emitting stage, the control end of the main light-emitting control unit 103 generates a main current drive signal under the control of the written sampling voltage to drive the corresponding light-emitting device.

[0091] In this embodiment, the switch storage unit includes a data writing unit and a voltage storage unit, the data writing unit is composed of a first MOS tube, and the voltage storage unit is composed of a capacitor. The main light emitting control unit in each main pixel circuit is composed of a second MOS tube.

[0092] When the main pixel circuit operates in the data writing stage, the gate of the first MOS tube obtains the scanning signal through the scanning line, and samples the voltage of the image data signal on the data line according to the scanning signal. The sampling voltage is stored by the capacitor, and the switch storage unit inputs the sampling voltage to the gate of the second MOS tube of the main light-emitting control unit 103.

[0093] The operation process of the main pixel circuit in a display frame may include a light-emitting stage. When the pixel circuit operates in the light-emitting stage, the gate of the second MOS tube of the main light-emitting control unit 103 generates a main current drive signal under the control of the input sampling voltage to drive the corresponding light-emitting device.

[0094] The current flowing through the light emitting device is I = k*(Vgs-Vth) 2 , where k is a parameter, k = 1 / 2u n C ox (W / L),u n is the electron mobility, C ox is the gate oxide capacitance, W is the width of the MOS tube, L is the length of the MOS tube, Vgs is the voltage difference between the gate voltage Vg and the source voltage Vs of the MOS tube, that is, the gate-source voltage; Vth is the threshold voltage of the MOS tube. In the light-emitting stage, when the second MOS tube is turned on based on the sampling voltage, the main light-emitting control unit can turn on the path of the light-emitting device, which generates current and lights up the light-emitting device. At this time, I = k*(Vgs-Vth) 2

[0095] =k*(Vdata-Vs-Vth) 2 Therefore, the sampling voltage Vdata can affect the current flowing through the light-emitting device, and further affect the display brightness of the light-emitting device. Within a certain current range, the brightness of the light-emitting device is proportional to the magnitude of the driving current flowing through it.

[0096] refer to Figure 8Each sub-pixel circuit includes a light-emitting device and four sub-light-emitting control units 104 electrically connected to the light-emitting device; the four sub-light-emitting control units 104 in each sub-pixel circuit are respectively connected to the switch storage units 102 in the four main pixel circuits adjacent to the same row and the upper row, and the four sub-light-emitting control units 104 in each sub-pixel circuit are configured to generate four sub-current driving signals respectively under the control of the sampling voltage input by the switch storage units 102 in the four connected main pixel circuits, and the four sub-current driving signals jointly drive the corresponding light-emitting device.

[0097] The output end of the sub-light emitting control unit 104 is connected to the positive electrode of the light emitting device, the input end of the sub-light emitting control unit 104 is connected to the power supply ELVDD, and the negative electrode of the light emitting device is connected to the common end ELVSS.

[0098] The sub-pixel circuit may include a data writing phase during a display frame operation process, and the data writing phase of the sub-pixel circuit is performed synchronously with the data writing phase of the four main pixel circuits connected to it. Assuming that the four main pixel circuits are the first main pixel circuit and the second main pixel circuit in the same column, and the third main pixel circuit and the fourth main pixel circuit in the same column, the switch storage unit of the first main pixel circuit is connected to the first sub-light-emitting control unit of the sub-pixel circuit, the switch storage unit of the second main pixel circuit is connected to the second sub-light-emitting control unit of the sub-pixel circuit, the switch storage unit of the third main pixel circuit is connected to the third sub-light-emitting control unit of the sub-pixel circuit, and the switch storage unit of the fourth main pixel circuit is connected to the fourth sub-light-emitting control unit of the sub-pixel circuit.

[0099] In this embodiment, the switch storage unit of the first main pixel circuit obtains the scan signal through the scan line ROW_WM, and samples and stores the image data signal on the data line COL_WN according to the scan signal, and writes it to the control end of the first sub-light-emitting control unit of the sub-pixel circuit. The switch storage unit of the second main pixel circuit obtains the scan signal through the scan line ROW_WM+1, and samples and stores the image data signal on the data line COL_WN according to the high-level scan signal, and writes it to the control end of the second sub-light-emitting control unit of the sub-pixel circuit. The switch storage unit of the third main pixel circuit obtains the scan signal through the scan line ROW_WM, and samples and stores the image data signal on the data line COL_WN+1 according to the scan signal, and writes it to the control end of the third sub-light-emitting control unit of the sub-pixel circuit. The switch storage unit of the fourth main pixel circuit obtains the scan signal through the scan line ROW_WM+1, and samples and stores the image data signal on the data line COL_WN+1 according to the high-level scan signal, and writes it to the control end of the fourth sub-light-emitting control unit of the sub-pixel circuit.

[0100] The sub-pixel circuit may also include a light-emitting stage during the operation of a display frame. When the sub-pixel circuit operates in the light-emitting stage, the control end of the first sub-light-emitting control unit of the sub-pixel circuit generates a first current drive signal under the control of the written sampling voltage, the control end of the second sub-light-emitting control unit of the sub-pixel circuit generates a second current drive signal under the control of the written sampling voltage, the control end of the third sub-light-emitting control unit of the sub-pixel circuit generates a third current drive signal under the control of the written sampling voltage, and the control end of the fourth sub-light-emitting control unit of the sub-pixel circuit generates a fourth current drive signal under the control of the written sampling voltage. The first current drive signal, the second current drive signal, the third current drive signal and the fourth current drive signal flow through the corresponding light-emitting device together to drive the light-emitting device to emit light.

[0101] Since the image data signals sampled by the switch storage unit of the first main pixel circuit and the switch storage unit of the second main pixel circuit come from the same data line during the data writing phase of the sub-pixel circuit, the sampling voltages Vdata of the control terminals of the first sub-light emitting control unit and the second sub-light emitting control unit synchronously written in the sub-pixel circuit are the same. According to the current I flowing through the light emitting device, I=k*(Vgs-Vth) 2 =k*(Vdata-Vs-Vth) 2 , where k is a parameter, k = 1 / 2u n C ox (W / L),u n is the electron mobility, C ox is the gate oxide capacitance, W is the width of the MOS tube, L is the length of the MOS tube, Vgs is the voltage difference between the gate voltage Vg and the source voltage Vs of the MOS tube, that is, the gate-source voltage; Vth is the threshold voltage of the MOS tube, and Vdata is the sampling voltage, which is input to the gate of the MOS tube to generate the gate voltage Vg. It can be seen that when the MOS tube specification parameters are the same, the k value of the MOS tube is the same, and the size of the first current drive signal generated by the first sub-light-emitting control unit and the size of the second current drive signal generated by the second sub-light-emitting control unit depend on the sampling voltage Vdata written at their control terminals. Therefore, when the sampling voltage Vdata is the same, the size of the first current drive signal is the same as that of the second current drive signal.

[0102] At the same time, since the image data signals sampled by the switch storage unit of the third main pixel circuit and the switch storage unit of the fourth main pixel circuit come from the same data line, the sampling voltage Vdata of the control end of the third sub-light-emitting control unit and the fourth sub-light-emitting control unit synchronously written in the sub-pixel circuit is the same, and when the MOS tube specification parameters are the same, the size of the third current drive signal generated by the third sub-light-emitting control unit is the same as the size of the fourth current drive signal generated by the fourth sub-light-emitting control unit. In order to ensure the consistency of the light-emitting brightness of the light-emitting device of the pixel array circuit, the sizes of the first current drive signal, the second current drive signal, the third current drive signal and the fourth current drive signal must be reasonably set according to the actual situation.

[0103] The consistency of the luminous brightness of the light-emitting device of the pixel array circuit in this embodiment determines the display quality of the pixel array circuit. The higher the consistency, the higher the display quality; otherwise, the display quality is low. In order to make the luminous brightness consistency of the pixel array circuit high, it is necessary to ensure that during the luminous process of the sub-pixel circuit, the current driving signal size generated by each sub-luminescent control unit of the sub-pixel circuit is configured to be no higher than 1 / 4 of the current driving signal size generated by the main luminescent control unit in the main pixel circuit connected thereto. Assuming that it is higher than one-fourth of the current driving signal size generated by the main luminescent control unit, the four sub-current driving signals are superimposed together, and the current driving signal flowing through the light-emitting device in the sub-pixel circuit is greater than the main current driving signal of any pixel circuit connected thereto. The luminous brightness of the sub-pixel circuit is higher than the luminous brightness of any of the four pixel circuits connected thereto, resulting in poor image display effect of the pixel array circuit.

[0104] Assuming that the main light-emitting control unit of the first main pixel circuit generates 1 unit driving current to drive the corresponding light-emitting device, and the main light-emitting control unit of the second main pixel circuit generates 1 unit driving current to drive the corresponding light-emitting device, then, when the sub-pixel circuits share the sampling voltage stored in the switch storage unit of the adjacent main pixel circuit, the current driving signal size generated by the first sub-light-emitting control unit and the second sub-light-emitting control unit in the sub-pixel circuit is not higher than 0.25 unit driving current. Similarly, assuming that the main light-emitting control unit of the third main pixel circuit generates 1.2 unit driving current to drive the corresponding light-emitting device, and the main light-emitting control unit of the fourth main pixel circuit generates 1.2 unit driving current to drive the corresponding light-emitting device, the current driving signal size generated by the third sub-light-emitting control unit and the fourth sub-light-emitting control unit is not higher than 0.3 unit driving current. Then, the sum of the current driving signal sizes generated by the four sub-light-emitting control units of the sub-pixel circuit should be between 1 unit driving current and 1.2 unit driving currents, and the pixel array circuit has a better image display effect. Therefore, it is more preferred that the current driving signal size generated by each sub-light-emitting control unit of the sub-pixel circuit is configured to be equal to 1 / 4 of the current driving signal size generated by the main light-emitting control unit in the main pixel circuit connected thereto.

[0105] In one embodiment of the present invention, if each sub-light emitting control unit of the sub-pixel circuit is composed of a MOS tube, the chip resources occupied by the sub-pixel circuit will be reduced. According to the current I flowing through the light emitting device = k*(Vgs-Vth) 2 =k*(Vdata-Vs-Vth) 2 , by changing the width and length of the MOS tube, the k value of the MOS tube is reduced. k is a parameter, k = 1 / 2u n C ox (W / L),u n is the electron mobility, C ox is the gate oxide capacitance, W is the width of the MOS tube, L is the length of the MOS tube, u n C ox It is related to the process and the designer cannot change it in general. By changing the k value, the current driving signal ratio generated by the sub-light-emitting control unit and the main light-emitting control unit connected to the switch storage unit is configured to be 1:2 under the control of the sampling voltage input by the switch storage unit of a main pixel circuit. However, this implementation scheme also has a large defect, so that in actual chip design, the parameters of the MOS tube will not be easily changed to change the guiding current. The specific reasons are as follows:

[0106] Changing the width and length of the MOS tube of the sub-light-emitting control unit of the sub-pixel circuit will cause the length and width of the MOS tube of the main light-emitting control unit of the main pixel circuit shared by the left and right connections to be inconsistent, resulting in inconsistent width and length deviation rates of the MOS tubes of the main light-emitting control unit and the sub-light-emitting control unit under the same integrated circuit manufacturing process. For example, the width of the MOS tube of the sub-light-emitting control unit is 1um, which is changed to 0.5um. When the manufacturing process error is 0.1um, the deviation rate of the width of the changed MOS tube increases from 10% to 20%. It should be noted that the increase in the deviation rate of MOS tube parameters has a very obvious impact on the current generated in the MOS tube. When the environment of the pixel array circuit changes, the current bias and deviation of the MOS tubes flowing through the main light-emitting control unit and the sub-light-emitting control unit are inconsistent due to the environmental changes, and the light-emitting consistency of the light-emitting devices of the main pixel circuit and the sub-pixel circuit cannot be guaranteed, and the anti-interference ability to the environment is poor.

[0107] Therefore, in a more preferred embodiment, Fig. 9 , each sub-light-emitting control unit in each sub-pixel circuit is formed by four third MOS tubes with the same specifications and parameters connected in series, and the gates of the four third MOS tubes are connected, and the gates of the four third MOS tubes are connected to the output end of the switch storage unit of the main pixel circuit. In each sub-light-emitting control unit, the source of the first third MOS tube is connected to ELVDD, and its drain is connected to the source of the second third MOS tube, the drain of the second third MOS tube is connected to the source of the third third MOS tube, the drain of the third third MOS tube is connected to the source of the fourth third MOS tube, the drain of the fourth third MOS tube is connected to the positive electrode of the light-emitting device, and the negative electrode of the light-emitting device is connected to ELVSS. The main light-emitting control unit in each main pixel circuit adopts a second MOS tube with the same specifications and parameters as the third MOS tube. By changing the number of third MOS tubes connected in series in the sub-light-emitting control unit of the sub-pixel circuit, the purpose of configuring the current driving signals respectively generated by the sub-light-emitting control unit and the main light-emitting control unit connected to the switch storage unit in a ratio of 1:4 under the control of the sampling voltage input by the switch storage unit of a main pixel circuit is achieved. When the environment of the pixel array circuit changes, the current deflection and deviation of the MOS tubes flowing through the main light-emitting control unit and the sub-light-emitting control unit are consistent due to the environmental changes, thereby ensuring the consistency of light emission of the light-emitting devices of the main pixel circuit and the sub-pixel circuit.

[0108] The switch storage unit of the first main pixel circuit obtains the scan signal through the scan line ROW_WM, and samples and stores the image data signal on the data line COL_WN according to the high-level scan signal, and writes it to the gate of the third MOS tube in the first sub-light-emitting control unit of the sub-pixel circuit. The switch storage unit of the second main pixel circuit obtains the scan signal through the scan line ROW_WM+1, and samples and stores the image data signal on the data line COL_WN according to the high-level scan signal, and writes it to the gate of the third MOS tube in the second sub-light-emitting control unit of the sub-pixel circuit. The switch storage unit of the third main pixel circuit obtains the scan signal through the scan line ROW_WM, and samples and stores the image data signal on the data line COL_WN+1 according to the scan signal, and writes it to the gate of the third MOS tube in the third sub-light-emitting control unit of the sub-pixel circuit. The switch storage unit of the fourth main pixel circuit obtains the scanning signal through the scanning line ROW_WM+1, and samples and stores the voltage of the image data signal on the data line COL_WN+1 according to the high-level scanning signal, and writes it to the gate of the third MOS tube in the fourth sub-light-emitting control unit of the sub-pixel circuit.

[0109] The sub-pixel circuit may also include a light-emitting stage during the operation of a display frame. When the sub-pixel circuit operates in the light-emitting stage, the gate of the third MOS tube in the first sub-light-emitting control unit of the sub-pixel circuit generates a first current drive signal under the control of the written sampling voltage, which is 1 / 4 of the main current drive signal; the gate of the third MOS tube in the second sub-light-emitting control unit of the sub-pixel circuit generates a second current drive signal under the control of the written sampling voltage, which is 1 / 4 of the main current drive signal; the gate of the third MOS tube in the third sub-light-emitting control unit of the sub-pixel circuit generates a third current drive signal under the control of the written sampling voltage, which is 1 / 4 of the main current drive signal; the gate of the third MOS tube in the fourth sub-light-emitting control unit of the sub-pixel circuit generates a fourth current drive signal under the control of the written sampling voltage, which is 1 / 4 of the main current drive signal; the first current drive signal, the second current drive signal, the third current drive signal and the fourth current drive signal flow through the corresponding light-emitting device together to drive the light-emitting device to emit light. The sum of the magnitudes of the first current drive signal, the second current drive signal, the third current drive signal and the fourth current drive signal is not higher than the magnitude of the main current drive signal generated in any one of the first main pixel circuit to the fourth main pixel circuit. At the same time, when affected by environmental changes, the impact of environmental changes on the second MOS tube and the third MOS tube is consistent, so that the current changes of the main pixel circuit and the sub-pixel circuit are consistent, thereby ensuring that no matter how the environment changes, the light-emitting devices of the main pixel circuit and the sub-pixel circuit have high light consistency and the pixel array circuit has strong resistance to environmental interference.

[0110] In a preferred solution of this embodiment, the type and parameters of the first MOS tubes in all main pixel circuits are the same, and the type and parameters of the voltage memories in all main pixel circuits are the same. The main light-emitting control units in all main pixel circuits use second MOS tubes of the same type and parameters, the gate of the second MOS tube is connected to the voltage memory, the second electrode of the second MOS tube is connected to ELVDD, the second electrode of the second MOS tube is connected to the positive electrode of the corresponding light-emitting device, and the negative electrode of the light-emitting device is connected to ELVSS. The impact of environmental changes on the devices is consistent, thereby improving the consistency of the light-emitting brightness of the pixel array circuit and the anti-interference ability to environmental changes.

[0111] In the present embodiment, compared with the existing pixel array circuit, the sub-pixel circuit of the present invention has fewer switch storage units. When the number of pixels in the entire pixel array circuit is the same, the present invention can save about half of the switch storage units, reduce the number of row and column drivers required and the row and column signal line wiring requirements, and significantly reduce the logical operation amount of the data storage drive unit and the output amount of the drive signal, thereby reducing the power consumption of the data storage drive unit and achieving a reduction in the power consumption of the micro display integrated circuit.

[0112] At the same time, the switch storage unit of the present invention includes a voltage storage device, and the circuit area of ​​the pixel circuit occupied by the switch storage unit is much larger than the area occupied by the light-emitting control unit and the light-emitting device. Therefore, even when the number of sub-light-emitting control units of the sub-pixel circuit is increased, the reduction in the number of switch storage units will greatly reduce the area of ​​the entire pixel array circuit. Fewer row and column signal lines will also reduce the area of ​​the entire pixel array circuit, that is, more pixel circuits can be integrated within the same chip area, thereby improving the resolution of the pixel array circuit.

[0113] When affected by environmental changes, the effects of environmental changes on the first MOS tube, the second MOS tube and the third MOS tube are consistent, so that the current changes of the main pixel circuit and the sub-pixel circuit are consistent, thereby ensuring that no matter how the environment changes, the light-emitting devices of the main pixel circuit and the sub-pixel circuit have high light consistency, thereby improving the ability of the pixel array circuit to resist environmental interference.

[0114] In another embodiment of the present invention, the main pixel circuit and the sub-pixel circuit are arranged crosswise in the form of: each main pixel circuit is adjacent to a sub-pixel circuit above and below, and each sub-pixel circuit is adjacent to a main pixel circuit above and below. The change in the arrangement of the pixel circuits does not change the technical principle of the present invention. When describing the embodiment, the technical solution of the present invention should be explained according to the orientation in the embodiment.

[0115] In this embodiment, another implementation scheme of a switch storage unit is provided, referring to Figure 6 The circuit structure of the switch storage unit in the invention comprises a data writing unit and a voltage storage unit, wherein the data writing unit is composed of two N-type MOS tubes NMN and NMBN, and the voltage storage unit is composed of two inverters, the input end of the first inverter is connected to the output end of the second inverter, and the input end of the second inverter is connected to the output end of the first inverter; each inverter is composed of a P-type MOS tube and an N-type MOS tube connected in series, the control ends of the two inverters are respectively connected to the two N-type MOS tubes of the data writing unit, the control end of each inverter is connected to the phase connection point in the other inverter, and the control end of one of the inverters is connected to the control end of a main light-emitting control unit in a main pixel circuit and a sub-light-emitting control unit in two sub-pixel circuits.

[0116] Specifically, in the main pixel circuit on the left, the source of the N-type MOS tube NMN is connected to the data line COL_WN, the gate thereof is connected to the scan line ROW_WM, the drain thereof is connected to the gates of the P-type MOS tube PM1N and the N-type MOS tube NM1N, the drain of the P-type MOS tube PM1N is connected to the drain of the N-type MOS tube NM1N, the source of the P-type MOS tube PM1N is connected to the scan line ROW_WM, the source of the N-type MOS tube NM1N is connected to ELVSS; the drain of the N-type MOS tube NMBN is connected to the data line -COL_WN, the data signal of the data line is opposite to the data signal of the above-mentioned data line COL_WN, and the gate of the N-type MOS tube NMBN is connected to the scan line R OW_WM, the source of the N-type MOS tube NMBN is connected to the gates of the P-type MOS tube PM2N and the N-type MOS tube NM2N, the drain of the P-type MOS tube PM2N is connected to the drain of the N-type MOS tube NM2N, the source of the P-type MOS tube PM2N is connected to the scan line ROW_WM, the source of the N-type MOS tube NM2N is connected to ELVSS, the gate of the P-type MOS tube PM2N is connected to the drain of the P-type MOS tube PM1N, the gate of the P-type MOS tube PM1N is connected to the drain of the P-type MOS tube PM12N, and the gate of the P-type MOS tube PM2N is connected to the control end of the main light-emitting control unit and the control end of the sub-light-emitting control unit as the output end of the switch storage unit.

[0117] In this embodiment, the pixel driving circuit adopts a digital pulse width modulation driving mode. The brightness control of the light-emitting device is realized by controlling the length of time the light-emitting control unit is turned on. The data writing unit in the switch storage unit of the main pixel circuit is composed of two MOS tubes NMN and NMBN. The two MOS tubes respectively receive a pair of opposite level data signals sent by the data storage driving unit. The storage unit in the switch storage unit is connected end to end by two inverters to form a digital level latch unit. When the row driving signal ROWM is at a high level, the two MOS tubes NMN and NMBN are turned on, and the level latch unit completes the latching of the column driving signal COLWN. The main light-emitting control unit is turned on, and the light-emitting device works. The luminous intensity of the light-emitting device is determined by the length of time the main light-emitting control unit is turned on. Figure 7 , the digital level latches the low level signal of COLWN and turns on the main light-emitting control unit. The pulse width period of the light-emitting time T2 is longer than the pulse width period of the light-emitting time T1, and the light-emitting device has a greater light intensity at the time length T2.

[0118] The data writing unit in the switch storage unit in the present embodiment is further composed of two MOS tubes NMN and NMBN, and respectively receives a pair of opposite data signals sent by the data storage driving unit. The voltage storage unit in the switch storage unit is connected end to end by two inverters to realize the storage function of the image data signal. The technical solution of the switch storage unit in the present embodiment can replace the traditional solution and realize the replacement of capacitors, which can further reduce the area of ​​the pixel circuit, thereby improving the resolution of the pixel array circuit.

[0119] In combination with Embodiment 1 and Embodiment 2, the technical solution of the present invention can further expand the number of sub-light-emitting control units of the sub-pixel circuit according to the same principle, and adjust the splicing mode of the sub-pixel circuit and the main pixel circuit to achieve the purpose of the sub-light-emitting control unit of the sub-pixel circuit multiplexing the switch storage unit in the main pixel circuit. Each sub-light-emitting control unit in each sub-pixel circuit is composed of N third MOS tubes with the same specifications and parameters connected in series, and the gates of the N third MOS tubes are connected, and the main light-emitting control unit in each main pixel circuit is composed of a second MOS tube with the same specifications and parameters as the third MOS tube. By changing the number of third MOS tubes in series of the sub-light-emitting control units of the sub-pixel circuit, the current driving signal size ratio generated by the sub-light-emitting control unit connected to the switch storage unit and the main light-emitting control unit is configured to be 1:N under the control of the sampling voltage input by the switch storage unit of a main pixel circuit, and N is greater than or equal to 2 and is a natural number.

[0120] Example 3, Reference Figure 4 and Fig.10In this embodiment, a micro display integrated circuit is also provided, including the pixel array circuit of the first embodiment or the second embodiment, and a data storage driving unit 101.

[0121] The data storage driving unit includes a column signal storage driving unit, a row signal storage driving unit and a data processing unit. After receiving the graphic image data outside the chip, the data processing unit performs conventional technical algorithm processing such as compression, analysis, and reorganization, and then analyzes the original graphic image data into row signals and column signals corresponding to the pixel array circuit, and sends them to the row signal storage driving unit and the column signal storage driving unit respectively. After the row signal storage driving unit and the column signal storage driving unit perform storage and analysis operations on the received row signals and column signals, they are output to the switch storage unit of the corresponding row of the pixel array circuit through the scan line and the data line respectively. The column signal storage driving unit and the row signal storage driving unit are prior art.

[0122] The data processing unit may include one or more processing cores. The data processing unit utilizes various interfaces and lines to connect various parts within the entire micro-display integrated circuit, and executes various functions and processes data within the micro-display integrated circuit by running or executing instructions, programs, code sets or instruction sets stored in the memory, and calling data stored in the memory.

[0123] In this embodiment, in the main pixel circuit, the switch storage unit provides pixel circuit driving voltage signals to the sub-light-emitting control units of the adjacently arranged and connected sub-pixel circuits respectively, and also provides pixel circuit driving voltage signals to the main light-emitting control unit of its own main pixel circuit. The sub-light-emitting control units of the sub-pixel circuits respectively receive the pixel circuit driving voltage signals stored in the switch storage units of the adjacent main pixel circuits, generate corresponding driving currents, and multiple sub-light-emitting control units jointly light up the light-emitting devices.

[0124] It can be seen that compared with the existing pixel array circuit, the sub-pixel circuit in the present invention has fewer switch storage units. When the number of pixels in the entire pixel array circuit is the same, the requirements for the number of row and column drivers and the wiring requirements for row and column signal lines are reduced, which significantly reduces the amount of logical operations and the output of the drive signal of the data storage drive unit, thereby reducing the power consumption of the data storage drive unit and achieving a reduction in the power consumption of the micro-display integrated circuit.

[0125] At the same time, the switch storage unit of the present invention includes a voltage storage unit, and the switch storage unit occupies more resources of the pixel circuit. Therefore, even when the number of sub-light-emitting control units of the sub-pixel circuit is increased, the reduction in the number of switch storage units will greatly reduce the area of ​​the entire pixel array circuit. The fewer row and column signal lines are arranged, the area of ​​the entire pixel array circuit will also be reduced, that is, more pixel circuits can be integrated within the same chip area, thereby improving the resolution of the pixel array circuit.

[0126] The above is only a preferred embodiment of the present invention. The protection scope of the present invention is not limited to the above embodiments. All technical solutions under the concept of the present invention belong to the protection scope of the present invention. It should be pointed out that for ordinary technicians in this technical field, some improvements and modifications without departing from the principle of the present invention should also be regarded as the protection scope of this template.

[0127] The above is a detailed description of an embodiment of the present invention, but the content is only a preferred embodiment of the present invention and cannot be considered to limit the scope of implementation of the present invention. All equivalent changes and improvements made within the scope of the present invention should still fall within the scope of the patent coverage of the present invention.

Claims

1. A pixel array circuit, characterized in that: It includes a plurality of main pixel circuits and sub-pixel circuits arranged crosswise; Each main pixel circuit includes a switch storage unit, a main light emitting control unit connected to the switch storage unit, and a light emitting device; the switch storage unit is configured to perform voltage sampling and storage on the image data signal, and input the sampled voltage to the main light emitting control unit, and the main light emitting control unit is configured to generate a main current driving signal under the control of the sampled voltage input by the switch storage unit to drive the corresponding light emitting device; Each sub-pixel circuit includes a light-emitting device and N sub-light-emitting control units electrically connected to the light-emitting device; the N sub-light-emitting control units in each sub-pixel circuit are respectively connected one-to-one with the switch storage units in the N main pixel circuits, and the N sub-light-emitting control units in each sub-pixel circuit are configured to generate N sub-current drive signals respectively under the control of the sampling voltage input by the switch storage units in the connected N main pixel circuits, and the N sub-current drive signals jointly drive the corresponding light-emitting devices, where N is greater than or equal to 2 and is a natural number.

2. A pixel array circuit as claimed in claim 1, characterized in that: The magnitude of the current driving signal generated by each sub-light emitting control unit of the sub-pixel circuit is configured to be no higher than 1 / N of the magnitude of the current driving signal generated by the main light emitting control unit in the main pixel circuit connected thereto.

3. A pixel array circuit as claimed in claim 2, characterized in that: Each sub-light-emitting control unit in each sub-pixel circuit is composed of N third MOS tubes with the same specifications and parameters connected in series, and the gates of the N third MOS tubes are connected, and the main light-emitting control unit in each main pixel circuit is composed of a second MOS tube with the same specifications and parameters as the third MOS tube, so as to achieve the goal that under the control of the sampling voltage input by the switch storage unit of a main pixel circuit, the current driving signal size ratio generated by the sub-light-emitting control unit connected to the switch storage unit and the main light-emitting control unit is configured to be 1:N.

4. A pixel array circuit as claimed in claim 3, characterized in that: Each sub-pixel circuit includes a light-emitting device and two sub-light-emitting control units electrically connected to the light-emitting device. Each sub-light-emitting control unit in each sub-pixel circuit is composed of two third MOS tubes with the same specifications and parameters connected in series, and the gates of the two third MOS tubes are connected. The main light-emitting control unit in each main pixel circuit is composed of a second MOS tube with the same specifications and parameters as the third MOS tube, so as to achieve the goal that under the control of the sampling voltage input by the switch storage unit of a main pixel circuit, the current driving signal size ratio generated by the sub-light-emitting control unit connected to the switch storage unit and the main light-emitting control unit is configured to be 1:

2.

5. A pixel array circuit as claimed in claim 4, characterized in that: The switch storage unit includes a data writing unit and a voltage storage unit, wherein the data writing unit is composed of a first MOS tube, and the voltage storage unit is composed of a capacitor; the gate of the first MOS tube is used to receive a scanning signal, the first electrode of the first MOS tube is used to receive an image data signal, the second electrode of the first MOS tube is used to perform voltage sampling on the image data signal according to the scanning signal, and is connected to the voltage storage unit, and the voltage storage unit is used to store the sampling voltage and input the sampling voltage into the control end of the main light-emitting control unit and the control end of the sub-light-emitting control unit connected thereto.

6. A pixel array circuit as claimed in claim 4, characterized in that: The switch storage unit includes a data writing unit and a voltage storage unit. The data writing unit is composed of two N-type MOS tubes, and the voltage storage unit is composed of two inverters. The input end of the first inverter is connected to the output end of the second inverter, and the input end of the second inverter is connected to the output end of the first inverter. Each inverter is composed of a P-type MOS tube and an N-type MOS tube connected in series. The control ends of the two inverters are respectively connected to the two N-type MOS tubes of the data writing unit. The control end of each inverter is connected to the phase connection point in the other inverter, and the control end of one of the inverters is connected to the control ends of the main light-emitting control unit and the sub-light-emitting control unit.

7. A pixel array circuit as claimed in claim 5, characterized in that: The type and parameters of the first MOS tubes in all main pixel circuits are the same, the type and parameters of the voltage memories in all main pixel circuits are the same; the type and parameters of the second MOS tubes in all main pixel circuits are the same, and the type and parameters of the third MOS tubes in all sub-pixel circuits are the same.

8. A pixel array circuit according to any one of claims 1 to 7, characterized in that: The sub-pixel circuits are arranged and distributed in the left-right direction or the up-down direction of the main pixel circuit.

9. A micro display integrated circuit, characterized in that: It comprises the pixel array circuit as described in any one of claims 1 to 8, and a data storage driving unit, wherein the data storage driving unit is electrically connected to the switch storage unit in the main pixel circuit, and is used to receive image data and perform analytical operations on the image data, and generate and output a pixel circuit driving voltage signal to the switch storage unit.

10. A micro display integrated circuit as claimed in claim 9, characterized in that: The data storage driving unit includes a column signal storage driving unit, a row signal storage driving unit and a data processing unit. After receiving the image data outside the chip, the data processing unit performs conventional technical algorithm processing such as compression, analysis and reorganization, and then parses the original graphic image data into row signals and column signals corresponding to the pixel array circuit, and sends them to the row signal storage driving unit and the column signal storage driving unit respectively. After the row signal storage driving unit and the column signal storage driving unit perform storage and analysis operations on the received row signals, they are output to the switch storage units of the corresponding rows of the pixel array circuit through the scan lines and the data lines respectively.

Images