One-time programmable memory cell

Abstract

The invention discloses a one-time programmable storage unit. The one-time programmable storage unit comprises an anti-fuse programming tube, a fuse and two control tubes, the gate end of the anti-fuse programming tube is used as the Q end of the one-time programmable storage unit; one end of the source drain of the first control tube is connected with one end of the source drain of the anti-fuse programming tube, and the other end of the first control tube is connected with one end of the source drain of the second control tube and one end of the fuse; the grid end of the first control tube is used as the WL end of the one-time programmable storage unit; the other end of the source drain of the second control tube is grounded, and the grid end of the second control tube is used as the WLP end of the one-time programmable storage unit; and the other end of the fuse is used as an FS end of the one-time programmable storage unit. According to the one-time programmable storage unit disclosed by the invention, error bits can be corrected by directly reprogramming, the circuit and layout design is simplified, the required layout area is smaller, and the reliability and the safety are higher.

Description

Technical Field

[0001] The present invention relates to integrated circuit design technology, and in particular to a one-time programmable (OTP) storage unit capable of performing a one-time correction operation on a programming result. Background Art

[0002] There are two common one-time programmable (OTP) memory cells, namely anti-fuse one-time programmable memory cells (anti-fuse) and fuse one-time programmable memory cells (eFuse). Both of these one-time programmable memory cells use standard CMOS technology, with small unit area, reduced total cost and good security.

[0003] The anti-fuse one-time programmable memory cell (anti-fuse) breaks down the insulating layer between the polysilicon layer and the N+ diffusion layer of the programming tube, causing the resistance value between the two layers to change (decrease), resulting in a change in the equivalent logic value, thereby realizing programming from "1" to "0". The anti-fuse one-time programmable memory cell (anti-fuse) can only be programmed once, that is, "1"→"0", which limits its application scope and flexibility.

[0004] The one-time programmable storage unit (eFuse) of fuse is programmed by blowing the fuse (Fuse) based on the characteristics of electron migration, causing the resistance value at both ends of the fuse to change. It can also only be programmed once, which greatly limits the user's on-site use conditions and product production and testing capabilities, and has poor redundancy.

[0005] Conventional fuse one-time programmable storage unit (eFuse) such as Figure 1 As shown. If you want to correct the one-time programming result of a conventional fuse one-time programmable storage unit (eFuse), it is usually implemented by using a dual-bit backup or redundant correction unit (bit). The former is to achieve reliable programming operation by recording the same data in two fuse one-time programmable storage units and backing up each other; the latter is to add redundant bits outside the normal bits, and after programming the redundant bits, the address information and actual value of the error bit (bit) are recorded in the redundant bits. If the input bit address happens to be the address where the error occurs, the system will ignore the stored error value and read the correct value of the corresponding redundant bit. Using dual-bit backup or redundant correction units (bit) to implement programming result correction will lead to complex circuit and layout design, increase the layout area, and low reliability. Summary of the invention

[0006] The technical problem to be solved by the present invention is to provide a one-time programmable (OTP) storage unit, which can directly correct the error bit by reprogramming, simplify the circuit and layout design, reduce the required layout area, improve reliability and safety, and increase applicability and flexibility.

[0007] In order to solve the above technical problems, the present invention provides a one-time programmable storage unit, which includes an anti-fuse programming tube M0, a fuse F and two control tubes;

[0008] The anti-fuse programming tube M0 has a gate end serving as a Q end of a one-time programmable storage unit, and the Q end is used to connect to a bit line BL;

[0009] The first control transistor M1 has one end of its source and drain connected to one end of the source and drain of the anti-fuse programming transistor M0, and the other end of its source and drain connected to one end of the source and drain of the second control transistor M2 and one end of the fuse F; its gate end serves as the WL end of the one-time programmable storage unit, and the WL end is connected to the main word line;

[0010] The second control transistor M2, the other end of the source and drain of which is grounded to GND, and the gate end of which is used as the WL_P end of the one-time programmable memory cell, and the WL_P end is used to connect to the auxiliary word line;

[0011] The other end of the fuse F is used as the FS end of the one-time programmable storage unit, and the FS end is used to connect the state selection line.

[0012] Preferably, the other end of the source and drain of the anti-fuse programming tube M0 is suspended.

[0013] Preferably, the anti-fuse programming transistor M0, the first control transistor M1 and the second control transistor M2 are all NMOS transistors;

[0014] A first control transistor M1, whose drain terminal is connected to the source terminal of the anti-fuse programming transistor M0, and whose source terminal is connected to the drain terminal of the second control transistor M2;

[0015] The source end of the second control tube M2 is grounded GND.

[0016] Preferably, before programming, the one-time programmable storage unit is in an initial state;

[0017] When the one-time programmable memory cell is in the initial state, the WL terminal, WL_P terminal, Q terminal, and FS terminal are all connected to 0V, a high-resistance state is present between the gate terminal and the source terminal of the anti-fuse programming tube M0, the fuse F is in a low-resistance state, the first NMOS control tube M1 is turned on, and the resistance between the Q terminal and the FS terminal is in a high-resistance state before programming. The logic state of the one-time programmable memory cell is defined as "1".

[0018] Preferably, when the one-time programmable memory cell performs a normal programming operation, the working voltage VDD is applied to both the WL terminal and the WL_P terminal, the FS terminal is left floating, and the gate oxide breakdown voltage VPPH is applied to the Q terminal; the first control tube M1 and the second control tube M2 are turned on; the gate oxide breakdown voltage VPPH is greater than the breakdown voltage between the gate terminal and the source terminal of the anti-fuse programming tube M0, resulting in the breakdown of the oxide layer between the gate and the source of the anti-fuse programming tube M0, and the resistance value between the gate and the source of the anti-fuse programming tube M0 decreases; the fuse F maintains a low resistance state because no current passes through it; after the normal programming operation, the one-time programmable memory cell presents a low resistance state between the Q terminal and the FS terminal, and the one-time programmable memory cell is programmed to a logic state "0".

[0019] Preferably, when the one-time programmable memory cell performs normal programming operation, the resistance value between the gate and source of the anti-fuse programming tube M0 is greater than 10M ohms before the oxide layer between the gate and source breaks down, and the resistance value between the gate and source is 20KΩ to 30KΩ after the breakdown.

[0020] Preferably, when performing a correction programming operation on a one-time programmable memory cell after normal programming, the Q terminal is left floating, the WL terminal is connected to 0V, the fuse blowing voltage VDDQ is applied to both the FS terminal and the WL_P terminal, the second control tube M2 is controlled to be turned on, and the first control tube M1 is turned off; the programming current passes through the FS terminal, the fuse F, and the second control tube M2 to the ground, so that the fuse F is blown; after the correction programming operation, the one-time programmable memory cell presents a high impedance state from the Q terminal to the FS terminal, that is, it is reprogrammed to the logic state "1".

[0021] Preferably, during a read operation, the WL_P terminal of the one-time programmable memory cell is connected to 0V, the WL terminal is connected to the operating voltage VDD, the FS terminal is grounded, and the Q terminal is connected to the sense amplifier;

[0022] The sense amplifier converts the equivalent resistance value between the Q terminal and the FS terminal into a logic value output when performing a read operation on the one-time programmable memory cell.

[0023] The one-time programmable (OTP) storage unit of the present invention is to add an anti-fuse programming tube to a conventional fuse programmable storage unit (eFuse) (2T1R structure, i.e., 2 control tubes and 1 fuse), and realize programming by breaking down the gate-source isolation layer of the anti-fuse programming tube (large resistance value becomes small resistance value), and realize programming again by using the fuse F to be blown (resistance value increases). Compared with the traditional anti-fuse OTP storage unit, the reprogramming capability is increased once, that is, after the normal programming operation is performed on the OTP storage unit, the programming result can be corrected once more. The one-time programmable (OTP) storage unit of the present invention has a one-time correction capability, and can modify the output data after the programming operation has been performed again, change the logical state after the first programming, expand the use flexibility, and improve the applicability of the OTP storage unit; at the same time, the one-time programmable (OTP) storage unit can directly use the reprogramming method to correct the error bit, compared with the existing method of increasing the one-time correction capability through redundancy, the circuit and layout design are simplified, the required layout area is smaller, and the reliability and safety are higher. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the technical solution of the present invention, the following briefly introduces the drawings required for use in the present invention. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0025] Figure 1 It is a circuit diagram of a conventional fuse one-time programmable memory cell;

[0026] Figure 2 It is a circuit diagram of an embodiment of a one-time programmable storage unit of the present invention;

[0027] Figure 3 is an initial state of an embodiment of a one-time programmable storage unit of the present invention;

[0028] Figure 4 It is a normal programming state of an embodiment of a one-time programmable memory cell of the present invention;

[0029] Figure 5 It is a one-time programmable memory cell of the present invention that corrects the programming state;

[0030] Figure 6It is a read state state of an embodiment of a one-time programmable storage unit of the present invention;

[0031] Figure 7 The invention discloses a storage array composed of one-time programmable storage cells according to an embodiment of the present invention. DETAILED DESCRIPTION

[0032] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0033] Embodiment 1

[0034] like Figure 2 As shown, a one-time programmable (OTP) storage unit includes an anti-fuse programming tube M0, a fuse F and two control tubes;

[0035] The anti-fuse programming tube M0 has a gate end serving as a Q end of a one-time programmable storage unit, and the Q end is used to connect to a bit line BL;

[0036] The first control transistor M1 has one end of its source and drain connected to one end of the source and drain of the anti-fuse programming transistor M0, and the other end of its source and drain connected to one end of the source and drain of the second control transistor M2 and one end of the fuse F; its gate end serves as the WL end of the one-time programmable storage unit, and the WL end is connected to the main word line;

[0037] The second control transistor M2, the other end of the source and drain of which is grounded to GND, and the gate end of which is used as the WL_P end of the one-time programmable memory cell, and the WL_P end is used to connect to the auxiliary word line;

[0038] The other end of the fuse F is used as the FS end of the one-time programmable storage unit, and the FS end is used to connect the state selection line.

[0039] Preferably, the other end of the source and drain of the anti-fuse programming tube M0 is suspended.

[0040] The one-time programmable (OTP) memory cell of the first embodiment is a conventional fuse programmable memory cell (eFuse) (2T1R structure, i.e., 2 control tubes and 1 fuse) with an anti-fuse programming tube added, programming is achieved by breaking down the gate-source isolation layer of the anti-fuse programming tube (large resistance value becomes small resistance value), and the fuse F is blown (resistance value increases) to achieve reprogramming. Compared with the conventional anti-fuse OTP memory cell, the reprogramming capability is increased once, i.e., after the normal programming operation is performed on the OTP memory cell, the programming result can be corrected once more.

[0041] The one-time programmable (OTP) storage unit of the first embodiment has a one-time correction capability, and can modify the output data after the programming operation has been performed again, change the logical state after the first programming, expand the flexibility of use, and improve the applicability of the OTP storage unit; at the same time, the one-time programmable (OTP) storage unit can directly use the reprogramming method to correct the error bit. Compared with the existing method of increasing the one-time correction capability through redundancy, it simplifies the circuit and layout design, requires a smaller layout area, and has higher reliability and safety.

[0042] Embodiment 2

[0043] Based on the one-time programmable (OTP) storage unit of the first embodiment, the anti-fuse programming transistor M0, the first control transistor M1 and the second control transistor M2 are all NMOS transistors;

[0044] A first control transistor M1, whose drain terminal is connected to the source terminal of the anti-fuse programming transistor M0, and whose source terminal is connected to the drain terminal of the second control transistor M2;

[0045] The source end of the second control tube M2 is grounded GND.

[0046] Preferably, the drain end of the anti-fuse programming tube M0 is suspended.

[0047] Embodiment 2

[0048] A one-time programmable (OTP) storage unit based on the first or second embodiment, wherein before programming, the one-time programmable storage unit is in an initial state;

[0049] When the one-time programmable memory cell is in the initial state, the WL terminal, WL_P terminal, Q terminal, and FS terminal are all connected to 0V, the gate terminal and the source terminal of the anti-fuse programming tube M0 are in a high-resistance state, the fuse F is in a low-resistance state, the first NMOS control tube M1 is turned on, and the resistance between the Q terminal and the FS terminal is in a high-resistance state before programming. The logic state of the one-time programmable memory cell is defined as "1", such as Figure 3 shown.

[0050] Preferably, when the one-time programmable memory cell is performing normal programming (first programming) operation, the working voltage VDD is applied to both the WL terminal and the WL_P terminal, the FS terminal is floating, and the gate oxide breakdown voltage VPPH is applied to the Q terminal; the first control tube M1 and the second control tube M2 are turned on; the gate oxide breakdown voltage VPPH is greater than the breakdown voltage between the gate terminal and the source terminal of the anti-fuse programming tube M0, causing the oxide layer between the gate and the source of the anti-fuse programming tube M0 to break down, and the resistance value between the gate and the source of the anti-fuse programming tube M0 decreases (before the oxide layer between the gate and the source of the anti-fuse programming tube M0 breaks down, the resistance value between the gate and the source is greater than 10M ohms, and after the breakdown, the resistance value between the gate and the source is about 20KΩ to 30KΩ); the fuse F maintains a low resistance state because there is no current passing through; after the normal programming operation, the one-time programmable memory cell presents a low resistance state between the Q terminal and the FS terminal, and the one-time programmable memory cell is programmed to the logic state "0". Figure 4 shown.

[0051] Preferably, if the one-time programmable memory cell after normal programming needs to be corrected, that is, if the logic state after the first programming needs to be corrected from "0" to "1", the programming operation can be performed again. When performing the correction programming (second programming) operation, the Q terminal is floating, the WL terminal is connected to 0V, and the fuse blowing voltage VDDQ is applied to the FS terminal and the WL_P terminal to control the second control tube M2 to be turned on and the first control tube M1 to be turned off; the programming current passes through the FS terminal, the fuse F, and the second control tube M2 to the ground, and the electromigration phenomenon occurs to blow the fuse F; after the correction programming operation, the one-time programmable memory cell presents a high impedance state from the Q terminal to the FS terminal, that is, it is reprogrammed to the logic state "1", such as Figure 5 shown.

[0052] Preferably, during a read operation, the WL_P terminal of the one-time programmable memory cell is connected to 0V, the WL terminal is connected to a working voltage VDD, the FS terminal is grounded, and the Q terminal is connected to a sense amplifier (SA);

[0053] The sense amplifier (SA) converts the equivalent resistance value between the Q terminal and the FS terminal into a logic value output when performing a read operation on the one-time programmable memory cell. Figure 6 shown.

[0054] The port status and resistance value changes of the one-time programmable (OTP) storage unit in the working mode of the third embodiment are shown in the following table:

[0055] Unit ports and resistors Initial state First programming Second programming Read Q 0V VPPH Floating VDD WL 0V VDD 0V VDD WL_P 0V VDD VDDQ 0V FS 0V Floating VDDQ 0V Q-FS resistance value High resistance Low resistance High resistance High / Low

[0056] The cell array composed of the one-time programmable (OTP) storage cells of the present invention is as follows Figure 7 In the array, the Q terminals of the cells in the same column are connected to the same bit line BLn and the corresponding sense amplifier SAn, the FS terminals of the cells in the same column are connected to the same state selection line FSn, the WL terminals of the cells in the same row are connected to the same main word line WLm, and the WL_P terminals of the cells in the same row are connected to the same auxiliary word line WL_Pm.

[0057] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A one-time programmable memory cell, characterized in that: It includes an anti-fuse programming tube M0, a fuse F and two control tubes; The anti-fuse programming tube M0 has a gate end serving as a Q end of a one-time programmable storage unit, and the Q end is used to connect to a bit line BL; The first control transistor M1 has one end of its source and drain connected to one end of the source and drain of the anti-fuse programming transistor M0, and the other end of its source and drain connected to one end of the source and drain of the second control transistor M2 and one end of the fuse F; its gate end serves as the WL end of the one-time programmable storage unit, and the WL end is connected to the main word line; The second control transistor M2, the other end of the source and drain of which is grounded to GND, and the gate end of which is used as the WL_P end of the one-time programmable memory cell, and the WL_P end is used to connect to the auxiliary word line; The other end of the fuse F is used as the FS end of the one-time programmable storage unit, and the FS end is used to connect the state selection line.

2. The one-time programmable memory cell according to claim 1, characterized in that: The other end of the source and drain of the anti-fuse programming tube M0 is suspended.

3. The one-time programmable memory cell according to claim 1, characterized in that: The anti-fuse programming transistor M0, the first control transistor M1 and the second control transistor M2 are all NMOS transistors; A first control transistor M1, whose drain terminal is connected to the source terminal of the anti-fuse programming transistor M0, and whose source terminal is connected to the drain terminal of the second control transistor M2; The source end of the second control tube M2 is grounded GND.

4. The one-time programmable memory cell according to claim 3, characterized in that: Before programming, the one-time programmable storage unit is in an initial state; When the one-time programmable memory cell is in the initial state, the WL terminal, WL_P terminal, Q terminal, and FS terminal are all connected to 0V, a high-resistance state is present between the gate terminal and the source terminal of the anti-fuse programming tube M0, the fuse F is in a low-resistance state, the first NMOS control tube M1 is turned on, and the resistance between the Q terminal and the FS terminal is in a high-resistance state before programming. The logic state of the one-time programmable memory cell is defined as "1".

5. The one-time programmable memory cell according to claim 4, characterized in that: When the one-time programmable memory cell performs a normal programming operation, the working voltage VDD is applied to both the WL terminal and the WL_P terminal, the FS terminal is left floating, and the gate oxide breakdown voltage VPPH is applied to the Q terminal; the first control tube M1 and the second control tube M2 are turned on; the gate oxide breakdown voltage VPPH is greater than the breakdown voltage between the gate terminal and the source terminal of the anti-fuse programming tube M0, resulting in the breakdown of the oxide layer between the gate and the source of the anti-fuse programming tube M0, and the resistance value between the gate and the source of the anti-fuse programming tube M0 decreases; the fuse F maintains a low resistance state because no current passes through it; after the normal programming operation, the one-time programmable memory cell presents a low resistance state between the Q terminal and the FS terminal, and the one-time programmable memory cell is programmed to a logic state "0".

6. The one-time programmable memory cell according to claim 5, characterized in that: When the one-time programmable memory cell performs normal programming operation, the resistance value between the gate and source of the anti-fuse programming tube M0 is greater than 10M ohms before the gate-source oxide layer is broken down, and the resistance value between the gate and source is 20KΩ to 30KΩ after the breakdown.

7. The one-time programmable memory cell according to claim 5, characterized in that: When performing a correction programming operation on a one-time programmable memory cell that has been normally programmed, the Q terminal is left floating, the WL terminal is connected to 0V, and the fuse blowing voltage VDDQ is applied to both the FS terminal and the WL_P terminal, so that the second control tube M2 is controlled to be turned on and the first control tube M1 is turned off; the programming current passes through the FS terminal, the fuse F, and the second control tube M2 to the ground, so that the fuse F is blown; after the correction programming operation, the one-time programmable memory cell presents a high impedance state from the Q terminal to the FS terminal, that is, it is reprogrammed to the logic state "1".

8. The one-time programmable memory cell according to any one of claims 3 to 7, characterized in that: During the read operation, the WL_P terminal of the one-time programmable memory cell is connected to 0V, the WL terminal is connected to the operating voltage VDD, the FS terminal is grounded, and the Q terminal is connected to the sense amplifier; The sense amplifier converts the equivalent resistance value between the Q terminal and the FS terminal into a logic value output when performing a read operation on the one-time programmable memory cell.

Images