Chip self-destruction device and manufacturing method

Abstract

The invention provides a chip self-destruction device and a manufacturing method. The chip self-destruction device comprises a chip, a through silicon via, a silicon dioxide layer, a metal micro heater layer, a first poly-p-xylylene layer, a second poly-p-xylylene layer and a backboard layer, the through silicon vias are arranged in the thickness direction of the chip; the chip groove structure is arranged on the back surface of the chip and is positioned between the adjacent through silicon vias; the silicon dioxide layer, the metal micro heater layer, the first poly-p-xylylene layer, the second poly-p-xylylene layer and the backboard layer are sequentially arranged in the direction from the active surface of the chip to the back surface of the chip; the silicon dioxide layer covers the back surface of the chip and the interior of a groove of the groove structure of the chip; the second poly-p-xylylene layer covers the first poly-p-xylylene layer and the opening direction of the chip groove structure, the chip groove structure is sealed into a sealing groove, and filler is arranged in the sealing groove; and the back plate layer covers the surface of the second poly-p-xylylene layer. Therefore, the purpose of effective self-destruction of the chip through the small-size self-destruction device is achieved.

Description

Technical Field

[0001] The present invention relates to the technical field of chip manufacturing, and in particular to a chip self-destruction device and a manufacturing method thereof. Background Art

[0002] As the core component of data computing, processing, transmission and storage, chips play an especially important role in today's rapidly developing information technology. They have also become an important target for various attacks. Attackers can dissect chips through physical attacks, reverse engineering and other methods to obtain key information stored inside. At the same time, attackers can also steal intellectual property rights and maliciously copy chips through reverse analysis of chips. Therefore, the security of chips has received more and more attention.

[0003] However, traditional protection technologies mainly enhance security and physical protection from the chip's own architecture, circuit design and packaging levels, but these measures only increase the difficulty of attacks or make attacks ineffective, and cannot fundamentally eliminate hidden dangers. In recent years, chip self-destruction technology has received more and more attention as a new type of microelectronics technology, and has been used more and more widely in chip security protection. The chip self-destruction currently developed mainly includes board-level auxiliary self-destruction, self-degradation self-destruction, stress damage self-destruction and microfluidic corrosion self-destruction. These self-destruction technologies have considerable limitations in actual environments, which limits their widespread application.

[0004] In the prior art, the chip can be crushed by setting a special movable plate on the PCB. It is also possible to use a boost circuit to provide a set high-voltage signal to the protection chip to destroy the protected chip. A sealed cavity is formed by an assembly, a control unit board and a pin adapter board, and a micro-explosion structure, an isolation layer and a storage chip are arranged in the cavity from top to bottom, and the chip is destroyed by micro-explosion. The chip can also be physically destroyed by piezoelectric ceramics and pressure mechanisms. The above methods all have problems such as large volume and insignificant self-destruction effect. Summary of the invention

[0005] In view of this, the embodiments of this specification provide a chip self-destruct device and a manufacturing method to achieve the purpose of effectively self-destructing the chip through a small-volume self-destruct device.

[0006] The embodiments of this specification provide the following technical solutions:

[0007] A chip self-destruction device, comprising:

[0008] A chip, a through silicon via, a silicon dioxide layer, a metal micro heater layer, a first polyparaxylene layer, a second polyparaxylene layer and a backplane layer;

[0009] The chip comprises a chip back surface and a chip active surface which are arranged opposite to each other;

[0010] The through silicon via is arranged in the thickness direction of the chip and penetrates the back side of the chip and the active side of the chip;

[0011] The chip groove structure is arranged on the back side of the chip and between adjacent through-silicon vias;

[0012] The silicon dioxide layer, the metal micro-heater layer, the first poly-p-xylene layer, the second poly-p-xylene layer and the backplane layer are sequentially arranged along the direction from the active surface of the chip to the back side of the chip;

[0013] The silicon dioxide layer covers the back of the chip and the inside of the groove of the chip groove structure;

[0014] The metal micro-heater layer covers the silicon dioxide layer between the through-silicon vias;

[0015] A first polyparaxylene layer covers the surface of the silicon dioxide layer and the metal micro-heater layer;

[0016] The second polyparaxylene layer covers the first polyparaxylene layer and the opening direction of the chip groove structure, sealing the chip groove structure into a sealing groove, and a filler is arranged in the sealing groove;

[0017] The backplane layer covers the surface of the second polyparaxylene layer.

[0018] Furthermore, the backplane layer is a silicon or glass substrate, and the backplane layer is bonded to the chip covered with the second polyparaxylene layer through an adhesive.

[0019] Furthermore, the self-destruct device also includes:

[0020] Rewiring layers and solder balls;

[0021] The chip also includes a chip pad;

[0022] The rewiring layer is arranged on the active surface of the chip, and the solder balls are arranged on the rewiring layer;

[0023] The chip bonding pad is arranged on the active surface of the chip.

[0024] Furthermore, the chip groove structure is in an inverted trapezoidal shape on the back side of the chip toward the active surface of the chip.

[0025] A method for manufacturing a chip self-destruct device, used for manufacturing a chip self-destruct device, the manufacturing method comprising the following steps:

[0026] Processing a chip groove structure on the back of the chip;

[0027] Prepare a rewiring layer on the surface of the chip and lead out solder balls;

[0028] Leading the pins of the metal micro-heater layer to the back side of the chip through through-silicon vias;

[0029] Prepare a silicon dioxide layer on the back side of the chip having the chip groove structure processed therein;

[0030] preparing a metal micro-heater layer on the silicon dioxide layer;

[0031] After the metal micro-heater layer is prepared, a first poly-para-xylene layer is coated on the metal micro-heater layer;

[0032] Select a filler according to the material of the chip, fill the filler into the chip groove structure, and use a second polyparaxylene layer to seal the opening direction of the chip groove structure;

[0033] The backplane layer is bonded to the chip prepared with the second polyparaxylene layer by using an adhesive.

[0034] Furthermore, a chip groove structure is processed on the back of the chip, including:

[0035] Use KOH solution to etch the chip groove structure on the back of the chip and / or,

[0036] A chip groove structure is etched on the back of the chip using a reactive ion etching method.

[0037] Further, the second polyparaxylene layer is used to seal the opening direction of the chip groove structure, including:

[0038] If the filler is in powder and / or gel form, a coating process is used to cover the second polyparaxylene layer to the opening direction of the chip groove structure;

[0039] If the filler is a solution, a coating process is used to cover the second polyparaxylene layer to the opening direction of the chip groove structure in an environment with a temperature below the freezing point of the solution.

[0040] Furthermore, the metal micro-heater layer is made of a serpentine metal wire, and the resistance of the metal wire is 10 ohms to 1000 ohms.

[0041] Furthermore, the adhesive is SU-8 photoresist and / or LCP material.

[0042] Furthermore, if the chip is made of silicon, the filler is a mixed solution of HF and HNO3, powder and / or gel of energetic materials; if the chip is made of gallium arsenide or gallium nitride, the filler is powder and / or gel of energetic materials.

[0043] Compared with the prior art, the at least one technical solution adopted in the embodiments of this specification can achieve the following beneficial effects:

[0044] Utilizing the space on the back of the chip to store corrosive liquid and energetic materials can be accomplished using wafer-level packaging technology, which has higher integration, smaller size, larger amounts of stored corrosive liquid / energetic materials, and more significant self-destruction effects. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0046] Figure 1 is a schematic diagram of the overall structure of the self-destruct device of the chip according to an embodiment of the present invention;

[0047] Figure 2 is a schematic diagram of a chip of a self-destruct device of a chip according to an embodiment of the present invention;

[0048] Figure 3 is a schematic diagram of the first step in the manufacturing steps of the self-destruct device according to an embodiment of the present invention;

[0049] Figure 4 is a schematic diagram of the second step in the manufacturing steps of the self-destruct device according to an embodiment of the present invention;

[0050] Figure 5 Schematic diagram of the third step in the manufacturing steps of the self-destruct device according to the embodiment of the present invention.

[0051] Reference numerals in the figure: 1. chip; 101. chip active surface; 102. chip pad; 103. chip groove structure; 2. redistribution layer; 3. solder ball; 4. through-silicon via; 5. silicon dioxide layer; 6. metal microheater layer; 7. first polyparaxylene layer; 8. second polyparaxylene layer; 9. adhesive; 10. backplane layer. DETAILED DESCRIPTION

[0052] The embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0053] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other. The present invention will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0054] like Figure 1 As shown, the self-destruct device of chip 1 includes:

[0055] Chip 1, redistribution layer 2, solder balls 3, through silicon vias 4, silicon dioxide layer 5, metal microheater layer 6, first polyparaxylene layer 7, second polyparaxylene layer 8 and backplane layer 10. Chip 1 includes a chip backside and a chip active surface 101 which are arranged opposite to each other, as well as a chip groove structure 103 and a chip pad 102.

[0056] The through silicon vias 4 are arranged in the thickness direction of the chip 1 and penetrate the chip backside and the chip active surface 101. The chip groove structure 103 is arranged on the chip backside and located between adjacent through silicon vias 4.

[0057] The silicon dioxide layer 5, the metal micro-heater layer 6, the first poly-p-xylene layer 7, the second poly-p-xylene layer 8 and the backplane layer 10 are sequentially arranged along the direction from the chip active surface 101 to the back of the chip. The silicon dioxide layer 5 covers the back of the chip and the inside of the groove of the chip groove structure 103. The metal micro-heater layer 6 covers the silicon dioxide layer 5 between the through-silicon vias 4. The first poly-p-xylene layer 7 covers the surface of the silicon dioxide layer 5 and the metal micro-heater layer 6. The second poly-p-xylene layer 8 covers the first poly-p-xylene layer 7 and the opening direction of the chip groove structure 103, and the chip groove structure 103 is sealed into a sealed groove, and a filler is arranged in the sealed groove. The backplane layer 10 covers the surface of the second poly-p-xylene layer 8.

[0058] The backplane layer 10 is a silicon or glass substrate, and the backplane layer 10 is bonded to the chip 1 covered with the second polyparaxylene layer 8 through an adhesive.

[0059] The rewiring layer 2 is disposed on the chip active surface 101 , and the solder balls 3 are disposed on the rewiring layer 2 . The chip pad 102 is disposed on the chip active surface 101 .

[0060] The chip groove structure 103 is in an inverted trapezoidal shape on the back side of the chip toward the chip active surface 101 .

[0061] The chip groove structure 103 of inverted trapezoidal shape is formed by etching on the back of the chip, and the etching liquid (such as HF / HNO3) or the energetic material in gel state (such as Al / CuO) is placed in the groove. The etching liquid or the energetic material is surrounded by polyparaxylene (Parylene), which can withstand the chemical erosion of the corrosive agent for a long time and has excellent barrier properties. There is a resistive heater formed by metal wiring above the polyparaxylene, and the heater is connected to the chip active surface 101 (that is, the control circuit is interconnected) through the rewiring layer 2 (TSV). If the chip 1 encounters a threat, the chip 1 outputs a high-power current through the rewiring layer 2 (TSV), so that the metal heater of the metal microheater layer 6 heats up, thereby dissolving the polyparaxylene (the first polyparaxylene layer 7 and the second polyparaxylene layer 8), so that the etching liquid flows out, or the energetic material is heated and detonated, so that the entire chip 1 self-destructs.

[0062] During the design, in order to isolate the corrosive liquid or energetic material in the chip groove structure 103 and maintain the rigidity of the entire chip 1, a back plate layer 10 is added to the back of the chip. The material can be silicon, glass, etc., which is bonded to the chip 1 through a polymer colloid such as SU-8.

[0063] Combined with the solution, the manufacturing process of the chip's self-destruct device is as follows:

[0064] like Figure 2 As shown, a chip groove structure 103 is prepared on the back of the chip. For silicon materials, a KOH solution can be used to etch an inverted groove on the back of the chip. In addition, a reactive ion etching method can be used to prepare the chip groove structure 103. Then, a wafer-level packaging technology is used to manufacture a rewiring layer 2 on the surface of the chip 1, and solder balls 3 are led out. At the same time, the pins of the metal-controlled microheater are led to the back of the chip through a through-silicon via 4 (TSV).

[0065] like Figure 3 As shown, a layer of silicon dioxide (silicon dioxide layer 5) is deposited on the back of the chip. The thickness of the silicon dioxide layer 5 is very thin (5-100nm), and it mainly plays an isolation role. Then, a metal microheater is made on the silicon dioxide layer 5 to generate a metal microheater layer 6. The typical shape of the metal microheater is a serpentine metal wire, and the material can be aluminum, copper, etc. The metal microheater is designed using the core value resistance design method, and the metal microheater usually has a resistance of 10 ohms to 1000 ohms. The chip 1 heats the metal microheater through the through silicon via 4 (TSV). The current output by the chip 1 needs to be calculated in combination with the resistance of the metal microheater and the power consumption required by the metal microheater.

[0066] After the metal micro-heater layer 6 is prepared, a layer of poly-p-xylene is coated on the back of the entire structure to generate a first poly-p-xylene layer 7. Poly-p-xylene has very good stability and can form an inverted trapezoidal container for storing the corrosive liquid and energetic materials required for self-destruction. Since the chip groove structure 103 is an inverted trapezoidal structure, the coating can be achieved by chemical vapor deposition or spraying process. Specifically, the thickness of poly-p-xylene can be 5 microns, and the coating effect is generally thinner at the upper part of the trapezoidal groove.

[0067] like Figure 4As shown, a corrosive liquid or an energetic material is placed as a filler in the chip groove structure 103, and polyparaxylene is used for sealing. If the chip 1 is made of silicon material, in order to achieve self-destruction, the corrosive liquid can be a mixed solution of HF and HNO3 (concentration ratio is 3:1). When the microheater heats and destroys the polyparaxylene layer, the corrosive liquid can quickly pass through silicon dioxide to achieve corrosion of silicon, or use powder and / or gel of energetic materials. If the chip 1 is made of materials such as gallium arsenide and gallium nitride, energetic material powder or gel can also be used to fill the groove. When the polyparaxylene layer is destroyed under heating, the energetic material is detonated at high temperature to achieve self-destruction.

[0068] After the chip groove structure 103 is filled with a filler, a layer of polyparaxylene needs to be coated on the surface to generate a second polyparaxylene layer 8 to achieve sealing and isolation of the corrosive liquid or energetic material.

[0069] If the filler is a powder or gel-like energetic material, it can be directly coated using a coating process; if the filler is a corrosive solution, it needs to be coated at a low temperature, and the temperature should be set below the freezing point of the corrosive solution.

[0070] like Figure 5 As shown, in order to further improve the reliability and stability of the entire structure, a backplane layer 10 needs to be prepared on the back side. The backplane layer 10 can be implemented using a silicon or glass substrate. The backplane layer 10 and the chip 1 (the chip 1 prepared with the second polyparaxylene layer 8) can be bonded and connected using an adhesive 9. The adhesive 9 can be made of organic materials such as SU-8 photoresist and LCP.

[0071] Beneficial effects of the embodiments of the present invention:

[0072] The embodiment of the present invention proposes a chip self-destruction device, which utilizes the back space of the chip to store corrosive liquid and energetic materials, can be completed by a wafer-level packaging process, has a higher degree of integration, a smaller volume, a larger amount of stored corrosive liquid / energetic material, and a more significant self-destruction effect; the embodiment of the present invention aims at the rapid self-destruction of the chip, especially the problems of high-density integration of corrosive solution and incomplete self-destruction caused by small amount of corrosive solution in microfluidic corrosion self-destruction technology, and adopts wafer-level packaging technology to propose a new type of high-density self-destruction structure and method, which increases the capacity of the corrosive solution inside the chip, and makes the corrosion effect faster and more significant.

[0073] The above is only a specific embodiment of the present invention, and cannot be used to limit the scope of the invention. Therefore, the replacement of equivalent components, or equivalent changes and modifications made according to the scope of protection of the patent of the present invention, should still fall within the scope of this patent. In addition, the technical features of the present invention can be freely combined with each other, with each other, and with each other.

Claims

1. A chip self-destruction device, characterized in that: include: A chip (1), a through-silicon via (4), a silicon dioxide layer (5), a metal microheater layer (6), a first polyparaxylene layer (7), a second polyparaxylene layer (8) and a backplane layer (10); The chip (1) comprises a chip back surface and a chip active surface (101) which are arranged opposite to each other; A through silicon via (4) is arranged in the thickness direction of the chip (1) and penetrates the back side of the chip and the active side (101) of the chip; The chip groove structure (103) is arranged on the back side of the chip and is located between adjacent through-silicon vias (4); The silicon dioxide layer (5), the metal micro-heater layer (6), the first poly-p-xylene layer (7), the second poly-p-xylene layer (8) and the backplane layer (10) are sequentially arranged along the chip active surface (101) toward the back side of the chip; The silicon dioxide layer (5) covers the back side of the chip and the inside of the groove of the chip groove structure (103); A metal micro-heater layer (6) covers the silicon dioxide layer (5) between the through-silicon vias (4); A first polyparaxylene layer (7) covers the surface of the silicon dioxide layer (5) and the metal micro-heater layer (6); The second polyparaxylene layer (8) covers the first polyparaxylene layer (7) and the opening direction of the chip groove structure (103), and seals the chip groove structure (103) into a sealed groove, and a filler is arranged in the sealed groove; The backplane layer (10) covers the surface of the second polyparaxylene layer (8).

2. The chip self-destruction device according to claim 1, characterized in that: The backplane layer (10) is a silicon or glass substrate, and the backplane layer (10) is bonded to the chip (1) covered with the second polyparaxylene layer (8) via an adhesive.

3. The chip self-destruction device according to claim 1, characterized in that: The self-destruct device also includes: Rewiring layer (2) and solder balls (3); The chip (1) also includes a chip bonding pad (102); The rewiring layer (2) is arranged on the chip active surface (101), and the solder ball (3) is arranged on the rewiring layer (2); The chip bonding pad (102) is arranged on the chip active surface (101).

4. The chip self-destruction device according to claim 1, characterized in that: The chip groove structure (103) is in an inverted trapezoidal shape on the back side of the chip in a direction toward the chip active surface (101).

5. A method for manufacturing a chip self-destruction device, used for manufacturing the chip self-destruction device according to any one of claims 1 to 4, characterized in that: The manufacturing method comprises the following steps: Processing a chip groove structure (103) on the back side of the chip; A rewiring layer (2) is prepared on the surface of the chip (1), and solder balls (3) are led out; Leading the pins of the metal micro-heater layer (6) to the back side of the chip (1) through a through-silicon via (4); Preparing a silicon dioxide layer (5) on the back side of the chip having the chip groove structure (103) processed thereon; Preparing a metal micro-heater layer (6) on the silicon dioxide layer (5); After the metal micro-heater layer (6) is prepared, a first poly-para-xylene layer (7) is coated on the metal micro-heater layer (6); Selecting a filler according to the material of the chip (1), filling the filler into the chip groove structure (103), and using a second polyparaxylene layer (8) to seal the opening direction of the chip groove structure (103); The backplane layer (10) is bonded to the chip (1) prepared with the second polyparaxylene layer (8) using an adhesive (9).

6. The method for manufacturing a self-destruct device according to claim 5, characterized in that: Processing a chip groove structure (103) on the back side of the chip includes: A chip groove structure (103) is etched on the back of the chip using a KOH solution and / or, A chip groove structure (103) is etched on the back side of the chip using a reactive ion etching method.

7. The method for manufacturing a self-destruct device according to claim 5, characterized in that: Using a second polyparaxylene layer (8) to seal the opening direction of the chip groove structure (103) includes: If the filler is in powder and / or gel form, a coating process is used to cover the second polyparaxylene layer (8) in the direction of the opening of the chip groove structure (103); If the filler is a solution, a coating process is used to cover the second polyparaxylene layer (8) in the direction of the opening of the chip groove structure (103) in an environment with a temperature below the freezing point of the solution.

8. The method for manufacturing a self-destruct device according to claim 5, characterized in that: The metal micro-heater layer (6) is made of a serpentine metal wire, and the resistance of the metal wire is 10 ohms to 1000 ohms.

9. The method for manufacturing a self-destruct device according to claim 5, characterized in that: The adhesive (9) is SU-8 photoresist and / or LCP material.

10. The method for manufacturing a self-destruct device according to claim 5, characterized in that: The filler is selected according to the material of the chip (1), including: If the material of the chip (1) is silicon, the filler is a mixed solution of HF and HNO3, powder of energetic material and / or gel; If the chip (1) is made of gallium arsenide or gallium nitride, the filler is powder and / or gel of an energetic material.

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