Substrate structure and forming method thereof, storage device and manufacturing method thereof, and electronic equipment

Abstract

The invention discloses a base structure and a forming method thereof, a storage device and a manufacturing method thereof, and electronic equipment, and the base structure comprises a first substrate which is provided with a substrate flow channel; and the second substrate is provided with a chip flow channel, and the chip flow channel is communicated with the substrate flow channel. A substrate flow channel of a first substrate in the base structure is communicated with a chip flow channel of a second substrate, and the substrate flow channel and the chip flow channel are suitable for providing circulation of cooling liquid; when the cooling liquid flows through the substrate structure, heat dissipation can be more efficiently realized, that is, the heat dissipation efficiency of the substrate structure is higher, the heat dissipation capability of the electronic device can be effectively improved by using the substrate structure, and the heat dissipation capability of the storage device can be effectively improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and in particular to a substrate structure and a forming method thereof, a storage device and a manufacturing method thereof, and an electronic device. Background Art

[0002] The storage device includes a memory and a system chip connected to each other, wherein the system chip is used to control the access of data in the memory. In the three-dimensional stacking process, the memory and the on-chip system chip are arranged in a stacked manner, which can effectively improve the computing performance.

[0003] However, during the operation of the storage device, the storage device will generate a large amount of heat energy. Due to the packaging structure of the stacking process, the heat generated during the operation is difficult to dissipate effectively, which can easily cause the problem of device performance degradation.

[0004] It can be seen that the heat dissipation problem of three-dimensional stacked storage devices is a key to the development of the industry. Summary of the invention

[0005] The problem solved by the present invention is how to improve the heat dissipation capability of a three-dimensionally stacked storage device.

[0006] In order to solve the above problems, the present invention provides a method for forming a substrate structure, comprising:

[0007] A first substrate is formed, wherein the first substrate has a substrate flow channel; a second substrate is formed, wherein the second substrate has a chip flow channel; the second substrate is disposed on the first substrate, and the chip flow channel is connected to the substrate flow channel.

[0008] Accordingly, the present invention also provides a substrate structure, comprising:

[0009] A first substrate, wherein the first substrate has a substrate flow channel; and a second substrate, wherein the second substrate has a chip flow channel, wherein the chip flow channel is connected to the substrate flow channel.

[0010] In addition, the present invention also provides a method for manufacturing a storage device, comprising:

[0011] A memory structure is formed; a base structure is formed, and the base structure is the base structure of the present invention; the memory structure is bonded to a second substrate of the base structure; and the base structure is mounted on a circuit board.

[0012] Accordingly, the present invention further provides a storage device, comprising:

[0013] A circuit board; a base structure, the base structure is located on the circuit board, the base structure is the base structure of the present invention, wherein the first substrate is located between the second substrate and the circuit board; a memory structure, the memory structure is located on the base structure.

[0014] Furthermore, the present invention further provides an electronic device, comprising:

[0015] A storage device, wherein the storage device is the storage device of the present invention; a cooling liquid, wherein the cooling liquid flows in the connected chip flow channel and substrate flow channel.

[0016] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0017] In the technical solution of the present invention, the substrate flow channel of the first substrate and the chip flow channel of the second substrate in the substrate structure are connected, and the substrate flow channel and the chip flow channel are suitable for providing the circulation of cooling liquid; when the cooling liquid flows through the substrate structure, heat dissipation can be achieved more efficiently, that is, the heat dissipation efficiency of the substrate structure is higher, and the use of the substrate structure can effectively improve the heat dissipation capacity of the electronic device and can effectively improve the heat dissipation capacity of the storage device.

[0018] In an optional solution of the present invention, the chip flow channel is an open structure without a bottom surface on the side close to the second surface of the second substrate; the second surface of the second substrate is suitable for setting a memory structure, and the chip flow channel is set as an open structure without a bottom surface on the side close to the second surface of the second substrate, so that the coolant flowing in the chip flow channel can directly contact the structure of the second substrate away from the first substrate side, which can better achieve heat dissipation and enable the base structure to have better heat dissipation capacity. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 is a schematic diagram of the structure of a storage device;

[0020] Figure 2 Schematic diagrams of cross-sectional structures of some embodiments of the substrate structure of the present invention;

[0021] Figure 3 is a schematic diagram of a top view of a first surface of a first substrate in some embodiments of a base structure of the present invention;

[0022] Figure 4 is a schematic diagram of a top view of the first surface of the second substrate in some embodiments of the substrate structure of the present invention;

[0023] Figure 5 It is a schematic diagram of the top view of the second surface of the second substrate in some embodiments of the base structure of the present invention.

[0024] Figures 6 to 19is a schematic structural diagram of each step in some embodiments of the method for forming a substrate structure of the present invention;

[0025] Fig. 20 It is a schematic diagram of the structure of some embodiments of the storage device of the present invention.

[0026] Figure 21 to Figure 26 It is a structural schematic diagram of each step in some embodiments of the method for manufacturing the storage device of the present invention. DETAILED DESCRIPTION

[0027] As can be seen from the background technology, the three-dimensional stacked storage device in the prior art has a heat dissipation problem. Now, the cause of the heat dissipation problem is analyzed in combination with the structure of a three-dimensional stacked storage device:

[0028] refer to Figure 1 , showing a schematic structural diagram of a storage device.

[0029] The storage device is a three-dimensional stacked storage device, which includes: a circuit board 11, a system-on-chip chip (SOC chip) 12 and a memory stack 14, wherein the memory stack 14 includes a plurality of stacked memories 13, and the system-on-chip chip 12 and the memory stack 14 are sequentially stacked on the surface of the circuit board 11.

[0030] During the operation of the storage device, the main heat is generated by the system-on-chip chip 12. However, the system-on-chip chip 12 is located between the memory stack 14 and the circuit board 11. The heat dissipation path of the system-on-chip chip 12 is seriously congested, and it is difficult to contact with an external heat dissipation device (such as a heat sink, a cooling fan, etc.), thereby causing a heat dissipation problem for the storage device.

[0031] In order to solve the technical problem, the present invention provides a substrate structure, comprising:

[0032] A first substrate, wherein the first substrate has a substrate flow channel; and a second substrate, wherein the second substrate has a chip flow channel, wherein the chip flow channel is connected to the substrate flow channel.

[0033] In the technical solution of the present invention, the substrate flow channel of the first substrate and the chip flow channel of the second substrate in the substrate structure are connected, and the substrate flow channel and the chip flow channel are suitable for providing circulation of cooling liquid; when the cooling liquid flows through the substrate structure, heat dissipation can be achieved more efficiently, that is, the heat dissipation efficiency of the substrate structure is higher, and the use of the substrate structure can effectively improve the heat dissipation capacity of the electronic device and can effectively improve the heat dissipation capacity of the storage device.

[0034] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0035] refer to Figure 2 , showing schematic cross-sectional structures of some embodiments of the substrate structure of the present invention.

[0036] The base structure includes: a first substrate 110 , wherein the first substrate 110 has a substrate flow channel 111 ; and a second substrate 120 , wherein the second substrate 120 has a chip flow channel 121 , wherein the chip flow channel 121 is connected to the substrate flow channel 111 .

[0037] The substrate flow channel and the chip flow channel are suitable for providing circulation of cooling liquid; when the cooling liquid flows through the substrate structure, heat dissipation can be achieved more efficiently, that is, the heat dissipation efficiency of the substrate structure is higher. The use of the substrate structure can effectively improve the heat dissipation capacity of the electronic device and can effectively improve the heat dissipation capacity of the storage device.

[0038] The technical solution of the substrate structure embodiment is described in detail below with reference to the accompanying drawings.

[0039] The first substrate 110 may be connected to an external circuit; the substrate 110 has a substrate flow channel 111 therein, and the substrate flow channel 111 may provide a flow path between a cooling liquid and the outside.

[0040] In some embodiments of the present invention, the substrate flow channel 111 is a closed structure with a bottom surface on the side close to the first surface 120a of the first substrate 110 and the side close to the second surface 120b of the first substrate 110, that is, the substrate flow channel 111 is a flow channel buried inside the first substrate 110, and the four walls of the flow channel are all formed by the first substrate 110. The first surface 110a of the first substrate 110 and the second surface 110b of the first substrate 110 are two surfaces of the first substrate 110 that are arranged opposite to each other.

[0041] Combined with reference Figure 3 , showing a schematic diagram of the top view of the first surface of the first substrate in some embodiments of the base structure of the present invention.

[0042] In some embodiments of the present invention, the first surface 120a of the first substrate 110 has a first opening 110i, a second opening 110o, a first lower interface 112 and a second lower interface 113, the first opening 110i and the first lower interface 112 are connected through a first substrate flow channel 111a, and the second opening 110o and the second lower interface 112b are connected through a second substrate flow channel 111b.

[0043] Specifically, one of the first opening 110i and the second opening 110o can be used as an inlet for the coolant, and the other can be used as an outlet for the coolant, thereby realizing the circulation of the coolant in the entire substrate structure; the first lower interface 112 and the second lower interface 113 serve as connecting ports between the substrate flow channel 111 and the chip flow channel, one of which serves as an interface for the coolant to flow from the substrate flow channel 111 into the chip flow channel, and the other serves as an interface for the coolant to flow back from the chip flow channel to the substrate flow channel 111.

[0044] like Figure 3 As shown, the first opening 110i and the second channel 111o are circular, thereby improving the adaptability with the pipeline in the circulation device to reduce the difficulty of external connection of the coolant flow path; the first lower interface 112 and the second lower interface 113 are long strips.

[0045] The substrate flow channel 111 is used to achieve the connection between the coolant flow path in the substrate structure and the external flow path. Specifically, the substrate flow channel 111 is divided into two parts, namely the first substrate flow channel 111a and the second substrate flow channel 111b; one end of the first substrate flow channel 111a is connected to the first opening 110i, and the other end is connected to the first lower interface 112; one end of the second substrate flow channel 111b is connected to the second opening 110o, and the other end is connected to the second lower interface 113.

[0046] In some embodiments of the present invention, the first substrate 110 further has metal wiring 115. The metal wiring 115 can realize electrical connection of structures on both sides of the first substrate 110. The metal wiring 115 extends from the first surface 110a of the first substrate 110 to the second surface 110b of the first substrate 110 to realize electrical connection between the first surface 110a and the second surface 110b.

[0047] In some embodiments, the second surface 120b of the first substrate 110 has an external pad (not shown). The first surface 110a of the first substrate 110 has an electrical contact point 114, one end of the metal wiring 115 contacts the electrical contact point 114, and the other end contacts the external pad, so as to provide electrical connection between the electrical contact point 114 and the external pad.

[0048] In some embodiments of the present invention, the first substrate 110 is a glass substrate, that is, the material of the first substrate 110 can be glass; in other embodiments of the present invention, the first substrate can also be an organic glass substrate or other plate substrate.

[0049] Continue to refer Figure 2 , combined with reference Figure 4 and Figure 5In the base structure, the second substrate 120 can be connected to the structure to be cooled; the second substrate 120 has a chip flow channel 121, and the chip flow channel 121 can provide a flow path for the coolant to contact the structure to be cooled.

[0050] In some embodiments of the present invention, the chip flow channel 121 is a closed structure with a bottom surface (such as Figure 4 The chip flow channel 121 is an open structure without a bottom surface on the side close to the second surface 120b of the second substrate 120 (as shown); Figure 5 As shown in FIG. 1 , in the second substrate 120, the chip flow channel 121 is a groove with an opening located on the second surface 120b of the second substrate 120, and the sidewall and bottom surface of the groove are both formed by the second substrate 120. The first surface 120a of the second substrate 120 and the second surface 120b of the second substrate 120 are two surfaces of the second substrate 120 that are arranged opposite to each other, and the first surface 120a of the second substrate 120 faces the first substrate 110.

[0051] The chip channel 121 is an open structure without a bottom surface on the side close to the second surface 120b of the second substrate 120, which can enable the coolant flowing in the chip channel 121 to directly contact the structure to be cooled on the second surface 120b, thereby effectively improving the cooling efficiency and the heat dissipation effect.

[0052] In some embodiments of the present invention, the first surface 120a of the second substrate 120 has a first upper interface 122 and a second upper interface 123, the first upper interface 122 and the second upper interface 123 are connected through the chip flow channel 121, the first upper interface 122 and the first lower interface 112 are connected correspondingly, and the second upper interface 123 and the second lower interface 113 are connected correspondingly.

[0053] Specifically, the first upper interface 122 and the first lower interface 112 are used as connection ports with the substrate flow channel 111, one of which is used as an interface for the coolant to flow from the substrate flow channel 111 into the chip flow channel 121, and the other is used as an interface for the coolant to flow back from the chip flow channel 121 to the substrate flow channel 111. For example, the first upper interface 122 and the first lower interface 112 (such as Figure 3 ) are connected to each other, the second upper interface 123 and the second lower interface 113 (as shown Figure 3 as shown) are connected correspondingly.

[0054] In some embodiments, the first upper interface 122 has the same shape as the first lower interface 112; the second upper interface 123 has the same shape as the second lower interface 113. The first upper interface 122 has the same shape as the first lower interface 112, and the second upper interface 123 has the same shape as the second lower interface 113. The first upper interface 122 and the first lower interface 112, and the second upper interface 123 and the second lower interface 113 have a higher degree of adaptability, and the caliber of the flow path can be fully utilized.

[0055] Specifically, the first lower interface 112 and the second lower interface 113 are respectively long strips; the first upper interface 122 and the second upper interface 123 are also long strips, and the length and width of the first upper interface 122 and the first lower interface 112 are the same; the length and width of the second upper interface 123 and the second lower interface 113 are the same.

[0056] The chip flow channel 121 is used to achieve the contact between the cooling liquid flow path in the base structure and the structure to be cooled. Figure 4 In some of the embodiments shown, the chip channel 121 is divided into three parts, namely, a first chip channel 121a, a second chip channel 121b and a third chip channel 121c, the first chip channel 121a, the second chip channel 121b and the third chip channel 121c are arranged in parallel between the first upper interface 122 and the second upper interface 123, one end of the first chip channel 121a, the second chip channel 121b and the third chip channel 121c are connected to the first upper interface 122, and the other ends of the first chip channel 121a, the second chip channel 121b and the third chip channel 121c are connected to the second upper interface 123.

[0057] In some embodiments of the present invention, the second substrate 120 is a silicon substrate, that is, the material of the second substrate 110 can be silicon, such as single crystal silicon, polycrystalline silicon or amorphous silicon; in other embodiments of the present invention, the second substrate can also be a semiconductor substrate such as a germanium substrate, a gallium arsenide substrate or a silicon germanium substrate; the second substrate can also be selected from a silicon structure having an epitaxial layer or an epitaxial layer; the second substrate can also be other semiconductor materials.

[0058] Continue to refer Figure 2 In some embodiments of the present invention, the substrate structure further includes: a through silicon via TSV1, wherein the through silicon via TSV1 penetrates the second substrate 120. The through silicon via TSV1 is suitable for realizing electrical connection of structures on both sides of the second substrate 120.

[0059] In some embodiments, the chip flow channel 121 surrounds the through silicon via TSV1. The second substrate 120 has a plurality of through silicon vias TSV1, and the chip flow channel 121 surrounds all the through silicon vias TSV1. Figure 4 In some of the illustrated embodiments, the first upper interface 122 , the first chip flow channel 121 a , the second upper interface 123 , and the third chip flow channel 121 c surround all of the through silicon vias TSV1 .

[0060] In some embodiments, the chip flow channel 121 is located between the through silicon vias TSV1. The chip flow channel 121 passes through the gaps between adjacent through silicon vias TSV1 to increase the flow area of ​​the coolant in the second substrate 120 and improve the heat dissipation efficiency. Figure 4 In some of the embodiments shown, the second chip flow channel 121b passes through adjacent through silicon vias TSV, that is, a portion of the through silicon vias TSV1 is located between the first chip flow channel 121a and the second chip flow channel 121b; the remaining portion of the through silicon vias TSV1 is located between the second chip flow channel 121b and the third chip flow channel 121c.

[0061] Continue to refer Figure 2 In some embodiments of the present invention, the base structure further includes: an interconnection layer 140, the interconnection layer 140 is located on the first surface 120a of the second substrate 120, the interconnection layer 140 has a connection bump, and the connection bump is electrically connected to the through silicon via TSV1.

[0062] Specifically, the interconnection layer 140 can realize the connection between the first substrate 110 and the second substrate 120 ; the interconnection layer 140 can also realize the electrical connection between the first substrate 110 and the second substrate 120 .

[0063] In some embodiments, the first substrate 110 further has a metal wiring 115 ; the metal wiring 115 is in electrical contact with a connection bump in the interconnection layer 140 .

[0064] The connection bump runs through the entire thickness of the interconnection layer 140 , one end of the connection bump contacts the through silicon via TSV1 in the second substrate 120 , and the other end of the connection bump contacts the electrical contact point 114 on the first surface 110 a of the first substrate 110 .

[0065] In some embodiments, the second surface 120b of the first substrate 110 also has an external solder pad (not shown in the figure); the metal wiring 115 connects the connection bump and the external solder pad; and the electrical connection between the structure to be cooled and the external circuit is achieved through the connection bump, the metal wiring 115 and the external solder pad.

[0066] It should be noted that, in some embodiments, the interconnection layer 140 also has a dielectric material (not shown in the figure) filled between adjacent connection bumps to achieve electrical insulation between adjacent connection bumps, and is also used to achieve the connection between the first substrate 110 and the second substrate 120 in the area outside the connection bumps. One side of the dielectric material of the interconnection layer 140 is in direct contact with the first surface 110a of the first substrate 110, and the other side of the dielectric material of the interconnection layer 140 is in direct contact with the first surface 120a of the second substrate 120.

[0067] It should also be noted that there may be two interconnection openings (not shown in the figure) in the interconnection layer 140, one of the interconnection openings is located between the first upper interface 122 and the first lower interface 112 to achieve connectivity between the first upper interface 122 and the first lower interface 112, and the other interconnection opening is located between the second upper interface 123 and the second lower interface 113 to achieve connectivity between the second upper interface 123 and the second lower interface 113.

[0068] In some embodiments of the present invention, the base structure further includes: a bonding layer 130 , wherein the bonding layer 130 is located on the second surface 120 b of the second substrate 120 , and the second surface 120 b is disposed opposite to the first surface 120 a .

[0069] Specifically, the bonding connection layer 130 is used to realize the bonding connection between the second substrate 120 and the structure to be cooled. The bonding connection layer 130 has a metal layer and a dielectric material filled between the metal layers to form a metal wiring; wherein the metal wiring includes: an internal wiring INM and a redistribution structure RDL, wherein the internal wiring INM is located between the redistribution structure RDL and the second substrate 120.

[0070] like Figure 2 In some of the embodiments shown, the bonding layer 130 is located on the second surface 120b of the second substrate 120 , that is, the bonding layer 130 is directly formed on the second surface 120b of the second substrate 120 , and the bonding layer 130 is in direct contact with the second surface 120b of the second substrate 120 .

[0071] The metal wiring in the bonding layer 130 is electrically connected to the through silicon via TSV1, and the bottom metal (not shown in the figure) of the metal wiring in the bonding layer 130 is electrically connected to one end of the through silicon via TSV1, wherein the bottom metal is the metal in the metal wiring of the bonding layer 130 that is closest to the second substrate 120.

[0072] It should be noted that in some embodiments, the chip flow channel 121 is an open structure without a bottom surface on the side close to the second surface 120b of the second substrate 120 (eg Figure 5 The dielectric material of the bonding connection layer 130 covers the open structure of the chip flow channel 121 close to the second surface 120b of the second substrate 120 to form a flow channel and prevent the coolant from overflowing.

[0073] It should also be noted that, in some embodiments, the dielectric material of the bonding layer 130 covers the entire second surface 120b of the second substrate 120, and the bottom metal of the metal wiring in the bonding layer 130 can be located on the surface of the dielectric material covering the open structure away from the second substrate 120, and the bottom metal and the through silicon via TSV1 are electrically connected through a via structure.

[0074] In other embodiments of the present invention, the bottom layer metal may also be directly located on the second surface of the second substrate, that is, the bottom layer metal is in direct contact with the second surface of the second substrate, and the bottom layer metal is in direct contact with the through silicon via; the dielectric material filled between the bottom layer metals covers the open structure of the chip flow channel 121, that is, the bottom layer metal avoids the position corresponding to the open structure of the chip flow channel 121 to avoid the influence of the coolant on the electrical connection.

[0075] Correspondingly, the present invention also provides a method for forming a substrate structure.

[0076] The forming method comprises: referring to Figure 6 and Figure 7 , forming a first substrate 210, wherein the first substrate 210 has a substrate flow channel 211; Figures 8 to 18 , forming a second substrate 220 , wherein the second substrate 220 has a chip flow channel 221 ; disposing the second substrate 220 on the first substrate 210 , and making the chip flow channel 221 communicate with the substrate flow channel 211 .

[0077] It should be noted that, in some embodiments of the present invention, the forming method is suitable for forming the substrate structure of the present invention, and the technical solution of the forming method can refer to the embodiments of the aforementioned substrate structure.

[0078] refer to Figure 6 and Figure 7First, a first substrate 210 is formed, wherein Figure 6 is a schematic diagram of a cross-sectional structure of a first substrate formed in some embodiments of the method for forming a substrate structure of the present invention; Figure 7 It is a schematic diagram of the top view of the first surface of the first substrate formed in some embodiments of the base structure forming method of the present invention.

[0079] In some embodiments of the present invention, the step of forming the first substrate 210 includes: providing a first prefabricated substrate; and forming the substrate flow channel 211 in the first prefabricated substrate to form the first substrate 210 .

[0080] The first prefabricated substrate is suitable for providing a basis for forming the first substrate 210. For example, the first prefabricated substrate may be a glass substrate to form the first substrate 210 made of glass. In other embodiments of the present invention, the first substrate may also be an organic glass substrate or other plate substrate.

[0081] In some embodiments, electrical contact points 214 are provided on the first surface 210a of the first prefabricated substrate, and external solder pads (not shown in the figure) are provided on the second surface 210b of the first prefabricated substrate; metal wiring 215 connecting the electrical contact points 214 and the external solder pads is pre-embedded in the first prefabricated substrate.

[0082] The substrate flow channel 211 is formed in the first prefabricated substrate to form the first substrate 210. Specifically, a first substrate flow channel 211a and a second substrate flow channel 211b are formed in the first prefabricated substrate.

[0083] In some embodiments of the present invention, in the step of forming the substrate flow channel 211 in the first prefabricated substrate to form the first substrate 210, the substrate flow channel 211 is formed in the first prefabricated substrate by laser engraving. For example, in the step of forming the substrate flow channel 211 in the first prefabricated substrate, a closed flow channel is formed in the first substrate 210 by laser engraving technology to serve as the substrate flow channel 211.

[0084] In some embodiments of the present invention, the step of forming the first substrate 210 also includes: forming a first opening 210i, a second opening 210o, a first lower interface 212 and a second lower interface 213 on the first surface 210a of the first preliminary substrate, the first opening 210i and the first lower interface 212 are connected to the first substrate flow channel 111a, and the second opening 210o and the second lower interface 213 are connected to the second substrate flow channel 111b.

[0085] Specifically, in the steps of forming the first opening 210i, the second opening 210o, the first lower interface 212 and the second lower interface 213, the first opening 210i and the first lower interface 212 are respectively formed at both ends of the first substrate flow channel 111a, and the second opening 210o and the second lower interface 213 are respectively formed at both ends of the second substrate flow channel 111b.

[0086] In some embodiments of the present invention, in the step of forming the first opening 210i, the second opening 210o, the first lower interface 212 and the second lower interface 213, the first opening 210i, the second opening 210o, the first lower interface 212 and the second lower interface 213 are formed by laser etching.

[0087] refer to Figures 8 to 18 The forming method further includes: forming a second substrate 220.

[0088] In some embodiments of the present invention, the step of forming the second substrate 220 includes: Figure 8 As shown, a second prefabricated substrate 229 is provided, wherein the second prefabricated substrate 229 has a first surface 220a and a second surface 220b disposed opposite to each other; Figures 9 to 18 As shown, the second surface 220b of the second prefabricated substrate 229 is etched to form a prefabricated groove 228 (such as Fig.14 As shown) to form the second substrate 220.

[0089] The second prefabricated substrate 229 can provide a basis for the formation of the second substrate. For example, the second prefabricated substrate 229 is a silicon substrate, that is, the material of the second prefabricated substrate 229 can be silicon, such as single crystal silicon, polycrystalline silicon or amorphous silicon. In other embodiments of the present invention, the second prefabricated substrate can also be a semiconductor substrate such as a germanium substrate, a gallium arsenide substrate or a silicon germanium substrate; the second prefabricated substrate can also be selected from a silicon structure having an epitaxial layer or an epitaxial layer; the second prefabricated substrate can also be other semiconductor materials.

[0090] like Figures 8 to 10 , forming a prefabricated groove 228 in the second prefabricated substrate 229 to form the second substrate 220 (eg Fig.18 Specifically, Fig.10 As shown, the second surface 220b of the second prefabricated substrate 220 is etched to form the first prefabricated groove 228a, the second prefabricated groove 228b and the third prefabricated groove 228c and the first opening prefabricated groove 228d and the second opening prefabricated groove 228e in the second prefabricated substrate 229.

[0091] In some embodiments of the present invention, the step of etching the second surface 220b of the second prefabricated substrate 220 includes: Figure 8As shown, a dielectric layer 220a is formed on the second surface 220b of the second prefabricated substrate 220; Fig. 9 and Fig.10 As shown, the prefabricated groove 228 is formed in the second surface 220b of the second prefabricated substrate 220 by means of photolithography (Litho) and etching (Etch).

[0092] It should be noted that Fig.10 yes Fig. 9 The schematic diagram of the top view of the second surface 220b of the second prefabricated substrate 229 in the forming method embodiment is shown; and, Fig.10 The dielectric layer 220a on the second surface 220b of the second prefabricated substrate 220 is not shown in the figure for clarity.

[0093] In some embodiments of the present invention, the forming method further comprises: forming a through silicon via TSV2 (such as Fig.18 Specifically, the step of forming the through silicon via TSV2 in the second substrate 220 includes: forming a prefabricated opening in the second prefabricated substrate 229 .

[0094] The prefabricated opening can provide a basis for the formation of the through silicon via. For example, Fig. 9 and Fig.10 In some of the illustrated embodiments, in the step of forming the prefabricated groove 228 in the second surface 220b, the second surface 220b of the second prefabricated substrate 229 is etched to form the prefabricated groove 228 and the prefabricated opening TSVO located in the second surface 220b, that is, the preset pattern is transferred to the second prefabricated substrate 229 through the same photolithography and etching process to form the prefabricated groove 228 and the prefabricated opening TSVO.

[0095] In some embodiments, a through silicon via TSV2 (eg, Fig.13 The steps shown in FIG. 1 also include: Fig.11 As shown, a sacrificial material is filled in the prefabricated groove 228 and the prefabricated opening TSVO ( Fig.11 as shown in yellow fill in the middle); Fig.12 As shown, the sacrificial material 123 in the prefabricated opening TSVO is removed to expose the prefabricated opening TSVO; and a through silicon via TSV2 is formed in the exposed prefabricated opening TSVO.

[0096] The pre-grooves 228 and the pre-opening TSVO are formed in the same process; therefore, sacrificial materials are filled in the pre-grooves 228 and the pre-opening TSVO to process the pre-grooves 228 and the pre-opening TSVO separately.

[0097] Specifically, the sacrificial material may be a dielectric material, such as an oxide. The step of filling the prefabricated groove 228 and the prefabricated opening TSVO with the sacrificial material includes: filling the prefabricated groove 228 and the prefabricated opening TSVO with the sacrificial material, wherein the filling material also extends to the second surface 220b of the second prefabricated substrate 229; and planarizing the filling material so that the top of the filling material in the prefabricated groove 228 and the prefabricated opening TSVO is flush with the second surface 220b of the second prefabricated substrate 220.

[0098] For example, in the step of filling the prefabricated groove 228 and the prefabricated opening TSVO with sacrificial material, the sacrificial material can be filled by deposition methods such as physical vapor deposition, chemical vapor deposition and atomic layer deposition; in the step of planarizing the filling material, the filling material can be planarized by etching or grinding (such as chemical mechanical grinding).

[0099] The step of removing the sacrificial material 123 in the pre-formed opening TSVO to expose the pre-formed opening TSVO provides a process basis for forming a through silicon via TSV.

[0100] Specifically, in the step of removing the sacrificial material in the prefabricated opening TSVO, the sacrificial material in the prefabricated opening TSVO may be removed by etching. Fig.12 As shown, the step of removing the sacrificial material in the prefabricated opening TSVO includes: sequentially forming a dielectric layer 228a and a graphic layer 228b on the second surface 220b of the second prefabricated substrate 229, wherein the dielectric layer 228a and the graphic layer 228b have an opening 228c, the dielectric layer 228a and the graphic layer 228b cover the sacrificial material in the prefabricated groove 228, and the bottom of the opening 228c exposes the sacrificial material in the prefabricated opening TSVO; using the dielectric layer 228a and the graphic layer 228b as a mask, etching the sacrificial material in the prefabricated opening TSVO to remove the sacrificial material in the prefabricated opening TSVO and expose the prefabricated opening TSVO.

[0101] Among them, the dielectric layer 228a can be a silicon nitride layer, and the graphic layer 228b can be a photoresist layer; in other embodiments, the dielectric layer 228a can also be other dielectric layers such as a silicon oxide layer, a silicon oxynitride layer, etc.; the graphic layer 228b can also be other graphic layers.

[0102] like Fig.13 As shown, in some embodiments, the step of forming a through silicon via TSV2 in the exposed pre-formed opening TSVO includes: forming a linear layer in the pre-formed opening TSVO; and filling metal in the pre-formed opening TSVO with the linear layer formed therein.

[0103] Specifically, the linear layer can be formed by deposition or furnace tube, etc.; the material of the linear layer can be a dielectric material, such as oxide; in other embodiments, the material of the linear layer can also be other dielectric materials such as nitride and nitride oxide.

[0104] Specifically, metal can be filled into the prefabricated open-hole TSVO with a linear layer by deposition or electroplating; the step of filling the prefabricated open-hole TSVO with metal includes: filling the prefabricated open-hole TSVO with a linear layer with metal material, and the metal material also extends to the second surface 220b of the second prefabricated substrate 229; planarizing the metal material, for example, by etching or grinding (for example, chemical mechanical grinding), so that the top of the metal in the prefabricated open-hole TSVO is flush with the second surface 220b of the second prefabricated substrate 220.

[0105] It should be noted that, in some embodiments of the present invention, the forming method further comprises: forming a bonding connection layer 230 located on the second surface of the second substrate. Fig.14 As shown, in some embodiments, after forming the through silicon via TSV2, a bonding connection layer 230 is formed on the second surface 220b of the second prefabricated substrate 229, and the bonding connection layer 230 is electrically connected to the through silicon via TSV2.

[0106] For example, in some embodiments, the step of forming the bonding connection layer 230 on the second surface 220b of the second prefabricated substrate 229 includes: forming internal wiring INM on the second surface 220b of the second prefabricated substrate 229; and forming a redistribution structure RDL on the surface of the internal wiring INM.

[0107] It should be noted that, in the step of forming the internal wiring INM on the second surface 220b of the second prefabricated substrate 229, a dielectric material is formed to cover the sacrificial material in the prefabricated groove 228. In some embodiments, the step of forming the internal wiring INM on the second surface 220b of the second prefabricated substrate 229 includes: forming a dielectric material covering the entire second surface 220b of the second prefabricated substrate 229; forming a via structure in the dielectric material, one end of the via structure is in contact with the through silicon via TSV2; forming a bottom metal (not shown in the figure) in the internal wiring INM on the surface of the dielectric material, the bottom metal is in contact with the via structure to achieve electrical connection with the internal wiring INM, wherein the bottom metal is the metal closest to the second substrate 120 in the metal wiring of the bonding connection layer 130.

[0108] In other embodiments of the present invention, the step of forming the internal wiring INM on the second surface 220b of the second prefabricated substrate 229 may also include: directly forming the underlying metal on the second surface 220b of the second prefabricated substrate 229, the underlying metal directly contacting the through silicon via in the second prefabricated substrate 229, and the underlying metal avoiding the position corresponding to the prefabricated groove 228; forming a dielectric material on the second surface 220b of the second prefabricated substrate 229 covering the underlying metal and the position corresponding to the prefabricated groove 228.

[0109] refer to Figures 15 to 18 In some embodiments of the present invention, the step of forming the second substrate 230 further includes: forming the second prefabricated substrate 229 (such as Fig.15 The first surface 220a of the second prefabricated substrate 229 is thinned, and the first surface 220a of the second prefabricated substrate 229 is arranged opposite to the second surface 220b of the second prefabricated substrate 229; after thinning, the first surface 220a of the second prefabricated substrate 229 forms a first upper interface 222 and a second upper interface 223 connected to the prefabricated groove 228, forming the chip flow channel 221.

[0110] By the second prefabricated substrate 229 (such as Fig.15 The step of thinning the second prefabricated substrate 229 on the first surface 220a of the substrate 220a can reduce the difficulty of forming the first upper interface 222 and the second upper interface 223.

[0111] In some embodiments, a through silicon via TSV2 is further formed in the second prefabricated substrate 229; Fig.15 As shown, in the step of thinning the second prefabricated substrate 229 through the first surface 220 a of the second prefabricated substrate 229 , after forming the through-silicon TSV2 holes, the second prefabricated substrate 229 is thinned through the first surface 220 a of the second prefabricated substrate 229 .

[0112] In some embodiments, a bonding layer 230 is further formed on the second surface 220b of the second prefabricated substrate 229; Fig.15 As shown, in the step of thinning the second prefabricated substrate 229 through the first surface 220 a of the second prefabricated substrate 229 , after forming the bonding connection layer 230 , the second prefabricated substrate 229 is thinned through the first surface 220 a of the second prefabricated substrate 229 .

[0113] Specifically, Fig.15As shown, the step of thinning the second prefabricated substrate 229 through the first surface 220a of the second prefabricated substrate 229 includes: bonding a carrier wafer on the surface of the bonding layer 230 facing away from the second prefabricated substrate 229; forming a second prefabricated substrate 229 with a bonding layer 223 by inverting the carrier wafer; and etching or grinding the first surface 220a of the second prefabricated substrate 229 to thin the second prefabricated substrate 229.

[0114] After the second prefabricated substrate 229 is thinned, the first upper interface 222 and the second upper interface 223 are formed on the first surface 220 a of the second prefabricated substrate 229 to form the chip flow channel 221 .

[0115] In some embodiments, a through silicon via TSV2 is further formed in the second prefabricated substrate 229, and the prefabricated groove 228 is filled with a sacrificial material, wherein the prefabricated groove 228 includes: a first prefabricated groove 228a, a second prefabricated groove 228b, and a third prefabricated groove 228c, and a first opening prefabricated groove 228d and a second opening prefabricated groove 228e; the steps of forming the first upper interface 222 and the second upper interface 223 on the first surface 220a of the second prefabricated substrate 229 include: Fig.15 and Fig.16 As shown, a protective layer 227 is formed on the first surface 220a, and the protective layer 227 covers the first prefabricated groove 228a, the second prefabricated groove 228b and the third prefabricated groove 228c, and exposes the first opening prefabricated groove 228d and the second opening prefabricated groove 228e; using the protective layer 227 as a mask, etching is performed on the exposed first surface 220a of the second prefabricated substrate 229 to form two pre-openings (not shown in the figure) in the first surface 220a, the bottom of one pre-opening exposes the sacrificial material in the first opening prefabricated groove 228d, and the bottom of the other pre-opening exposes the sacrificial material in the second opening prefabricated groove 228e; through the two pre-openings, the sacrificial materials in the first opening prefabricated groove 228d and the second opening prefabricated groove 228e are removed to form the first upper interface 222 and the second upper interface 223, respectively.

[0116] In some embodiments, the prefabricated groove 228 is filled with a sacrificial material, and the first prefabricated groove 228a, the second prefabricated groove 228b and the third prefabricated groove 228c are also filled with a sacrificial material; the step of forming the second substrate 220 further includes: in the process of forming the first upper interface 222 and the second upper interface 223 connected to the prefabricated groove 228 on the first surface 220a of the thinned second prefabricated substrate 229, removing the sacrificial material in the prefabricated groove 228 to form the chip flow channel 421

[0117] For example, in the step of removing the sacrificial material in the first opening prefabricated groove 228d and the second opening prefabricated groove 228e through the two pre-openings, the sacrificial material in the prefabricated groove 228 is removed through the two pre-openings, that is, the sacrificial material filled in the first opening prefabricated groove 228d and the second opening prefabricated groove 228e and the first prefabricated groove 228a, the second prefabricated groove 228b and the third prefabricated groove 228c is removed.

[0118] Specifically, Fig.16 and Fig.17 As shown, the sacrificial materials in the first prefabricated groove 228a, the second prefabricated groove 228b and the third prefabricated groove 228c are removed through the first upper interface 222 and the second upper interface 223 to form the first chip flow channel 221a, the second chip flow channel 221b and the third chip flow channel 221c respectively.

[0119] refer to Fig.18 and Fig.19 The forming method further includes: disposing the second substrate 220 on the first substrate 210 , and connecting the chip flow channel 221 with the substrate flow channel 211 .

[0120] Specifically, in the step of disposing the second substrate 220 on the first substrate 210 , the first surface 220 a of the second substrate 220 and the first surface 210 a of the first substrate 210 are welded relative to each other to achieve connection between the first substrate 210 and the second substrate 220 .

[0121] In the step of setting the second substrate 220 on the first substrate 210, the first upper interface 222 on the first surface 220a of the second substrate 220 and the first lower interface 212 on the first surface 210a of the first substrate 210 are relatively connected, and the second upper interface 223 on the first surface 220a of the second substrate 220 and the second lower interface 213 on the first surface 210a of the first substrate 210 are relatively connected, thereby realizing the connection between the chip flow channel 221 and the substrate flow channel 211.

[0122] In some embodiments of the present invention, the forming method further comprises: forming an interconnection layer 240 on the first surface 220a of the second substrate 220. Fig.18 As shown, in some embodiments, after the chip flow channel 221 is formed, an interconnection layer 240 is formed on the first surface 220 a of the second substrate 220 .

[0123] For example, in some embodiments, a through silicon via TSV2 is formed in the second substrate 220 ; after the through silicon via TSV2 is formed, an interconnection layer 240 is formed on the first surface 220 a of the second substrate 220 , and the interconnection layer 240 is electrically connected to the through silicon via TSV2 .

[0124] Specifically, the step of forming the interconnection layer 240 on the first surface 220 a of the second substrate 220 includes: forming a connection bump on the first surface 220 a of the second substrate 220 , wherein one end of the connection bump is in contact with the through silicon via TSV2 .

[0125] It should be noted that the step of forming the interconnection layer 240 on the first surface 220 a of the second substrate 220 further includes: forming a dielectric material filled between adjacent connection bumps.

[0126] Specifically, the formation method also includes: before forming the interconnection layer 240 on the first surface 220a of the second substrate 220, forming a filling material in the first upper interface 222 and the second upper interface 223; after forming the filling material, forming the interconnection layer 240 on the first surface 220a of the second substrate 220; after forming the interconnection layer 240, forming two interconnection openings (not shown in the figure) in the dielectric material of the interconnection layer 240, the two interconnection openings respectively corresponding to the positions of the first upper interface 222 and the second upper interface 223, the bottom of one interconnection opening exposes the filling material in the first upper interface 222, and the bottom of the other interconnection opening exposes the filling material in the second upper interface 223; removing the filling material in the first upper interface 222 and the second upper interface 223 to expose the first upper interface 222 and the second upper interface 223.

[0127] like Fig.19 As shown, in the step of disposing the second substrate 220 on the first substrate 210, the surface of the interconnection layer 240 and the first surface 210a of the first substrate 210 are welded relative to each other, so that the connection bumps 240 in the interconnection layer 240 are welded relative to the electrical contact points 214 of the first surface 210a of the first substrate 210, and the dielectric material of the interconnection layer 240 is bonded relative to the first surface 210a of the first substrate 210 by fusion bonding, thereby realizing the connection between the second substrate 220 and the first substrate 210.

[0128] In addition, the present invention also provides a storage device.

[0129] refer to Fig. 20 , the storage device comprises:

[0130] A circuit board 301 ; a base structure 302 , the base structure 302 being located on the circuit board 301 , and the base structure 302 being the base structure of the present invention; and a memory structure 303 , the memory structure 303 being located on the base structure 302 .

[0131] The substrate flow channel 311 of the first substrate 310 and the chip flow channel 321 of the second substrate 320 in the substrate structure 302 are connected, and the substrate flow channel 311 and the chip flow channel 321 are suitable for providing circulation of cooling liquid; the substrate structure 302 has good heat dissipation capability; the cooling liquid flowing through the substrate structure 302 can dissipate the heat generated by the memory structure 303 more efficiently, and the overall heat dissipation capability of the storage device is higher.

[0132] The circuit board 301 is suitable for realizing the connection between the storage device and an external circuit.

[0133] Specifically, in some embodiments, the circuit board 301 may be a printed circuit board (Printed Circuit Board, PCB); in other embodiments, the circuit board may also be a flexible circuit board (Flexible Printed Circuit, FPC).

[0134] The base structure 302 is fixed to the surface of the circuit board 301 .

[0135] The substrate structure 302 is the substrate structure of the present invention. The specific technical solution of the substrate structure can refer to the technical solution of the aforementioned substrate structure embodiment, and the present invention will not repeat it here.

[0136] In some embodiments of the present invention, the storage device further includes: an external solder ball 305, which is located between the base structure 302 and the circuit board 301. The external solder ball 305 can realize electrical connection between the base structure 302 and the circuit board 301.

[0137] Specifically, one end of the external solder ball 305 contacts the external solder pad on the second surface 310 b of the first substrate 310 in the base structure 302 , and the other end is connected to a circuit connection point (not shown) on the circuit board 301 .

[0138] The memory structure 303 is suitable for storing data.

[0139] The memory structure 303 is located on the base structure 302 , that is, the base structure 302 is located between the memory structure 303 and the circuit board 301 , which can realize the connection between the memory structure 303 and the circuit board 301 , and can also realize the electrical connection between the memory structure 303 and the circuit board 301 .

[0140] In the base structure 302, the substrate flow channel 311 and the chip flow channel 321 are connected, and the substrate flow channel 311 and the chip flow channel 321 can provide circulation of cooling liquid; the base structure 302 has a strong heat dissipation capacity, and the cooling liquid flowing through the base structure 302 can dissipate the heat generated by the memory structure 303 more efficiently, so as to improve the overall heat dissipation capacity of the storage device.

[0141] In some embodiments of the present invention, the first substrate is located between the second substrate and the circuit board; the memory structure is located on the side of the second substrate away from the first substrate. The second substrate is located between the first substrate and the memory structure, so that the coolant flowing in the chip flow channel is closer to the memory structure, which can better achieve the dissipation of heat generated by the memory structure.

[0142] In some embodiments of the present invention, the memory structure 303 includes: a stacked system-on-chip chip SOC and a memory chip ROM. Specifically, the system-on-chip chip SOC is connected to at least one of the memory chips ROM.

[0143] like Fig. 20 In some of the embodiments shown, the memory structure 303 has a plurality of memory chips ROM, and the plurality of memory chips ROM are stacked and bonded; the system-on-chip chip SOC is bonded and connected to the plurality of stacked and bonded memory chips ROM.

[0144] In addition, the memory structure 303 further includes: an auxiliary logic chip AUX, wherein the auxiliary logic chip AUX is located between the system-on-chip chip SOC and the memory chip ROM. Fig. 20 As shown, the auxiliary logic chip AUX is located between the system-on-chip chip SOC and all memory chips ROM, that is, one side of the auxiliary chip AUX is bonded to the system-on-chip chip SOC, and the other side is bonded to the bottom memory chip ROM, wherein the bottom memory chip ROM is the memory chip ROM closest to the system-on-chip chip SOC among multiple stacked and bonded memory chip ROMs.

[0145] In some embodiments, the base structure 302 further includes: a bonding connection layer 330, wherein the bonding connection layer 330 is located on a side of the second substrate 320 away from the first substrate 310; and the connection between the memory structure 303 and the base structure 302 is achieved through the bonding connection between the bonding connection layer 330 and the memory structure 303.

[0146] In some embodiments, the system-on-chip chip SOC is located between the memory chip ROM and the substrate structure 302. During the operation of the storage device, the system-on-chip chip SOC generates more heat. Placing the system-on-chip chip SOC between the memory chip ROM and the substrate structure 302 can make the heat dissipation path of the system-on-chip chip SOC smoother, which can effectively improve the heat dissipation problem of the storage device.

[0147] Specifically, Fig. 20 As shown, the surface of the bonding connection layer 330 in the base structure 302 facing away from the second substrate 320 is bonded to the surface of the system on chip SOC facing away from all memory chips ROM.

[0148] In some embodiments of the present invention, the storage device further includes: a plastic sealant 304 , wherein the plastic sealant 304 is located on the first substrate 310 and covers the memory structure 303 and the second substrate 320 .

[0149] Specific as Fig. 20 As shown, the plastic encapsulation adhesive 304 covers the top surface and sidewall surfaces of the memory structure 302 and extends to the sidewalls of the second substrate 320 in the base structure 302 until it contacts the first surface 310 a of the first substrate 310 .

[0150] The plastic sealant 304 at least exposes the first opening 310i and the second opening 310o on the first surface 310a of the first substrate 310 to achieve the connection between the substrate flow channel 310 and the external flow channel.

[0151] In some embodiments, the storage device further includes: a first flow tube (not shown in the figure) and a second flow tube (not shown in the figure), the first flow tube is connected to the first opening 310i; the second flow tube is connected to the second opening 310o to reduce the difficulty of connecting the substrate flow channel with the external flow channel.

[0152] In addition, the present invention also provides an electronic device.

[0153] The electronic device comprises: a storage device, which is the storage device of the present invention; and a cooling liquid, which flows in a chip flow channel and a substrate flow channel that are connected.

[0154] The storage device is the storage device of the present invention. The specific technical solution of the storage device can refer to the technical solution of the aforementioned storage device embodiment, and the present invention will not be repeated here.

[0155] The cooling liquid flows through the chip flow channel and the substrate flow channel to achieve the dissipation of heat generated by the storage device.

[0156] In some embodiments, in the storage device, one of the first opening 310i and the second opening 310o is a liquid inlet, and the other is a liquid outlet; the coolant flows into the first substrate flow channel 311a from the liquid inlet, and flows into the chip flow channel 321 through the first substrate flow channel 310a; after flowing through all the chip flow channels 321, the coolant flows back into the second substrate flow channel 311b, passes through the second substrate flow channel 311b, and flows out from the liquid outlet.

[0157] In some embodiments, the coolant may be water; in other embodiments of the present invention, the coolant may also be a liquid with a considerable specific heat capacity to achieve a cooling effect.

[0158] In some embodiments of the present invention, the electronic device further comprises: a circulation device, the circulation device is connected to the substrate flow channel, and the circulation device is suitable for controlling the flow of the cooling liquid.

[0159] Specifically, the circulation device is connected to the liquid inlet and the liquid outlet of the storage device to drive the coolant to flow in the substrate flow channel and the chip flow channel. For example, the circulation device can be connected to the liquid inlet and the liquid outlet through a first flow tube and a second flow tube, respectively.

[0160] Correspondingly, the present invention also provides a method for manufacturing a storage device.

[0161] refer to Figure 21 to Figure 26 As shown, the manufacturing method comprises:

[0162] A base structure is formed, wherein the base structure is the base structure of the present invention; a memory structure is formed; the memory structure is bonded to a second substrate of the base structure; and the base structure bonded to the memory structure is mounted to a circuit board.

[0163] In some embodiments of the present invention, the manufacturing method can manufacture the storage device of the present invention. The specific technical solution of the manufacturing method can refer to the above-mentioned embodiment of the storage device, and the present invention will not be repeated here.

[0164] The base structure is the base structure of the present invention. The specific technical solution of the base structure can refer to the embodiment of the aforementioned base structure, and the present invention will not be repeated here.

[0165] In some embodiments of the present invention, the step of forming a base structure includes: forming a first substrate having a substrate flow channel therein; forming a second substrate having a chip flow channel therein; and arranging the second substrate on the first substrate and connecting the chip flow channel to the substrate flow channel.

[0166] Specifically, in the step of forming the base structure, the base structure can be formed by using the base structure forming method of the present invention. The specific technical scheme of the step of forming the base structure can refer to the aforementioned base structure forming method, and the present invention will not repeat it again.

[0167] For example, Figure 6 and Figure 7 As shown, the step of forming the first substrate 210 includes: providing a first prefabricated substrate; and forming the substrate flow channel 211 in the first prefabricated substrate to form the first substrate 210 .

[0168] In some embodiments, the step of forming the second substrate includes: Figure 8 As shown, a second prefabricated substrate 229 is provided, wherein the second prefabricated substrate 229 has a first surface 220a and a second surface 220b disposed opposite to each other; Figures 9 to 14 As shown, the second surface 220b of the second prefabricated substrate 229 is etched to form a prefabricated groove 228 in the second surface 220b; Fig.21 and Fig. 22 As shown, the second prefabricated substrate 429 is thinned by the first surface 420a of the second prefabricated substrate 429, and the first surface 420a of the second prefabricated substrate 429 is arranged opposite to the second surface 420b of the second prefabricated substrate 429; as shown Fig.23 As shown, after thinning, the first surface 420a of the second prefabricated substrate 429 forms a groove 428 (such as Fig. 22 The first upper interface 422 and the second upper interface 423 are connected to form the chip flow channel 421.

[0169] Specifically, the steps of providing the second prefabricated substrate 229 and the specific technical solutions for forming the prefabricated groove 228 in the second surface 220 b may refer to the aforementioned method for forming the substrate structure, and the present invention will not be repeated again.

[0170] In some embodiments, Fig.21 As shown, after the prefabricated groove 228 is formed in the second surface 420b, as shown in Fig. 22 As shown, before thinning the second prefabricated substrate 429 through the first surface 420 a of the second prefabricated substrate, the memory structure 403 is bonded to the second substrate of the base structure 402 .

[0171] For example, the manufacturing method can manufacture the storage device of the present invention. The specific technical solution of the memory structure 403 can refer to the embodiment of the aforementioned storage device, and the present invention will not be repeated here.

[0172] Specifically, the step of forming the memory structure 403 includes: stacking and bonding a system on chip SOC and at least one memory chip ROM.

[0173] Specifically, Fig.21 As shown, after the prefabricated groove 428 is formed in the second surface 420b, a bonding connection layer 430 is also formed on the second surface 402b of the second prefabricated substrate 429; in the step of bonding the memory structure 403 to the second substrate of the base structure 402, the system-on-chip chip SOC in the memory structure 403 is bonded relative to the bonding connection layer 430 on the second surface 402b of the second prefabricated substrate 429.

[0174] For example, in the step of bonding the memory structure 403 to the second substrate of the base structure 402 , the memory structure 403 to the second substrate of the base structure 402 may be bonded to each other by fusion bonding.

[0175] Specifically, Fig. 22 As shown, after the memory structure 403 is bonded to the second substrate of the base structure 402 , the second prefabricated substrate 429 is thinned through the first surface 420 a of the second prefabricated substrate.

[0176] For example, the step of thinning the second prefabricated substrate through the first surface 420a of the second prefabricated substrate 429 includes: bonding a carrier wafer on a side of the bonding connection layer 430 away from the second prefabricated substrate 429; reversely bonding the base structure 402 with the memory structure 403 through the carrier wafer; and etching or grinding the first surface 420a of the second prefabricated substrate 429 to thin the second prefabricated substrate 429.

[0177] Specific as Fig. 22 and Fig.23 As shown, after the second prefabricated substrate 429 is thinned, the first upper interface 422 and the second upper interface 423 are formed on the first surface 420 a of the second prefabricated substrate 429 to form the chip flow channel 421 .

[0178] In some embodiments, the second prefabricated substrate 429 further has a through silicon via TSV4 formed therein, and the prefabricated trench 428 is filled with a sacrificial material (such as Fig. 22As shown), wherein the prefabricated groove 428 includes: a first opening prefabricated groove and a second opening prefabricated groove, one of the positions of the first opening prefabricated groove and the second opening prefabricated groove corresponds to the position of the first upper interface, and the other corresponds to the position of the second upper interface; the steps of forming the first upper interface 422 and the second upper interface 423 on the first surface 420a of the second prefabricated substrate 429 include: as Fig. 22 As shown, the first surface 420a of the second prefabricated substrate 429 is etched to form two pre-openings (not shown in the figure) in the first surface 420a, the bottom of one pre-opening exposes the sacrificial material in the prefabricated groove of the first opening, and the bottom of the other pre-opening exposes the sacrificial material in the prefabricated groove of the second opening; as shown in FIG. Fig.23 As shown, the sacrificial materials in the first opening prefabricated groove and the second opening prefabricated groove are removed through the two pre-openings to form the first upper interface 422 and the second upper interface 423 respectively.

[0179] In some embodiments, the prefabricated groove 428 is filled with a sacrificial material, and the prefabricated groove 428 also includes at least one other prefabricated groove, any of which is connected to the first opening prefabricated groove and the second opening prefabricated groove, and the other prefabricated grooves are also filled with a sacrificial layer; the step of forming the second substrate 420 also includes: in the process of forming a first upper interface 422 and a second upper interface 423 connected to the prefabricated groove 428 on the first surface 420a of the second prefabricated substrate 429 after thinning, removing the sacrificial material in the prefabricated groove 428 to form the chip flow channel 421.

[0180] For example, in the step of removing the sacrificial material in the first opening prefabricated groove and the second opening prefabricated groove through the two pre-openings, the sacrificial material in the prefabricated groove 428 is removed through the two pre-openings, that is, the sacrificial material filled in the first opening prefabricated groove, the second opening prefabricated groove and at least one other prefabricated groove is removed.

[0181] like Fig.24 and Fig.25 As shown, the step of forming the base structure further includes: disposing the second substrate 420 on the first substrate 210 , and connecting the chip flow channel 421 with the substrate flow channel 211 .

[0182] Specifically, Fig.24 As shown, the step of forming the base structure further includes: forming an interconnection layer 440 on the first surface 420a of the second substrate 420. For example, after forming the chip flow channel 421, the interconnection layer 440 is formed on the first surface 420a of the second substrate 420.

[0183] Specifically, the step of forming the interconnection layer 440 on the first surface 420 a of the second substrate 420 includes: forming a connection bump on the first surface 420 a of the second substrate 420 , wherein one end of the connection bump is in contact with the through silicon via TSV4 .

[0184] It should be noted that before the interconnection layer 440 is formed on the first surface 420a of the second substrate 420, a filling material is formed in the first upper interface 422 and the second upper interface 423; after the filling material is formed, the interconnection layer 440 is formed on the first surface 420a of the second substrate 420; after the interconnection layer 440 is formed, two interconnection openings are formed in the dielectric material of the interconnection layer 440 to remove the filling material and expose the first upper interface 422 and the second upper interface 423.

[0185] Specifically, Fig.25 As shown, in the step of disposing the second substrate 420 on the first substrate 210 , the surface of the interconnection layer 440 and the first surface 210 a of the first substrate 210 are welded relative to each other, thereby achieving connection between the second substrate 420 and the first substrate 210 to form the base structure 420 .

[0186] After the steps of forming the base structure 402 and forming the memory structure 403 , the manufacturing method further includes: bonding the memory structure 403 to the second substrate 420 of the base structure 402 .

[0187] In some embodiments of the present invention, after the prefabricated groove 228 is formed in the second surface 420b, before the second prefabricated substrate 429 is thinned through the first surface 420a, the memory structure 403 is bonded to the second substrate of the base structure 402, that is, in the step of setting the second substrate 420 on the first substrate 210, the memory structure 403 is bonded to the other side of the second substrate 420 set on the first substrate 210; while the second substrate 420 is set on the first substrate 210 to form the base structure 403, the memory structure 403 is bonded to the second substrate 420 of the base structure 402.

[0188] Continue to refer Fig.25 In some embodiments of the present invention, the manufacturing method further includes: after bonding the memory structure to the second substrate of the base structure, forming a plastic encapsulation glue 404, wherein the plastic encapsulation glue 404 is located on the first substrate 210 and covers the memory structure 403 and the second substrate 420.

[0189] For example, in the step of forming the plastic encapsulation glue 404, the plastic encapsulation glue 404 can be formed by injection molding; and in some embodiments, the manufacturing method also includes: before forming the plastic encapsulation glue 404, installing a first flow tube (not shown in the figure) and a second flow tube (not shown in the figure), the first flow tube is connected to the first opening 210i; the second flow tube is connected to the second opening 210o.

[0190] The manufacturing method further includes: mounting the base structure 402 on a circuit board 401 .

[0191] In some embodiments of the present invention, before the base structure 402 is installed on the circuit board 401, the memory structure 403 is bonded to the second substrate 420 of the base structure 402. That is, in the step of installing the base structure 402 on the circuit board 401, the base structure 402 bonded to the memory structure 403 is installed on the circuit board 401.

[0192] Specifically, an external solder ball 405 is formed on the surface of the base structure 402 facing away from the memory structure 403; in the step of installing the base structure 402 to the circuit board 401, the external solder ball 405 is welded to a circuit connection point (not shown) on the circuit board 301.

[0193] In the step of forming the external solder balls 405 on the surface of the base structure 402 facing away from the memory structure 403 , the external solder balls 405 are formed on the surface of the external pads on the second surface 210 b of the first substrate 210 in the base structure 402 .

[0194] In summary, the substrate flow channel of the first substrate and the chip flow channel of the second substrate in the substrate structure are connected, and the substrate flow channel and the chip flow channel are suitable for providing the circulation of cooling liquid; when the cooling liquid flows through the substrate structure, heat dissipation can be achieved more efficiently, that is, the heat dissipation efficiency of the substrate structure is higher, and the use of the substrate structure can effectively improve the heat dissipation capacity of the electronic device and can effectively improve the heat dissipation capacity of the storage device.

[0195] Moreover, the chip flow channel is an open structure without a bottom surface on the side close to the second surface of the second substrate; the second surface of the second substrate is suitable for setting a memory structure, and the chip flow channel is set as an open structure without a bottom surface on the side close to the second surface of the second substrate, so that the coolant flowing in the chip flow channel can directly contact the structure of the second substrate away from the first substrate side, which can better achieve heat dissipation and enable the base structure to have better heat dissipation capacity.

[0196] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for forming a base structure, characterized in that: forming a first substrate having a substrate flow channel therein; forming a second substrate, wherein the second substrate has a chip flow channel; The second substrate is disposed on the first substrate, and the chip flow channel is connected with the substrate flow channel.

2. The forming method according to claim 1, characterized in that: The step of forming the second substrate includes: providing a second prefabricated substrate, the second prefabricated substrate having a first surface and a second surface disposed opposite to each other; The second surface of the second prefabricated substrate is etched to form a prefabricated groove in the second surface to form the second substrate.

3. The forming method according to claim 2, characterized in that: The step of forming the second substrate further includes: thinning the second prefabricated substrate through the first surface of the second prefabricated substrate, the first surface of the second prefabricated substrate being disposed opposite to the second surface of the second prefabricated substrate; After thinning, a first upper interface and a second upper interface communicating with the prefabricated groove are formed on the first surface of the second prefabricated substrate to form the chip flow channel.

4. The forming method according to claim 1, characterized in that: Also includes: A through silicon via is formed in the second substrate.

5. The forming method according to claim 4, characterized in that: In the step of forming a prefabricated groove, the second surface of the second prefabricated substrate is etched to form a prefabricated groove and a prefabricated opening located in the second surface; The step of forming a through silicon via in the second substrate further comprises: Filling the prefabricated groove and the prefabricated opening with a sacrificial material; removing the sacrificial material in the prefabricated opening to expose the prefabricated opening; A through silicon via is formed in the exposed preformed opening.

6. The forming method according to claim 5, characterized in that: The step of forming the second substrate also includes: after forming a first upper interface and a second upper interface communicating with the prefabricated groove on the first surface of the thinned second prefabricated substrate, removing the sacrificial material in the prefabricated groove to form the chip flow channel.

7. The forming method according to claim 1, characterized in that: Also includes: A bonding layer is formed on the second surface of the second substrate.

8. The forming method according to claim 7, characterized in that: After forming the through silicon via, a bonding layer is formed on the second surface of the second prefabricated substrate, wherein the bonding layer is electrically connected to the through silicon via.

9. The forming method according to claim 7, characterized in that: After forming the through silicon via, the second prefabricated substrate is thinned through the first side of the second prefabricated substrate.

10. The forming method according to claim 1, characterized in that: Also includes: An interconnection layer is formed on the first surface of the second substrate.

11. The forming method according to claim 10, characterized in that: After forming the chip flow channel, an interconnection layer is formed on the first surface of the second substrate.

12. The forming method according to claim 10, characterized in that: After forming the through silicon via, an interconnection layer is formed on the first surface of the second substrate, and the interconnection layer is electrically connected to the through silicon via.

13. The forming method according to claim 1, characterized in that: The step of forming the first substrate includes: providing a first prefabricated substrate; and forming the substrate flow channel in the first prefabricated substrate to form the first substrate.

14. The forming method according to claim 13, characterized in that: In the step of forming the substrate flow channel in the first prefabricated substrate to form the first substrate, the substrate flow channel is formed in the first prefabricated substrate by laser engraving.

15. A base structure, characterized in that: include: a first substrate having a substrate flow channel; The second substrate has a chip flow channel, and the chip flow channel is connected with the substrate flow channel.

16. The base structure according to claim 15, characterized in that The chip flow channel is an open structure without a bottom surface on a side close to the second surface of the second substrate; and the substrate flow channel is a closed structure with a bottom surface on a side close to the first surface of the second substrate.

17. The base structure according to claim 15, characterized in that The substrate flow channel is a closed structure having a bottom surface on a side close to the first surface of the first substrate and a side close to the second surface of the first substrate.

18. The base structure according to claim 15, characterized in that The first surface of the first substrate has a first opening, a second opening, a first lower interface and a second lower interface, the first opening and the first lower interface are connected through a first substrate flow channel, and the second opening and the second lower interface are connected through a second substrate flow channel; The first surface of the second substrate has a first upper interface and a second upper interface, the first upper interface and the second upper interface are connected through the chip flow channel, the first upper interface and the first lower interface are correspondingly connected, and the second upper interface and the second lower interface are correspondingly connected.

19. The base structure according to claim 18, characterized in that The first upper interface has the same shape as the first lower interface; the second upper interface has the same shape as the second lower interface.

20. The base structure according to claim 15, characterized in that Also includes: A bonding connection layer is located on the second surface of the second substrate, and the second surface is arranged opposite to the first surface.

21. The base structure according to claim 15, characterized in that Also includes: A through silicon via (TSV) passes through the second substrate.

22. The substrate structure according to claim 21, characterized in that The chip flow channel surrounds the through silicon via.

23. The substrate structure according to claim 21, characterized in that The chip flow channel is located between the through silicon vias.

24. The base structure according to claim 15, characterized in that Also includes: An interconnection layer, the interconnection layer is located on the first surface of the second substrate, the interconnection layer has a connection bump, and the connection bump is electrically connected to the through silicon via; The first substrate further has metal wiring, and the metal wiring is electrically connected to the connection bump.

25. The base structure according to claim 24, characterized in that An external pad is provided on the second surface of the first substrate, and the metal wiring connects the connection bump and the external pad.

26. A method for manufacturing a storage device, characterized in that: include: forming a memory structure; forming a substrate structure as claimed in any one of claims 15 to 25; Bonding the memory structure to a second substrate of the base structure; The base structure is mounted to a circuit board.

27. The manufacturing method according to claim 26, characterized in that: In the step of mounting the substrate structure on a circuit board, the substrate structure bonded to the memory structure is mounted on the circuit board.

28. The manufacturing method according to claim 26, characterized in that: The step of forming a base structure includes: forming a first substrate having a substrate flow channel therein; forming a second substrate, wherein the second substrate has a chip flow channel; The second substrate is disposed on the first substrate, and the chip flow channel is connected with the substrate flow channel.

29. The manufacturing method according to claim 28, characterized in that: The step of forming the second substrate includes: providing a second prefabricated substrate, the second prefabricated substrate having a first surface and a second surface disposed opposite to each other; etching the second surface of the second prefabricated substrate to form a prefabricated groove in the second surface; thinning the second prefabricated substrate through the first surface of the second prefabricated substrate, the first surface of the second prefabricated substrate being disposed opposite to the second surface of the second prefabricated substrate; After thinning, a first upper interface and a second upper interface communicating with the prefabricated groove are formed on the first surface of the second prefabricated substrate to form the chip flow channel.

30. The manufacturing method according to claim 29, characterized in that: After forming the prefabricated groove in the second surface and before thinning the second prefabricated substrate through the first surface of the second prefabricated substrate, the memory structure is bonded to the second substrate of the base structure.

31. A storage device, characterized in that: include: Circuit boards; A substrate structure, the substrate structure being located on the circuit board, the substrate structure being as claimed in any one of claims 15 to 25; A memory structure is located on the base structure.

32. The storage device according to claim 31, wherein: The first substrate is located between the second substrate and the circuit board; The memory structure is located on a side of the second substrate away from the first substrate.

33. The storage device according to claim 31, wherein: The memory structure comprises: a system-on-chip chip and a memory chip which are stacked.

34. The storage device according to claim 33, wherein: The system-on-chip chip is located between the memory chip and the substrate structure.

35. The storage device according to claim 31, characterized in that Also includes: A plastic sealant is located on the first substrate and covers the memory structure and the second substrate.

36. An electronic device, characterized in that: include: A storage device, the storage device being as claimed in any one of claims 31 to 35; A cooling liquid flows in the connected chip flow channel and substrate flow channel.

37. The electronic device according to claim 36, characterized in that Also includes: A circulation device is connected to the substrate flow channel and is suitable for controlling the flow of the cooling liquid.

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