Power converter with spread spectrum control mechanism

Abstract

The invention discloses a power converter with a spread spectrum control mechanism. In the power converter, a buffer circuit determines a plurality of buffer ratios respectively used in a plurality of frequency bands according to a plurality of energy upper limit values respectively in the plurality of frequency bands in a switching frequency range. In a power converter, a buffer circuit buffers a voltage signal from an inductor according to a plurality of buffer ratios, respectively, when switching frequencies of an upper bridge switch and a lower bridge switch are within a plurality of frequency bands, respectively. In the power converter, a turn-on time decision circuit decides the turn-on time of an upper bridge switch and a lower bridge switch according to a buffered output voltage signal.

Description

Technical Field

[0001] The invention relates to a power converter, and in particular to a power converter with a spread spectrum control mechanism. Background Art

[0002] With the rapid development of electronic power technology, electronic devices are increasingly closely related to people's operation and life. Switch components are widely used in various electronic devices, such as power converters. Switch components can operate at higher frequencies, but when switch components operate at higher frequencies, they will cause stronger electromagnetic interference (EMI) signals. This EMI signal will interfere with the power converter, causing the power converter to fail to operate normally and reduce the operating efficiency of the power converter. Summary of the invention

[0003] The technical problem to be solved by the present invention is to provide a power converter with a spread spectrum control mechanism in view of the shortcomings of the prior art. The power converter includes an upper bridge switch, a lower bridge switch, a driving circuit, a control circuit, a buffer circuit and a conduction time determination circuit. The first end of the upper bridge switch is coupled to an input voltage. The first end of the lower bridge switch is connected to the second end of the upper bridge switch. The second end of the lower bridge switch is grounded. The node between the first end of the lower bridge switch and the second end of the upper bridge switch is connected to the first end of an inductor. The driving circuit is connected to the control end of the upper bridge switch and the control end of the lower bridge switch. The control circuit is connected to the driving circuit. The control circuit is configured to control the driving circuit to drive the upper bridge switch and the lower bridge switch to operate. The input end of the buffer circuit is connected to the second end of the inductor. The buffer circuit is configured to determine the multiple buffer ratios of the upper bridge switch and the lower bridge switch when switching in the multiple frequency bands according to the multiple energy upper limit values ​​in the multiple frequency bands within a switching frequency range. The buffer circuit is configured to buffer the voltage of the voltage signal received by the input end of the buffer circuit from the inductor according to the multiple buffer ratios when the switching frequencies of the upper bridge switch and the lower bridge switch are respectively within the multiple frequency bands. The on-time determination circuit is connected to the buffer circuit and the control circuit. The on-time determination circuit is configured to determine the on-time of the upper bridge switch and the lower bridge switch according to the voltage signal buffered by the buffer circuit, so as to output an on-time indication signal. The control circuit controls the drive circuit to drive the upper bridge switch and the lower bridge switch to operate according to the on-time indication signal.

[0004] In an embodiment, the buffer circuit includes a plurality of buffer modulation circuits. Each of the buffer modulation circuits includes a plurality of first transistors. In each of the buffer modulation circuits, a first end of one of the plurality of first transistors is connected to an input end of the buffer circuit, a second end of another of the plurality of first transistors is connected to an input end of the conduction time determination circuit, and a first end of each of the other plurality of first transistors is connected to a second end of an adjacent first transistor. A control end of at least the first transistor in each of the buffer modulation circuits is connected to an oscillator circuit, and a control end of each of the other first transistors is coupled to an operation control voltage.

[0005] In an embodiment, the buffer circuit further includes a first buffer auxiliary circuit, the first buffer auxiliary circuit including a second transistor, a third transistor, a fourth transistor and a fifth transistor. The first end of the second transistor is connected to the input end of the buffer circuit. The first end of the third transistor is connected to the second end of the second transistor. The first end of the fourth transistor is connected to the input end of the buffer circuit. The first end of the fifth transistor is connected to the second end of the fourth transistor and the second end of the third transistor. The second end of the fifth transistor is connected to the input end of the conduction time determination circuit. The control ends of the second transistor, the third transistor and the fourth transistor are respectively coupled to an operation control voltage. The control end of the fifth transistor is coupled to a first reference potential.

[0006] In an embodiment, the buffer circuit further includes a second buffer auxiliary circuit. The second buffer auxiliary circuit includes a sixth transistor and a seventh transistor. The first end of the sixth transistor is connected to the input end of the buffer circuit. The control end of the sixth transistor is coupled to an operation control voltage. The first end of the seventh transistor is connected to the second end of the sixth transistor. The second end of the seventh transistor is coupled to the second reference potential. The control end of the seventh transistor is coupled to the second reference potential.

[0007] In an embodiment, the buffer circuit further comprises a switching transistor. A first terminal of the switching transistor is connected to an input terminal of the buffer circuit. A second terminal of the switching transistor is connected to a control terminal of the sixth transistor, and the control terminal of the switching transistor is coupled to an operation control voltage.

[0008] In an embodiment, the buffer circuit further includes an eighth transistor, a ninth transistor, a tenth transistor and an eleventh transistor. The first end of the eighth transistor is connected to the input end of the buffer circuit. The first end of the ninth transistor is connected to the second end of the eighth transistor. The second end of the ninth transistor is connected to the control end of the sixth transistor. The control end of the ninth transistor is coupled to the second reference potential. The first end of the tenth transistor is connected to the input end of the buffer circuit. The first end of the eleventh transistor is connected to the second end of the tenth transistor. The second end of the eleventh transistor is connected to the control end of the eighth transistor and the control end of the tenth transistor. The control end of the eleventh transistor is coupled to the second reference potential.

[0009] In an embodiment, the buffer circuit further includes a twelfth transistor, a thirteenth transistor, a fourteenth transistor and a fifteenth transistor. The first end of the twelfth transistor is connected to the input end of the buffer circuit. The first end of the thirteenth transistor is connected to the second end of the twelfth transistor. The control end of the thirteenth transistor is coupled to the first reference potential. The first end of the fourteenth transistor is connected to the input end of the buffer circuit, and the control end of the fourteenth transistor is connected to the control end of the twelfth transistor. The first end of the fifteenth transistor is connected to the second end of the fourteenth transistor. The second end of the fifteenth transistor is coupled to the second reference potential. The control end of the fifteenth transistor is connected to the control end of the control end of the thirteenth transistor and coupled to the first reference potential.

[0010] In an embodiment, the buffer circuit further comprises a switching transistor. A first terminal of the switching transistor is connected to an input terminal of the buffer circuit. A second terminal of the switching transistor is connected to a control terminal of the twelfth transistor. The control terminal of the switching transistor is coupled to an operation control voltage.

[0011] In an embodiment, the buffer circuit further includes a sixteenth transistor and a seventeenth transistor. The first end of the sixteenth transistor is connected to the input end of the buffer circuit. The control end of the sixteenth transistor is connected to the control end of the fourteenth transistor. The first end of the seventeenth transistor is connected to the second end of the sixteenth transistor. The second end of the seventeenth transistor is coupled to the first reference potential. The control end of the seventeenth transistor is connected to the control end of the fifteenth transistor.

[0012] In an embodiment, the buffer circuit further includes an eighteenth transistor, a nineteenth transistor, a twentieth transistor, and a twenty-first transistor. The first end of the eighteenth transistor is connected to the second end of the ninth transistor. The first end of the nineteenth transistor is connected to the second end of the eighteenth transistor. The second end of the nineteenth transistor is coupled to the second reference potential. The first end of the twentieth transistor is connected to the second end of the eleventh transistor. The control end of the twentieth transistor is connected to the control end of the eighteenth transistor. The first end of the twenty-first transistor is connected to the second end of the twentieth transistor. The second end of the twenty-first transistor is coupled to the second reference potential. The control end of the twenty-first transistor is connected to the control end of the nineteenth transistor.

[0013] In an embodiment, the buffer circuit further includes a 22nd transistor and a 23rd transistor. The first end of the 22nd transistor is connected to the second end of the 13th transistor. The second end of the 22nd transistor is connected to the first end of the 21st transistor. The control end of the 22nd transistor is connected to the second end of the 7th transistor. The first end of the 23rd transistor is connected to the second end of the 13th transistor. The second end of the 23rd transistor is connected to the first end of the 19th transistor. The control end of the 23rd transistor is coupled to a control potential.

[0014] In an embodiment, the buffer circuit further includes a 24th transistor and a 25th transistor. The first end of the 24th transistor is connected to the second end of the 15th transistor. The control end of the 24th transistor is connected to the control end of the 20th transistor. The first end of the 25th transistor is connected to the second end of the 24th transistor. The second end of the 25th transistor is coupled to the second reference potential. The control end of the 25th transistor is connected to the first end of the 24th transistor.

[0015] In an embodiment, the buffer circuit further comprises a 26th transistor. A first terminal of the 26th transistor is connected to a control terminal of the 24th transistor. A second terminal of the 26th transistor is coupled to the second reference potential. A control terminal of the 26th transistor is coupled to an operation control voltage.

[0016] In an embodiment, the on-time determination circuit further comprises a constant current source, a capacitor and a comparator. The constant current source is coupled to a power supply voltage. The first end of the capacitor is connected to the power supply. The second end of the capacitor is grounded. The first input end of the comparator is connected to the first end of the capacitor. The second input end of the comparator is connected to the output end of the buffer circuit. The output end of the comparator is connected to the input end of the control circuit.

[0017] In an embodiment, the on-time determination circuit comprises a variable current source, a capacitor and a comparator. The control end of the variable current source is connected to the output end of the oscillator circuit. The first end of the capacitor is connected to the output end of the variable current source. The first input end of the comparator is connected to the first end of the capacitor. The second end of the capacitor is grounded. The second input end of the comparator is connected to the output end of the buffer circuit. The output end of the comparator is connected to the input end of the control circuit.

[0018] In an embodiment, the on-time determining circuit comprises a constant current source, a variable capacitor and a comparator. The constant current source is coupled to a power supply voltage. The first end of the variable capacitor is connected to the output end of the constant current source. The second end of the variable capacitor is grounded. The control end of the variable capacitor is connected to the output end of the oscillator circuit. The first input end of the comparator is connected to the first end of the variable capacitor. The second input end of the comparator is connected to the output end of the buffer circuit. The output end of the comparator is connected to the input end of the control circuit.

[0019] In an embodiment, the on-time determination circuit comprises a variable resistor, a capacitor and a comparator. The first end of the variable resistor is coupled to a power supply voltage. The control end of the variable resistor is connected to the output end of the oscillator circuit. The first end of the capacitor is connected to the second end of the variable resistor. The second end of the capacitor is grounded. The first input end of the comparator is connected to the first end of the capacitor. The second input end of the comparator is connected to the output end of the buffer circuit. The output end of the comparator is connected to the input end of the control circuit.

[0020] As described above, the present invention provides a power converter with a spread spectrum control mechanism. In the power converter of the present invention, the switching frequencies of the upper bridge switch and the lower bridge switch are dispersed in a plurality of frequency bands within a frequency range, so as to limit the switching frequencies of the upper bridge switch and the lower bridge switch each time to not exceed an upper limit value, thereby effectively reducing the strength value of the electromagnetic interference (EMI) signal caused by each switching of the upper bridge switch and the lower bridge switch, so that the power converter operates normally and improves the operating efficiency of the power converter.

[0021] To further understand the features and technical contents of the present invention, please refer to the following detailed description and drawings of the present invention. However, the drawings provided are only for reference and description and are not intended to limit the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 FIG. 4 is a circuit diagram of a power converter with a spread spectrum control mechanism according to a first embodiment of the present invention.

[0023] Figure 2 FIG. 4 is a circuit diagram of a power converter with a spread spectrum control mechanism according to a second embodiment of the present invention.

[0024] Figure 3 FIG. 4 is a circuit diagram of a power converter with a spread spectrum control mechanism according to a third embodiment of the present invention.

[0025] Figure 4 FIG. 4 is a circuit diagram of a power converter with a spread spectrum control mechanism according to a fourth embodiment of the present invention.

[0026] Figure 5A A circuit diagram of a buffer circuit using an oscillator in a power converter with a spread spectrum control mechanism according to a fifth embodiment of the present invention.

[0027] Figure 5B A circuit diagram of a buffer circuit using a random number generator in a power converter with a spread spectrum control mechanism according to a sixth embodiment of the present invention.

[0028] Figure 6 1 and 2 are waveform diagrams of signals of a power converter with a spread spectrum control mechanism according to the first to sixth embodiments of the present invention.

[0029] Figure 7 1 and 2 are waveform diagrams of signals of a power converter with a spread spectrum control mechanism according to the first to sixth embodiments of the present invention.

[0030] Figure 8 1 and 2 are waveform diagrams of signals of a power converter with a spread spectrum control mechanism according to the first to sixth embodiments of the present invention. DETAILED DESCRIPTION

[0031] The following is an explanation of the embodiments of the present invention through specific embodiments. Those skilled in the art can understand the advantages and effects of the present invention from the contents disclosed in this specification. The present invention can be implemented or applied through other different specific embodiments, and the details in this specification can also be modified and changed in various ways based on different viewpoints and applications without departing from the concept of the present invention. In addition, the drawings of the present invention are only simple schematic illustrations and are not depicted according to actual dimensions. It is stated in advance. The following embodiments will further explain the relevant technical contents of the present invention in detail, but the disclosed contents are not intended to limit the scope of protection of the present invention. In addition, the term "or" used herein may include any one or more combinations of the associated listed items depending on the actual situation.

[0032] See also Figure 1 , which is a circuit diagram of a power converter with a spread spectrum control mechanism according to a first embodiment of the present invention.

[0033] like Figure 1As shown, the power converter of the present invention may include an upper bridge switch UG, a lower bridge switch LG, a control circuit 100 , a driving circuit 200 , a buffer circuit 300 and an on-time determination circuit 401 .

[0034] The first end of the upper bridge switch UG is coupled to the input voltage VIN. The first end of the lower bridge switch LG is connected to the second end of the upper bridge switch UG. The second end of the lower bridge switch LG is grounded. The node LX between the first end of the lower bridge switch LG and the second end of the upper bridge switch UG is connected to the first end of the inductor L.

[0035] The input end of the buffer circuit 300 is connected to the second end of the inductor L. The output end of the buffer circuit 300 is connected to the input end of the on-time determination circuit 401 . The output end of the on-time determination circuit 401 is connected to the input end of the control circuit 100 .

[0036] For example, in the first embodiment of the present invention, the on-time determination circuit 401 of the power converter of the present invention includes a capacitor C and a comparator CMP, which is only an example and the present invention is not limited thereto. The first end of the capacitor C is connected to the constant current source PS. The second end of the capacitor C is grounded. The first input end (e.g., the inverting input end) of the comparator CMP is connected to the first end of the capacitor C. The second input end (e.g., the non-inverting input end) of the comparator CMP is connected to the output end of the buffer circuit 300. The output end of the comparator CMP is connected to the input end of the control circuit 100.

[0037] The output end of the control circuit 100 is connected to the input end of the driving circuit 200. The output end of the driving circuit 200 is connected to the control end of the upper bridge switch UG and the control end of the lower bridge switch LG.

[0038] It is worth noting that in order to prevent the electromagnetic interference (EMI) signal generated by the switching of the upper bridge switch UG and the lower bridge switch LG from having too high energy at a certain point in time and affecting the operation of the power converter, the power converter of the present invention disperses the amplitude of the switching frequency of the upper bridge switch UG and the lower bridge switch LG into multiple frequency bands within a switching frequency range to disperse the energy of the EMI signal generated by each switching, so that the operation of the power converter will not be affected by the EMI signal and abnormality will occur each time the upper bridge switch UG and the lower bridge switch LG are switched.

[0039] In detail, the buffer circuit 300 of the power converter of the present invention determines the buffer ratios of the upper bridge switch UG and the lower bridge switch LG when switching in the multiple frequency bands according to the energy upper limit values ​​of the multiple frequency bands in a switching frequency range.

[0040] The buffer circuit 300 of the power converter of the present invention buffers the voltage of an output voltage signal VOUT received by the input end of the buffer circuit from the inductor L according to a plurality of buffer ratios when the switching frequencies of the upper bridge switch UG and the lower bridge switch LG are respectively within a plurality of frequency bands. Each time, a buffer voltage signal VODSSC is output. That is, when the upper bridge switch UG and the lower bridge switch LG are switched at different switching frequencies, the buffer circuit 300 buffers the energy received from the inductor L at different buffer ratios.

[0041] In the power converter of the present invention, the on-time determination circuit 401 can determine the on-time of the upper bridge switch UG and the lower bridge switch LG according to a buffer voltage signal VODSSC received from the buffer circuit 300 to output an on-time indication signal.

[0042] For example, the on-time determination circuit 401 includes a comparator CMP, which compares the voltage of the first end of the capacitor C received by the first input terminal (e.g., the inverting input terminal) of the comparator CMP (i.e., the voltage of the above-mentioned on-time signal TONS) with a buffer voltage signal VODSSC received by the second input terminal (e.g., the non-inverting input terminal) of the comparator CMP from the buffer circuit 300 to output a on-time indication signal.

[0043] In the power converter of the present invention, the control circuit 100 can control the driving circuit 200 to drive the upper bridge switch UG and the lower bridge switch LG to operate according to an on-time indication signal received from (the output end of the comparator CMP of) the on-time determination circuit 401 .

[0044] See also Figure 1 as well as Figures 6 to 8 ,in Figures 6 to 8 1 and 2 are waveform diagrams of signals of a power converter with a spread spectrum control mechanism according to the first to sixth embodiments of the present invention.

[0045] For example, in Figures 6 to 8 In the example, the input voltage Vin received by the first end of the upper bridge switch UG is 5V, and the inductance value of the inductor L is 0.68uH.

[0046] exist Figure 6 In the example, an inductor current signal IL1 flowing through the inductor L is as follows: Figure 6 The buffer circuit 300 of the power converter of the present invention buffers the voltage of an output voltage signal Vout1 received from the inductor L with a buffer ratio SSC of 16% to output a buffer voltage signal Vodssc1 having a peak voltage VOD1.

[0047] like Figure 6As shown in FIG. 1 , when a buffer voltage signal Vodssc1 received by the second input terminal of the comparator CMP of the on-time determining circuit 401 from the buffer circuit 300 gradually changes, a capacitor voltage signal TonS1 of the capacitor C received by the first input terminal of the comparator CMP for charging or discharging also gradually changes. As a result, the control circuit 100 outputs an on-time indication signal of the comparator CMP of the on-time determining circuit 401 as shown in FIG. Figure 6 The upper bridge switch UG and the lower bridge switch LG are switched at a switching frequency of 32 KHz indicated by a switching frequency signal FLX1.

[0048] exist Figure 7 In the example, an inductor current signal IL2 flowing through the inductor L is as follows: Figure 7 The buffer circuit 300 of the power converter of the present invention buffers the voltage of an output voltage signal Vout2 received from the inductor L with a buffer ratio SSC of 15% to output a buffer voltage signal Vodssc2 having a peak voltage VOD2.

[0049] like Figure 7 As shown in FIG. 1 , when a buffer voltage signal Vodssc2 received by the second input terminal of the comparator CMP of the on-time determining circuit 401 from the buffer circuit 300 gradually changes, a capacitor voltage signal TonS2 of the capacitor C received by the first input terminal of the comparator CMP also gradually changes. As a result, the control circuit 100 outputs an on-time indication signal of the comparator CMP of the on-time determining circuit 401 as shown in FIG. Figure 7 The upper bridge switch UG and the lower bridge switch LG are switched at a switching frequency of 64KHz indicated by a switching frequency signal FLX2.

[0050] exist Figure 8 In the example, an inductor current signal IL3 flowing through the inductor L is as follows: Figure 8 The buffer circuit 300 of the power converter of the present invention buffers the voltage of an output voltage signal Vout3 received from the inductor L with a buffer ratio SSC of 13% to output a buffer voltage signal Vodssc3 having a peak voltage VOD3.

[0051] like Figure 8 As shown in FIG. 1 , when a buffer voltage signal Vodssc3 received by the second input terminal of the comparator CMP of the on-time determining circuit 401 from the buffer circuit 300 gradually changes, a capacitor voltage signal TonS3 of the capacitor C received by the first input terminal of the comparator CMP also gradually changes. As a result, the control circuit 100 outputs an on-time indication signal of the comparator CMP of the on-time determining circuit 401 as shown in FIG. Figure 8The upper bridge switch UG and the lower bridge switch LG are switched at a switching frequency of 128 KHz indicated by a switching frequency signal FLX3.

[0052] See also Figure 2 , which is a circuit diagram of a power converter with a spread spectrum control mechanism according to a second embodiment of the present invention. The similarities between the second embodiment and the first embodiment of the present invention are not repeated here.

[0053] The difference between the second embodiment of the present invention and the first embodiment is that the on-time determination circuit 402 of the power converter of the second embodiment of the present invention comprises a variable current source PSb, a comparator CMP and a capacitor C.

[0054] The first end of the variable current source PSb is coupled to a power supply voltage Vs. The control end of the variable current source PSb is connected to the output end of the oscillator circuit 900. The output end of the variable current source PSb is connected to the first end of the capacitor C. The second end of the capacitor C is grounded. The first input end of the comparator CMP, for example, the inverting input end, is connected to the first end of the capacitor C. The second input end of the comparator CMP, for example, the non-inverting input end, is connected to the output end of the buffer circuit 300. The output end of the comparator CMP is connected to the input end of the control circuit 100. The output end of the control circuit 100 is connected to the control end of the upper bridge switch UG and the control end of the lower bridge switch LG.

[0055] The buffer circuit 300 buffers an output signal flowing through the inductor L to the second input terminal, such as the non-inverting input terminal, of the comparator CMP. Meanwhile, the variable current source PSb determines the frequency of supplying current to the first terminal of the variable capacitor Cb according to the frequency or duty cycle of the waveform of an oscillation signal received from the oscillator circuit 900, thereby determining the speed at which the voltage of the first input terminal, such as the inverting input terminal, of the comparator CMP rises.

[0056] The control circuit 100 controls the switching of the upper bridge switch UG and the lower bridge switch LG according to the level of a conduction time indication signal received from the comparator CMP.

[0057] See also Figure 3 , which is a circuit diagram of a power converter with a spread spectrum control mechanism according to a third embodiment of the present invention.

[0058] The similarities between the third embodiment of the present invention and the first embodiment are not repeated here.

[0059] The difference between the third embodiment of the present invention and the first embodiment is that the on-time determining circuit 403 of the power converter in the third embodiment of the present invention comprises a constant current source PS, a comparator CMP and a variable capacitor Cb.

[0060] A first end of the constant current source PS is coupled to a power supply voltage Vs. An output end of the constant current source PS is connected to a first end of a variable capacitor Cb. A control end of the variable capacitor Cb is connected to an output end of the oscillator circuit 900. A second end of the variable capacitor Cb is grounded. A first input end of the comparator CMP, such as an inverting input end, is connected to a first end of the variable capacitor Cb. A second input end of the comparator CMP, such as a non-inverting input end, is connected to an output end of the buffer circuit 300. An output end of the comparator CMP is connected to an input end of the control circuit 100. An output end of the control circuit 100 is connected to a control end of an upper bridge switch UG and a control end of a lower bridge switch LG.

[0061] The constant current source PS provides a constant current to the variable capacitor Cb.

[0062] The capacitance value of the variable capacitor Cb depends on an oscillation signal received from the oscillator circuit 900. The capacitance value of the variable capacitor Cb can change with the oscillation signal received from the oscillator circuit 900, so that the voltage value of the first end of the variable capacitor Cb input to the first input end of the comparator CMP changes accordingly, thereby changing a conduction time indication signal output by the comparator CMP. The control circuit 100 controls the switching of the upper bridge switch UG and the lower bridge switch LG according to the level of the conduction time indication signal received from the comparator CMP.

[0063] See also Figure 4 , which is a circuit diagram of a power converter with a spread spectrum control mechanism according to a fourth embodiment of the present invention.

[0064] The similarities between the fourth embodiment of the present invention and the first embodiment are not repeated here.

[0065] The difference between the fourth embodiment of the present invention and the first embodiment is that the on-time determining circuit 404 of the power converter of the fourth embodiment of the present invention includes a variable resistor R, a comparator CMP and a capacitor C.

[0066] The control end of the variable resistor R is connected to the output end of the oscillator circuit 900. The first end of the variable resistor R is coupled to a power supply voltage Vs. The second end of the variable resistor R is connected to the first end of the capacitor C. The second end of the capacitor C is grounded. The first input end of the comparator CMP, for example, the inverting input end, is connected to the first end of the capacitor C. The second input end of the comparator CMP, for example, the non-inverting input end, is connected to the output end of the buffer circuit 300. The output end of the comparator CMP is connected to the input end of the control circuit 100. The output end of the control circuit 100 is connected to the control end of the upper bridge switch UG and the control end of the lower bridge switch LG.

[0067] The resistance value of the variable resistor R depends on an oscillation signal received from the oscillator circuit 900. The resistance value of the variable resistor R can change with the oscillation signal received from the oscillator circuit 900 to change the current flowing through the capacitor C, so that the voltage value of the first end of the capacitor C input to the first input end of the comparator CMP changes. The control circuit 100 controls the switching of the upper bridge switch UG and the lower bridge switch LG according to the level of a conduction time indication signal received from the comparator CMP.

[0068] See also Figure 5A , which is a circuit diagram of a power converter with a spread spectrum control mechanism using an oscillator buffer circuit according to a fifth embodiment of the present invention.

[0069] For the convenience of explanation, the buffer circuit of the present invention (eg Figures 1 to 4 The buffer circuit 300 may include Figure 5A All circuit components shown are shown here as examples, but the present invention is not limited to them. In practice, the configuration can be appropriately omitted according to actual needs. Figure 5A Part of the circuit elements shown, the circuit elements originally connected to the omitted elements can be coupled to an appropriate operating control voltage.

[0070] It is worth noting that the buffer circuit (eg Figures 1 to 4 The buffer circuit 300 may include a main buffer circuit 31, wherein the main buffer circuit 31 includes a plurality of buffer modulation circuits such as but not limited to: Figure 5A Four buffer modulation circuits 3011 to 3014 are shown.

[0071] Each buffer modulation circuit of the buffer circuit 300 of the power converter of the present invention may include a plurality of first transistors. Figure 5A As shown, the buffer modulation circuit 3011 includes six first transistors T111 to T116, the buffer modulation circuit 3012 includes four first transistors T121 to T124, the buffer modulation circuit 3013 includes three first transistors T131 to T133, and the buffer modulation circuit 3014 includes three first transistors T141 to T143. This is only an example and the present invention is not limited thereto.

[0072] The first end of the first transistor T111 of the buffer modulation circuit 3011 is connected to the end of the buffer circuit 300 receiving the input voltage Vd (ie, the input end of the buffer circuit 300, and the inductor connected thereto is for example Figures 1 to 4 The second end of the inductor L).

[0073] The second end of the first transistor T111 is connected to the first end of the first transistor T112, the second end of the first transistor T112 is connected to the first end of the first transistor T113, the second end of the first transistor T113 is connected to the first end of the first transistor T114, the second end of the first transistor T114 is connected to the first end of the first transistor T115, and the second end of the first transistor T115 is connected to the first end of the first transistor T116. The second end of the first transistor T116 of the buffer modulation circuit 3011 is connected to the output end of the buffer circuit 300 (i.e., the end where the buffer circuit 300 outputs a buffer voltage signal Vodssc).

[0074] The first end of the first transistor T121 of the buffer modulation circuit 3012 is connected to the end of the buffer circuit 300 that receives the input voltage Vd. In the buffer modulation circuit 3012, the second end of the first transistor T121 is connected to the first end of the first transistor T122, the second end of the first transistor T122 is connected to the first end of the first transistor T123, and the second end of the first transistor T123 is connected to the first end of the first transistor T124. The second end of the first transistor T124 of the buffer modulation circuit 3012 is connected to the output end of the buffer circuit 300.

[0075] The first end of the first transistor T131 of the buffer modulation circuit 3013 is connected to the end of the buffer circuit 300 that receives the input voltage Vd. In the buffer modulation circuit 3013, the second end of the first transistor T131 is connected to the first end of the first transistor T132, and the second end of the first transistor T132 is connected to the first end of the first transistor T133. The second end of the first transistor T133 of the buffer modulation circuit 3013 is connected to the output end of the buffer circuit 300.

[0076] The first end of the first transistor T141 of the buffer modulation circuit 3014 is connected to the end of the buffer circuit 300 that receives the input voltage Vd. In the buffer modulation circuit 3014, the second end of the first transistor T141 is connected to the first end of the first transistor T142, and the second end of the first transistor T142 is connected to the first end of the first transistor T143. The second end of the first transistor T143 of the buffer modulation circuit 3014 is connected to the output end of the buffer circuit 300.

[0077] It is worth noting that the control end of at least one of the plurality of first transistors included in each of the plurality of buffer modulation circuits of the buffer circuit 300 of the power converter of the present invention is connected to the output end of the oscillator circuit 900 so as to be turned on and off by the control of the oscillator circuit 900. By controlling the operation of different numbers of first transistors of the oscillator circuit 900, the buffering ratio of the voltage of an output voltage signal of the inductor L of the power converter of the present invention is set.

[0078] For example, Figure 5A As shown, the control end of the first transistor T115 of the buffer modulation circuit 3011, the control end of the first transistor T123 of the buffer modulation circuit 3012, the control end of the first transistor T132 of the buffer modulation circuit 3013 and the control end of the first transistor T142 of the buffer modulation circuit 3014 are connected to the output end of the oscillator circuit 900. This is only an example and the present invention is not limited to this.

[0079] For example, if the multiple first transistors T115, T123, T132, and T142 are actually NMOS transistors, the voltage levels of the multiple oscillation signals that the oscillator circuit 900 can output to the multiple first transistors T115, T123, T132, and T142 respectively may initially be 0, 0, 0, and 0, respectively, represented as "0000", and then may be 0001→0010→0011→0100→0101→0110→0111→1000→1001→1010→1011→1100→1101→1110→1111. This is just an example and the present invention is not limited thereto. That is, the oscillator circuit 900 can turn on the plurality of first transistors T115 , T123 , T132 , T142 at the voltage level “1” in turn according to the arrangement order of the plurality of first transistors T115 , T123 , T132 , T142 .

[0080] Alternatively, if the plurality of first transistors T115, T123, T132, T142 are Figure 5A The oscillator circuit 900 is shown as a PMOS transistor. The voltage levels of the multiple oscillation signals outputted by the oscillator circuit 900 to the multiple first transistors T115, T123, T132, and T142 may be 1, 1, 1, and 1, respectively, expressed as "1111", and then may be 1110→1101→1100→1011→1010→1001→1000→0111→0110→0101→0100→0011→0010→0001→0000, which is only an example, and the present invention is not limited thereto. That is, the oscillator circuit 900 may turn on the multiple first transistors T115, T123, T132, and T142 at the voltage level "0" in turn according to the arrangement order of the multiple first transistors T115, T123, T132, and T142.

[0081] Alternatively, the oscillator circuit 900 turns on the plurality of first transistors T115 , T123 , T132 , T142 in a random manner.

[0082] When the oscillator circuit 900 turns on the first transistor T115 of the buffer modulation circuit 3011 and the other first transistors T111 to T114 and T116 are turned on, the buffer modulation circuit 3011 can increase the voltage buffering of an output voltage signal of the inductor L by 1%.

[0083] When the oscillator circuit 900 turns on the first transistor T123 of the buffer modulation circuit 3012 and the other first transistors T121 , T122 , and T124 are turned on, the buffer modulation circuit 3012 can increase the voltage buffering of an output voltage signal of the inductor L by 2%.

[0084] When the oscillator circuit 900 turns on the first transistor T132 of the buffer modulation circuit 3013 and the other first transistors T131 and T133 are turned on, the buffer modulation circuit 3013 can increase the voltage buffering of an output voltage signal of the inductor L by 4%.

[0085] When the oscillator circuit 900 turns on the first transistor T142 of the buffer modulation circuit 3014 and the other first transistors T141 and T143 are turned on, the buffer modulation circuit 3014 can increase the voltage buffering of an output voltage signal of the inductor L by 8%.

[0086] If necessary, the buffer circuit of the power converter of the present invention may further include all or some of the following other auxiliary buffer circuit components: the second transistor T2 to the twenty-sixth transistor T26, the switching transistors Ts1 to Ts3, the first capacitor C1 to the fourth capacitor C4, the first resistor R1 to the third resistor R3, the inverter NOT1, the first auxiliary resistor Rs1 and the second auxiliary resistor Rs2.

[0087] The first end of the first capacitor C1 and the first end of the second capacitor C2 are connected to the end of the buffer circuit 300 receiving the input voltage Vd. The second end of the first capacitor C1 and the second end of the second capacitor C2 are connected to the first ends of the first transistors T111, T121, T131, T141.

[0088] A first end of the second transistor T2 is connected to a terminal of the buffer circuit 300 that receives the input voltage Vd. A second end of the second transistor T2 is connected to a first end of the third transistor T3.

[0089] The second end of the third transistor T3 is connected to the first end of the fifth transistor T5. The first end of the fourth transistor T4 is connected to the end of the buffer circuit 300 that receives the input voltage Vd. The first end of the fifth transistor T5 is connected to the second end of the fourth transistor T4. The second end of the fifth transistor T5 is connected to the output end of the buffer circuit 300 (i.e., the end where the buffer circuit 300 outputs a buffer voltage signal VODSSC). The output end of the buffer circuit 300 is connected to the conduction time determination circuit (e.g. Figures 1 to 4The on-time determining circuit 401 to 404 is an input terminal of the circuit.

[0090] The second end of the fifth transistor T5 can also be connected to the first end of the second auxiliary resistor Rs2. The second end of the second auxiliary resistor Rs2 is coupled to the second reference potential VG.

[0091] The control end of the second transistor T2, the control end of the third transistor T3, and the control end of the fourth transistor T4 can be connected to the second end of the first resistor R1. The control end of the fifth transistor T5 is coupled to the first reference potential VF. The first end of the first resistor R1 can be connected to the control ends of the first transistors T111 to T114, T121, T122, T131, and T141. The control ends of the first transistors T116, T124, T133, and T143 can be coupled to the first reference potential VF and connected to the control end of the fifth transistor T5.

[0092] A first end of the third capacitor C3 is connected to the end of the buffer circuit 300 receiving the input voltage Vd. A second end of the third capacitor C3 is connected to the control end of the fifth transistor T5.

[0093] The first end of the second resistor R2 is connected to the control end of the second transistor T2, the control end of the third transistor T3, the control end of the fourth transistor T4 and the first end of the first resistor R1. The second end of the first resistor R1 is connected to the control end of the sixth transistor T6.

[0094] The first end of the sixth transistor T6 is connected to the end of the buffer circuit 300 receiving the input voltage Vd. The second end of the sixth transistor T6 is connected to the first end of the seventh transistor T7. The control end of the seventh transistor T7 is coupled to the first reference potential VF and connected to the control end of the fifth transistor T5. The second end of the seventh transistor T7 is connected to the first end of the first auxiliary resistor Rs1. The voltage of the second end of the seventh transistor T7 is Figure 5A The second terminal of the first auxiliary resistor Rs1 is coupled to the second reference potential VG.

[0095] The first end of the eighth transistor T8 is connected to the end of the buffer circuit 300 receiving the input voltage Vd. The second end of the eighth transistor T8 is connected to the first end of the ninth transistor T9. The control end of the ninth transistor T9 is coupled to the first reference potential VF. The second end of the ninth transistor T9 is connected to the control end of the sixth transistor T6 and the second end of the switching transistor Ts1. The first end of the switching transistor Ts1 is connected to the end of the buffer circuit 300 receiving the input voltage Vd. The control end of the switching transistor Ts1 is connected to the input end of the inverter NOT (this is a non-essential component). The input end of the inverter NOT is coupled to an operation control voltage VW.

[0096] The first end of the tenth transistor T10 is connected to the end of the buffer circuit 300 receiving the input voltage Vd. The second end of the tenth transistor T10 is connected to the first end of the eleventh transistor T11. The second end of the eleventh transistor T11 is connected to the control end of the eighth transistor T8 and the control end of the tenth transistor T10. The control end of the eleventh transistor T11 is coupled to the first reference potential VF.

[0097] The first end of the twelfth transistor T12 is connected to the end of the buffer circuit 300 receiving the input voltage Vd. The first end of the thirteenth transistor T13 is connected to the second end of the twelfth transistor T12.

[0098] The first end of the fourteenth transistor T14 is connected to the end of the buffer circuit 300 receiving the input voltage Vd. The control end of the fourteenth transistor T14 is connected to the control end of the twelfth transistor T12. The first end of the fifteenth transistor T15 is connected to the second end of the fourteenth transistor T14. The second end of the fifteenth transistor T15 is coupled to the second reference potential VG. The control end of the fifteenth transistor T15 and the control end of the thirteenth transistor T13 are coupled to the first reference potential VF.

[0099] The first end of the switching transistor Ts2 is connected to the end of the buffer circuit 300 receiving the input voltage Vd. The second end of the switching transistor Ts2 is connected to the control end of the twelfth transistor T12 and the control end of the fourteenth transistor T14. The control end of the switching transistor Ts2 is connected to the input end of the inverter NOT. The input end of the inverter NOT is coupled to an operation control voltage VW.

[0100] The first end of the sixteenth transistor T16 is connected to the end of the buffer circuit 300 receiving the input voltage Vd. The control end of the sixteenth transistor T16 is connected to the control end of the fourteenth transistor T14 and the control end of the twelfth transistor T12 and the first end of the third resistor R3.

[0101] The first end of the seventeenth transistor T17 is connected to the second end of the sixteenth transistor T16. The second end of the seventeenth transistor T17 is connected to the first end of the third resistor R3. The second end of the third resistor R3 is coupled to the first reference potential VF. The control end of the seventeenth transistor T17 is connected to the control end of the fifteenth transistor T15 and coupled to the first reference potential VF.

[0102] The control terminal of the switching transistor Ts3 is connected to the terminal of the buffer circuit 300 receiving the input voltage Vd. The first terminal and the second terminal of the switching transistor Ts3 can be coupled to the first control potential and the second control potential respectively.

[0103] The first end of the eighteenth transistor T18 is connected to the second end of the ninth transistor T9 and the control end of the sixth transistor T6. The second end of the eighteenth transistor T18 is connected to the first end of the nineteenth transistor T19. The second end of the nineteenth transistor T19 is coupled to the second reference potential VG.

[0104] The first end of the twentieth transistor T20 is connected to the second end of the eleventh transistor T11. The control end of the twentieth transistor T20 is connected to the control end of the eighteenth transistor T18. The first end of the twenty-first transistor T21 is connected to the second end of the twentieth transistor T20. The second end of the twenty-first transistor T21 is coupled to the second reference potential VG. The control end of the twenty-first transistor T21 is connected to the control end of the nineteenth transistor T19.

[0105] A first end of the capacitor C4 is connected to a second end of the seventh transistor T7 , and a second end of the capacitor C4 is connected to a first end of the nineteenth transistor T19 .

[0106] The first end of the 22nd transistor T22 is connected to the second end of the 13th transistor T13. The second end of the 22nd transistor T22 is connected to the first end of the 21st transistor T21. The control end of the 22nd transistor T22 is connected to the second end of the 7th transistor T7. The first end of the 23rd transistor T23 is connected to the second end of the 13th transistor T13. The second end of the 23rd transistor T23 is connected to the first end of the 19th transistor T19. The control end of the 23rd transistor T23 is coupled to a control potential Vp.

[0107] The first end of the twenty-fourth transistor T24 is connected to the second end of the fourth resistor R4. The first end of the fourth resistor R4 is connected to the second end of the fifteenth transistor T15. The control end of the twenty-fourth transistor T24 is connected to the control end of the twentieth transistor T20.

[0108] The first end of the 25th transistor T25 is connected to the second end of the 24th transistor T24. The second end of the 25th transistor T25 is coupled to the second reference potential VG. The control end of the 25th transistor T25 is connected to the first end of the 24th transistor T24 and the control end of the 21st transistor T21.

[0109] The first end of the 26th transistor T26 is connected to the control end of the 24th transistor T24 and the control end of the 20th transistor T20. The second end of the 26th transistor T26 is coupled to the second reference potential VG. The control end of the 26th transistor T26 is coupled to an operation control voltage VW.

[0110] See also Figure 5B, which is a circuit diagram of a power converter with a spread spectrum control mechanism using a buffer circuit of a random number generator according to a sixth embodiment of the present invention. The sixth embodiment of the present invention is similar to the fifth embodiment and will not be described in detail herein.

[0111] A power converter according to a sixth embodiment of the present invention comprises: Figure 5B The random number generator 1000 shown is used to output multiple random number signals (having random values), replacing Figure 5A The oscillator circuit 900 for outputting a plurality of oscillation signals (with default values) in the fifth embodiment is shown in FIG. Figures 2 to 4 The oscillator circuit 900 shown may also be replaced by a random number generator 1000 .

[0112] In summary, the present invention provides a power converter with a spread spectrum control mechanism. In the power converter of the present invention, the switching frequencies of the upper bridge switch and the lower bridge switch are dispersed in multiple frequency bands within a frequency range, so as to limit the switching frequencies of the upper bridge switch and the lower bridge switch each time to not exceed an upper limit value, thereby effectively reducing the strength value of the electromagnetic interference (EMI) signal caused by each switching of the upper bridge switch and the lower bridge switch, so that the power converter operates normally and improves the operating efficiency of the power converter.

[0113] The contents disclosed above are only preferred feasible embodiments of the present invention, and are not intended to limit the claims of the present invention. Therefore, all equivalent technical changes made using the description and drawings of the present invention are included in the claims of the present invention.

Claims

1. A power converter with a spread spectrum control mechanism, characterized in that: The power converter with spread spectrum control mechanism comprises: An upper bridge switch, wherein a first end of the upper bridge switch is coupled to an input voltage; A lower bridge switch, wherein a first end of the lower bridge switch is connected to a second end of the upper bridge switch, the second end of the lower bridge switch is grounded, and a node between the first end of the lower bridge switch and the second end of the upper bridge switch is connected to a first end of an inductor; A driving circuit connected to the control end of the upper bridge switch and the control end of the lower bridge switch; A control circuit, connected to the driving circuit, configured to control the driving circuit to drive the upper bridge switch and the lower bridge switch to operate; a buffer circuit, wherein the input end of the buffer circuit is connected to the second end of the inductor, and is configured to determine a plurality of buffer ratios when the upper bridge switch and the lower bridge switch are switched in the plurality of frequency bands according to a plurality of energy upper limit values ​​in the plurality of frequency bands within a switching frequency range, and to buffer the voltage of a voltage signal received by the input end of the buffer circuit from the inductor according to the plurality of buffer ratios when the switching frequencies of the upper bridge switch and the lower bridge switch are respectively within the plurality of frequency bands; as well as A conduction time determination circuit connected to the buffer circuit and the control circuit, configured to determine the conduction time of the upper bridge switch and the lower bridge switch according to the voltage signal buffered by the buffer circuit, so as to output a conduction time indication signal; The control circuit controls the driving circuit to drive the upper bridge switch and the lower bridge switch to operate according to the conduction time indication signal.

2. The power converter with spread spectrum control mechanism according to claim 1, characterized in that: The buffer circuit comprises: a plurality of buffer modulation circuits, each of the buffer modulation circuits comprising a plurality of first transistors, wherein in each of the buffer modulation circuits, a first end of one of the plurality of first transistors is connected to an input end of the buffer circuit, a second end of another of the plurality of first transistors is connected to an input end of the conduction time determination circuit, and a first end of each of the other plurality of first transistors is connected to a second end of an adjacent first transistor; At least the control end of the first transistor in each of the buffer modulation circuits is connected to an oscillator circuit, and the control ends of the other first transistors are coupled to an operation control voltage.

3. The power converter with spread spectrum control mechanism according to claim 2, characterized in that: The buffer circuit further includes a first buffer auxiliary circuit, wherein the first buffer auxiliary circuit includes: a second transistor, wherein a first terminal of the second transistor is connected to an input terminal of the buffer circuit; a third transistor, a first terminal of the third transistor being connected to the second terminal of the second transistor; a fourth transistor, a first end of the fourth transistor being connected to an input end of the buffer circuit; as well as a fifth transistor, wherein a first end of the fifth transistor is connected to a second end of the fourth transistor and a second end of the third transistor, and a second end of the fifth transistor is connected to an input end of the conduction time determination circuit; The control end of the second transistor, the control end of the third transistor and the control end of the fourth transistor are coupled to an operation control voltage, and the control end of the fifth transistor is coupled to a first reference potential.

4. The power converter with spread spectrum control mechanism according to claim 3, characterized in that: The buffer circuit further includes a second buffer auxiliary circuit, wherein the second buffer auxiliary circuit includes: a sixth transistor, wherein a first terminal of the sixth transistor is connected to the input terminal of the buffer circuit, and a control terminal of the sixth transistor is coupled to an operation control voltage; A seventh transistor, wherein a first end of the seventh transistor is connected to the second end of the sixth transistor, a second end of the seventh transistor is coupled to a second reference potential, and a control end of the seventh transistor is coupled to the second reference potential.

5. The power converter with spread spectrum control mechanism according to claim 4, characterized in that: The buffer circuit further comprises: A switching transistor, wherein a first terminal of the switching transistor is connected to the input terminal of the buffer circuit, a second terminal of the switching transistor is connected to the control terminal of the sixth transistor, and the control terminal of the switching transistor is coupled to an operation control voltage.

6. The power converter with spread spectrum control mechanism according to claim 4, characterized in that: The buffer circuit further comprises: an eighth transistor, a first end of the eighth transistor being connected to the input end of the buffer circuit; a ninth transistor, wherein a first end of the ninth transistor is connected to the second end of the eighth transistor, a second end of the ninth transistor is connected to the control end of the sixth transistor, and the control end of the ninth transistor is coupled to the second reference potential; a tenth transistor, a first end of the tenth transistor being connected to the input end of the buffer circuit; as well as an eleventh transistor, wherein the first end of the eleventh transistor is connected to the second end of the tenth transistor, the second end of the eleventh transistor is connected to the control end of the eighth transistor and the control end of the tenth transistor, and the control end of the eleventh transistor is coupled to the second reference potential.

7. The power converter with spread spectrum control mechanism according to claim 6, characterized in that: The buffer circuit further comprises: a twelfth transistor, a first end of the twelfth transistor being connected to an input end of the buffer circuit; a thirteenth transistor, a first end of the thirteenth transistor being connected to the second end of the twelfth transistor, and a second end of the thirteenth transistor being coupled to the second reference potential; a fourteenth transistor, a first end of the fourteenth transistor being connected to the input end of the buffer circuit, and a control end of the fourteenth transistor being connected to the control end of the twelfth transistor; as well as A fifteenth transistor, wherein the first end of the fifteenth transistor is connected to the second end of the fourteenth transistor, the second end of the fifteenth transistor is coupled to the second reference potential, and the control end of the fifteenth transistor is connected to the control end of the thirteenth transistor and coupled to the first reference potential.

8. The power converter with spread spectrum control mechanism according to claim 7, characterized in that: The buffer circuit further comprises: A switching transistor, wherein a first terminal of the switching transistor is connected to the input terminal of the buffer circuit, a second terminal of the switching transistor is connected to the control terminal of the twelfth transistor, and the control terminal of the switching transistor is coupled to an operation control voltage.

9. The power converter with spread spectrum control mechanism according to claim 7, characterized in that: The buffer circuit further comprises: a sixteenth transistor, a first end of the sixteenth transistor being connected to the input end of the buffer circuit, and a control end of the sixteenth transistor being connected to the control end of the fourteenth transistor; as well as A seventeenth transistor, wherein the first end of the seventeenth transistor is connected to the second end of the sixteenth transistor, the second end of the seventeenth transistor is coupled to the first reference potential, and the control end of the seventeenth transistor is connected to the control end of the fifteenth transistor.

10. The power converter with spread spectrum control mechanism according to claim 9, characterized in that: The buffer circuit further comprises: an eighteenth transistor, a first end of the eighteenth transistor being connected to the second end of the ninth transistor; a nineteenth transistor, a first end of the nineteenth transistor being connected to the second end of the eighteenth transistor, and a second end of the nineteenth transistor being coupled to the second reference potential; a twentieth transistor, wherein a first end of the twentieth transistor is connected to the second end of the eleventh transistor, and a control end of the twentieth transistor is connected to the control end of the eighteenth transistor; as well as A twenty-first transistor, the first end of the twenty-first transistor is connected to the second end of the twentieth transistor, the second end of the twenty-first transistor is coupled to the second reference potential, and the control end of the twenty-first transistor is connected to the control end of the nineteenth transistor.

11. The power converter with spread spectrum control mechanism according to claim 10, characterized in that: The buffer circuit further comprises: a twenty-second transistor, a first end of the twenty-second transistor being connected to the second end of the thirteenth transistor, a second end of the twenty-second transistor being connected to the first end of the twenty-first transistor, and a control end of the twenty-second transistor being connected to the second end of the seventh transistor; as well as A twenty-third transistor, wherein the first end of the twenty-third transistor is connected to the second end of the thirteenth transistor, the second end of the twenty-third transistor is connected to the first end of the nineteenth transistor, and the control end of the twenty-third transistor is coupled to a control potential.

12. The power converter with spread spectrum control mechanism according to claim 11, characterized in that: The buffer circuit further comprises: a twenty-fourth transistor, a first end of the twenty-fourth transistor being connected to the second end of the fifteenth transistor, and a control end of the twenty-fourth transistor being connected to the control end of the twenty-th transistor; as well as A twenty-fifth transistor, the first end of the twenty-fifth transistor is connected to the second end of the twenty-fourth transistor, the second end of the twenty-fifth transistor is coupled to the second reference potential, and the control end of the twenty-fifth transistor is connected to the first end of the twenty-fourth transistor and the control end of the twenty-first transistor.

13. The power converter with spread spectrum control mechanism according to claim 12, characterized in that: The buffer circuit further comprises: A twenty-sixth transistor, wherein the first end of the twenty-sixth transistor is connected to the control end of the twenty-fourth transistor, the second end of the twenty-sixth transistor is coupled to the second reference potential, and the control end of the twenty-sixth transistor is coupled to an operation control voltage.

14. The power converter with spread spectrum control mechanism according to claim 1, characterized in that: The on-time determination circuit further comprises: A constant current source coupled to a power supply voltage; a capacitor, a first end of the capacitor being connected to the constant current source, and a second end of the capacitor being grounded; and A comparator, wherein a first input terminal of the comparator is connected to a first terminal of the capacitor, a second input terminal of the comparator is connected to an output terminal of the buffer circuit, and an output terminal of the comparator is connected to an input terminal of the control circuit.

15. The power converter with spread spectrum control mechanism according to claim 1, characterized in that: The on-time determining circuit comprises: A variable current source, wherein a control end of the variable current source is connected to an output end of an oscillator circuit; A capacitor, a first end of the capacitor is connected to the output end of the variable current source, and a second end of the capacitor is grounded; as well as A comparator, wherein a first input terminal of the comparator is connected to a first terminal of the capacitor, a second input terminal of the comparator is connected to an output terminal of the buffer circuit, and an output terminal of the comparator is connected to an input terminal of the control circuit.

16. The power converter with spread spectrum control mechanism according to claim 1, characterized in that: The on-time determining circuit comprises: A constant current source coupled to a power supply voltage; A variable capacitor, wherein a first end of the variable capacitor is connected to an output end of the constant current source, a second end of the variable capacitor is grounded, and a control end of the variable capacitor is connected to an output end of an oscillator circuit; as well as A comparator, wherein a first input terminal of the comparator is connected to a first terminal of the variable capacitor, a second input terminal of the comparator is connected to an output terminal of the buffer circuit, and an output terminal of the comparator is connected to an input terminal of the control circuit.

17. The power converter with spread spectrum control mechanism according to claim 1, characterized in that: The on-time determining circuit comprises: A variable resistor, wherein a first end of the variable resistor is coupled to a power supply voltage, and a control end of the variable resistor is connected to an output end of an oscillator circuit; A capacitor, wherein a first end of the capacitor is connected to a second end of the variable resistor, and a second end of the capacitor is grounded; as well as A comparator, wherein a first input terminal of the comparator is connected to a first terminal of the capacitor, a second input terminal of the comparator is connected to an output terminal of the buffer circuit, and an output terminal of the comparator is connected to an input terminal of the control circuit.

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