Liquid crystal display screen comprising output stage circuit

Abstract

The invention discloses a voltage level converter which is characterized by comprising a second-stage circuit working between a high-voltage AVDD and a medium-voltage VMID and used for receiving a pair of control signals to output a pair of inverted output signals; and the first-stage circuit comprises a P-type transistor P1, a P-type transistor P2, an N-type transistor N2 and an N-type transistor N1 which are sequentially connected in series, and a P-type transistor P3, a P-type transistor P4, an N-type transistor N4 and an N-type transistor N3 which are sequentially connected in series.

Description

[0001] This application is a divisional application of the invention patent application with application number 2024112391052. The filing date of the original application is September 5, 2024. Technical Field

[0002] The present application belongs to the field of voltage level converter or level shifter (hereinafter referred to as LVSH, level shifter), and relates to a voltage level converter including fewer transistors. Background Art

[0003] Please refer to Figure 1 , which is a block diagram of a conventional liquid crystal display screen 100. In order to control a liquid crystal display 110, the liquid crystal display screen 100 includes a gate control circuit 120 and an output stage circuit 122 of a corresponding gate drive circuit. The liquid crystal display screen 100 also includes a source control circuit 130 and an output stage circuit 132 of a corresponding source drive circuit. The output stage circuit 132 of the conventional source drive circuit generally includes a plurality of LVSHs.

[0004] Please refer to Figure 2 , which is a block diagram of an existing LVSH 200. The existing LVSH 200 generally includes a pair of inverted input ports 210 and a pair of inverted output ports 220. Please refer to Figure 3 As shown in FIG. 1 , it is a schematic diagram of the voltage values ​​of the input port 210 signal and the output port 220 signal of the LVSH 200. Figure 3 Among them, the inverted signal of the input port 210 is usually a lower logic circuit level and a ground voltage GND, which can represent a logic signal 1 and a logic signal 0 respectively. The above-mentioned logic circuit levels are usually 1.5V and 0V, but a person skilled in the art of the present application can understand that the logic circuit level referred to in the present application is not limited to 1.5V. For example, it can be 0.9V, 1.2V, 1.8V, etc. After the level shift of the LVSH 200, the voltage value range of the signal of the output port 220 is increased to the medium voltage VMID and the high voltage VADD.

[0005] In the application of small and medium-sized liquid crystal display screens 100, the liquid crystal flip voltage is within 6V. Therefore, for the full positive half-voltage liquid crystal panel architecture, the high voltage VADD will be within 12V. Therefore, unlike the source drive circuit of a large-sized liquid crystal screen, high-voltage components, such as 32V, are required. The source drive circuit used in small and medium-sized liquid crystal display screens 100 often uses medium-voltage components. That is, the voltage of the signal at the output port 220 of the existing LVSH 200 is 6V to 12V. A person of ordinary skill in the art to which this application belongs can understand that the use of the medium voltage VMID of 6V and the high voltage VADD of 12V in this application is only an exemplary description. The voltage of the medium voltage VMID can generally be half of the voltage of the high voltage VADD, for example, 6V is 12V / 2. The medium voltage VMID and high voltage VADD involved in this application can be other voltage values.

[0006] Please refer to Figure 4 As shown in FIG. 4 , it is a block diagram of an existing LVSH 400. Figure 4 The LVSH 400 shown includes a LVSH core circuit 410, which requires the supply of a relay high voltage VQH and a relay low voltage VQL. Therefore, the LVSH 400 also includes a VQH rectifier circuit 420 and a VQL rectifier circuit 430, which are used to supply the relay high voltage VQH and the relay low voltage VQL to the LVSH core circuit 410, respectively.

[0007] The aforementioned relay high voltage VQH can usually be three quarters of the high voltage VADD. The aforementioned relay low voltage VQL can usually be one quarter of the high voltage VADD. When the high voltage VADD is 12V, the relay high voltage VQH is 9V, and the relay low voltage VQL is 3V.

[0008] Please refer to Figure 5 As shown, it is Figure 4 The circuit diagram of the LVSH core circuit 410 is shown in FIG. Figure 5 As can be seen from the circuit diagram, the LVSH core circuit 410 includes five circuits 510 to 550. Each circuit includes a circuit combination of four transistors. The first circuit 510 includes a pair of inverted input ports IN and INB. The last fifth circuit 550 includes a pair of inverted output ports OUT and OUTB.

[0009] A pair of output signals O1 and O1B of the first stage circuit 510 respectively control the gates of the two transistors of the second stage circuit 520. Similarly, a pair of output signals O2 and O2B of the second stage circuit 520 respectively control the gates of the two transistors of the third stage circuit 530. A pair of output signals O3 and O3B of the third stage circuit 530 respectively control the gates of the two transistors of the fourth stage circuit 540. A pair of output signals O4 and O4B of the fourth stage circuit 540 respectively control the gates of the two transistors of the fifth stage circuit 550.

[0010] Please refer to Figure 6 As shown, it is a schematic diagram of the operating voltage of each level of the LVSH core circuit 410. The LVSH core circuit 410 converts the VDD and GND voltages of the input signals IN and INB into high voltage AVDD and medium voltage VMID through the 20 transistors of the five-level circuit. The cross voltage of the first-level circuit 510 is between VMID and GND, which is 6V. The cross voltage of the second-level circuit 520 is between the relay low voltage VQL and the medium voltage VMID, which is 3V. The cross voltage of the third-level circuit 530 is between the relay low voltage VQL and the relay high voltage VQH, which is 6V. The cross voltage of the fourth-level circuit 540 is between the medium voltage VMID and the relay high voltage VQH, which is 3V. The cross voltage of the last fifth-level circuit 550 is between the medium voltage VMID and the high voltage AVDD, which is 6V. Since all the cross voltages of these five-level circuits 510 to 550 are within 6V, they can be implemented using general medium voltage components.

[0011] In other words, Figure 4 The LVSH core circuit 410 shown requires the use of 20 medium voltage metal oxide semiconductor field effect transistors (MOSFET). In addition, Figure 4 The LVSH 400 shown also requires a VQH rectifier circuit 420 and a VQL rectifier circuit 430 to supply a relay low voltage VQL and a relay high voltage VQH to the LVSH core circuit 410. Since the existing LVSH 400 is connected to more voltages, additional wells of transistors need to be cut in the layout, which occupies a larger area, resulting in higher costs and more power consumption.

[0012] Therefore, a LVSH design that occupies a smaller area is needed to reduce costs and save energy. In particular, small and medium-sized LCD screens 100 are usually used in mobile electronic devices, such as mobile phones, tablet computers, etc. These mobile electronic devices usually use batteries to supply power to the LCD screen 100. If a LVSH design with a smaller area and higher energy efficiency can be used, the size and energy consumption of the mobile electronic device can be reduced, and the performance of the mobile electronic device can be further improved. Summary of the invention

[0013] The present application is a voltage level converter proposed to solve the deficiencies in the prior art, with the purpose of using a smaller area and having higher energy efficiency, so as to reduce costs and increase the use time of mobile devices.

[0014] In order to achieve the above purpose, this application adopts the following technical solutions:

[0015] According to an embodiment of the present application, a voltage level converter is provided, characterized in that it includes: a second-stage circuit operating between a high voltage AVDD and a medium voltage VMID, for receiving a pair of control signals to output a pair of inverted output signals; and a first-stage circuit, further including a P-type transistor P1, a P-type transistor P2, an N-type transistor N2 and an N-type transistor N1 connected in series in sequence, and a P-type transistor P3, a P-type transistor P4, an N-type transistor N4 and an N-type transistor N3 connected in series in sequence, wherein the source of the P-type transistor P1 and the P-type transistor P3 are respectively connected to the high voltage AVDD, the gate of the P-type transistor P3 is connected to the drain of the P-type transistor P1 as the first signal O1 of the pair of control signals, the gate of the P-type transistor P1 is connected to the drain of the P-type transistor P3 as the second signal O1B of the pair of control signals, the drains of the N-type transistor N1 and the N-type transistor N3 are respectively connected to the ground voltage GND, and the gates of the N-type transistor N1 and the N-type transistor N3 are respectively connected to a pair of inverted input signals.

[0016] In order to reduce the occupied area, the voltage level converter is characterized in that the P-type transistor P2, the P-type transistor P4, the N-type transistor N2 and the N-type transistor N4 are medium voltage components.

[0017] In order to reduce the types of supply voltages, the voltage level converter is characterized in that the gates of the P-type transistor P2, the P-type transistor P4, the N-type transistor N2 and the N-type transistor N4 are respectively connected to the medium voltage VMID.

[0018] In order to reduce the occupied area, the voltage level converter is characterized in that the breakdown voltage of the P-type transistor P2 and the P-type transistor P4 is greater than the sum of the intermediate voltage VMID and the corresponding threshold voltage VTH.

[0019] In order to reduce the occupied area, the voltage level converter is characterized in that the breakdown voltage of the N-type transistor N2 and the N-type transistor N4 is greater than a difference, which is the sum of the high voltage VADD and the corresponding threshold voltage VTH minus the medium voltage VMID.

[0020] In order to provide an output signal with a voltage swing from VMID to AVDD, the above-mentioned voltage level converter is characterized in that the second-stage circuit also includes a P-type transistor P5 and an N-type transistor N5 connected in series between the high voltage VADD and the medium voltage VMID, and a P-type transistor P6 and an N-type transistor N6 connected in series between the high voltage VADD and the medium voltage VMID, wherein the gate of the P-type transistor P5 receives the above-mentioned first signal O1, the gate of the P-type transistor P6 receives the above-mentioned second signal O1B, the drain of the P-type transistor P5 is connected to the gate of the N-type transistor N6 as one of the pair of inverted output signals, and the drain of the P-type transistor P6 is connected to the gate of the N-type transistor N5 as the other of the pair of inverted output signals.

[0021] The voltage level converter is characterized in that the medium voltage VMID is approximately half of the high voltage AVDD.

[0022] According to an embodiment of the present application, an output stage circuit is provided, characterized in that it includes: a voltage supply module, which supplies an AVGP voltage and an AVGN voltage respectively; and more than one voltage level converter, which is used to output a pair of inverted output signals, and the pair of inverted output signals work between the high voltage AVDD and the medium voltage VMID, and the voltage level converter includes: a P-type transistor P1, a P-type transistor P2, an N-type transistor N2 and an N-type transistor N1 connected in series in sequence; and a P-type transistor P3, a P-type transistor P4, an N-type transistor N4 and an N-type transistor N3 connected in series in sequence, wherein the source of the P-type transistor P1 and the P-type transistor P3 are respectively connected to the high voltage AVDD. DD, the gate of the P-type transistor P3 is connected to the drain of the P-type transistor P1 to serve as the first signal OUT of a pair of inverted output signals, the gate of the P-type transistor P1 is connected to the drain of the P-type transistor P3 to serve as the second signal OUTB of the pair of inverted output signals, the drains of the N-type transistor N1 and the N-type transistor N3 are respectively connected to the ground voltage GND, the gates of the N-type transistor N1 and the N-type transistor N3 are respectively connected to a pair of inverted input signals, the gates of the above-mentioned P-type transistor P2 and the P-type transistor P4 are respectively connected to the AVGP voltage, and the gates of the above-mentioned N-type transistor N2 and the N-type transistor N4 are respectively connected to the AVGN voltage.

[0023] In order to reduce the occupied area, the output stage circuit is characterized in that the breakdown voltage of the P-type transistor P2 and the P-type transistor P4 is greater than the medium voltage VMID.

[0024] In order to reduce the occupied area, the output stage circuit is characterized in that the breakdown voltage of the N-type transistor N2 and the N-type transistor N4 is greater than the difference between the high voltage VADD and the medium voltage VMID.

[0025] In order to provide the AVGP voltage and the AVGN voltage, the above-mentioned output stage circuit is characterized in that the voltage supply module includes a P-type transistor PS and an N-type transistor NS, wherein the source of the P-type transistor PS is connected to the medium voltage VMID, and the gate and the drain of the P-type transistor PS are connected to the ground voltage through a first current source to provide the above-mentioned AVGP voltage, wherein the drain of the N-type transistor NS is connected to the medium voltage VMID, and the gate and the source of the N-type transistor NS are connected to the high voltage AVDD through a second current source to provide the above-mentioned AVGN voltage.

[0026] In order to reduce the occupied area, the output stage circuit is characterized in that the P-type transistor P2, the P-type transistor P4, the N-type transistor N2 and the N-type transistor N4 are medium voltage components.

[0027] According to an embodiment of the present application, a liquid crystal display screen is provided, comprising a source output circuit to control the display of the liquid crystal display screen, wherein the source output circuit comprises the voltage level converter or output stage circuit as described above.

[0028] Due to the adoption of the above scheme, the beneficial effects of the present application are as follows: the voltage level converter, output stage circuit and liquid crystal display screen provided by the present application have fewer components than the voltage level converter in the prior art, can reduce the chip area and have higher energy efficiency, which can not only reduce costs and increase reliability, but also reduce the size and energy consumption of mobile electronic devices, and further improve the performance of mobile electronic devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 It is a block diagram of a conventional liquid crystal display screen 100 .

[0030] Figure 2 It is a block diagram of the existing LVSH 200.

[0031] Figure 3 FIG. 2 is a schematic diagram of voltage values ​​of a signal at an input port 210 and a signal at an output port 220 of the LVSH 200 .

[0032] Figure 4 It is a block diagram of the existing LVSH 400.

[0033] Figure 5 for Figure 4 A circuit diagram of the LVSH core circuit 410 is shown.

[0034] Figure 6 FIG. 4 is a schematic diagram of operating voltages of various stages of the LVSH core circuit 410 .

[0035] Figure 7 FIG. 1 is a circuit diagram of a LVSH 700 according to a first embodiment of the present application.

[0036] Figure 8 Schematic diagram of the operating voltage of each level of the LVSH 700.

[0037] Fig. 9 FIG. 1 is a circuit diagram of an output stage circuit 900 according to a second embodiment of the present application.

[0038] Fig.10 is a schematic diagram of the operating voltage of the output stage circuit 900.

[0039] Fig.11 is a block diagram of an output stage circuit 1100 according to an embodiment of the present application. DETAILED DESCRIPTION

[0040] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other implementation methods obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0041] The terms "first", "second", "third", etc. (if any) in the specification and claims of this application and the drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the objects described in these descriptions can be interchanged where appropriate. In the description of this application, "plurality" means two or more, unless otherwise clearly and specifically defined. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. Some of the block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities can be implemented in software form, or in one or more hardware circuits or integrated circuits, or in different networks and / or processor devices and / or microcontroller devices.

[0042] In the description of the present application, it should be understood that the terms "center", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating directions or positional relationships, are based on the directions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or component referred to must have a specific direction, be constructed and operated in a specific direction, and therefore should not be understood as a limitation on the present application.

[0043] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, an electrical connection, or mutual communication; it can be a direct connection, or an indirect connection through an intermediate medium, it can be the internal connection of two components or the interaction relationship between two components. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0044] In order to make the purpose, features and advantages of the present application more obvious and easy to understand, the present application is further described in detail below in conjunction with drawings and specific implementation methods.

[0045] Please refer to Figure 7 , which is a circuit diagram of the LVSH 700 according to the first embodiment of the present application. Figure 7 The LVSH 700 shown includes two stages of circuits. The first stage circuit 710 includes eight transistors. The upper half of the first stage circuit 710 includes four P-type transistors, P1-P4. The lower half of the first stage circuit 710 includes four N-type transistors, N1-N4. The second stage circuit 720 includes four transistors, namely, P-type transistors P5 and P6 and N-type transistors N5 and N6.

[0046] and Figure 4 Compared with the existing LVSH 400 shown, Figure 7 The LVSH 700 shown omits the VQH rectifier circuit 420 and the VQL rectifier circuit 430. The LVSH 700 uses 12 transistors, and Figure 5 Compared to the 20 transistors used in the LVSH core circuit 410 shown, the number of components is also greatly reduced, from 20 transistors to 12 transistors.

[0047] The four transistors P2, P4, N2, and N4 of the first-stage circuit 710 can use medium-voltage components to distribute the high voltage AVDD to each transistor. When the voltage of the input signal IN is 1.5V, the voltage of the inverted input signal INB is the ground voltage GND or 0V. At this time, the potential of point D will be the ground voltage GND or 0V, and the potential of point C will also be the ground voltage GND or 0V. The potential of point O1B is pulled to VMID+VTH, where VTH is the threshold voltage or critical voltage (threshold voltage) of the transistor. The potential of point O1 is high voltage AVDD. The potential of point A will also be high voltage AVDD, and the potential of point B will be VMID-VTH.

[0048] In the above case, the voltage Drain-to-Source (VDS) of the P-type transistor P4 is equal to the potential difference from point C to point O1B, that is, 0V to VMID+VTH. The voltage across the P-type transistor P4 is VMID+VTH. The VDS of the N-type transistor N2 is equal to the potential difference from point B to point A, that is, VMID-VTH to VADD, that is, VADD-(VMID-VTH) or VADD-VMID+VTH. Since the VDS of the P-type transistor P4 and the N-type transistor N2 do not exceed their respective breakdown voltages, medium-voltage components can be used to implement the P-type transistor P4 and the N-type transistor N2.

[0049] Conversely, when the voltage of the input signal IN is the ground voltage GND or 0V, the voltage of the inverted input signal INB is 1.5V. At this time, the potential of point B will be the ground voltage GND or 0V, and the potential of point A will also be the ground voltage GND or 0V. The potential of point O1 is pulled to VMID+VTH. The potential of point O1B is high voltage AVDD. The potential of point C will also be high voltage AVDD, and the potential of point D is VMID-VTH.

[0050] In the above case, the voltage Drain-to-Source (VDS) of the P-type transistor P2 is equal to the potential difference from point A to point O1, that is, 0V to VMID+VTH. The voltage across the P-type transistor P2 is VMID+VTH. The VDS of the N-type transistor N4 is equal to the potential difference from point D to point C, that is, VMID-VTH to VADD, that is, VADD-(VMID-VTH) or VADD-VMID+VTH. Since the VDS of the P-type transistor P2 and the N-type transistor N4 do not exceed their respective breakdown voltages, medium-voltage components can be used to implement the P-type transistor P2 and the N-type transistor N4.

[0051] A pair of output signals O1 and O1B of the first stage circuit 710 respectively control the gates of two P-type transistors P5 and P6 of the second stage circuit 720. The function of the second stage circuit 720 is to convert the voltage from the original VMID+VTH to AVDD to VMID to AVDD, because VMID to AVDD is the voltage required for the LVSH output. Compared with the existing LVSH 400, the LVSH700 only uses two stages of circuits, and only needs a pair of output signals O1 and O1B of the first stage circuit 710 to control the second stage circuit 720. In addition, the LVSH 700 omits the VQH rectifier circuit 420 and the VQL rectifier circuit 430. Therefore, the LVSH 700 can reduce the occupied area and reduce power consumption.

[0052] Please refer to Figure 8 As shown, it is a schematic diagram of the operating voltage of each stage of the LVSH 700. The voltage values ​​of the output points O1 and O1B of the first stage circuit 710 are between the high voltage AVDD and VMID+VTH. The voltage values ​​of the output points OUT and OUTB of the second stage circuit 720 are between the high voltage AVDD and the medium voltage VMID.

[0053] Since the LVSH 700 has only two stages 710 and 720, the signal passes through fewer stages during transmission, so the signal propagation delay is shorter and the energy consumed during signal transmission is less. Figure 5 Compared with the five-level circuit of the prior art LVSH 400, the output signal can be faster and more power-saving.

[0054] Please refer to Fig. 9 , which is a circuit diagram of an output stage circuit 900 according to a second embodiment of the present application. Figure 7 Compared with the LVSH 700 shown, the output stage circuit 900 removes the second stage circuit 720 and has an additional voltage supply module 930 including two bias circuits.

[0055] LVSH910 and Figure 7 The first stage circuit 710 shown has the same structure of eight transistors. There are also four P-type transistors P1-P4 and four N-type transistors N1-N4. The sources of the P-type transistors P1 and P3 are also connected to the high voltage AVDD. The drains of the N-type transistors N1 and N3 are also connected to the ground voltage GND or 0V. Except that the gates of the P-type transistors P2 and P4 are connected to the AVGP voltage, and the gates of the N-type transistors N2 and N4 are connected to the AVGN voltage, the rest of the connections are the same as Figure 7 The first stage circuit 710 is shown to be the same. Its outputs are still the original O1 and O1 B, but are renamed OUT and OUTB.

[0056] Fig. 9 The second embodiment shown in the figure further adds a voltage supply module 930. The voltage supply module 930 includes two bias circuits to supply AVGP voltage and AVGN voltage to the gates of the P-type transistors P2 and P4 and the gates of the N-type transistors N2 and N4, respectively. The P-type transistors P2 and P4 and the N-type transistors N2 and N4 can use medium voltage components.

[0057] The AVGP bias circuit operates between the medium voltage VMID and the ground voltage GND or 0V. The AVGP bias circuit includes a P-type transistor PS and a first current source 931. The source of the P-type transistor PS is connected to the medium voltage VMID. The drain of the P-type transistor PS is connected to the gate and the positive electrode of the first current source 931 to supply the AVGP voltage to the gates of the P-type transistors P2 and P4. The AVGP voltage is equal to VMID minus one VGS, and when current passes through P2 and P4, their source voltage is equal to AVGP plus one VGS. Therefore, after proper design, the source voltage of P2 and P4 when current passes through can be made equal to VMID.

[0058] The AVGN bias circuit operates between the high voltage AVDD and the medium voltage VMID. The AVGN bias circuit includes an N-type transistor NS and a second current source 932. The drain of the N-type transistor PN is connected to the medium voltage VMID. The source of the N-type transistor PN is connected to the gate and the negative electrode of the second current source 932 to supply the AVGN voltage to the gates of the N-type transistors N2 and N4. The AVGN voltage is equal to VMID plus one VGS, and when current passes through N2 and N4, its source voltage is equal to AVGN minus one VGS. Therefore, after appropriate design, the source voltage of N2 and N4 when current passes through can be made equal to VMID.

[0059] Thus, the maximum VDS voltage across the N-type transistors N2 and N4 is reduced from AVDD-VMID+VTH to AVDD-VMID, and the maximum VDS voltage across the P-type transistors P2 and P4 is reduced from VMID+VTH to VMID. The low voltage level of OUT and OUTB is changed from VMID+VTH in the first embodiment to VMID in the second embodiment, so the second stage circuit 720 in the first embodiment can be removed.

[0060] Fig. 9 The voltage supply module 930 shown provides AVGP and AVGN voltages to the gates of the P-type transistors P2 and P4 and the gates of the N-type transistors N2 and N4, respectively. Figure 7Compared with the LVSH 700 shown, the VDS voltage of the P-type transistors P2 and P4 and the N-type transistors N2 and N4 in the first stage circuit 910 is reduced, so that the reliability of the P-type transistors P2 and P4 and the N-type transistors N2 and N4 can be increased.

[0061] Please refer to Fig.10 As shown, it is Fig. 9 The operating voltage diagram of the output stage circuit 900 is shown in FIG. The voltage values ​​of the output points OUT and OUTB are between the high voltage AVDD and the medium voltage VMID. Figure 7 LVSH 700 or Fig. 9 The output level of the LVSH 910 must be between the high voltage AVDD and the medium voltage VMID. The output of the first stage circuit 710 of the LVSH 700 is between the high voltage AVDD and (VMID+VTH), so the second stage circuit 720 is required to convert the output to between the high voltage AVDD and the medium voltage VMID. Since the output of the LVSH 910 is directly between the high voltage AVDD and the medium voltage VMID, the second stage circuit 720 can be omitted.

[0062] Please refer to Fig.11 As shown, it is a block diagram of an output stage circuit 1000 according to an embodiment of the present application. Fig.11 The output stage circuit 1100 shown may include only a single Fig. 9 The voltage supply module 930 shown in the figure can supply AVGP voltage and AVGN voltage which can be connected to a plurality of voltage level converters 910. Fig.10 The illustrated embodiment may include a plurality of voltage level converters 910 - 1 , 910 - 2 , . . . , 910 -N, where N is a positive integer greater than 1.

[0063] When the output stage circuit 1100 is applied to Figure 1 In the source driving circuit of the liquid crystal display screen 100 shown, the above N can be a positive integer greater than 1000. Since only one voltage supply module 930 is needed for thousands of voltage level converters 910, the proportion of the increased area is quite limited, but the VDS of thousands of components in thousands of voltage level converters 910 can be reduced, and the second stage of the first embodiment is removed, so each voltage level converter 910 can have 4 fewer components than the voltage level converter 700 of the first embodiment. Therefore, whether it is LVSH 700 or 910, when used in the source driving circuit, it can reduce a lot of components compared with the traditional source driving circuit. Not only does it reduce the cost, but also improve the reliability of the source driving circuit.

[0064] According to an embodiment of the present application, a voltage level converter is provided, characterized in that it includes: a second-stage circuit operating between a high voltage AVDD and a medium voltage VMID, for receiving a pair of control signals to output a pair of inverted output signals; and a first-stage circuit, further including a P-type transistor P1, a P-type transistor P2, an N-type transistor N2 and an N-type transistor N1 connected in series in sequence, and a P-type transistor P3, a P-type transistor P4, an N-type transistor N4 and an N-type transistor N3 connected in series in sequence, wherein the source of the P-type transistor P1 and the P-type transistor P3 are respectively connected to the high voltage AVDD, the gate of the P-type transistor P3 is connected to the drain of the P-type transistor P1 as the first signal O1 of the pair of control signals, the gate of the P-type transistor P1 is connected to the drain of the P-type transistor P3 as the second signal O1B of the pair of control signals, the drains of the N-type transistor N1 and the N-type transistor N3 are respectively connected to the ground voltage GND, and the gates of the N-type transistor N1 and the N-type transistor N3 are respectively connected to a pair of inverted input signals.

[0065] In order to reduce the occupied area, the voltage level converter is characterized in that the P-type transistor P2, the P-type transistor P4, the N-type transistor N2 and the N-type transistor N4 are medium voltage components.

[0066] In order to reduce the types of supply voltages, the voltage level converter is characterized in that the gates of the P-type transistor P2, the P-type transistor P4, the N-type transistor N2 and the N-type transistor N4 are respectively connected to the medium voltage VMID.

[0067] In order to reduce the occupied area, the voltage level converter is characterized in that the breakdown voltage of the P-type transistor P2 and the P-type transistor P4 is greater than the sum of the intermediate voltage VMID and the corresponding threshold voltage VTH.

[0068] In order to reduce the occupied area, the voltage level converter is characterized in that the breakdown voltage of the N-type transistor N2 and the N-type transistor N4 is greater than a difference, which is the sum of the high voltage VADD and the corresponding threshold voltage VTH minus the medium voltage VMID.

[0069] In order to provide an output signal with a voltage swing from VMID to AVDD, the above-mentioned voltage level converter is characterized in that the second-stage circuit also includes a P-type transistor P5 and an N-type transistor N5 connected in series between the high voltage VADD and the medium voltage VMID, and a P-type transistor P6 and an N-type transistor N6 connected in series between the high voltage VADD and the medium voltage VMID, wherein the gate of the P-type transistor P5 receives the above-mentioned first signal O1, the gate of the P-type transistor P6 receives the above-mentioned second signal O1B, the drain of the P-type transistor P5 is connected to the gate of the N-type transistor N6 as one of the pair of inverted output signals, and the drain of the P-type transistor P6 is connected to the gate of the N-type transistor N5 as the other of the pair of inverted output signals.

[0070] The voltage level converter is characterized in that the medium voltage VMID is approximately half of the high voltage AVDD.

[0071] According to an embodiment of the present application, an output stage circuit is provided, characterized in that it includes: a voltage supply module, which supplies an AVGP voltage and an AVGN voltage respectively; and more than one voltage level converter, which is used to output a pair of inverted output signals, and the pair of inverted output signals work between the high voltage AVDD and the medium voltage VMID, and the voltage level converter includes: a P-type transistor P1, a P-type transistor P2, an N-type transistor N2 and an N-type transistor N1 connected in series in sequence; and a P-type transistor P3, a P-type transistor P4, an N-type transistor N4 and an N-type transistor N3 connected in series in sequence, wherein the source of the P-type transistor P1 and the P-type transistor P3 are respectively connected to the high voltage AVDD. DD, the gate of the P-type transistor P3 is connected to the drain of the P-type transistor P1 to serve as the first signal OUT of a pair of inverted output signals, the gate of the P-type transistor P1 is connected to the drain of the P-type transistor P3 to serve as the second signal OUTB of the pair of inverted output signals, the drains of the N-type transistor N1 and the N-type transistor N3 are respectively connected to the ground voltage GND, the gates of the N-type transistor N1 and the N-type transistor N3 are respectively connected to a pair of inverted input signals, the gates of the above-mentioned P-type transistor P2 and the P-type transistor P4 are respectively connected to the AVGP voltage, and the gates of the above-mentioned N-type transistor N2 and the N-type transistor N4 are respectively connected to the AVGN voltage.

[0072] In order to reduce the occupied area, the output stage circuit is characterized in that the breakdown voltage of the P-type transistor P2 and the P-type transistor P4 is greater than the medium voltage VMID.

[0073] In order to reduce the occupied area, the output stage circuit is characterized in that the breakdown voltage of the N-type transistor N2 and the N-type transistor N4 is greater than the difference between the high voltage VADD and the medium voltage VMID.

[0074] In order to provide the AVGP voltage and the AVGN voltage, the above-mentioned output stage circuit is characterized in that the voltage supply module includes a P-type transistor PS and an N-type transistor NS, wherein the source of the P-type transistor PS is connected to the medium voltage VMID, and the gate and the drain of the P-type transistor PS are connected to the ground voltage through a first current source to provide the above-mentioned AVGP voltage, wherein the drain of the N-type transistor NS is connected to the medium voltage VMID, and the gate and the source of the N-type transistor NS are connected to the high voltage AVDD through a second current source to provide the above-mentioned AVGN voltage.

[0075] In order to reduce the occupied area, the output stage circuit is characterized in that the P-type transistor P2, the P-type transistor P4, the N-type transistor N2 and the N-type transistor N4 are medium voltage components.

[0076] According to an embodiment of the present application, a liquid crystal display screen is provided, comprising a source output circuit to control the display of the liquid crystal display screen, wherein the source output circuit comprises the voltage level converter or output stage circuit as described above.

[0077] Due to the adoption of the above scheme, the beneficial effects of the present application are as follows: the voltage level converter, output stage circuit and liquid crystal display screen provided by the present application have fewer components than the voltage level converter in the prior art, can reduce the chip area and have higher energy efficiency, which can not only reduce costs and increase reliability, but also reduce the size and energy consumption of mobile electronic devices, and further improve the performance of mobile electronic devices.

[0078] The above is only a preferred specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can make equivalent substitutions or changes within the technical scope disclosed in the present application according to the technical solution and application concept of the present application, which should be covered by the protection scope of the present application.

Claims

1. A liquid crystal display screen, characterized in that: Include: The output stage circuit controls the display of the liquid crystal display screen, comprising: A voltage supply module, supplying an AVGP voltage and an AVGN voltage respectively; and One or more voltage level converters are used to output a pair of inverted output signals, wherein the pair of inverted output signals operates between the high voltage AVDD and the medium voltage VMID, and the voltage level converter comprises: A P-type transistor P1, a P-type transistor P2, an N-type transistor N2 and an N-type transistor N1 connected in series in sequence; and The P-type transistor P3, the P-type transistor P4, the N-type transistor N4 and the N-type transistor N3 are connected in series in sequence. The source of the P-type transistor P1 and the P-type transistor P3 are respectively connected to the high voltage AVDD, the gate of the P-type transistor P3 is connected to the drain of the P-type transistor P1 to serve as the first signal OUT of a pair of inverted output signals, the gate of the P-type transistor P1 is connected to the drain of the P-type transistor P3 to serve as the second signal OUTB of the pair of inverted output signals, the drain of the N-type transistor N1 and the N-type transistor N3 are respectively connected to the ground voltage GND, the gate of the N-type transistor N1 and the N-type transistor N3 are respectively connected to a pair of inverted input signals, the gate of the above-mentioned P-type transistor P2 and the P-type transistor P4 are respectively connected to the AVGP voltage, and the gate of the above-mentioned N-type transistor N2 and the N-type transistor N4 are respectively connected to the AVGN voltage.

2. The liquid crystal display screen according to claim 1, characterized in that: The breakdown voltages of the P-type transistor P2 and the P-type transistor P4 are greater than the middle voltage VMID.

3. The liquid crystal display screen according to claim 1, characterized in that: The breakdown voltage of the N-type transistor N2 and the N-type transistor N4 is greater than the difference between the high voltage VADD and the medium voltage VMID.

4. The liquid crystal display screen according to claim 1, characterized in that: The voltage supply module includes a P-type transistor PS and an N-type transistor NS, wherein the source of the P-type transistor PS is connected to the medium voltage VMID, and the gate and drain of the P-type transistor PS are connected to the ground voltage through a first current source to provide the above-mentioned AVGP voltage, wherein the drain of the N-type transistor NS is connected to the medium voltage VMID, and the gate and source of the N-type transistor NS are connected to the high voltage AVDD through a second current source to provide the above-mentioned AVGN voltage.

5. The liquid crystal display screen according to claim 1, characterized in that: The P-type transistor P2 , the P-type transistor P4 , the N-type transistor N2 , and the N-type transistor N4 are medium voltage components.

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