Formation method of semiconductor structure

Abstract

A semiconductor structure forming method comprises the steps that a substrate and a base layer structure located on the surface of the substrate are formed, and a plurality of grooves are formed in the base layer structure; a first material layer is formed on the surface of the side wall of each groove, the material of the first material layer is a two-dimensional material, the two-dimensional material is provided with a plurality of monatomic layers arranged along a first direction, the first direction is perpendicular to the surface of the side wall of the groove, the arrangement plane of each monatomic layer is parallel to the surface of the side wall of the groove, and the arrangement plane of each monatomic layer is parallel to the surface of the side wall of the groove. Each first material layer exposes the bottom surface of the groove; and removing the base layer structure between the first material layers. According to the forming method of the semiconductor structure, the forming process difficulty of the two-dimensional material structure is reduced, and the device performance and the integration degree are improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for forming a semiconductor structure. Background Art

[0002] High-performance integrated circuit technology developed since the 1960s is mainly based on silicon-based processes, especially thin-body field-effect transistor technology, such as fin transistors or silicon-on-insulator technology. However, as the size of silicon-based transistor devices decreases, the thickness of the thin layer of single-crystal silicon used as the channel continues to decrease. In particular, in thin-layer single-crystal silicon transistors with a channel thickness of less than about 3nm, the reduction in channel thickness causes the carrier transport in the channel to be increasingly seriously scattered by the rough interface, resulting in a significant decrease in mobility, which seriously affects the performance of silicon-based devices.

[0003] On this basis, two-dimensional semiconductor materials, such as transition metal chalcogenides, graphene, black phosphorus, etc., have become ideal materials for the next generation of transistor devices after silicon-based transistors due to their high mobility, adjustable energy bands, good flexibility, and uniform surface flatness. Using two-dimensional materials as channels can significantly improve carrier mobility and further reduce the thickness of the channel, which can be controlled to below 1nm-2nm, greatly improving the density and performance of transistors in integrated circuits.

[0004] For transistors with two-dimensional material channels, by contacting the layer-toward edge surface of the two-dimensional material with the metal connection structure, a strong chemical bond-like interaction can be formed between the layer-toward edge surface and the metal connection structure, which is beneficial to charge migration. Therefore, by contacting the layer-toward edge surface of the two-dimensional material with the metal connection structure, the contact resistance is reduced and the contact performance is optimized.

[0005] In the prior art, two-dimensional material transistor devices mostly use the traditional planar channel structure, which occupies a large working area and is not conducive to the miniaturization of device size. The two-dimensional material transistor device with vertically stacked channels can reduce the working area occupied by the channel. However, its formation process is very difficult and costly, and the production feasibility and efficiency need to be improved. Summary of the invention

[0006] The technical problem solved by the present invention is to provide a method for forming a semiconductor structure, which uses a self-alignment process to form a stable two-dimensional material channel, changes the direction of the single atomic layer arrangement plane of the two-dimensional material channel relative to the substrate surface, and reduces the difficulty of the formation process of the two-dimensional material structure in which the layer edge surface is parallel to the substrate, thereby improving the device performance and integration.

[0007] To solve the above technical problems, the technical solution of the present invention provides a method for forming a semiconductor structure, including: forming a substrate and a base structure located on the surface of the substrate, wherein the base structure has a plurality of grooves; forming a first material layer on the side wall surface of each groove, wherein the material of the first material layer is a two-dimensional material, wherein the two-dimensional material has a plurality of single atomic layers arranged along a first direction, wherein the first direction is perpendicular to the side wall surface of the groove, and the arrangement plane of each single atomic layer is parallel to the side wall surface of the groove, and each first material layer exposes the bottom surface of the groove; and removing the base structure between each first material layer.

[0008] Optionally, the method further includes: forming a device structure spanning the first material layer.

[0009] Optionally, before forming the device structure, the method further includes: forming an isolation structure located between the first material layers on the surface of the substrate, wherein at least a portion of the isolation structure is located in each trench.

[0010] Optionally, the device structure includes a gate, and the gate is perpendicular to an extension direction of the first material layer.

[0011] Optionally, the material of the base structure includes a single crystal material; the single crystal material includes a non-metallic single material or a metallic single material.

[0012] Optionally, the non-metallic single-element material includes single-crystal silicon, quartz, silicon carbide or a germanium-containing compound; and the metallic single-element material includes single-crystal copper.

[0013] Optionally, the material of the first material layer includes transition metal chalcogenide, graphene, black phosphorus, indium selenide, gallium selenide or bismuth oxyselenide.

[0014] Optionally, after forming the trench and before forming the first material layer, the method further includes: forming an auxiliary layer on the surface of the trench sidewall; the material of the auxiliary layer includes silicon dioxide, nickel, copper, silver or gold.

[0015] Optionally, when the material of the first material layer is a transition metal chalcogenide, the material of the auxiliary layer includes silicon dioxide; when the material of the first material layer is graphene, the material of the auxiliary layer includes copper or nickel.

[0016] Optionally, each first material layer has 1 to 2 monoatomic layers.

[0017] Optionally, the method for forming a substrate and a base structure includes: providing a substrate; forming a first mask layer on the surface of the substrate, the first mask layer exposing a portion of the substrate surface; using the first mask layer as a mask, etching the substrate to form a substrate and a base structure with grooves.

[0018] Optionally, the process of forming the first mask layer includes: a self-aligned double patterning process or a self-aligned quadruple patterning process.

[0019] Optionally, the method for forming the first material layer includes: depositing an initial first material layer on the groove sidewalls, the groove bottom and the top of the base structure; etching back the initial first material layer at the groove bottom and the top of the base structure to form a first material layer located on the surface of the groove sidewalls.

[0020] Optionally, the formation process of the initial first material layer includes an atomic layer deposition process or an epitaxial growth process.

[0021] Optionally, before etching back the initial first material layer, the method further includes: forming a first etching protection layer at least on a surface of the initial first material layer on the sidewall of the trench.

[0022] Optionally, the distance between adjacent first material layers ranges from 10 nanometers to 20 nanometers.

[0023] Optionally, a top surface of the isolation structure is higher than a top surface of the first material layer.

[0024] Optionally, the first material layer has a first side wall and a second side wall opposite to each other, the first side wall and the second side wall are both parallel to the arrangement plane of the single atomic layer, and the gate is in contact with the first side wall and the second side wall respectively and simultaneously.

[0025] Optionally, the substrate includes a first region and second regions located on both sides of the first region, the first material layer is formed on surfaces of the first region and the second region, and the gate is formed between two adjacent second regions.

[0026] Optionally, the method further includes: forming a source-drain contact conductive structure on a top surface of the first material layer on the second region.

[0027] Optionally, a bottom surface of the source-drain contact conductive structure is flush with a top surface of the first material layer.

[0028] Optionally, part of the source-drain contact conductive structure is located in the first material layer.

[0029] Optionally, the source-drain contact conductive structure includes: a contact layer located on the surface of the first material layer and a conductive layer located on the surface of the contact layer; the material of the contact layer includes bismuth, tellurium or other semi-metallic materials.

[0030] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0031] In the method for forming a semiconductor structure provided by the technical solution of the present invention, the monoatomic layer of the first material layer grows along the side wall of the groove, and the arrangement plane of the formed monoatomic layer is parallel to the surface of the side wall of the groove, that is, perpendicular to the surface of the substrate. In the process of forming the first material layer, the groove can self-align to form a stable two-dimensional material channel, so as to better control the growth position of the first material layer, make the controllability and flexibility of the spacing size between the first material layers better, and reduce the process difficulty of forming the first material layer composed of two-dimensional materials; secondly, in the process of forming the first material layer on the surface of the groove side wall, the number of monoatomic layers formed can be better controlled by controlling the process parameters, so that the thickness size of the first material layer is more controllable, and the stability and adjustability of the formation process are optimized.

[0032] Furthermore, after forming the first material layer, a gate across the first material layer is also formed. Since the gate across the first material layer, gate control can be formed on the sidewall surfaces of both sides of the first material layer, thereby realizing a dual-gate transistor composed of two-dimensional materials and realizing two channel regions for carrier migration, thereby being able to reduce the working area occupied by the channel while improving the channel carrier mobility, thereby improving device performance and integration.

[0033] Furthermore, before forming the first material layer, an auxiliary layer is pre-formed on the surface of the groove sidewall, and the auxiliary layer can optimize the lattice adaptation conditions of the surface of the base structure and release stress, thereby assisting the growth of the two-dimensional material atomic layer on its surface, and further helping to improve the formation quality of the first material layer on its surface, and optimizing the morphology, uniformity and controllability of the formation process of the first material layer.

[0034] Furthermore, the formation process of the first mask layer required to form the groove includes: a self-aligned double patterning process or a self-aligned quadruple patterning process. The two processes can form grooves of smaller sizes, thereby also achieving a significant reduction in the spacing between the first material layers, thereby further improving device performance and integration. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 It is a schematic diagram of the cross-sectional structure of a two-dimensional material transistor device;

[0036] Figures 2 to 19 is a structural schematic diagram of a formation process of a semiconductor structure according to an embodiment of the present invention;

[0037] Fig. 20 It is a schematic diagram of a partial cross-sectional structure of a semiconductor structure forming process in another embodiment of the present invention. DETAILED DESCRIPTION

[0038] As described in the background technology, under the existing technology, two-dimensional material transistor devices mostly use traditional planar channel structures, which occupy a large working area and are not conducive to the miniaturization of device size. By forming a two-dimensional material transistor device with vertically stacked channels, the working area occupied by the channel can be reduced. However, its formation process is very difficult and costly, and the production feasibility and efficiency need to be improved.

[0039] Figure 1 This is a schematic diagram of the cross-sectional structure of a two-dimensional material transistor device.

[0040] Please refer to Figure 1 The two-dimensional material transistor device includes: a substrate 100; an initial oxide layer 101 located on the substrate 100; a two-dimensional material channel layer 102 located on the initial oxide layer 101, wherein the two-dimensional material channel layer 102 has a plurality of single atomic layers stacked and arranged parallel to the surface of the substrate 100; a gate dielectric layer 105 located on the surface of the two-dimensional material channel layer 102; a gate electrode 104 located on the surface of the gate dielectric layer 105; and source-drain electrodes 103 located on the layer-toward edge surfaces on both sides of the two-dimensional material channel layer 102, wherein the contact resistance between the layer-toward edge surfaces and the source-drain electrodes 103 is small and the contact performance is good.

[0041] Among them, since the carriers migrate between the source and drain electrodes 103 when the two-dimensional material transistor device is working, the channel of the two-dimensional material transistor device is parallel to the surface of the substrate 100, resulting in a large actual working area occupied by the channel, and the device performance and integration need to be improved.

[0042] In order to solve the above technical problems, the technical solution of the present invention provides a method for forming a semiconductor structure, wherein a single atomic layer of a first material layer grows along the side wall of a groove, so that the arrangement plane of the formed single atomic layer is parallel to the surface of the groove side wall, that is, perpendicular to the surface of the substrate. In the process of forming the first material layer, a stable two-dimensional material layer is formed on the surface of the groove through a self-alignment process, thereby better controlling the growth position of the first material layer, making the controllability and flexibility of the spacing size between the first material layers better, and reducing the process difficulty of forming the first material layer composed of two-dimensional materials; secondly, in the process of forming the first material layer on the surface of the groove side wall, the number of single atomic layers formed can be better controlled by controlling the process parameters, so that the thickness size of the first material layer is more controllable, and the stability and adjustability of the formation process are optimized.

[0043] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0044] Figures 2 to 19 It is a structural schematic diagram of a formation process of a semiconductor structure according to an embodiment of the present invention.

[0045] Please refer to Figure 2 , providing a substrate 200; forming a first mask layer 201 on the surface of the substrate 200, wherein the first mask layer 201 exposes a portion of the surface of the substrate 200.

[0046] The substrate 200 provides raw materials for the base and base structure to be formed subsequently. In this embodiment, the material of the substrate 200 is single crystal silicon.

[0047] In other embodiments, the material of the substrate includes other single crystal materials; the single crystal material includes non-metallic single material or metallic single material silicon. Specifically, the non-metallic single material includes quartz, silicon carbide, other silicon-containing compounds or germanium-containing compounds; the metallic single material includes single crystal copper. In this embodiment, the first mask layer 201 is used to define the pattern of the grooves subsequently formed in the substrate 200.

[0048] In this embodiment, the process of forming the first mask layer 201 includes: a self-aligned quadruple patterning process.

[0049] Among them, the process of forming the first mask layer 201 using a self-aligned quadruple patterning process includes: forming a first graphic material layer (not shown) on the substrate 200; forming a second graphic material layer (not shown) on the first graphic material layer; forming a first mandrel structure (not shown) on the second graphic material layer; forming a first side wall (not shown) on both sides of the first mandrel structure; removing the first mandrel structure; using the first side wall as a mask, etching the second graphic material layer to form a second mandrel structure (not shown); forming a second side wall (not shown) on both sides of the second mandrel structure; removing the second mandrel structure; using the second side wall as a mask, etching the first graphic material layer to form a first mask layer 201.

[0050] In this embodiment, the first mask layer 201 is formed by the self-aligned quadruple patterning process, which can significantly reduce the size of the trench subsequently formed in the substrate 200, thereby facilitating the formation of a device with high integration and smaller size.

[0051] Specifically, the pitch size of the first mask layer 201 ranges from 20 nanometers to 40 nanometers.

[0052] In another embodiment, the process of forming the first mask layer includes: a self-aligned double patterning process.

[0053] Among them, the process of forming the first mask layer using a self-aligned double patterning process includes: forming a first graphic material layer on the substrate 200; forming a first core shaft structure on the first graphic material layer; forming a first side wall on both sides of the first core shaft structure; removing the first core shaft structure; using the first side wall as a mask, etching the first graphic material layer to form a first mask layer.

[0054] Please refer to Figure 3 , using the first mask layer 201 as a mask, etching the substrate 200 to form a base 230 and a base structure 204 having a groove 202 .

[0055] The trench 202 provides space for the first material layer to be formed subsequently, and the sidewall of the trench 202 also defines the growth position of the first material layer to be formed subsequently. The bottom of the trench 202 is flush with the bottom of the base structure 204. The material of the base structure 204 includes silicon.

[0056] In the present embodiment, the trench 202 with a smaller size is formed by a self-aligned patterning process, thereby achieving a significant reduction in the spacing between the first material layers formed subsequently, thereby improving the device performance and integration.

[0057] In this embodiment, the process of etching the substrate 200 includes a dry etching process.

[0058] Next, a first material layer is formed on the side wall surface of each groove 202. The material of the first material layer is a two-dimensional material. The two-dimensional material has several layers of single atomic layers arranged along a first direction. The first direction is perpendicular to the side wall surface of the groove 202. The arrangement plane of each single atomic layer is parallel to the side wall surface of the groove 202. Each first material layer exposes the bottom surface of the groove 202.

[0059] Specifically, in this embodiment, the steps of forming the first material layer are as follows: Figures 4 to 7 shown.

[0060] Please refer to Figure 4 , forming an auxiliary layer 205 on the sidewall surface of the trench 202 .

[0061] In this embodiment, the auxiliary layer 205 can optimize the lattice adaptation conditions of the silicon surface of the base structure 204 and release stress, thereby assisting the growth of subsequent two-dimensional material atomic layers on its surface, and further helping to improve the formation quality of subsequent first material layers on its surface, thereby optimizing the morphology, uniformity and controllability of the formation process of the first material layer.

[0062] In this embodiment, the material of the auxiliary layer 205 includes silicon dioxide, nickel, copper, silver or gold.

[0063] Specifically, the thickness of the auxiliary layer 205 is in the range of 1 nm to 5 nm. The formation process of the auxiliary layer 205 includes a chemical vapor deposition process or an atomic layer deposition process.

[0064] In this embodiment, the auxiliary layer 205 is also located on the top surface of the base structure 204 .

[0065] Please refer to Figure 5 An initial first material layer 210 is deposited on the auxiliary layer 205 on the sidewall of the trench 202 , the bottom of the trench 202 and the top of the base structure 204 .

[0066] In this embodiment, the initial first material layer 210 provides raw materials for forming subsequent first material layers.

[0067] The material of the initial first material layer 210 is a two-dimensional material. The initial first material layer 210 is divided into a horizontal two-dimensional layer 215 and a vertical two-dimensional layer 216 deposited simultaneously. The horizontal two-dimensional layer 215 is located on the top surface of the base structure 204, and the horizontal two-dimensional layer 215 has several layers of single atomic layers 215a arranged along a direction S perpendicular to the surface of the substrate 230, and the arrangement plane of each single atomic layer 215a is parallel to the surface of the substrate 230. The vertical two-dimensional layer 216 is located on the side wall surface of the groove 202, and the vertical two-dimensional layer 216 has several layers of single atomic layers 216a arranged along a direction T perpendicular to the side wall surface of the groove 202, and the arrangement plane of each single atomic layer 216a is parallel to the side wall surface of the groove 202.

[0068] In this embodiment, the arrangement plane of the single atomic layer 215a of the horizontal two-dimensional layer 215 represents the plane where each single atomic layer 215a in the horizontal two-dimensional layer 215 is located, and the plane where the single atomic layer 215a is located is perpendicular to the stacking direction (S direction) of the single atomic layer 215a. The arrangement plane of the single atomic layer 216a of the vertical two-dimensional layer 216 represents the plane where each single atomic layer 216a in the vertical two-dimensional layer 216 is located, and the plane where the single atomic layer 216a is located is perpendicular to the stacking direction (T direction) of the single atomic layer 216a.

[0069] Wherein, each monoatomic layer in the two-dimensional material is stacked in a van der Waals manner, and each monoatomic layer is a crystalline monoatomic layer.

[0070] Because an auxiliary layer 205 is formed on the side wall surface of the groove 202 before forming the initial first material layer 210, the auxiliary layer 205 can optimize the lattice adaptation conditions of the silicon surface of the base structure 204 and release stress, thereby assisting the growth of the two-dimensional material atomic layer on its surface, and further helping to improve the formation quality of the initial first material layer 210 on its surface, thereby optimizing the morphology, uniformity and controllability of the formation process of the initial first material layer 210.

[0071] In this embodiment, the initial first material layer 210 has two monoatomic layers.

[0072] In another embodiment, the number of monoatomic layers of the initial first material layer is 1. Based on the characteristics of two-dimensional materials, when the number of monoatomic layers is small, the bandwidth is suitable for manufacturing transistors.

[0073] In other embodiments, the initial first material layer has a monoatomic layer number ranging from 3 to 10 layers.

[0074] In this embodiment, the material of the initial first material layer 210 is molybdenum disulfide, and the material of the auxiliary layer 205 is silicon dioxide. The presence of the auxiliary layer 205 of silicon dioxide is conducive to better deposition of molybdenum disulfide.

[0075] In other embodiments, the material of the initial first material layer includes other transition metal chalcogenides, graphene, black phosphorus, indium selenide, gallium selenide or bismuth selenide oxide compounds. When the material of the initial first material layer is a transition metal chalcogenide, the material of the auxiliary layer includes silicon dioxide; when the material of the initial first material layer is graphene, the material of the auxiliary layer includes copper or nickel, so as to facilitate better deposition of the initial first material layer.

[0076] In this embodiment, the formation process of the initial first material layer 210 includes an atomic layer deposition process or an epitaxial growth process. After the initial first material layer 210 is formed, the initial first material layer 210 is further annealed.

[0077] Please refer to Figure 6 , forming a first etching protection layer 211 on the surface of the initial first material layer 210 .

[0078] In this embodiment, the first etching protection layer 211 is formed on the surface of the horizontal two-dimensional layer 215 and the vertical two-dimensional layer 216 .

[0079] The first etching protection layer 211 is used to protect the vertical two-dimensional layer 216 to prevent the thickness of the vertical two-dimensional layer 216 from being affected during the subsequent removal of the horizontal two-dimensional layer 215 .

[0080] The material of the first etching protection layer 211 includes silicon nitride or silicon oxide.

[0081] Please refer to Figure 7 , the initial first material layer 210 at the bottom of the trench 202 and the top of the base structure 204 is etched back to form a first material layer 220 located on the sidewall surface of the trench 202 .

[0082] Among them, by removing the horizontal two-dimensional layer 215 on the top of the base structure 204, the vertical two-dimensional layer 216 located on the side wall surface of the groove 202 is retained, that is, the first material layer 220 is formed. The two-dimensional material of the first material layer 220 has a plurality of single atomic layers 220a arranged along a first direction T, the first direction T is perpendicular to the side wall surface of the groove 202, the arrangement plane of each single atomic layer 220a is parallel to the side wall surface of the groove 202, and each first material layer 220 exposes the bottom surface of the groove 202. The arrangement plane of the single atomic layer 220a represents the plane where each single atomic layer 220a in the two-dimensional material is located.

[0083] In this embodiment, the process of etching the initial first material layer 210 includes: a neutral beam etching process (neutral beam etching) or a soft plasma etching process (soft plasma etching).

[0084] The first material layer 220 is subsequently used as a channel of a two-dimensional material transistor. During the formation of the first material layer 220, since the single atomic layer of the initial first material layer 210 grows along the side wall of the groove 202 in a self-aligned manner, the arrangement plane of the formed single atomic layer is parallel to the side wall surface of the groove 202. Therefore, the growth position of the first material layer 220 can be better controlled through the groove 202, so that the spacing size between the first material layers 220 is more controllable and flexible. In this embodiment, on the basis of forming the first mask layer 201 by a self-aligned quadruple patterning process, the first material layer 220 can be formed on the side wall of the groove 202, further reducing the pitch size between the first material layers 220.

[0085] Secondly, in the process of forming the first material layer 220 on the side wall surface of the groove 202, the number of single atomic layers formed can be better controlled by controlling the process parameters, so that the thickness size of the first material layer 220 is more controllable, the stability and adjustability of the formation process are optimized, and the process difficulty of forming the first material layer 220 composed of two-dimensional materials is reduced.

[0086] Please refer to Figure 8, a second etching protection layer 221 is deposited on the sidewall surface of the first material layer 220 and a portion of the surface of the auxiliary layer 205 parallel to the substrate 230 .

[0087] In this embodiment, the material of the second etching protection layer 221 includes silicon nitride and silicon oxide.

[0088] Please refer to Fig. 9 , filling the first isolation material layer 225 in the trench 202 ; and performing a planarization process on the first isolation material layer 225 until the top surface of the first material layer 220 is exposed.

[0089] Specifically, the material of the first isolation material layer 225 includes silicon oxide.

[0090] During the planarization process, the second etching protection layer 221 is used as an etching stop layer.

[0091] Please refer to Figures 10 to 12 ,in, Fig.11 for Fig.10 Along the P direction, Fig.12 The three-dimensional structure diagram along the Q direction, Fig.10 for Fig.11 The cross-sectional structure diagram along the AA' direction, Fig.12 for Fig.11 The cross-sectional structure along the BB' direction, Fig.12 still Fig.10 Cross-sectional structure diagram along XX' direction.

[0092] The base structure 204 between each first material layer 220 is removed until the substrate 230 is exposed; a second isolation material layer 231 is deposited on the surface of the substrate 230, the surface of the first material layer 220 and the surface of the first isolation material layer 225, and the top of the second isolation material layer 231 is higher than the top surface of the first material layer 220; an interlayer dielectric layer 232 is formed on the surface of the second isolation material layer 231.

[0093] In this embodiment, the first isolation material layer 225 and the second isolation material layer 231 together form an isolation structure (not shown). The isolation structure is located on the surface of the substrate 230 and between the first material layers 220. The isolation structure plays an electrical isolation role for the subsequently formed two-dimensional material transistor.

[0094] In this embodiment, the distance D between adjacent first material layers 220 ranges from 10 nanometers to 20 nanometers, which greatly reduces the area occupied by the transistor channel and can meet the needs of more small-sized and highly integrated transistor designs.

[0095] It should be noted that, for ease of understanding, Fig.11The interlayer dielectric layer 232 , the isolation structure, the second etching protection layer 221 and the auxiliary layer 205 are omitted, and only the positional relationship between the substrate 230 and the first material layer 220 is shown.

[0096] Next, a gate is formed across the first material layer 220 , and the gate is perpendicular to the extension direction of the first material layer 220 .

[0097] In this embodiment, the substrate 230 includes a first region I and second regions II located on both sides of the first region I (eg, Fig.11 As shown), the first material layer 220 is formed on the surfaces of the first region I and the second region II, and the gate is formed between two adjacent second regions II.

[0098] Specifically, the specific steps of forming the gate are as follows: Figures 13 to 16 shown.

[0099] Please refer to Fig.13 and Fig.14 ,in, Fig.13 and Fig.12 The viewing direction is the same as Fig.14 and Fig.10 In the same viewing direction, a gate opening 240 is formed in the isolation structure and the interlayer dielectric layer 232 .

[0100] In this embodiment, the gate opening 240 is located in the interlayer dielectric layer 232 and the isolation structure between two adjacent second regions II.

[0101] The gate opening 240 exposes the surface of the first material layer 220 , and the bottom of the gate opening 240 is higher than the top surface of the substrate 230 .

[0102] In this embodiment, the method for forming the gate opening 240 includes: forming a second mask layer (not shown) on the interlayer dielectric layer 232, the second mask layer exposing a portion of the surface of the interlayer dielectric layer 232 on the first region I; using the second mask layer as a mask, etching the interlayer dielectric layer 232 and the isolation structure to form the gate opening 240.

[0103] While etching the interlayer dielectric layer 232 and the isolation structure, a portion of the second etching protection layer 221 on the surface of the first material layer 220 is also etched.

[0104] In this embodiment, during the formation of the interlayer dielectric layer 232 and the gate opening 240, the structure of each first material layer 220 located on the second region II is always surrounded by the isolation structure, and the top surface of the isolation structure is higher than the top surface of the first material layer 220. Therefore, the isolation structure can help support the first material layer 220 and maintain the stability of the first material layer 220, avoid large-area exposure of the first material layer 220, resulting in peeling or tipping, and improve the integrity of the structure of the first material layer 220.

[0105] In other embodiments, after the isolation structure is formed, the isolation structure is thinned as a whole, and the top surface of the thinned isolation structure is lower than the top surface of the first material layer, thereby exposing the complete top surface and part of the side wall surface of the first material layer on part of the first region and the second region; an interlayer dielectric layer is formed on the surface of the thinned isolation structure; and a gate opening located on the first region and a gate located in the gate opening are formed in the interlayer dielectric layer and the isolation structure.

[0106] Please refer to Fig.15 and Fig.16 ,in, Fig.15 The viewing direction and Fig.13 same, Fig.16 The viewing direction and Fig.14 A gate dielectric layer 251 is formed in the gate opening 240 ; and a gate 250 is formed on the surface of the gate dielectric layer 251 .

[0107] In this embodiment, the material of the gate dielectric layer 251 includes silicon oxide, aluminum oxide, zirconium oxide or boron nitride, so as to cooperate with the first material layer 220 of the two-dimensional material.

[0108] In other embodiments, the gate dielectric layer further includes other oxides; and the process of forming the gate dielectric layer includes an in-situ oxidation process.

[0109] In this embodiment, the gate 250 includes: a work function layer (not shown) located on the surface of the gate dielectric layer 251 and a gate electrode (not shown) located on the surface of the work function layer.

[0110] In this embodiment, the gate 250 material includes metal. In other embodiments, the gate material includes polysilicon. In this embodiment, the distance between the central axes of adjacent gates 250 ranges from 15 nm to 40 nm.

[0111] Please refer to Figures 17 to 19 ,in, Fig.18 for Fig.17 Along the Q direction, Fig.19 The three-dimensional structure diagram along the P direction, Fig.17 for Fig.18 The cross-sectional structure along the DD' direction, Fig.19 for Fig.18 Cross-sectional structure diagram along CC' direction, Fig.19 still Fig.17 A cross-sectional structural diagram along the YY' direction A source-drain contact conductive structure 263 is formed on the top surface of the first material layer 220 on the second region II.

[0112] It should be noted that, for ease of understanding, Fig.18 The interlayer dielectric layer 232, the isolation structure, the second etching protection layer 221, and the auxiliary layer 205 are omitted.

[0113] In this embodiment, the bottom surface of the source-drain contact conductive structure 263 is flush with the top surface of the first material layer 220 .

[0114] The first material layer 220 is located on the surface of the first region I and the second region II. When the transistor is working, the first material layer 220 on the surface of the second region II is applied with a source voltage and a drain voltage, so that the first material layer 220 on the surface of the second region II plays the function of source and drain. The source-drain contact conductive structure 263 enables the first material layer 220 used as source and drain to be electrically connected to the external electrical interconnection layer.

[0115] In this embodiment, the source-drain contact conductive structure 263 is in contact with the top surfaces of several discrete first material layers 220 at the same time. The extension direction of the source-drain contact conductive structure 263 is parallel to the extension direction of the gate 250, and the extension direction of the source-drain contact conductive structure 263 is perpendicular to the extension direction of the first material layer 220.

[0116] The source-drain contact conductive structure 263 includes: a contact layer 262 located on the surface of the first material layer 220 and a conductive layer 261 located on the surface of the contact layer 262; the material of the contact layer 262 includes bismuth, tellurium or other semi-metallic materials; the material of the conductive layer 261 includes metal. The contact layer 262 is used to reduce the Schottky barrier and optimize the contact effect between the two-dimensional material and the metal.

[0117] In this embodiment, the source-drain contact conductive structure 263 is in direct contact with the top surface of the first material layer 220. Since the top surface of the first material layer 220 is perpendicular to the arrangement surface of the single atomic layer of the two-dimensional material, the top surface is directly in contact with the source-drain contact conductive structure 263, so that the edge surface of the two-dimensional material layer contacts the metal, which can avoid the Fermi pinning effect, form an ohmic contact on the interface, reduce the contact resistance, and improve the contact performance.

[0118] In addition, since the source-drain contact conductive structure 263 is located on the top surface of the first material layer 220 on the second region II, it is vertically stacked with the first material layer 220 in a direction perpendicular to the surface of the substrate 230, vertical space is efficiently utilized, further reducing the area of ​​the working area.

[0119] In this embodiment, the method for forming the source-drain contact conductive structure 263 includes: forming a source-drain contact through hole (not shown) in the interlayer dielectric layer 232 and the isolation structure on the second region II; depositing a contact material (not shown) and a source-drain contact conductive material (not shown) in the source-drain contact through hole; and planarizing the contact material and the source-drain contact conductive material until the surface of the interlayer dielectric layer 232 is exposed to form a contact layer 262 and a conductive layer 261.

[0120] Please continue to combine Fig.18 ,refer to Fig.17 and Fig.19 The first material layer 220 is located on the surface of the first region I and the second region II, the gate 250 spans the first material layer 220, the extension direction of the gate 250 is perpendicular to the extension direction of the first material layer 220, and the extension direction of the gate 250 is parallel to the extension direction of the source-drain contact conductive structure 263. The gate 250 is located on the surface of the first region I, and the gate 250 is located between two adjacent second regions II.

[0121] In this embodiment, when the transistor is working, the first material layer 220 at the bottom of the gate 250 acts as a channel layer of the two-dimensional material transistor device, and the first material layer 220 on the second region II on both sides of the gate 250 acts as the source and drain of the transistor, thereby enabling the transistor to perform a switching function.

[0122] The first material layer 220 has a first side wall 270a and a second side wall 270b opposite to each other. The first side wall 270a and the second side wall 270b are parallel to the arrangement plane of the single atomic layer. The gate 250 is in contact with the first side wall 270a and the second side wall 270b respectively and simultaneously. Since the material of the first material layer 220 is a two-dimensional material, the two-dimensional material has several layers of single atomic layers, and the arrangement plane of each single atomic layer is perpendicular to the surface of the substrate 230, and the first side wall 270a and the second side wall 270b are both parallel to the arrangement plane of the single atomic layer, and the first side wall 270a and the second side wall 270b parallel to the arrangement plane of the single atomic layer are perpendicular to the surface of the substrate 230, therefore, a first gate control and a second gate control can be formed on the surfaces of the first side wall 270a and the second side wall 270b respectively, thereby realizing a vertically stacked channel dual-gate transistor composed of two-dimensional materials, realizing two channel regions for carrier migration, and further, while improving the channel carrier mobility, it is possible to reduce the working area occupied by the channel, thereby improving the device performance and integration.

[0123] Secondly, since the first material layer 220 grows along the side wall of the groove 202 in a self-aligned manner, the spacing dimensions between the first material layers 220 and the thickness dimensions of the first material layers 220 are more controllable and flexible, and the process difficulty of forming the first material layer 220 is reduced, and a smaller first material layer 220 can be formed more stably, thereby achieving a significant reduction in the spacing between the first material layers 220.

[0124] Again, the first material layer 220 is located on both the first region I and the second region II. When the transistor is working, the first material layer 220 at the bottom of the gate 250 in the first region I acts as the channel layer of the transistor, and the first material layer 220 on the second region II acts as the source and drain of the transistor. The channel layer and the source and drain are integrally formed, which can simplify the process steps and optimize the contact resistance between the source and drain and the source and drain contact conductive structure 263, thereby improving the device performance.

[0125] In this embodiment, the first material layer 220 and the gate 250 constitute a two-dimensional material transistor device in which single atomic layers are vertically stacked.

[0126] In other embodiments, Figures 2 to 7 The process of forming the first material layer 220 can also be used in the process of forming other two-dimensional material devices that require a single atomic layer vertical stacking structure, that is, other device structures other than the gate that span the first material layer can also be formed on the surface of the first material layer.

[0127] Fig. 20 It is a schematic diagram of a partial cross-sectional structure of a semiconductor structure forming process in another embodiment of the present invention.

[0128] Please Fig.15 and Fig.16 Based on reference Fig. 20 , Fig. 20 The viewing direction and Fig.15 The viewing direction is consistent.

[0129] Source-drain contact holes (not shown) are formed in the interlayer dielectric layer 332 and the isolation structure 331 on both sides of the gate 350; the first material layer 320 is further etched to form a groove (not shown) recessed toward the substrate 330 in the first material layer 320, and the groove and the source-drain contact hole are interconnected; a source-drain contact conductive structure 363 is formed in the groove and the source-drain contact hole.

[0130] The top surface of the first material layer 320 is higher than the bottom surface of the source-drain contact conductive structure 363 , so that part of the source-drain contact conductive structure 363 is located in the first material layer 320 .

[0131] Specifically, the source-drain contact conductive structure 363 is partially located in the card groove in the first material layer 320, so that the bottom of the card groove and the side wall surfaces on both sides of the first material layer 320 can form contact with the source-drain contact conductive structure 363, thereby further increasing the surface contact area between the source-drain contact conductive structure 363 and the first material layer 320, reducing the contact resistance and improving the contact effect.

[0132] It should be noted that Fig. 20 The semiconductor structure shown is Fig.17 The semiconductor structure in the illustrated embodiment is different only in the relative positions of the first material layer 320 and the source-drain contact conductive structure 363 .

[0133] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: forming a substrate and a base structure located on a surface of the substrate, wherein the base structure has a plurality of grooves; A first material layer is formed on the sidewall surface of each groove, wherein the material of the first material layer is a two-dimensional material, and the two-dimensional material has a plurality of single atomic layers arranged along a first direction, wherein the first direction is perpendicular to the sidewall surface of the groove, and the arrangement plane of each single atomic layer is parallel to the sidewall surface of the groove, and each first material layer exposes the bottom surface of the groove; The base structure between the first material layers is removed.

2. The method for forming a semiconductor structure according to claim 1, wherein: Also includes: A device structure is formed across the first material layer.

3. The method for forming a semiconductor structure according to claim 2, wherein: Before forming the device structure, the method further includes: forming an isolation structure located between the first material layers on the surface of the substrate, wherein at least a portion of the isolation structure is located in each trench.

4. The method for forming a semiconductor structure according to claim 2, wherein: The device structure includes a gate, and the gate is perpendicular to an extension direction of the first material layer.

5. The method for forming a semiconductor structure according to claim 1, wherein: The material of the base structure includes a single crystal material; the single crystal material includes a non-metallic single material or a metallic single material.

6. The method for forming a semiconductor structure according to claim 5, wherein: The non-metallic single-element material includes single-crystal silicon, quartz, silicon carbide or a germanium-containing compound; the metal single-element material includes single-crystal copper.

7. The method for forming a semiconductor structure according to claim 1, wherein: The material of the first material layer includes transition metal chalcogenide, graphene, black phosphorus, indium selenide, gallium selenide or bismuth oxyselenide.

8. The method for forming a semiconductor structure according to claim 7, wherein: After forming the trench and before forming the first material layer, the method further includes: forming an auxiliary layer on the surface of the sidewall of the trench; The material of the auxiliary layer includes silicon dioxide, nickel, copper, silver or gold.

9. The method for forming a semiconductor structure according to claim 8, wherein: When the material of the first material layer is a transition metal chalcogenide, the material of the auxiliary layer includes silicon dioxide; when the material of the first material layer is graphene, the material of the auxiliary layer includes copper or nickel.

10. The method for forming a semiconductor structure according to claim 1, wherein: Each first material layer has 1 to 2 monoatomic layers.

11. The method for forming a semiconductor structure according to claim 1, wherein: The method for forming a substrate and a base structure includes: providing a substrate; forming a first mask layer on the surface of the substrate, wherein the first mask layer exposes a portion of the substrate surface; and etching the substrate using the first mask layer as a mask to form a substrate and a base structure with grooves.

12. The method for forming a semiconductor structure according to claim 11, wherein: The process of forming the first mask layer includes: a self-aligned double patterning process or a self-aligned quadruple patterning process.

13. The method for forming a semiconductor structure according to claim 1, wherein: The method for forming the first material layer includes: depositing an initial first material layer on the groove sidewall, the groove bottom and the top of the base structure; etching back the initial first material layer at the groove bottom and the top of the base structure to form a first material layer located on the surface of the groove sidewall.

14. The method for forming a semiconductor structure according to claim 13, wherein: The formation process of the initial first material layer includes an atomic layer deposition process or an epitaxial growth process.

15. The method for forming a semiconductor structure according to claim 13, wherein: Before etching back the initial first material layer, the method further includes: forming a first etching protection layer at least on the surface of the initial first material layer on the sidewall of the trench.

16. The method for forming a semiconductor structure according to claim 1, wherein: The distance between adjacent first material layers ranges from 10 nanometers to 20 nanometers.

17. The method for forming a semiconductor structure according to claim 3, wherein: A top surface of the isolation structure is higher than a top surface of the first material layer.

18. The method for forming a semiconductor structure according to claim 4, wherein: The first material layer has a first side wall and a second side wall opposite to each other. The first side wall and the second side wall are both parallel to the arrangement plane of the single atomic layer. The gate is in contact with the first side wall and the second side wall respectively and simultaneously.

19. The method for forming a semiconductor structure according to claim 4, wherein: The substrate includes a first region and second regions located on both sides of the first region. The first material layer is formed on surfaces of the first region and the second region, and the gate is formed between two adjacent second regions.

20. The method for forming a semiconductor structure according to claim 19, wherein: Also includes: A source-drain contact conductive structure is formed on a top surface of the first material layer on the second region.

21. The method for forming a semiconductor structure according to claim 20, wherein: The bottom surface of the source-drain contact conductive structure is flush with the top surface of the first material layer.

22. The method for forming a semiconductor structure according to claim 20, wherein: Part of the source-drain contact conductive structure is located in the first material layer.

23. The method for forming a semiconductor structure according to claim 20, wherein: The source-drain contact conductive structure includes: a contact layer located on the surface of the first material layer and a conductive layer located on the surface of the contact layer; the material of the contact layer includes bismuth, tellurium or other semi-metallic materials.

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