Semiconductor device and manufacturing method thereof

Abstract

The invention discloses a semiconductor device and a manufacturing method thereof, relates to the technical field of semiconductors, and aims to solve the problem of signal line congestion caused by device miniaturization. The semiconductor device includes a substrate, a first layer semiconductor structure, a second layer semiconductor structure, a first contact structure, and a second contact structure. The second layer of semiconductor structures are arranged above the first layer of semiconductor structures at intervals along the thickness direction of the substrate. The first contact structure is disposed within the substrate. The first contact structure comprises a first contact part which is in electrical contact with a first source / drain region included in the transistor in the first layer of semiconductor structure, and a second contact part which is in electrical contact with the first gate stack structure. The second contact structure is arranged on the side, away from the first layer of semiconductor structure, of the second layer of semiconductor structure. And the second contact structure comprises a third contact part which is electrically contacted with a second source / drain region included in the transistor in the second layer of semiconductor structure, and a fourth contact part which is electrically contacted with the second gate stack structure.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device and a manufacturing method thereof. Background Art

[0002] IC interconnection technology is a critical and necessary part of packaging. Specifically, IC interconnection technology is the technology of connecting the independent components in the same chip into circuit modules with certain functions in a certain way. It is of high importance in advanced packaging. Chips are interconnected through packaging to receive power, exchange signals and finally operate. Since the speed, density and function of semiconductor products vary according to the interconnection method, the interconnection method is also constantly changing and developing.

[0003] However, as device sizes shrink, signal line congestion is prone to occur after interconnecting individual components in existing semiconductor devices, resulting in poor voltage drop and lower performance of semiconductor devices. Summary of the invention

[0004] The object of the present invention is to provide a semiconductor device and a method for manufacturing the same, which are used to alleviate the problem of signal line congestion caused by device miniaturization, reduce voltage drop, improve the working performance of the semiconductor device; and help increase the yield of the semiconductor device.

[0005] In order to achieve the above-mentioned object, in a first aspect, the present invention provides a semiconductor device, which includes: a substrate, a first semiconductor structure, a second semiconductor structure, a first contact structure and a second contact structure. The first semiconductor structure is arranged on the substrate. The second semiconductor structure is arranged above the first semiconductor structure at intervals along the thickness direction of the substrate. The first semiconductor structure and the second semiconductor structure both include a plurality of transistors spaced and distributed along the thickness direction perpendicular to the substrate. The first contact structure is arranged in the substrate. The first contact structure includes a first contact portion electrically contacting a first source / drain region included in the transistor in the first semiconductor structure, and a second contact portion electrically contacting a first gate stack structure included in at least some of the transistors in the first semiconductor structure. The first contact portion and the second contact portion are insulated from each other. The second contact structure is arranged on a side of the second semiconductor structure away from the first semiconductor structure. The second contact structure includes a third contact portion electrically contacting a second source / drain region included in the transistor in the second semiconductor structure, and a fourth contact portion electrically contacting a second gate stack structure included in at least some of the transistors in the second semiconductor structure. The third contact portion and the fourth contact portion are insulated from each other.

[0006] In the case of adopting the above technical solution, the semiconductor device provided by the present invention includes a first semiconductor structure and a second semiconductor structure that are spaced apart and distributed along the thickness direction of the substrate, so as to improve the integration of the semiconductor device and facilitate further miniaturization of the semiconductor device. In addition, for the first semiconductor structure located in the lower layer, the first source / drain region and at least part of the first gate stack structure included therein are respectively in electrical contact with the first contact portion and the second contact portion included in the first contact structure; and the first contact structure is arranged below the first semiconductor structure, that is, the first source / drain region and at least part of the first gate stack structure in the first semiconductor structure are interconnected downward. The second semiconductor structure located in the upper layer, the second source / drain region and at least part of the second gate stack structure included therein are respectively in electrical contact with the third contact portion and the fourth contact portion included in the second contact structure; and the second contact structure is arranged on the side of the second semiconductor structure away from the first semiconductor structure, that is, the second source / drain region and at least part of the second gate stack structure in the second semiconductor structure are interconnected upward. At this time, compared with the existing method of interconnecting two adjacent semiconductor structures upward, or the back-side power supply method of interconnecting only the source / drain regions in two adjacent semiconductor structures downward, when in the semiconductor device provided by the present invention, the first source / drain region and at least part of the first gate stack structure included in the first semiconductor structure located in the lower layer are interconnected downward, and the second source / drain region and at least part of the second gate stack structure included in the second semiconductor structure located in the upper layer are interconnected upward, at least most of the interconnected contact structures of different layers can be separated along the thickness direction of the substrate, which can alleviate the problem of signal line congestion caused by device miniaturization, and is also beneficial to reducing the length of the interconnection transmission path, reducing voltage drop, and improving the working performance of the semiconductor device; and the first contact portion and the second contact portion included in the first contact structure are insulated from each other, and the third contact portion and the fourth contact portion included in the second contact structure are insulated from each other, preventing short-circuit failure and facilitating increasing the yield of the semiconductor device.

[0007] In one example, the contact between the first contact portion and the first source / drain region is back-side direct contact.

[0008] In one example, the contact between the second contact portion and at least a portion of the first gate stack structure is direct back contact.

[0009] In an example, the first contact portion is self-aligned with the first source / drain region.

[0010] In an example, the semiconductor device further includes a dielectric spacer, which is located between the first contact portion and the second contact portion, and is located below the first gate spacer of at least part of the transistors in the first semiconductor structure.

[0011] In an example, the first contact portion, the second contact portion, and the end of the dielectric spacer facing away from the second semiconductor structure are aligned.

[0012] In a second aspect, the present invention provides a method for manufacturing a semiconductor device, which further comprises: first, forming a first semiconductor structure and a substrate. The first semiconductor structure is disposed on the substrate. Next, a first contact structure is formed in the substrate. Next, a second semiconductor structure is formed and is disposed above the first semiconductor structure in a spaced relationship along the thickness direction of the substrate. Both the first semiconductor structure and the second semiconductor structure include a plurality of transistors spaced and distributed along a thickness direction perpendicular to the substrate. The first contact structure includes a first contact portion electrically contacting a first source / drain region included in the transistor in the first semiconductor structure, and a second contact portion electrically contacting a first gate stack structure included in at least some of the transistors in the first semiconductor structure. The first contact portion and the second contact portion are insulated from each other. Next, a second contact structure is formed and is disposed on a side of the second semiconductor structure away from the first semiconductor structure. The second contact structure includes a third contact portion electrically contacting a second source / drain region included in the transistor in the second semiconductor structure, and a fourth contact portion electrically contacting a second gate stack structure included in at least some of the transistors in the second semiconductor structure. The third contact portion and the fourth contact portion are insulated from each other.

[0013] In one example, a first semiconductor structure is formed, including: providing a semiconductor substrate. Next, a plurality of fin structures are formed on the semiconductor substrate and are spaced apart along a thickness direction perpendicular to the substrate, and a mask structure is formed across the fin structures. Next, the portion of each fin structure exposed outside the mask structure is selectively removed. Next, under the protection of the mask structure, a portion of the semiconductor substrate is selectively etched to form a first opening groove; and a preformed structure is formed to fill the first opening groove. The preformed structure and the semiconductor substrate are made of different materials. Next, a first source / drain region is formed above the preformed structure. Next, a first channel region included in the transistor in the first semiconductor structure is formed based on the remaining fin structure; and a first gate stack structure is formed on the periphery of the first channel region.

[0014] In one example, forming a substrate and a first contact structure includes: selectively removing a semiconductor substrate. Next, forming a substrate on a side of the first semiconductor structure facing away from the second semiconductor structure. The substrate and the preformed structure are flush with each other on a side facing away from the first semiconductor structure, and the materials of the substrate and the preformed structure are different. Next, selectively removing the preformed structure; and forming a first contact portion in the first opening groove. Next, selectively removing a portion of the substrate below the first gate stack structure to form a second opening groove. Next, forming a dielectric sidewall at least covering the sidewall of the first contact portion in the second opening groove and along the length direction of the first gate stack structure. And forming a second contact portion in the remaining second opening groove to obtain a first contact structure.

[0015] In one example, the material of the preformed structure includes at least one of silicon nitride, silicon oxynitride and amorphous carbon.

[0016] In one example, after forming a second semiconductor structure spaced above the first semiconductor structure along a thickness direction of the substrate, a substrate is formed, and a first contact structure is formed in the substrate.

[0017] The beneficial effects of the second aspect of the present invention and its various implementations can be analyzed by referring to the beneficial effects of the first aspect and its various implementations, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0019] Figure 1 Parts (1) and (2) are schematic diagrams of the structure of the semiconductor device provided in the embodiment of the present invention during the manufacturing process. Figure 1 and hint Figure 2 ;

[0020] Figure 2 Parts (1) and (2) are schematic diagrams of the structure of the semiconductor device provided in the embodiment of the present invention during the manufacturing process. Figure 3 and hint Figure 4 ;

[0021] Figure 3 Parts (1) and (2) are schematic diagrams of the structure of the semiconductor device provided in the embodiment of the present invention during the manufacturing process. Figure 5 and hint Figure 6 ;

[0022] Figure 4 Parts (1) and (2) are schematic diagrams of the structure of the semiconductor device provided in the embodiment of the present invention during the manufacturing process. Figure 7 and hint Figure 8 ;

[0023] Figure 5 Parts (1) and (2) are schematic diagrams of the structure of the semiconductor device provided in the embodiment of the present invention during the manufacturing process. Figure 9 and hint Figure 10 ;

[0024] Figure 6 Parts (1) and (2) are schematic diagrams of the structure of the semiconductor device provided in the embodiment of the present invention during the manufacturing process. Figure 10 A hint Figure 10 two;

[0025] Figure 7 Parts (1) and (2) are schematic diagrams of the structure of the semiconductor device provided in the embodiment of the present invention during the manufacturing process. Figure 10 Sanhe hint Figure 10 Four;

[0026] Figure 8 A schematic diagram of the structure of a semiconductor device during the manufacturing process provided by an embodiment of the present invention Figure 10 five;

[0027] Fig. 9 A schematic diagram of the structure of a semiconductor device during the manufacturing process provided by an embodiment of the present invention Figure 10 six;

[0028] Fig.10 A schematic diagram of the structure of a semiconductor device during the manufacturing process provided by an embodiment of the present invention Figure 10 seven;

[0029] Fig.11 A schematic diagram of the structure of a semiconductor device during the manufacturing process provided by an embodiment of the present invention Figure 10 eight;

[0030] Fig.12 A schematic diagram of the structure of a semiconductor device during the manufacturing process provided by an embodiment of the present invention Figure 10 Nine;

[0031] Fig.13 A schematic diagram of the structure of a semiconductor device during the manufacturing process provided by an embodiment of the present invention Figure 2 ten;

[0032] Fig.14 A schematic diagram of the structure of a semiconductor device during the manufacturing process provided by an embodiment of the present invention Figure 2 eleven;

[0033] Fig.15 A schematic diagram of the structure of a semiconductor device during the manufacturing process provided by an embodiment of the present invention Figure 2 twelve;

[0034] Fig.16 A schematic diagram of the structure of a semiconductor device during the manufacturing process provided by an embodiment of the present invention Figure 2 Thirteen;

[0035] Fig.17 A schematic diagram of the structure of a semiconductor device during the manufacturing process provided by an embodiment of the present invention Figure 2 fourteen.

[0036] Figure numerals: 11 is a substrate, 12 is a first semiconductor structure, 13 is a second semiconductor structure, 14 is a transistor, 15 is a first contact structure, 16 is a first contact portion, 17 is a second contact portion, 18 is a first source / drain region, 19 is a first gate stack structure, 20 is a second contact structure, 21 is a third contact portion, 22 is a fourth contact portion, 23 is a second source / drain region, 24 is a second gate stack structure, 25 is a dielectric sidewall, 26 is a first gate sidewall, 27 is a semiconductor substrate, 28 is a fin structure, 29 is a mask structure, 30 is a first opening groove, 31 is a pre-formed structure, 32 is a first channel region, 33 is a second opening groove, 34 is a second channel region, 35 is a second gate sidewall, 36 is a sacrificial gate, and 37 is an interlayer dielectric layer. DETAILED DESCRIPTION

[0037] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the present invention. In addition, in the following description, descriptions of known structures and technologies are omitted to avoid unnecessary confusion of the concept of the present invention.

[0038] Various structural schematic diagrams according to embodiments of the present invention are shown in the accompanying drawings. These figures are not drawn to scale, and some details are magnified and some details may be omitted for a clearer expression. The shapes of various regions and layers shown in the figures and the relative sizes and positional relationships therebetween are only exemplary, and may deviate in practice due to manufacturing tolerances or technical limitations, and those skilled in the art may additionally design regions / layers with different shapes, sizes, and relative positions according to actual needs.

[0039] In the context of the present invention, when a layer / element is referred to as being "on" another layer / element, the layer / element may be directly on the other layer / element, or there may be an intermediate layer / element between them. In addition, if a layer / element is "on" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "under" the other layer / element. In order to make the technical problems, technical solutions and beneficial effects to be solved by the present invention clearer, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0040] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined. The meaning of "several" is one or more, unless otherwise clearly and specifically defined.

[0041] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0042] IC interconnection technology is a critical and necessary part of packaging. Specifically, IC interconnection technology is the technology of connecting the independent components in the same chip into circuit modules with certain functions in a certain way. It is of high importance in advanced packaging. Chips are interconnected through packaging to receive power, exchange signals and finally operate. Since the speed, density and function of semiconductor products vary according to the interconnection method, the interconnection method is also constantly changing and developing.

[0043] However, as the size of devices shrinks, after interconnecting the independent components in existing semiconductor devices, the problem of signal line congestion is prone to occur, resulting in poor voltage drop and low performance of semiconductor devices. Although technicians in this field have developed a back power supply network that improves the bottleneck of power and signal lines and battery utilization by arranging power wiring on the back of the wafer, due to the small size of the device, there is an alignment accuracy problem when making a buried power layer on the back that is in direct electrical contact with the source / drain region included in the transistor. The buried power layer is easily short-circuited with the gate stack structure of the transistor, resulting in device failure, which is still not conducive to improving the performance of the semiconductor device.

[0044] In order to solve the above technical problems, an embodiment of the present invention provides a semiconductor device and a method for manufacturing the same. In the semiconductor device provided by the embodiment of the present invention, when the first source / drain region and at least part of the first gate stack structure included in the first semiconductor structure located in the lower layer are interconnected downward, and the second source / drain region and at least part of the second gate stack structure included in the second semiconductor structure located in the upper layer are interconnected upward, at least most of the interconnection contact structures of different layers can be separated along the thickness direction of the substrate, which can alleviate the problem of signal line congestion caused by device miniaturization.

[0045] Specifically, the first aspect is Fig.13 and Fig.17 As shown, the semiconductor device provided by the embodiment of the present invention includes: a substrate 11, a first semiconductor structure 12, a second semiconductor structure 13, a first contact structure 15 and a second contact structure 20. The first semiconductor structure 12 is arranged on the substrate 11. The second semiconductor structure 13 is arranged above the first semiconductor structure 12 at intervals along the thickness direction of the substrate 11. The first semiconductor structure 12 and the second semiconductor structure 13 both include a plurality of transistors 14 spaced apart and distributed along the thickness direction perpendicular to the substrate 11. The first contact structure 15 is arranged in the substrate 11. The first contact structure 15 includes a first contact portion 16 electrically contacting a first source / drain region 18 included in the transistor 14 in the first semiconductor structure 12, and a second contact portion 17 electrically contacting a first gate stack structure 19 included in at least part of the transistors 14 in the first semiconductor structure 12. The first contact portion 16 and the second contact portion 17 are insulated from each other. The second contact structure 20 is arranged on a side of the second semiconductor structure 13 away from the first semiconductor structure 12. The second contact structure 20 includes a third contact portion 21 electrically contacting a second source / drain region 23 included in the transistor 14 in the second semiconductor structure 13, and a fourth contact portion 22 electrically contacting a second gate stack structure 24 included in at least a portion of the transistors 14 in the second semiconductor structure 13. The third contact portion 21 and the fourth contact portion 22 are insulated from each other.

[0046] When the above technical solution is adopted, Fig.13 and Fig.17 As shown, the semiconductor device provided by the embodiment of the present invention includes a first semiconductor structure 12 and a second semiconductor structure 13 that are spaced apart and distributed along the thickness direction of the substrate 11, so as to improve the integration of the semiconductor device and facilitate further miniaturization of the semiconductor device. In addition, for the first semiconductor structure 12 located in the lower layer, the first source / drain region 18 and at least a portion of the first gate stack structure 19 included therein are respectively electrically contacted with the first contact portion 16 and the second contact portion 17 included in the first contact structure 15; and the first contact structure 15 is arranged below the first semiconductor structure 12, that is, the interconnection method corresponding to the first source / drain region 18 and at least a portion of the first gate stack structure 19 in the first semiconductor structure 12 is downward interconnection. The second semiconductor structure located on the upper layer includes a second source / drain region 23 and at least a portion of the second gate stack structure 24, which are respectively electrically contacted with the third contact portion 21 and the fourth contact portion 22 included in the second contact structure 20; and the second contact structure 20 is arranged on the side of the second semiconductor structure 13 away from the first semiconductor structure 12, that is, the interconnection method corresponding to the second source / drain region 23 and at least a portion of the second gate stack structure 24 in the second semiconductor structure 13 is upward interconnection. At this time, compared with the existing method of interconnecting two adjacent semiconductor structures upward, or the back-side power supply method of interconnecting only the source / drain regions in two adjacent semiconductor structures downward, when in the semiconductor device provided by the embodiment of the present invention, the first source / drain region 18 and at least part of the first gate stack structure 19 included in the first semiconductor structure 12 located in the lower layer are interconnected downward, and the second source / drain region 23 and at least part of the second gate stack structure 24 included in the second semiconductor structure located in the upper layer are interconnected upward, at least most of the interconnected contact structures of different layers can be separated along the thickness direction of the substrate 11, which can alleviate the problem of signal line congestion caused by device miniaturization, and is also beneficial to reducing the length of the interconnection transmission path, reducing voltage drop, and improving the working performance of the semiconductor device; and the first contact portion 16 and the second contact portion 17 included in the first contact structure 15 are insulated from each other, and the third contact portion 21 and the fourth contact portion 22 included in the second contact structure 20 are insulated from each other, preventing short-circuit failure and increasing the yield of the semiconductor device.

[0047] In actual application, the present invention does not specifically limit the structure and material of the substrate, as long as it can be applied to the semiconductor device provided by the present invention. For example, the material of the substrate may include insulating materials such as silicon oxide, silicon nitride or silicon oxynitride, so as to further reduce the risk of leakage between the first contact portion and the second contact portion in the first contact structure provided in the substrate.

[0048] Specifically, the substrate may be a single-layer structure including only one material. Alternatively, the substrate may be a laminated structure including at least two materials. In this case, the distribution between regions of different materials in the substrate may be determined according to the specific manufacturing process of the substrate, and is not specifically limited here. For example, regions of different materials in the substrate may be stacked along the thickness direction of the substrate.

[0049] For the above-mentioned first semiconductor structure and second semiconductor structure, along the thickness direction of the substrate, the first semiconductor structure is located below the second semiconductor structure, and the spacing between the two can be set according to actual needs. In addition, the number and type of transistors included in the first semiconductor structure and the second semiconductor structure, as well as the distribution between different transistors can be set according to the actual application scenario, as long as they can be applied to the semiconductor device provided in the embodiment of the present invention. Exemplarily, the different transistors included in the first semiconductor structure and / or the second semiconductor structure can be fin field effect transistors and / or ring gate transistors. Specifically, for the same first semiconductor structure or the same second semiconductor structure, the device types of different transistors can be the same, such as different transistors are fin field effect transistors or ring gate transistors; or, the device types of different transistors can also be different, such as some transistors in different transistors are fin field effect transistors, and the remaining transistors are ring gate transistors. The device type of the transistor included in the first semiconductor structure and the device type of the transistor included in the second semiconductor structure can be the same or different.

[0050] For a single transistor, Fig.17 As shown, the transistor 14 in the first semiconductor structure 12 includes a first source / drain region 18, a first channel region 32 and a first gate stack structure 19. The first channel region 32 is located between the first source / drain regions 18, and its two sides along the length direction are respectively in contact with the first source / drain region 18. The first gate stack structure 19 is located at the periphery of the first channel region 32. Secondly, the transistor in the first semiconductor structure 12 may also include at least a first gate sidewall 26 located on both sides of the first gate stack structure 19 along its own length direction. In addition, in the case where the transistor 14 in the first semiconductor structure 12 is a ring-gate transistor, the transistor 14 in the first semiconductor structure 12 may also include a first inner sidewall located between the first gate stack structure 19 and the first source / drain region 18.

[0051] Among them, the material of the first source / drain region and the first channel region may include any semiconductor material such as silicon, silicon germanium or germanium. The first gate stack structure may include a first gate dielectric layer and a first gate located at the periphery of the first channel region, and the material of the first gate dielectric layer may include an insulating material with a high dielectric constant such as HfO2, ZrO2, TiO2 or Al2O3. The material of the above-mentioned first gate may be a conductive material such as TiN, TaN or TiSiN. The material of the above-mentioned first gate sidewall and inner sidewall may include an insulating material such as SiO2, SiN, SiCO or SiCON.

[0052] As for the transistors in the second semiconductor structure, such as Fig.17 As shown, it includes a second source / drain region 23, a second channel region 34 and a second gate stack structure 24. The second channel region 34 is located between the second source / drain regions 23, and its two sides along the length direction are respectively in contact with the second source / drain region 23. The second gate stack structure 24 is located at the periphery of the second channel region 34. Secondly, the transistor 14 in the second semiconductor structure 13 may also include at least a second gate sidewall 35 located on both sides of the second gate stack structure 24 along its own length direction. In addition, in the case where the transistor 14 in the second semiconductor structure 13 is a ring-gate transistor, the transistor 14 in the second semiconductor structure 13 may also include a second inner sidewall located between the second gate stack structure 24 and the second source / drain region 23.

[0053] As for the materials of the second source / drain region, the second channel region, the second gate stack structure, the second gate sidewall and the second inner sidewall, reference may be made to the materials of the first source / drain region, the first channel region, the first gate stack structure, the first gate sidewall and the first inner sidewall described above, and no further details will be given here.

[0054] For the first contact structure, Fig.17 As shown, the first contact structure 15 is arranged in the substrate 11 to lead out the first source / drain region 18 and at least a portion of the first gate stack structure 19 in the first layer semiconductor structure 12 by downward interconnection. Specifically, the first contact structure 15 includes a first contact portion 16 electrically contacting the first source / drain region 18, and a second contact portion 17 electrically contacting the first gate stack structure 19 included in at least a portion of the transistor 14. The material of the first contact portion 16 and / or the second contact portion 17 may include conductive materials such as copper, tungsten, silver or doped polysilicon. The material of the first contact portion 16 and the material of the second contact portion 17 may be the same or different.

[0055] Secondly, the first contact portion and the first source / drain region are interconnected by a deep trench via (DTV); or Fig.17As shown, the contact method between the first contact portion 16 and the first source / drain region 18 can also be direct back contact, so as to further reduce the occupied area of ​​the first contact structure 15 and further reduce the voltage drop; in addition, in this case, the first contact portion 16 can be self-aligned with the first source / drain region 18, which reduces the risk of leakage and helps to reduce the difficulty of subsequent interconnection processes.

[0056] As for the second contact portion, the contact method between the second contact portion and at least part of the first gate stack structure can be a deep trench hole method or a direct back contact. Secondly, it can be that different second contacts are respectively electrically contacted with all the first gate stack structures included in the first layer semiconductor structure; or, it can also be that among all the first gate stack structures, some of the first gate stack structures are interconnected downward and led out through the second contact portion, while the remaining first gate stack structures are interconnected upward and led out through the fifth contact portion included in the second contact structure.

[0057] In addition, the first contact portion and the second contact portion are insulated from each other, and specifically, the first contact portion and the second contact portion may be insulated from each other by a non-conductive substrate. Fig.17 As shown, the semiconductor device may further include a dielectric spacer 25, the dielectric spacer 25 being located between the first contact portion 16 and the second contact portion 17, and the dielectric spacer 25 being located below the first gate spacer 26 of at least a portion of the transistors 14 in the first semiconductor structure 12. In this case, the first contact portion 16 and the second contact portion 17 may be electrically isolated by the dielectric spacer 25, and the dielectric spacer 25 is located below the first gate spacer 26. At this time, along the arrangement direction of the first contact portion 16 and the second contact portion 17, the existence of the dielectric spacer 25 will not occupy too much of the formation space of the first contact portion 16 and the second contact portion 17, thereby ensuring that the first contact portion 16 and the second contact portion 17 have a larger lateral transmission area.

[0058] Specifically, the material of the dielectric sidewall may include any insulating material such as silicon oxide, silicon nitride or silicon oxynitride. Fig.17 As shown, the ends of the first contact portion 16, the second contact portion 17 and the dielectric side wall 25 facing away from the second semiconductor structure 13 can be aligned to prevent the first contact portion 16 and the second contact portion 17 from short-circuiting and failing due to the second contact material on the first contact portion 16 and the dielectric side wall 25 not being completely removed during the formation of the second contact portion 17 after the first contact portion 16 and the dielectric side wall 25 are formed, thereby ensuring that the semiconductor device has high electrical reliability.

[0059] For the above second contact structure, if Fig.17As shown, the second contact structure 20 is arranged on the side of the second semiconductor structure 13 away from the first semiconductor structure 12, so as to lead out the second source / drain region 23 and at least part of the second gate stack structure 24 in the second semiconductor structure 13 by means of upward interconnection. Specifically, the second contact structure 20 includes a third contact portion 21 electrically contacting the second source / drain region 23, and a fourth contact portion 22 electrically contacting at least part of the second gate stack structure 24. The embodiment of the present invention does not specifically limit the contact method between the third contact portion 21 and the second source / drain region 23, and the contact method between the fourth contact portion 22 and at least part of the second gate stack structure 24. The materials of the third contact portion 21 and the fourth contact portion 22 can refer to the materials of the first contact portion 16 and the second contact portion 17 described above, and will not be repeated here. In addition. The third contact portion 21 and the fourth contact portion 22 can be insulated from each other by an insulating structure such as an interlayer dielectric layer 37.

[0060] In a second aspect, an embodiment of the present invention provides a method for manufacturing a semiconductor device. Figures 1 to 17 The manufacturing process is described in detail with reference to the cross-sectional view of the operation shown in FIG. 1 . Specifically, the manufacturing method of the semiconductor device includes the following steps:

[0061] First, a first semiconductor structure and a substrate are formed. The first semiconductor structure is disposed on the substrate.

[0062] Next, a first contact structure is formed in the substrate.

[0063] Next, a second semiconductor structure is formed and arranged above the first semiconductor structure along the thickness direction of the substrate. The first semiconductor structure and the second semiconductor structure both include a plurality of transistors spaced and distributed along the thickness direction perpendicular to the substrate. The first contact structure includes a first contact portion electrically contacting a first source / drain region included in the transistor in the first semiconductor structure, and a second contact portion electrically contacting a first gate stack structure included in at least some of the transistors in the first semiconductor structure. The first contact portion and the second contact portion are insulated from each other.

[0064] Next, a second contact structure is formed on a side of the second semiconductor structure away from the first semiconductor structure. The second contact structure includes a third contact portion electrically contacting a second source / drain region included in the transistor in the second semiconductor structure, and a fourth contact portion electrically contacting a second gate stack structure included in at least part of the transistors in the second semiconductor structure. The third contact portion and the fourth contact portion are insulated from each other.

[0065] The beneficial effects of the second aspect and its various implementations in the embodiments of the present invention can be analyzed with reference to the beneficial effects of the first aspect and its various implementations, and will not be repeated here.

[0066] Specifically, the structure of the semiconductor device manufactured by the second aspect of the embodiment of the present invention is the same as the structure of the semiconductor device provided by the first aspect described above. Based on this, the specific structures and materials of the first semiconductor structure, substrate, first contact structure, second semiconductor structure and second contact structure in the semiconductor device manufactured by the second aspect can be referred to above and will not be repeated here.

[0067] Exemplarily, the formation of the first semiconductor structure may include the following steps: First, a semiconductor substrate is provided, which may be a substrate made of any semiconductor material, such as a silicon substrate, a silicon-on-insulator substrate, a germanium silicon substrate or a germanium substrate.

[0068] Next, a plurality of fin structures are formed on the semiconductor substrate and spaced apart along a thickness direction perpendicular to the base, and a mask structure is formed crossing the fin structures.

[0069] Specifically, the specific manufacturing process of the above-mentioned fin-shaped structure can be determined according to the device type of the transistor included in the first-layer semiconductor structure. For example: in the case where the transistor included in the first-layer semiconductor structure is a fin field effect transistor, processes such as photolithography and etching can be used to directly etch the semiconductor substrate to obtain the fin; then deposition and other processes can be used to form a shallow trench isolation structure, wherein the portion of the fin exposed outside the shallow trench isolation structure is the fin-shaped structure. Alternatively, epitaxy and other processes can be used to first form a semiconductor layer on a semiconductor substrate, and then photolithography and etching and other processes can be used to etch the semiconductor layer and part of the semiconductor substrate to obtain the fin; then deposition and other processes can be used to form a shallow trench isolation structure (the top height of the shallow trench isolation structure is less than or equal to the bottom height of the semiconductor layer), wherein the portion of the fin exposed outside the shallow trench isolation structure is the fin-shaped structure.

[0070] For another example, when the transistor included in the first-layer semiconductor structure is a ring-gate transistor, epitaxy and other processes can be first used to form alternatingly stacked sacrificial layers and channel layers on a semiconductor substrate, wherein the sacrificial layers and channel layers that are alternately stacked are located at the bottom film layer. Then, photolithography and etching processes are used to etch the alternatingly stacked sacrificial layers and channel layers, as well as part of the semiconductor substrate, to obtain fins. Then, deposition and other processes are used to form a shallow trench isolation structure (the top height of the shallow trench isolation structure is less than or equal to the bottom height of the semiconductor layer), wherein the portion of the fin exposed outside the shallow trench isolation structure is a fin-shaped structure.

[0071] After forming the fin structure, a mask structure may be formed by using processes such as deposition and etching. The embodiment of the present invention does not specifically limit the specific structure and material of the mask structure. For example, the mask junction may include a sacrificial gate. For another example, Figure 1As shown in parts (1) and (2) of FIG. 2 , the mask structure 29 may include a sacrificial gate 36 and first gate spacers 26 located on both sides of the sacrificial gate 36 along the length direction.

[0072] Next, if Figure 1 As shown in parts (1) and (2) in the figure, a wet etching or dry etching process may be used to selectively remove the portion of each fin structure 28 exposed outside the mask structure 29 .

[0073] Next, if Figure 2 As shown in parts (1) and (2) of FIG. 1 , under the protection of the mask structure 29, a portion of the semiconductor substrate 27 is selectively etched to form a first opening groove 30; Figure 3 As shown in parts (1) and (2) of FIG. 1 , a preformed structure 31 is formed to fill the first opening groove 30. The preformed structure 31 and the semiconductor substrate 27 are made of different materials.

[0074] Specifically, the first opening groove is used to fill and form the first contact portion, and the preformed structure serves as a pre-occupying position. Subsequently, after at least the first layer of semiconductor structure is formed, the first opening groove can be released by selectively removing the preformed structure to prevent the first contact portion from being directly formed first and affecting the formation of other structures and the formation quality of the first contact portion. The material of the preformed structure may include a dielectric material or a semiconductor material, as long as it is different from the material of the semiconductor substrate. Exemplarily, the material of the preformed structure may include at least one of silicon nitride, silicon oxynitride and amorphous carbon.

[0075] Next, if Figure 4 As shown in parts (1) and (2) in FIG. 1 , a first source / drain region 18 may be formed on top of the preformed structure 31 by using a process such as epitaxy.

[0076] Next, if Figure 5 As shown in parts (1) and (2) of FIG. 1 , an interlayer dielectric layer 37 may be formed on the semiconductor substrate 27 by using processes such as deposition and chemical mechanical polishing, and the top of the interlayer dielectric layer 37 is flush with the top of the mask structure 29. The material of the interlayer dielectric layer 37 may include insulating materials such as silicon oxide or silicon nitride.

[0077] Next, if Figure 6 As shown in parts (1) and (2) of FIG. 1 , a first channel region 32 including a transistor in a first-layer semiconductor structure is formed based on the remaining fin-shaped structure; Figure 7 As shown in parts (1) and (2) in FIG. 1 , a first gate stack structure 19 is formed on the periphery of the first channel region 32 .

[0078] Specifically, the specific process of forming the first channel region and the first gate stack structure can be determined according to the device type of the transistor included in the first semiconductor structure, and is not specifically limited here.

[0079] For example, when the transistor included in the first semiconductor structure is a fin field effect transistor, a process such as wet etching or dry etching can be used to selectively remove at least a portion of the mask structure. At this time, the remaining fin structure forms a first channel region. Then, a process such as atomic layer deposition is used to form a first gate stack structure.

[0080] For another example, when the transistor included in the first semiconductor structure is a ring-gate transistor, a process such as wet etching or dry etching can be used to selectively remove at least part of the mask structure and the remaining sacrificial layer. At this time, the remaining channel layer forms a first channel region. Then, a process such as atomic layer deposition is used to form a first gate stack structure.

[0081] like Figure 8 As shown in parts (1) and (2) of the invention, after forming the first semiconductor structure 12, the second semiconductor structure 13 can be formed first. The specific manufacturing process of the second semiconductor structure 13 can refer to the manufacturing process of the first semiconductor structure 12 described above, and will not be repeated here. The difference is that when manufacturing the second semiconductor structure 13, it is not necessary to form the first opening groove and the pre-formed structure. Then, a substrate is formed, and a first contact structure is formed in the substrate.

[0082] Alternatively, before forming the second semiconductor structure, a substrate may be formed, and the first contact structure may be formed in the substrate. The specific formation order of the substrate and the first contact structure may be determined according to actual needs and is not specifically limited here.

[0083] Exemplarily, the above-mentioned forming of the substrate and the first contact structure may include the following steps: Fig. 9 and Fig.10 As shown in parts (1) and (2) of FIG. 1 , the semiconductor substrate can be selectively removed by wet etching or dry etching. At this time, since the preformed structure 31 and the semiconductor substrate are made of different materials, the preformed structure 31 is retained after the semiconductor substrate is removed.

[0084] Next, if Fig.11As shown in parts (1) and (2) of the invention, a substrate 11 can be formed on the side of the first semiconductor structure 12 facing away from the second semiconductor structure 13 by using processes such as deposition and chemical mechanical polishing. The substrate 11 and the preformed structure 31 are flush with each other on the side facing away from the first semiconductor structure 12, and the materials of the substrate 11 and the preformed structure 31 are different. Specifically, the material and structure of the substrate 11 can refer to the above text. Among them, the substrate 11 and the preformed structure 31 are flush with each other on the side facing away from the first semiconductor structure 12, and the preformed structure 31 can be exposed to the outside, which is convenient for the subsequent selective removal of the preformed structure 31.

[0085] Next, if Fig.12 As shown in parts (1) and (2) of FIG. 1 , a wet etching or dry etching process can be used to selectively remove the preformed structure. At this time, the first opening groove 30 is released. Then, as shown in FIG. Fig.13 As shown in parts (1) and (2) of FIG. 1 , the first contact portion 16 can be formed in the first opening groove by using a process such as sputtering or evaporation.

[0086] Next, if Fig.14 As shown in parts (1) and (2) of FIG. 1 , a wet etching or dry etching process can be used to selectively remove a portion of the substrate 11 located below the first gate stack structure 19 to form a second opening groove 33. The second opening groove 33 is at least used to fill the second contact portion.

[0087] It should be noted that, in the process of forming the second opening groove, only the portion of the substrate located below the first gate stack structure may be removed; or Fig.14 As shown in parts (1) and (2) in the figure, the part of the first gate dielectric layer in contact with the substrate 11 can also be removed at the same time, so that the second contact part formed subsequently can directly make electrical contact with the first gate, thereby reducing the contact resistance.

[0088] Next, if Fig.15 As shown in parts (1) and (2), deposition and etching processes can be used to form a dielectric sidewall 25 at least covering the sidewall of the first contact portion 16 in the second opening groove 33 and along the length direction of the first gate stack structure 19. The material of the dielectric sidewall 25 can be referred to above.

[0089] Next, if Fig.16 As shown in parts (1) and (2) of FIG. 1 , a process such as sputtering or evaporation can be used to form a second contact portion 17 in the remaining second opening groove to obtain a first contact structure 15 .

[0090] It should be noted that if the first contact portion and the second contact portion are separated by the substrate, the above-mentioned process of manufacturing the dielectric sidewall may not be performed.

[0091] As for the manufacturing process of the second contact structure, Fig.17 As shown in parts (1) and (2) of the invention, a deposition process or the like can be used to first form an interlayer dielectric layer 37 on the side of the second semiconductor structure 13 away from the substrate. Then, an etching process or the like is used to form a contact hole; and a sputtering or evaporation process or the like is used to form a third contact portion 21 and a fourth contact portion 22 filled in the contact hole, thereby obtaining a second contact structure 20.

[0092] It should be noted that the second contact structure and the second semiconductor structure can be formed in a variety of ways. How to form the above structure is not the main feature of the present invention, so in this specification, only a brief introduction is given so that ordinary technicians in the field can easily implement the present invention. Ordinary technicians in the field can completely imagine other ways to make the second contact structure and the second semiconductor structure.

[0093] In the above description, the technical details of the patterning and etching of each layer are not described in detail. However, those skilled in the art should understand that various technical means can be used to form layers, regions, etc. of desired shapes. In addition, in order to form the same structure, those skilled in the art can also design methods that are not completely the same as the methods described above. In addition, although the various embodiments are described above separately, this does not mean that the measures in the various embodiments cannot be used in combination to advantage.

[0094] The embodiments of the present invention are described above. However, these embodiments are only for a clearer description and are not intended to limit the scope of the present invention. The scope of the present invention is defined by the appended claims and their equivalents. Without departing from the scope of the present invention, a person skilled in the art may make various substitutions and modifications, which should all fall within the scope of the present invention.

Claims

1. A semiconductor device, characterized in that: Includes: base, A first semiconductor structure is disposed on the substrate; A second semiconductor structure is arranged above the first semiconductor structure along the thickness direction of the substrate; the first semiconductor structure and the second semiconductor structure both include a plurality of transistors spaced apart and distributed along the thickness direction perpendicular to the substrate; a first contact structure, disposed in the substrate; the first contact structure comprises a first contact portion electrically contacting a first source / drain region included in the transistor in the first semiconductor structure, and a second contact portion electrically contacting a first gate stack structure included in at least part of the transistor in the first semiconductor structure; the first contact portion and the second contact portion are insulated from each other; A second contact structure is arranged on a side of the second semiconductor structure facing away from the first semiconductor structure; the second contact structure includes a third contact portion electrically contacting a second source / drain region included in the transistor in the second semiconductor structure, and a fourth contact portion electrically contacting a second gate stack structure included in at least part of the transistor in the second semiconductor structure; the third contact portion and the fourth contact portion are insulated from each other.

2. The semiconductor device according to claim 1, wherein: The contact mode between the first contact portion and the first source / drain region is back-side direct contact; And / or, the second contact portion is in direct back-side contact with at least a portion of the first gate stack structure.

3. The semiconductor device according to claim 1, wherein: The first contact portion is self-aligned with the first source / drain region.

4. The semiconductor device according to claim 1, wherein: The semiconductor device further includes a dielectric spacer, wherein the dielectric spacer is located between the first contact portion and the second contact portion, and the dielectric spacer is located below at least a portion of the first gate spacer of the transistor in the first semiconductor structure.

5. The semiconductor device according to claim 4, characterized in that The first contact portion, the second contact portion, and an end portion of the dielectric spacer facing away from the second semiconductor structure are aligned.

6. A method for manufacturing a semiconductor device, characterized in that: include: forming a first semiconductor structure and a substrate; The first semiconductor structure is disposed on the substrate; forming a first contact structure in the substrate; A second semiconductor structure is formed and arranged above the first semiconductor structure along the thickness direction of the substrate; the first semiconductor structure and the second semiconductor structure both include a plurality of transistors distributed along the thickness direction perpendicular to the substrate; the first contact structure includes a first contact portion electrically contacting a first source / drain region included in the transistor in the first semiconductor structure, and a second contact portion electrically contacting a first gate stack structure included in at least part of the transistor in the first semiconductor structure; the first contact portion and the second contact portion are insulated from each other; A second contact structure is formed on the side of the second semiconductor structure facing away from the first semiconductor structure; the second contact structure includes a third contact portion electrically contacting a second source / drain region included in the transistor in the second semiconductor structure, and a fourth contact portion electrically contacting a second gate stack structure included in at least part of the transistor in the second semiconductor structure; the third contact portion and the fourth contact portion are insulated from each other.

7. The method for manufacturing a semiconductor device according to claim 6, wherein: The first semiconductor structure is formed, comprising: Providing a semiconductor substrate; Forming a plurality of fin-shaped structures spaced apart from each other in a thickness direction perpendicular to the base on the semiconductor substrate, and forming a mask structure spanning over the fin-shaped structures; Selectively removing a portion of each of the fin structures exposed outside the mask structure; Under the protection of the mask structure, a portion of the semiconductor substrate is selectively etched to form a first opening groove; and a preformed structure filled in the first opening groove is formed; the preformed structure and the semiconductor substrate are made of different materials; forming the first source / drain region above the preformed structure; A first channel region included in the transistor in the first semiconductor structure is formed based on the remaining fin structure; and the first gate stack structure is formed around the first channel region.

8. The method for manufacturing a semiconductor device according to claim 7, wherein: Forming the substrate and the first contact structure includes: selectively removing the semiconductor substrate; The substrate is formed on a side of the first semiconductor structure away from the second semiconductor structure; the substrate is flush with a side of the preformed structure away from the first semiconductor structure, and the substrate and the preformed structure are made of different materials; Selectively removing the preformed structure; and forming the first contact portion in the first opening groove; Selectively removing a portion of the substrate below the first gate stack structure to form a second opening groove; A dielectric sidewall at least covering the sidewall of the first contact portion is formed in the second opening groove and along the length direction of the first gate stack structure; and the second contact portion is formed in the remaining second opening groove to obtain the first contact structure.

9. The method for manufacturing a semiconductor device according to claim 7, wherein: The material of the preformed structure includes at least one of silicon nitride, silicon oxynitride and amorphous carbon.

10. The method for manufacturing a semiconductor device according to any one of claims 6 to 9, characterized in that: After forming the second semiconductor structure disposed above the first semiconductor structure at intervals along the thickness direction of the substrate, the substrate is formed, and a first contact structure is formed in the substrate.

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