Manufacturing method and application of Sub layer of aluminum-copper laminated die chip

Abstract

The invention discloses a manufacturing method and application of a Sub layer of an aluminum-copper laminated die chip, and the method comprises the steps: removing an aluminum oxide layer on the surface of the chip through the etching of RIE equipment, and exposing an aluminum metal layer; removing the exposed aluminum metal layer through a wet chemical reaction to expose the silicon substrate layer; etching and removing the silicon substrate layer and the copper oxide layer by using RIE (Reactive Ion Etching) equipment to expose the copper wiring layer; a part of the copper wiring layer is removed through a wet chemical reaction until 1-2 copper wiring layers adjacent to the Sub layer are left, and the barrier layer between the copper wiring layers is removed through a grinding method; and removing the residual copper wiring layer by using a mixed solution of hydrofluoric acid and sodium chloride. According to the manufacturing method and application of the Sub layer of the aluminum-copper laminated die chip provided by the invention, a multi-layer structure of the aluminum-copper laminated die chip is accurately removed by using a process of combining dry etching and wet chemical reaction in stages, and high-quality exposure of the Sub layer is realized.

Description

Technical Field

[0001] The present invention belongs to the technical field of chip detection, and specifically relates to a method for manufacturing a Sub layer of an aluminum-copper stacked die chip and an application thereof. Background Art

[0002] In the modern electronics industry, chip manufacturing and failure analysis are crucial. With the continuous upgrading of chip technology, chip structures are becoming increasingly complex, especially the increasing application of stacked chips, which brings huge challenges to chip failure analysis. In the process of chip failure analysis, it is usually necessary to unpack the chip and remove the metal layer and passivation layer inside the chip in order to conduct detailed inspection and analysis of the internal structure of the chip.

[0003] In the prior art, there are great limitations in the de-layering method for aluminum-copper stacked die chips. Aluminum-copper stacked die chips are a special chip structure, which includes a chip unit formed by superimposing an aluminum process and a copper process. The structure includes an aluminum oxide layer, an aluminum metal layer, a silicon substrate layer, a copper oxide layer, multiple copper wiring layers and a Sub layer from top to bottom, and a barrier layer is provided between adjacent copper wiring layers. When performing failure analysis on chips with this structure, a common method is to directly immerse the chip in an acid solution and remove the metal layer and passivation layer in the chip by acid etching.

[0004] However, this traditional acid etching method has exposed many problems in practical applications. The particularity of the aluminum-copper stacked die chip structure leads to significant differences in the chemical properties of its various layers of materials, and the corrosion rates of acid solutions on different metal layers are inconsistent. To ensure that the metal layer can be completely removed, a long period of acid immersion is usually required. However, long-term acid immersion will not only accelerate the dissolution of the metal layer, but also cause serious over-corrosion of the chip Sub layer. This over-corrosion phenomenon leads to the destruction of the Sub layer structure, which directly affects the accuracy and reliability of subsequent chip failure analysis results.

[0005] Therefore, it is necessary to provide a new solution to the above technical problems. Summary of the invention

[0006] The purpose of the present invention is to provide a method for manufacturing a Sub layer of an aluminum-copper stacked die chip and its application, which can avoid excessive corrosion of the chip Sub layer and facilitate chip failure analysis.

[0007] To achieve the above purpose, the technical solution provided by the present invention is as follows:

[0008] In a first aspect, the present invention provides a method for manufacturing a Sub layer of an aluminum-copper stacked die chip, wherein the aluminum-copper stacked die chip comprises an aluminum oxide layer, an aluminum metal layer, a silicon substrate layer, a copper oxide layer, a plurality of copper wiring layers and a Sub layer stacked sequentially from top to bottom, and a barrier layer is provided between adjacent copper wiring layers, and the manufacturing method comprises:

[0009] S201: Use RIE equipment to etch and remove the aluminum oxide layer on the surface of the chip to expose the aluminum metal layer;

[0010] S202: removing the exposed aluminum metal layer through a wet chemical reaction to expose the silicon substrate layer;

[0011] S203: using RIE equipment to etch and remove the silicon substrate layer and the copper oxide layer to expose the copper wiring layer;

[0012] S204: removing a portion of the copper wiring layer by wet chemical reaction until 1 to 2 layers of copper wiring layers adjacent to the Sub layer remain, wherein the barrier layer between the copper wiring layers is removed by grinding;

[0013] S205: using a mixed solution of hydrofluoric acid and sodium chloride to remove the remaining copper wiring layer.

[0014] In one or more embodiments, in step S201, the RIE etching time of the aluminum oxide layer is 5 to 10 minutes, and the reactive gas is CHF 3 and O 2 The mixed gas has an etching power of 200-400W.

[0015] In one or more embodiments, in step S202, a mixed solution of hydrochloric acid and hydrogen peroxide is used to remove the exposed aluminum metal layer.

[0016] In one or more embodiments, the concentration of hydrochloric acid in the mixed solution of hydrochloric acid and hydrogen peroxide is 15-30%, and the concentration of hydrogen peroxide is 15-30%.

[0017] In one or more embodiments, in step S203, the etching time of the silicon substrate layer by RIE is 5 to 10 minutes, and the reactive gas is SF 6 and O 2 The mixed gas has an etching power of 150 to 300W.

[0018] In one or more embodiments, in step S203, the RIE etching time of the copper oxide layer is 5 to 10 minutes, and the reactive gases are Ar and O. 2 The mixed gas has an etching power of 250-400W.

[0019] In one or more embodiments, in step S204, a hydrofluoric acid solution with a concentration of 40-50% is used to remove the upper copper wiring layer.

[0020] In one or more embodiments, in step S204, a hydrofluoric acid solution with a concentration of 30-40% is used to remove the middle copper wiring layer until 1-2 copper wiring layers adjacent to the Sub layer remain.

[0021] In one or more embodiments, in step S205, the concentration of hydrofluoric acid is 30-40%, and the molar ratio of hydrofluoric acid to sodium chloride is 1:(0.7-1).

[0022] In a second aspect, the present invention provides the application of the aforementioned method for making the Sub layer of the aluminum-copper stacked die chip in chip failure analysis.

[0023] Compared with the prior art, the manufacturing method and application of the Sub layer of the aluminum-copper stacked die chip provided by the present invention uses a process combining dry etching and wet chemical reaction in stages to accurately remove the multi-layer structure of the aluminum-copper stacked die chip, thereby achieving high-quality exposure of the Sub layer; the aluminum oxide layer, the silicon substrate layer and the copper oxide layer are etched by RIE equipment, thereby effectively controlling the etching depth and selectivity and avoiding damage to the underlying structure; at the same time, a mixed solution of hydrofluoric acid and sodium chloride is used to remove the copper wiring layer in steps, thereby reducing the common over-corrosion and surface roughness problems in traditional methods and significantly improving the integrity and flatness of the Sub layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the prior art descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0025] Figure 1 This is a schematic diagram of the structure of an aluminum-copper stacked die chip in one embodiment of the present invention;

[0026] Figure 2 This is a flow chart of a method for manufacturing a Sub layer of an aluminum-copper stacked die chip in one embodiment of the present invention;

[0027] Figure 3 This is a microscopic image of the Sub layer produced in Example 1 of the present invention;

[0028] Figure 4 This is a microscopic image of the Sub layer produced in Example 2 of the present invention;

[0029] Figure 5This is a microscopic image of the Sub layer produced in Example 3 of the present invention;

[0030] Figure 6 This is a microscopic image of the Sub layer produced in Comparative Example 1 of the present invention;

[0031] Figure 7 This is a microscopic image of the Sub layer produced in Comparative Example 2 of the present invention.

[0032] Description of main reference numerals:

[0033] 101 - aluminum oxide layer, 102 - aluminum metal layer, 103 - silicon substrate layer, 104 - copper oxide layer, 105 - copper wiring layer, 106 - Sub layer, 107 - barrier layer. DETAILED DESCRIPTION

[0034] In order to enable those skilled in the art to better understand the technical solutions in the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0035] It should be noted that in the following description, the "%" indicating the amount is a weight basis unless otherwise specified. Unless otherwise specified, all numbers used in this specification and claims to indicate characteristic dimensions, quantities and physical properties should be understood to be modified by the term "about" in all cases. Therefore, unless otherwise specified, the numerical parameters listed in the above specification and the attached claims are approximate values, and those skilled in the art can use the teachings disclosed herein to seek to obtain the desired properties and appropriately change these approximate values. The use of numerical ranges expressed as endpoints includes all numbers within the range and any range within the range, for example, 1 to 5 includes 1, 1.2, 1.4, 1.55, 2, 2.75, 3, 3.80, 4 and 5, etc.

[0036] In today's electronics industry, with the rapid development of chip technology and the intensification of miniaturization, the structure of chips has become more and more complex, especially the application of aluminum-copper stacked die chips has become more and more popular. Such chips usually contain multi-layer metal structures and complex material layouts, which makes it more difficult to expose and detect the inner layers of the chip during failure analysis.

[0037] After studying the prior art, the inventors found that conventional de-layering methods mostly use acid etching, which has significant defects: due to the different chemical properties of the various layers of materials in the aluminum-copper stacked die chip, the acid etching method cannot provide consistent and controllable material removal effects. This usually leads to two major problems: First, in order to ensure that the metal layer can be completely removed, a long period of acid immersion is required, and this long-term acid etching often causes over-corrosion of the underlying Sub layer, damaging the structure of the Sub layer (silicon substrate), thereby affecting the accuracy of subsequent failure analysis; second, the acid etching process easily causes the roughness of the chip surface to increase, affecting the recognition ability of the detection equipment, thereby reducing the analysis efficiency and accuracy. In addition, the permeability of the acid during the acid etching process may destroy the integrity of other areas of the chip, further reducing the reliability of the failure analysis.

[0038] In response to the above problems, the present invention proposes an innovative step-by-step de-layering method, which aims to remove chip materials layer by layer through a process that combines dry etching with wet chemical reactions. Specifically, the present invention first uses a highly controllable dry etching technology to remove the oxide layer and other specific metal layers on the surface of the chip to ensure the selectivity and accuracy of the de-layering process, thereby effectively avoiding the problem of over-corrosion. Subsequently, an optimized wet chemical reaction is used to remove other target metal layers, and specific chemicals are added to reduce corrosiveness to further protect the underlying Sub layer structure.

[0039] Please refer to Figure 1 , which is a schematic diagram of the structure of an aluminum-copper stacked die chip in one embodiment of the present invention. The aluminum-copper stacked die chip includes an aluminum oxide layer 101, an aluminum metal layer 102, a silicon substrate layer 103, a copper oxide layer 104, a plurality of copper wiring layers 105 and a sub layer 106 stacked in sequence from top to bottom, and a barrier layer 107 is provided between adjacent copper wiring layers 105.

[0040] The aluminum oxide layer 101 is located on the top of the entire chip and is usually used as a protective layer or passivation layer to prevent the external environment from corroding and damaging the inside of the chip. Aluminum oxide has good insulation and corrosion resistance, which allows it to protect the chip while ensuring the overall electrical insulation performance.

[0041] Under the aluminum oxide layer 101 is the aluminum metal layer 102, which is mainly used for electrical connection and signal transmission within the chip. Aluminum has the characteristics of strong conductivity, low cost and good processing performance, so it is widely used in chip manufacturing. However, the conductivity and thermal stability of aluminum may not be as good as copper in some high-frequency or high-power applications, so more copper structures with excellent conductivity are introduced under the aluminum metal layer 102. This design achieves an effective balance between performance and cost by selecting suitable metal materials in different functional layers.

[0042] Below the aluminum metal layer 102 is the silicon substrate layer 103, which plays a supporting role in the chip. The silicon substrate provides mechanical strength and stability for the entire aluminum die.

[0043] The copper oxide layer 104 is used as an isolation layer or protective layer in the chip to prevent copper from diffusing into other layers and maintain the integrity of the overall structure. Copper is a material that diffuses easily and may cause unnecessary electrical interference if not effectively controlled. Therefore, the copper oxide layer 104 not only plays a protective role, but also prevents the degradation of electrical performance.

[0044] The core part of the chip is composed of multiple copper wiring layers 105, which are responsible for the efficient transmission of electrical signals. The copper wiring layer 105 has excellent electrical conductivity and is more suitable for high-density and high-frequency applications than aluminum. These layers connect different circuit units through complex wiring methods to realize the various functions of the chip. Since mutual interference between copper wiring layers 105 may cause signal transmission problems, in order to improve the stability of the signal, a barrier layer 107 is set between adjacent copper wiring layers 105. These barrier layers 107 are usually made of materials such as titanium and tantalum nitride, which can prevent the diffusion of copper atoms and provide isolation and protection for electrical signals. The role of the barrier layer 107 is to reduce the parasitic capacitance and inductance effects between the wiring layers and improve the overall performance of the chip.

[0045] Sub layer 106 is located at the bottom of the chip and is the base layer of the entire chip structure. The integrity of sub layer 106 is crucial in failure analysis and structural stability. Sub layer 106 not only provides additional mechanical support for the entire chip, but also plays a heat dissipation function in certain applications, helping the chip to maintain stable operation in high power or high temperature environments.

[0046] Please refer to Figure 2 FIG. 1 is a flow chart of a method for manufacturing a Sub layer of an aluminum-copper stacked die chip in one embodiment of the present invention. The method for manufacturing a Sub layer of an aluminum-copper stacked die chip specifically comprises the following steps:

[0047] S201: Use RIE equipment to etch and remove the aluminum oxide layer on the surface of the chip to expose the aluminum metal layer.

[0048] The purpose of step S201 is to ensure that the aluminum metal layer can be exposed by removing the aluminum oxide layer for subsequent processing. In the chip structure, the aluminum oxide layer is usually used as a protective layer or passivation layer, and has excellent corrosion resistance and electrical insulation properties. However, when it is necessary to further remove the underlying material, this protective layer needs to be effectively removed. RIE equipment can gradually etch away the aluminum oxide layer molecules by combining plasma chemical reactions and physical sputtering effects. This etching method not only has extremely high selectivity, but also can accurately control the depth and range of etching to ensure that no damage is caused to the aluminum metal layer below.

[0049] In an exemplary embodiment, in step S201, the RIE etching time of the aluminum oxide layer is 5 to 10 minutes, and the reactive gas is CHF 3 and O 2 The mixed gas has an etching power of 200-400W.

[0050] In step S201, CHF 3 and O 2 The mixed gas is injected into the RIE etching chamber to form a high-energy plasma. 3 It is a fluorine-containing compound that produces highly active fluorine free radicals after decomposition. These free radicals can react chemically with aluminum oxide to produce volatile compounds (such as AlF 3 ), thereby removing the aluminum oxide layer. 2 The addition of gas plays an auxiliary role, can enhance the reactivity of plasma and improve the overall efficiency of etching. In addition, oxygen can help remove carbon-based residues produced during the etching process and maintain the cleanliness of the etched surface.

[0051] The etching time range is set to 5 to 10 minutes to accommodate aluminum oxide layers of different thicknesses. Shorter etching times are suitable for thinner aluminum oxide layers to avoid unnecessary material consumption and energy waste; while longer times are suitable for thicker aluminum oxide layers to ensure that the target material can be completely removed. The etching power is between 200 and 400 W, and the choice of this range directly affects the energy level and reactivity of the plasma. Lower power (around 200 W) is suitable for fine etching, which can provide higher etching selectivity and reduce damage to the underlying aluminum metal layer; while higher power (around 400 W) can speed up the etching rate and improve processing efficiency, but requires precise control to avoid over-etching.

[0052] S202: removing the exposed aluminum metal layer through a wet chemical reaction to expose the silicon substrate layer.

[0053] The aluminum metal layer is removed by a highly selective chemical solution, usually a mixed solution of hydrochloric acid (HCl) and hydrogen peroxide. As a strong acid, hydrochloric acid can effectively react with aluminum to form aluminum chloride, a compound that is easily soluble in water and can be easily removed by the chemical solution. As an oxidant, hydrogen peroxide can further accelerate the dissolution process of aluminum, oxidize the aluminum surface and form new soluble products, thereby improving the reaction efficiency and material removal rate. This wet etching process is carried out under mild reaction conditions, which can ensure that the aluminum metal layer is completely removed and minimize chemical erosion of the silicon substrate layer.

[0054] In an exemplary embodiment, in step S202, a mixed solution of hydrochloric acid and hydrogen peroxide is used to remove the exposed aluminum metal layer. The concentration of hydrochloric acid in the mixed solution of hydrochloric acid and hydrogen peroxide is preferably 15-30%, and the concentration of hydrogen peroxide is preferably 15-30%.

[0055] The concentration range of hydrochloric acid is set at 15-30%, which can not only ensure that the reaction rate is fast enough to meet the efficiency requirements of industrial processing, but also control the intensity of the reaction to a certain extent to prevent excessive corrosion to the surrounding environment and other layers of the chip.

[0056] S203: Use RIE equipment to etch and remove the silicon substrate layer and the copper oxide layer to expose the copper wiring layer.

[0057] In an exemplary embodiment, in step S203, the etching time of the silicon substrate layer etched by RIE is 5 to 10 minutes, and the reactive gas is SF 6 and O 2 The mixed gas has an etching power of 150 to 300W.

[0058] When removing the silicon substrate layer, the RIE etching time range is set to 5 to 10 minutes, depending on the thickness of the silicon layer and the required etching depth. The reactive gas used is SF 6 and O 2 Mixed gas. SF 6 It is a sulfur-containing hexafluoride gas that can decompose highly active fluorine radicals in a plasma environment. These free radicals react with silicon materials to form volatile products such as SiF 4 (silicon tetrafluoride), thereby achieving silicon removal. Oxygen (O 2) plays multiple roles. On the one hand, it can improve the activity and density of plasma, enhance the uniformity and rate of etching; on the other hand, oxygen can also remove carbon-based residues produced during the etching process to ensure the cleanliness of the etched surface. The etching power range is set at 150-300W. This range is designed to provide appropriate plasma energy to balance the etching rate and selectivity. If the power setting is too low, the etching efficiency is insufficient, while too high a power may cause over-etching or damage the sensitive layer below.

[0059] In an exemplary embodiment, in step S203, the RIE etching time of the copper oxide layer is 5 to 10 minutes, and the reactive gases are Ar and O. 2 The mixed gas has an etching power of 250-400W.

[0060] Copper oxide (CuO) is a material with relatively stable chemical properties. The etching time is still set to 5 to 10 minutes, and the reactive gases used are Ar (argon) and O 2 Argon produces high-energy ions in the plasma, which physically bombard the copper oxide surface, stripping its atoms from the substrate, forming a sputtering effect. Physical etching can provide precise material removal while reducing the impact of chemical reactions on the copper wiring layer below. 2 The addition of can assist the oxidation reaction during the etching process, further promote the decomposition of copper oxide, and improve the overall etching efficiency. The etching power is set at 250-400W to ensure efficient physical bombardment energy.

[0061] S204: removing a portion of the copper wiring layer by wet chemical reaction until 1 to 2 layers of copper wiring layers adjacent to the Sub layer remain, wherein the barrier layer between the copper wiring layers is removed by grinding.

[0062] Copper is an active metal that reacts easily with certain acidic or oxidizing solutions. In order to remove part of the copper wiring layer, chemical solutions can be used. These solutions can effectively dissolve copper and form stable copper ions, thereby gradually removing the copper wiring layer. Wet chemical reactions are highly controllable. By adjusting the concentration, temperature and reaction time of the solution, the depth and rate of etching can be accurately controlled to avoid excessive corrosion of the copper wiring layer below. In addition, in order to reduce the impact of the chemical solution on other areas of the chip, the chip can be immersed in a reaction vessel and a stirrer can be used to ensure uniform distribution of the solution, thereby improving etching efficiency and uniformity.

[0063] The barrier layer between the copper wiring layers is removed by grinding. The barrier layer is usually made of materials such as titanium (Ti) or tantalum nitride (TaN), which have good anti-diffusion properties and prevent copper ions from diffusing into other layers. Grinding is a mechanical removal process that uses fine grinding materials and equipment to physically grind the barrier layer and gradually remove these materials. Grinding has the advantages of high precision and high efficiency, and is particularly suitable for removing hard barrier layers without damaging surrounding structures. In order to achieve a uniform grinding effect, a precision grinding disc and control system can be used to adjust the grinding pressure and speed to achieve the desired removal effect.

[0064] In an exemplary embodiment, in step S204, a hydrofluoric acid solution with a concentration of 40-50% is used to remove the upper copper wiring layer; a hydrofluoric acid solution with a concentration of 30-40% is used to remove the middle copper wiring layer until 1-2 copper wiring layers adjacent to the Sub layer remain.

[0065] The upper copper wiring layer is removed using a 40-50% hydrofluoric acid solution. Hydrofluoric acid is a strong acid that is highly corrosive and can effectively dissolve metal oxides and certain metals. This high concentration of hydrofluoric acid solution is used to treat the outermost copper wiring layer in order to quickly dissolve and remove this layer of metal in order to expose the structure underneath as quickly as possible. Since high concentrations of hydrofluoric acid are highly reactive and remove the copper wiring layer quickly, it is necessary to control the immersion time and operating conditions to avoid excessive corrosion and runaway chemical reactions.

[0066] After removing the upper copper wiring layer, switch to a hydrofluoric acid solution with a concentration of 30-40% to further remove the middle copper wiring layer until only 1 to 2 layers of copper wiring adjacent to the Sub layer remain. The purpose of using a lower concentration of hydrofluoric acid solution is to slow down the corrosion rate and provide higher selectivity and controllability to ensure that the final exposed copper wiring layer and Sub layer will not be damaged unnecessarily. A lower hydrofluoric acid concentration can make the etching process more gentle and balanced by reducing the activity of the solution, so that the etching process can be precisely controlled even if the immersion time is long.

[0067] S205: using a mixed solution of hydrofluoric acid and sodium chloride to remove the remaining copper wiring layer.

[0068] In an exemplary embodiment, in step S205, the concentration of hydrofluoric acid is 30-40%, and the molar ratio of hydrofluoric acid to sodium chloride is 1:(0.7-1).

[0069] The concentration of hydrofluoric acid is controlled at 30-40%, providing moderate chemical activity, which can effectively etch copper without causing excessive corrosion. When etching copper, hydrofluoric acid forms soluble copper fluoride with copper, which gradually dissolves and removes the copper wiring layer. Since HF has a high corrosive ability, a concentration of 30-40% can provide sufficient etching speed while preventing the solution from causing chemical damage to the exposed Sub layer.

[0070] The addition of sodium chloride plays a role in regulating the reaction. The molar ratio of hydrofluoric acid to sodium chloride is set to 1: (0.7-1), which is based on optimized chemical reaction kinetics and corrosive regulation. Sodium chloride dissociates in the solution to form sodium ions and chloride ions, which can interact with hydrogen ions and fluoride ions in hydrofluoric acid, thereby changing the pH value and etching properties of the solution. The presence of sodium chloride can slow down the excessive corrosion of copper by hydrofluoric acid, and at the same time help prevent the excessive release of byproducts (such as hydrogen fluoride gas) produced during the etching process, thereby improving the safety and stability of the etching process.

[0071] The method for manufacturing the Sub layer of the aluminum-copper stacked die chip provided by the present invention can be applied to the field of chip failure analysis to improve the accuracy of chip failure analysis.

[0072] The present invention will be further described below in conjunction with specific embodiments.

[0073] Example 1

[0074] Place an aluminum-copper stacked die chip (including 6 layers of copper wiring) into the RIE machine and use CHF 3 and O 2 The mixed gas etched the aluminum oxide layer for 8 minutes, with the power set to 300 W and the pressure set to 30 mTorr. It was observed that the top aluminum layer turned white, indicating that the aluminum oxide layer had been removed.

[0075] The chip was taken out and wet reacted with a mixed solution of 20% hydrochloric acid and hydrogen peroxide for 5 minutes to remove the aluminum metal layer. The chip was rinsed with deionized water and dried.

[0076] Put the chip into the RIE machine again and use SF 6 and O 2 The mixed gas etches the silicon substrate layer for 8 minutes, with the power set to 250W and the pressure set to 20mTorr, to remove the silicon substrate layer of the upper die (aluminum die).

[0077] Continue RIE etching the copper oxide layer of the lower die (copper die) using Ar and O 2 Plasma etching was performed for 8 minutes with the power set to 350 W and the pressure to 15 mTorr to expose the copper wiring layer.

[0078] The chip was immersed in a 45% hydrofluoric acid solution for 2 minutes to initially etch the upper copper wiring layer. The chip was immersed in a 30% hydrofluoric acid solution for 3 minutes to remove the remaining middle copper wiring layer, leaving 1 to 2 layers of copper wiring layers adjacent to the Sub layer. The barrier layer between the copper wiring layers was removed by grinding.

[0079] Finally, soak the chip in a mixed solution of hydrofluoric acid and sodium chloride (hydrofluoric acid concentration is 35%, and the molar ratio of hydrofluoric acid to sodium chloride is 1:0.8) for 3 minutes, and finely etch to the Sub layer. Take it out and rinse it with deionized water to ensure that the surface is free of pollution, and the production of the Sub layer is completed.

[0080] Figure 3 is a microscopic image of the Sub layer produced in Example 1, Figure 3 It can be seen that the Sub layer is relatively intact and has not been corroded.

[0081] Example 2

[0082] Place an aluminum-copper stacked die chip (including 6 layers of copper wiring) into the RIE machine and use CHF 3 and O 2 The mixed gas etched the aluminum oxide layer for 8 minutes, with the power set to 300 W and the pressure set to 30 mTorr. It was observed that the top aluminum layer turned white, indicating that the aluminum oxide layer had been removed.

[0083] The chip was taken out and wet reacted with a mixed solution of 20% hydrochloric acid and hydrogen peroxide for 5 minutes to remove the aluminum metal layer. The chip was rinsed with deionized water and dried.

[0084] Put the chip into the RIE machine again and use SF 6 and O 2 The mixed gas etches the silicon substrate layer for 8 minutes, with the power set to 250W and the pressure set to 20mTorr, to remove the silicon substrate layer of the upper die (aluminum die).

[0085] Continue RIE etching the copper oxide layer of the lower die (copper die) using Ar and O 2 Plasma etching was performed for 8 minutes with the power set to 350 W and the pressure to 15 mTorr to expose the copper wiring layer.

[0086] The chip was immersed in a 45% hydrofluoric acid solution for 2 minutes to initially etch the upper copper wiring layer. The chip was immersed in a 30% hydrofluoric acid solution for 3 minutes to remove the remaining middle copper wiring layer, leaving 1 to 2 layers of copper wiring layers adjacent to the Sub layer. The barrier layer between the copper wiring layers was removed by grinding.

[0087] Finally, use a mixed solution of hydrofluoric acid and sodium chloride (hydrofluoric acid concentration is 40%, and the molar ratio of hydrofluoric acid to sodium chloride is 1:1) to soak the chip for 3 minutes, and finely etch it to the Sub layer. Take it out and rinse it with deionized water to ensure that there is no pollution on the surface, and the production of the Sub layer is completed.

[0088] Figure 4 is a microscopic image of the Sub layer produced in Example 2, Figure 4 It can be seen that the Sub layer is relatively intact and has not been corroded.

[0089] Example 3

[0090] Place an aluminum-copper stacked die chip (including 6 layers of copper wiring) into the RIE machine and use CHF 3 and O 2 The mixed gas etched the aluminum oxide layer for 8 minutes, with the power set to 300 W and the pressure set to 30 mTorr. It was observed that the top aluminum layer turned white, indicating that the aluminum oxide layer had been removed.

[0091] The chip was taken out and wet reacted with a mixed solution of 20% hydrochloric acid and hydrogen peroxide for 5 minutes to remove the aluminum metal layer. The chip was rinsed with deionized water and dried.

[0092] Put the chip into the RIE machine again and use SF 6 and O 2 The mixed gas etches the silicon substrate layer for 8 minutes, with the power set to 250W and the pressure set to 20mTorr, to remove the silicon substrate layer of the upper die (aluminum die).

[0093] Continue RIE etching the copper oxide layer of the lower die (copper die) using Ar and O 2 Plasma etching was performed for 8 minutes with the power set to 350 W and the pressure to 15 mTorr to expose the copper wiring layer.

[0094] The chip was immersed in a 40% hydrofluoric acid solution for 3 minutes to initially etch the upper copper wiring layer. The chip was immersed in a 30% hydrofluoric acid solution for 3 minutes to remove the remaining middle copper wiring layer, leaving 1 to 2 layers of copper wiring layers adjacent to the Sub layer. The barrier layer between the copper wiring layers was removed by grinding.

[0095] Finally, soak the chip in a mixed solution of hydrofluoric acid and sodium chloride (hydrofluoric acid concentration is 35%, and the molar ratio of hydrofluoric acid to sodium chloride is 1:0.8) for 3 minutes, and finely etch to the Sub layer. Take it out and rinse it with deionized water to ensure that the surface is free of pollution, and the production of the Sub layer is completed.

[0096] Figure 5 is a microscopic image of the Sub layer produced in Example 3, Figure 5 It can be seen that the Sub layer is relatively intact and has not been corroded.

[0097] Comparative Example 1

[0098] An aluminum-copper stacked die chip (including 6 copper wiring layers) with the same specifications as the embodiment is placed in an acid solution and soaked for 1 hour; taken out and rinsed with deionized water to ensure that the surface is free of contamination, thus completing the production of the Sub layer.

[0099] Figure 6 is a microscopic image of the Sub layer prepared in Comparative Example 1. Figure 6 It can be seen that the Sub layer has obvious over-corrosion.

[0100] Comparative Example 2

[0101] Compared with Example 1, in Comparative Example 2, a 30% hydrofluoric acid solution (without sodium chloride) was used to immerse the chip for 3 minutes to etch the chip to the Sub layer. The other conditions were the same as those in Example 1.

[0102] Figure 7 is a microscopic image of the Sub layer prepared in Comparative Example 2, Figure 7 It can be seen that the Sub layer is over-corroded.

[0103] In summary, the method for manufacturing the Sub layer of the aluminum-copper stacked die chip provided by the present invention uses a process combining dry etching and wet chemical reaction in stages to accurately remove the multi-layer structure of the aluminum-copper stacked die chip, thereby achieving high-quality exposure of the Sub layer; the aluminum oxide layer, the silicon substrate layer and the copper oxide layer are etched by RIE equipment, thereby effectively controlling the etching depth and selectivity to avoid damage to the underlying structure; at the same time, a mixed solution of hydrofluoric acid and sodium chloride is used to remove the copper wiring layer in steps, thereby reducing the common over-corrosion and surface roughness problems in traditional methods, and significantly improving the integrity and flatness of the Sub layer.

[0104] It will be apparent to those skilled in the art that the invention is not limited to the details of the exemplary embodiments described above and that the invention can be implemented in other specific forms without departing from the spirit or essential features of the invention. Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description, and it is intended that all variations falling within the meaning and scope of the equivalent elements of the claims be included in the invention. Any reference numeral in a claim should not be considered as limiting the claim to which it relates.

[0105] In addition, it should be understood that although the present specification is described according to implementation modes, not every implementation mode contains only one independent technical solution. This description of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment may also be appropriately combined to form other implementation modes that can be understood by those skilled in the art.

Claims

1. A method for manufacturing a Sub layer of an aluminum-copper stacked die chip, characterized in that: The aluminum-copper stacked die chip includes an aluminum oxide layer, an aluminum metal layer, a silicon substrate layer, a copper oxide layer, a plurality of copper wiring layers and a Sub layer stacked in sequence from top to bottom, and a barrier layer is provided between adjacent copper wiring layers. The manufacturing method includes: S201: Use RIE equipment to etch and remove the aluminum oxide layer on the surface of the chip to expose the aluminum metal layer; S202: removing the exposed aluminum metal layer through a wet chemical reaction to expose the silicon substrate layer; S203: using RIE equipment to etch and remove the silicon substrate layer and the copper oxide layer to expose the copper wiring layer; S204: removing a portion of the copper wiring layer by wet chemical reaction until 1 to 2 layers of copper wiring layers adjacent to the Sub layer remain, wherein the barrier layer between the copper wiring layers is removed by grinding; S205: using a mixed solution of hydrofluoric acid and sodium chloride to remove the remaining copper wiring layer.

2. The method for manufacturing the Sub layer of the aluminum-copper stacked die chip according to claim 1, characterized in that: In step S201, the RIE etching time of the aluminum oxide layer is 5 to 10 minutes, the reactive gas is a mixture of CHF3 and O2, and the etching power is 200 to 400W.

3. The method for manufacturing the Sub layer of the aluminum-copper stacked die chip according to claim 1, characterized in that: In step S202, a mixed solution of hydrochloric acid and hydrogen peroxide is used to remove the exposed aluminum metal layer.

4. The method for manufacturing the Sub layer of the aluminum-copper stacked die chip according to claim 3, characterized in that: The concentration of hydrochloric acid in the mixed solution of hydrochloric acid and hydrogen peroxide is 15-30%, and the concentration of hydrogen peroxide is 15-30%.

5. The method for manufacturing the Sub layer of the aluminum-copper stacked die chip according to claim 1, characterized in that: In step S203, the etching time of the silicon substrate layer by RIE etching is 5 to 10 minutes, the reactive gas is a mixture of SF6 and O2, and the etching power is 150 to 300W.

6. The method for manufacturing the Sub layer of the aluminum-copper stacked die chip according to claim 1, characterized in that: In step S203, the etching time of RIE etching the copper oxide layer is 5 to 10 minutes, the reactive gas is a mixture of Ar and O2, and the etching power is 250 to 400W.

7. The method for manufacturing the Sub layer of the aluminum-copper stacked die chip according to claim 1, characterized in that: In step S204, a hydrofluoric acid solution with a concentration of 40-50% is used to remove the upper copper wiring layer.

8. The method for manufacturing the Sub layer of the aluminum-copper stacked die chip according to claim 7, characterized in that: In step S204, a hydrofluoric acid solution with a concentration of 30-40% is used to remove the middle copper wiring layer until 1-2 copper wiring layers adjacent to the Sub layer remain.

9. The method for manufacturing the Sub layer of the aluminum-copper stacked die chip according to claim 1, characterized in that: In step S205, the concentration of hydrofluoric acid is 30-40%, and the molar ratio of hydrofluoric acid to sodium chloride is 1:(0.7-1).

10. Application of the method for manufacturing the Sub layer of an aluminum-copper stacked die chip according to any one of claims 1 to 9 in chip failure analysis.

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