Preparation method of semiconductor element with recessed grid electrode

Abstract

The invention provides a preparation method of a semiconductor element. The preparation method comprises the following steps: providing a substrate comprising a first surrounding area and a second surrounding area; forming a mandrel layer on the first peripheral area; conformally forming a layer of interstitial material on the substrate and covering the mandrel layer; performing a spacer etch process to convert the layer of spacer material into sacrificial spacers on each side of the mandrel layer; forming a lower layer on the substrate and covering the mandrel layer and the plurality of sacrificial spacers; recessing the lower layer to expose the mandrel layer and the plurality of sacrificial spacers; selectively removing the plurality of sacrificial spacers to expose the first surrounding region; forming a plurality of gate recesses in the first peripheral region; and forming a plurality of recessed gates over the plurality of gate recesses.

Description

[0001] This application is a divisional application of Chinese invention patent application No. 2023113405518, filed on October 17, 2023, with the invention name of "Semiconductor element with recessed gate and preparation method thereof". Application No. 2023113405518 claims priority and benefits of U.S. formal application No. 18 / 236,490 filed on August 22, 2023. The contents of the U.S. formal application are incorporated herein by reference in their entirety. Technical Field

[0002] The present disclosure relates to a method for preparing a semiconductor element, and more particularly to a method for preparing a semiconductor element having a recessed gate. Background Art

[0003] Semiconductor components are used in various electronic applications, such as personal computers, mobile phones, digital cameras, or other electronic devices. The size of semiconductor components is gradually getting smaller to meet the increasing demand for computing power. However, during the process of decreasing size, different problems are added, and such problems continue to increase. Therefore, there is still a constant challenge to achieve improved quality, yield, performance and reliability, as well as reduced complexity.

[0004] The above “prior art” description only provides background technology, does not admit that the above “prior art” description reveals the subject matter of the present disclosure, does not constitute the prior art of the present disclosure, and any description of the above “prior art” should not be regarded as any part of this case. Summary of the invention

[0005] One embodiment of the present disclosure provides a method for preparing a semiconductor element, including providing a substrate including a first peripheral region and a second peripheral region; forming a core axis layer on the first peripheral region; conformally forming a layer of spacer material on the substrate and covering the core axis layer; performing a spacer etching process to transform the layer of spacer material into a plurality of sacrificial spacers on each side of the core axis layer; forming a lower layer on the substrate and covering the core axis layer and the plurality of sacrificial spacers; recessing the lower layer to expose the core axis layer and the plurality of sacrificial spacers; selectively removing the plurality of sacrificial spacers to expose the first peripheral region; forming a plurality of gate recesses in the first peripheral region; and forming a plurality of recessed gates on the plurality of gate recesses.

[0006] Due to the design of the semiconductor device disclosed herein, leakage problems associated with smaller gate sizes can be effectively controlled by utilizing a recessed gate dielectric layer. In addition, multiple recessed gates (e.g., recessed gates) and multiple planar gates (e.g., surrounding gate structures) can be manufactured simultaneously, resulting in a possible reduction in manufacturing costs.

[0007] The above has outlined the technical features and advantages of the present disclosure in a fairly broad manner, so that the detailed description of the present disclosure below can be better understood. Other technical features and advantages that constitute the subject matter of the claims of the present disclosure will be described below. It should be understood by those with ordinary knowledge in the technical field to which the present disclosure belongs that the concepts and specific embodiments disclosed below can be used to modify or design other structures or processes to achieve the same purpose as the present disclosure. It should also be understood by those with ordinary knowledge in the technical field to which the present disclosure belongs that such equivalent constructions cannot depart from the spirit and scope of the present disclosure as defined by the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] When with Figure 1 When read together, various aspects of the present disclosure can be best understood from the following detailed description. It should be understood that, in accordance with standard industry practice, various features are not drawn to scale. In fact, the size of various features can be arbitrarily increased or reduced for clarity of discussion.

[0009] Figure 1 1 is a flow chart illustrating a method for preparing a semiconductor device according to an embodiment of the present disclosure.

[0010] Figures 2 to 20 It is a cross-sectional schematic diagram illustrating a partial process of preparing a semiconductor device according to an embodiment of the present disclosure.

[0011] Figure 21 to Figure 26 It is a partial cross-sectional schematic diagram illustrating a partial process of preparing a semiconductor device according to an embodiment of the present disclosure.

[0012] Fig. 27 It is a cross-sectional schematic diagram illustrating a partial process of preparing a semiconductor device according to an embodiment of the present disclosure.

[0013] Figure 28 to Figure 31 It is a cross-sectional schematic diagram illustrating a partial process of preparing a semiconductor element according to another embodiment of the present disclosure.

[0014] The reference numerals are described as follows:

[0015] 10: Preparation method

[0016] 1A: Semiconductor components

[0017] 1B: Semiconductor components

[0018] 101: Base

[0019] 101TS: Top surface

[0020] 103-1: Character line groove

[0021] 103-3: Character line groove

[0022] 107: Isolation layer

[0023] 200: Character line structure

[0024] 201: word line dielectric layer

[0025] 203: Character line conductive layer

[0026] 205: Conductive layer on the character line

[0027] 207: Character line cover layer

[0028] 300: Peripheral gate structure

[0029] 301: Gate dielectric layer

[0030] 303: Conductive layer under the gate

[0031] 305: Conductive layer on the gate

[0032] 307: Gate cover layer

[0033] 400: Recessed gate

[0034] 401: Recessed gate dielectric layer

[0035] 403: Conductive layer under the recessed gate

[0036] 403BP: lower part

[0037] 403TS: Top surface

[0038] 405: Conductive layer on recessed gate

[0039] 405TS: Upper surface

[0040] 405BS: Lower surface

[0041] 407: Recessed gate capping layer

[0042] 407BP: lower part

[0043] 511: First hard mask layer

[0044] 513: The First Pattern

[0045] 515: Sacrificial Interstitial

[0046] 531: Lower level

[0047] 533: Opening

[0048] 711: First insulation material

[0049] 713: Interstitial Materials

[0050] 721: First mask layer

[0051] 723: Mandrel layer

[0052] 723S: Side

[0053] 725: Second mask layer

[0054] 727: Gate mask layer

[0055] 731: Gate dielectric materials

[0056] 733: First conductive material

[0057] 735: Second conductive material

[0058] 735BS: Lower surface

[0059] 737: Upper insulation material

[0060] 737BS: Lower surface

[0061] AR: Array Area

[0062] D1: Distance

[0063] GR: Gate Recess

[0064] PR1: First peripheral area

[0065] PR2: Second peripheral area

[0066] S11: Steps

[0067] S13: Steps

[0068] S15: Steps

[0069] S17: Steps

[0070] VL1: Vertical plane

[0071] VL2: Vertical plane

[0072] VL3: Vertical plane

[0073] VL4: Vertical plane

[0074] VY1: First Valley

[0075] VY2: Second Valley

[0076] W1: Width

[0077] W2: Width

[0078] W3: Width DETAILED DESCRIPTION

[0079] Specific examples of components and configurations are described below to simplify the embodiments of the present disclosure. Of course, these embodiments are for illustration only and are not intended to limit the scope of the present disclosure. For example, in the description, the first component is formed on the second component, which may include an embodiment in which the first and second components are in direct contact, and may also include an embodiment in which additional components are formed between the first and second components so that the first and second components are not in direct contact. In addition, the embodiments of the present disclosure may repeat reference numbers and / or letters in many examples. The purpose of these repetitions is to simplify and clarify, and unless otherwise specified in the text, they do not themselves represent a specific relationship between the various embodiments and / or the configurations discussed.

[0080] Furthermore, for ease of description, spatially relative terms such as "beneath," "below," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or feature shown in the figures to another (other) element or feature. The spatially relative terms are intended to encompass different orientations of the elements in use or operation in addition to the orientation depicted in the figures. The device may have other orientations (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may be interpreted accordingly.

[0081] It should be understood that when forming a component on, connected to, and / or coupled to another component, it may include embodiments in which these components are in direct contact, and may also include embodiments in which additional components are formed between these components so that these components are not in direct contact.

[0082] It should be understood that although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers, or sections, these elements, components, regions, layers, or sections are not limited by these terms. Instead, these terms are only used to distinguish one element, component, region, layer, or section from another region, layer, or section. Therefore, without departing from the teachings of the progressive conception of the present invention, the first element, component, region, layer, or section discussed below may be referred to as a second element, component, region, layer, or section.

[0083] Unless the context indicates otherwise, as used herein, terms such as "same," "equal," "planar," or "coplanar" when referring to orientation, layout, location, shapes, sizes, amounts, or other measures do not necessarily mean an exactly identical orientation, layout, location, shape, size, amount, or other measure, but rather mean nearly identical orientation, layout, location, shape, size, amount, or other measure within acceptable variances that may occur, for example, due to manufacturing processes. The term "substantially" may be used herein to convey this meaning. For example, substantially the same, substantially equal, or substantially planar, is exactly the same, equal, or planar, or it may be the same, equal, or planar within an acceptable variance, and for example, the acceptable variance may occur due to the manufacturing process.

[0084] In the present disclosure, a semiconductor device generally refers to a device that can operate by utilizing semiconductor characteristics, and an electro-optic device, a light-emitting display device, a semiconductor circuit, and an electronic device are all included in the category of semiconductor devices.

[0085] It should be understood that in the description of the present disclosure, above (or up) corresponds to the direction of the Z-direction arrow, and below (or down) corresponds to the relative direction of the Z-direction arrow.

[0086] It should be understood that the terms "forming", "formed" and "form" may refer to and include any method of creating, building, patterning, implanting or depositing an element, a dopant or a material. Examples of formation methods may include, but are not limited to, atomic layer deposition, chemical vapor deposition, physical vapor deposition, sputtering, spin coating, diffusing, depositing, growing, implantation, photolithography, dry etching and wet etching.

[0087] It should be understood that in the description of the present disclosure, the functions or steps mentioned herein may occur in a different order than in the various drawings. For example, two drawings shown in succession may actually be performed substantially simultaneously, or may sometimes be performed in the reverse order, depending on the functions or steps included.

[0088] Figure 1 1 is a flow chart illustrating a method 10 for manufacturing a semiconductor device 1A according to an embodiment of the present disclosure. Figures 2 to 20 1 is a cross-sectional schematic diagram illustrating a partial process of manufacturing a semiconductor device 1A according to an embodiment of the present disclosure. Figure 21 to Figure 26 It is a partial cross-sectional schematic diagram illustrating a partial process of preparing a semiconductor device 1A according to an embodiment of the present disclosure. Fig. 27 1 is a cross-sectional schematic diagram illustrating a partial process of manufacturing a semiconductor device 1A according to an embodiment of the present disclosure.

[0089] Please refer to Figures 1 to 9 In step S11, a substrate 101 may be provided, the substrate 101 including an array region AR, a first peripheral region PR1 and a second peripheral region PR2, a plurality of word line trenches 103-1 and 103-3 may be formed in the array region AR, a layer of first insulating material 711, a plurality of word line lower conductive layers 203, a plurality of word line conductive layers 205 and a word line capping layer 207 may be sequentially formed on the plurality of word line trenches 103-1 and 103-3.

[0090] Please refer to Figure 2, in some embodiments, the array area AR and the first peripheral area PR1 may be adjacent to each other. For example, in a top view, the array area AR may be surrounded by the first peripheral area PR1 (not shown). In some embodiments, the first peripheral area PR1 and the second peripheral area PR2 may be adjacent to each other. For example, in a top view, the first peripheral area PR1 may be surrounded by the second peripheral area PR2 (not shown). In some embodiments, the first peripheral area PR1 and the second peripheral area PR2 may be separated from each other. It should be understood that the array area AR may include a portion of the substrate 101 and a space above the portion of the substrate 101. Describing an element as being disposed on the array area AR means that the element is disposed on an upper surface of the portion of the substrate 101. Describing an element as being disposed in the array area AR means that the element is disposed in the portion of the substrate 101; however, an upper surface of the element may be flush with the upper surface of the portion of the substrate 101. Describing an element as being disposed above the array area AR means that the element is disposed above the upper surface of the portion of the substrate 101. Therefore, the first peripheral region PR1 and the second peripheral region PR2 may include other portions of the substrate 101 and a space above the other portions of the substrate 101 , respectively.

[0091] Please refer to Figure 2 The substrate 101 may be a bulk semiconductor substrate. For example, the bulk semiconductor substrate may include an element semiconductor or a compound semiconductor, such as silicon or germanium, or a compound semiconductor such as silicon germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, or other III-V compound semiconductors or II-VI compound semiconductors.

[0092] Please refer to Figure 2 , an isolation layer 107 may be formed in the substrate 101. For example, the isolation layer 107 may be formed in the array region AR of the substrate 101. A series of deposition processes may be performed to deposit a pad oxide layer (not shown) and a pad nitride layer (not shown) on the substrate 101. A lithography process and a subsequent etching process, such as an anisotropic dry etching process, may be performed to form a plurality of trenches penetrating the pad oxide layer, the pad nitride layer and extending to the substrate 101. An insulating material may be deposited into the trenches, and a planarization process such as chemical mechanical polishing may be subsequently performed until the upper surface 101TS of the substrate 101 is exposed to remove excess filling material, provide a substantially flat surface for subsequent processing steps, and simultaneously form the isolation layer 107. For example, the insulating material may be silicon oxide or other suitable insulating materials.

[0093] Please refer to Figure 3, a first hard mask layer 511 may be formed on the substrate 101. In some embodiments, the first hard mask layer 511 may include a material having an etching selectivity to the substrate 101. In some embodiments, the first hard mask layer 511 may include a material having an etching selectivity to the substrate 101 and the isolation layer 107. In some embodiments, for example, the first hard mask layer 511 may include silicon nitride, boron nitride, silicon boron nitride, boron phosphide, or silicon boron carbon nitride. In some embodiments, for example, the manufacturing technology of the first hard mask layer 511 may include atomic layer deposition, chemical vapor deposition, or other applicable deposition processes.

[0094] In some embodiments, the manufacturing technology of the first hard mask layer 511 may include a film forming process and a treatment process. Specifically, in the film forming process, a plurality of first precursors (which may be boron-based precursors) may be introduced onto the substrate 101 to form a boron-based layer. Subsequently, in the treatment process, a plurality of second precursors, which may be nitrogen-based precursors, may be introduced to react with the boron-based layer and convert the boron-based layer into the first hard mask layer 511.

[0095] In some embodiments, for example, the first precursor can be diborane, borazine, or an alkyl-substituted derivative of borazine. In some embodiments, the first precursor can be introduced at a flow rate between about 5 sccm and about 50 slm (standard liters per minute) or between about 10 sccm and about 1 slm. In some embodiments, the first precursor can be introduced by a diluent gas such as nitrogen, hydrogen, argon, or a combination thereof. The diluent gas can be introduced at a flow rate between about 5 sccm and about 50 slm or between about 1 slm and about 10 slm.

[0096] In some embodiments, the film forming process may be performed without plasma assistance. In this case, the base temperature of the film forming process may be between about 100° C. and about 1000° C. For example, the base temperature of the film forming process may be between about 300° C. and about 500° C. The process pressure of the film forming process may be between about 10 mTorr and about 760 Torr. For example, the process pressure of the film forming process may be between about 2 Torr and about 10 Torr.

[0097] In some embodiments, the film forming process may be performed in the presence of plasma. In this case, the substrate temperature of the film forming process may be between about 100°C and about 1000°C. For example, the substrate temperature of the film forming process may be between about 300°C and about 500°C. The process pressure of the film forming process may be between about 10mTorr and about 760Torr. For example, the process pressure of the film forming process may be between about 2Torr and about 10Torr. The plasma may be generated by an RF power between 2W and 5000W. For example, the RF power may be between 30W and 1000W.

[0098] In some embodiments, for example, the second precursor can be ammonia or hydrazine. In some embodiments, the second precursor can be introduced at a flow rate between about 5 sccm and about 50 slm or between about 10 sccm and about 1 slm.

[0099] In some embodiments, an oxygen-based precursor may be introduced with the second precursor during the treatment process. For example, the oxygen-based precursor may be oxygen, nitric oxide, nitrous oxide, carbon dioxide, or water.

[0100] In some embodiments, a silicon-based precursor may be introduced during the process with a second precursor. For example, the silicon-based precursor may be silane, trisilylamine, trimethylsilane, or a silazane (eg, hexamethylcyclotrisilazane).

[0101] In some embodiments, a phosphorus-based precursor may be introduced during the process with a second precursor. For example, the phosphorus-based precursor may be phosphine.

[0102] In some embodiments, an oxygen-based precursor, a silicon-based precursor, or a phosphorus-based precursor may be introduced together with the second precursor during the processing.

[0103] In some embodiments, the treatment process may be performed with the assistance of a plasma process, a UV curing process, a thermal annealing process, or a combination thereof.

[0104] When the treatment process is performed with the assistance of a plasma process, the plasma of the plasma process may be generated by RF power. In some embodiments, the RF power may be between about 2 W and about 5000 W at a single low frequency between about 100 kHz and about 1 MHz. In some embodiments, the RF power may be between about 30 W and about 1000 W at a single high frequency greater than about 13.6 MHz. In this case, the substrate temperature of the treatment process may be between about 20° C. and about 1000° C. The process pressure of the treatment process may be between about 10 mTorr and about 760 Torr.

[0105] When the treatment process is performed with the assistance of a UV curing process, in this case, the substrate temperature of the treatment process can be between about 20°C and about 1000°C. The process pressure of the treatment process can be between about 10mTorr and about 760Torr. UV curing can be provided by any UV source, such as a mercury microwave arc lamp, a pulsed xenon flash lamp, or an array of high-efficiency UV light emitting diodes. The UV source can have a wavelength between about 170nm and about 400nm. The UV source can provide a photon energy between about 0.5eV and about 10eV, or between about 1eV and about 6eV. The assistance of the UV curing process can remove hydrogen from the first hard mask layer 511. Since hydrogen may diffuse to other areas of the semiconductor element 1A and may reduce the reliability of the semiconductor element 1A, removing hydrogen with the assistance of the UV curing process can improve the reliability of the semiconductor element 1A. In addition, the UV curing process can increase the density of the first hard mask layer 511.

[0106] When the treatment process is performed with the assistance of a thermal annealing process, in this case, the substrate temperature of the treatment process may be between about 20° C. and about 1000° C. The process pressure of the treatment process may be between about 10 mTorr and about 760 Torr.

[0107] Please refer to Figure 3 A first mask layer 721 may be formed on the first hard mask layer 511 . In some embodiments, the first mask layer 721 may be a photoresist layer and may include a pattern of a plurality of word line structures 200 .

[0108] Please refer to Figure 4 , an etching process may be performed to remove a portion of the first hard mask layer 511. In some embodiments, during the etching process, an etching rate ratio of the first hard mask layer 511 to the substrate 101 may be between about 100:1 and about 2:1, between about 15:1 and about 2:1, or between about 10:1 and about 2:1. In some embodiments, during the etching process, an etching rate ratio of the first hard mask layer 511 to the isolation layer 107 may be between about 100:1 and about 2:1, between about 15:1 and about 2:1, or between about 10:1 and about 2:1. The pattern of the first mask layer 721 may be transferred to the first hard mask layer 511 and may be referred to as a first pattern 513. Portions of the isolation layer 107 and portions of the substrate 101 may be exposed by the first pattern 513. After the etching process, the first mask layer 721 may be removed by ashing or other applicable processes.

[0109] Please refer to Figure 5, a trench etching process may be performed using the first hard mask layer 511 as a mask to remove portions of the isolation layer 107 and portions of the substrate 101 while forming a plurality of word line trenches 103-1, 103-3. In some embodiments, the plurality of word line trenches 103-1 formed in the substrate 101 may be shallower than the plurality of word line trenches 103-3 formed in the isolation layer 107. In some embodiments, during the trench etching process, an etching rate ratio of the isolation layer 107 to the first hard mask layer 511 may be between about 100:1 and about 5:1, between about 15:1 and about 5:1, or between about 10:1 and about 5:1. In some embodiments, during the trench etching process, an etching rate ratio of the substrate 101 to the first hard mask layer 511 may be between about 80:1 and about 5:1, between about 10:1 and about 5:1, or between about 8:1 and about 5:1.

[0110] Please refer to Figure 6 , the layer of first insulating material 711 may be conformally formed on the first hard mask layer 511 and in the plurality of word line trenches 103-1, 103-3. The layer of first insulating material 711 may have a U-shaped cross-sectional profile in the plurality of word line trenches 103-1, 103-3. In some embodiments, the layer of first insulating material 711 may have a thickness in a range of about 1 nm to about 7 nm, including about 1 nm, about 2 nm, about 3 nm, about 4 nm, about 5 nm, about 6 nm, or about 7 nm.

[0111] In some embodiments, the manufacturing technique of the layer of first insulating material 711 may include a thermal oxidation process. For example, the manufacturing technique of the layer of first insulating material 711 may include oxidizing the surfaces of the plurality of word line trenches 103-1, 103-3. In some embodiments, the manufacturing technique of the layer of first insulating material 711 may include a deposition process such as chemical vapor deposition or atomic layer deposition. The first insulating material 711 may include a high-k material, an oxide, a nitride, an oxynitride, or a combination thereof. In some embodiments, after depositing a liner polysilicon layer (not shown for clarity), the manufacturing technique of the layer of first insulating material 711 may include free radical oxidation of the liner polysilicon layer. In some embodiments, after forming the liner silicon nitride layer (not shown for clarity), the manufacturing technique of the layer of first insulating material 711 may include free radical oxidation of the liner silicon nitride layer.

[0112] In some embodiments, the high-k dielectric material may include a hafnium-containing material. For example, the hafnium-containing material may be hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, or a combination thereof. In some embodiments, for example, the high-k dielectric material may be lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, silicon zirconium oxide, zirconium silicon oxynitride, aluminum oxide, or a combination thereof.

[0113] Please refer to Figure 7 , a plurality of word line lower conductive layers 203 may be formed in the plurality of word line trenches 103-1, 103-3 respectively. For example, a conductive material (not shown) may be formed to fill the plurality of word line trenches 103-1, 103-3. An etch-back process may then be performed to partially remove the conductive material formed in the plurality of word line trenches 103-1, 103-3, and simultaneously form a plurality of word line lower conductive layers 203. In some embodiments, the conductive material may be a work function material, such as titanium, titanium nitride, silicon, silicon germanium, or a combination thereof. It should be understood that the term "work function" refers to the overall chemical potential of a material (e.g., a metal) relative to the degree of vacuum.

[0114] For example, in the present embodiment, the conductive material is titanium nitride, and its manufacturing technology may include chemical vapor deposition. In some embodiments, the deposition of the conductive material may include a source gas introduction step, a first cleaning step, a reactant flow step, and a second cleaning step. The source gas introduction step, the first cleaning step, the reactant flow step, and the second cleaning step may be referred to as a cycle. Multiple cycles may be performed to fill multiple word line trenches 103-1, 103-3.

[0115] In detail, Figure 6 The intermediate semiconductor element shown can be loaded in a reaction chamber. In the source gas introduction step, a source gas containing a precursor and a reactant can be introduced into the reaction chamber containing the intermediate semiconductor element. The precursor and the reactant can diffuse through the boundary layer and reach the surface of the intermediate semiconductor element. The precursor and the reactant can be adsorbed on the above-mentioned surface and then migrate on the above-mentioned surface. The adsorbed precursor and the adsorbed reactant can react on the above-mentioned surface and form solid by-products. The solid by-products can form nuclei on the above-mentioned surface. The nuclei can grow into multiple islands and the islands can merge into a continuous film on the above-mentioned surface. In the first cleaning step, a cleaning gas such as argon can be injected into the reaction chamber to clean out gaseous by-products, unreacted precursors and unreacted reactants.

[0116] In the reactant flow step, the reactants can be introduced into the reaction chamber alone to convert the continuous film into a titanium nitride layer. In the second purge step, a purge gas such as argon can be injected into the reaction chamber to purge out gaseous byproducts and unreacted reactants.

[0117] In some embodiments, the deposition of the conductive material using chemical vapor deposition can be performed with the assistance of a plasma. For example, the plasma source can be argon, hydrogen, or a combination thereof.

[0118] For example, the precursor may be titanium tetrachloride. The reactant may be ammonia. Due to the incomplete reaction between titanium tetrachloride and ammonia, titanium tetrachloride and ammonia may react on the surface and form a titanium nitride layer containing high chloride contamination. The ammonia in the reactant flow step may reduce the chloride content of the titanium nitride layer.

[0119] In some embodiments, during etch back, an etch rate ratio of the wordline lower conductive layer 203 to the first insulating material 711 may be between about 100:1 and about 5:1, between about 15:1 and about 5:1, or between about 10:1 and about 5:1.

[0120] Please refer to Figure 8 , a plurality of conductive layers 205 on word lines may be formed in the plurality of word line trenches 103-1, 103-3. In some embodiments, for example, the plurality of conductive layers 205 on word lines may include polysilicon, polycrystalline germanium, polycrystalline silicon germanium, doped polysilicon, doped polycrystalline germanium, doped polycrystalline silicon germanium, or a combination thereof. In some embodiments, the plurality of conductive layers 205 on word lines may be doped with p-type dopants or n-type dopants. In some embodiments, a conductive material such as polysilicon, polycrystalline germanium, or polycrystalline silicon germanium may be deposited into the plurality of word line trenches 103-1, 103-3. An etch-back process may then be performed to remove portions of the conductive layer to form the plurality of conductive layers 205 on word lines. In some embodiments, dopants may be incorporated into the deposition process of the conductive material. In some embodiments, an implantation process may be used to dope the dopants after the etch-back process.

[0121] The term "p-type dopant" refers to an impurity that creates a valence electron defect when added to an intrinsic semiconductor material. In a silicon-containing semiconductor material, examples of p-type dopants include, but are not limited to, boron, aluminum, gallium, or indium. The term "n-type dopant" refers to an impurity that contributes free electrons to the intrinsic semiconductor material when added to an intrinsic semiconductor material. In silicon-containing materials, examples of n-type dopants include, but are not limited to, antimony, arsenic, or phosphorus.

[0122] Please refer to Fig. 9, a word line capping layer 207 may be formed on the first hard mask layer 511 to completely fill the plurality of word line trenches 103-1, 103-3. For example, in some embodiments, the word line capping layer 207 may include silicon nitride, silicon oxynitride, silicon oxynitride, or other applicable dielectric materials. For example, in some embodiments, the fabrication technique of the word line capping layer 207 may include chemical vapor deposition, plasma enhanced chemical vapor deposition, or other applicable deposition processes. A planarization process, such as chemical mechanical polishing, may be performed to remove excess material and provide a substantially flat surface for subsequent processing steps.

[0123] It should be understood that silicon oxynitride in the present disclosure refers to a substance containing silicon, nitrogen and oxygen, wherein the proportion of oxygen is greater than the proportion of nitrogen. Silicon nitride oxide refers to a substance containing silicon, oxygen and nitrogen, wherein the proportion of nitrogen is greater than the proportion of oxygen.

[0124] Please refer to Figure 1 as well as Figure 10 to Figure 13 In step S13 , a mandrel layer 723 may be formed on the word line cap layer 207 and on the first peripheral region PR1 , a plurality of sacrificial spacers 515 may be formed on each side 723S of the mandrel layer 723 , and a lower layer 531 may be formed on the word line cap layer 207 .

[0125] Please refer to Fig.10 , the mandrel layer 723 may be formed on the word line cap layer 207 and on the first peripheral region PR1. In some embodiments, the mandrel layer 723 may be a photoresist layer. In some embodiments, the mandrel layer 723 may be a photoresist layer characterized by a pattern of a plurality of gate recesses GR (to be illustrated later). The layer may be composed of several segments, which may have different widths or have approximately the same width, depending on the specific embodiment. Similarly, the distance between adjacent pairs of segments may be uniformly the same or vary.

[0126] Please refer to Fig.11, a layer of spacer material 713 can be conformally formed on the word line cap layer 207 and can cover the mandrel layer 723. For example, in some embodiments, the spacer material 713 can be silicon oxide. For example, in some embodiments, the manufacturing technology of the layer of spacer material 713 can include a deposition process (e.g., an atomic layer deposition process). Generally speaking, the atomic layer deposition process can supply two (or more) different source gases one by one alternately to the processing object (i.e., the word line cap layer 207) under predetermined process conditions, so that the chemical substances are adsorbed on the processing object at the single atomic layer level and deposited on the processing object through surface reaction. For example, the first source gas and the second source gas are alternately supplied to the processing object to flow along its surface, whereby the molecules contained in the first source gas are adsorbed on the surface, and the molecules contained in the second source gas react with the adsorbed molecules from the first source gas to form a film with a single molecule level thickness. The above process steps are repeated so that a high-quality film can be formed on the processing object.

[0127] In some embodiments, the layer of spacer material 713 formed by an atomic layer deposition process may be performed by sequentially exposing the word line cap layer 207 to a gaseous silicon-containing precursor, such as tetrachlorosilane, and an oxygen-containing precursor, such as water, at a temperature of about 320° C. to about 530° C. In some embodiments, forming the layer of spacer material 713 may include placing a Fig.10 The intermediate semiconductor element shown is exposed to a silicon-containing precursor to achieve chemical adsorption of silicon material onto the intermediate semiconductor element. In theory, chemical adsorption will form a silicon-containing monolayer uniformly one atom or molecule thick over the entire exposed substrate. Excess silicon-containing precursor is removed from the reaction chamber, and the intermediate semiconductor element can be exposed to an oxygen-containing precursor. The oxygen-containing precursor chemically adsorbs onto the silicon-containing monolayer to form an oxygen-containing monolayer. Excess oxygen-containing precursor is then removed from the reaction chamber. These actions are repeated to form silicon dioxide having a desired thickness. The silicon-and-oxygen precursor can be mixed with a catalyst, such as pyridine, to accelerate deposition while reducing the reaction temperature to a range of about 50° C. to about 100° C. Due to the thermally sensitive nature of the substrate or the material deposited thereon, depositing the layer of interstitial material 713 at low temperatures may be advantageous in many cases.

[0128] In detail, in a first reaction of the atomic layer deposition process, a silicon-containing precursor can be introduced into the reaction chamber along with pyridine and can be chemisorbed onto the substrate surface. In some embodiments, the silicon-containing precursor can include silicon hydride or silane, such as hexachlorodisilane, dichlorosilane, silane, disilane, trichlorosilane, or any other silicon-containing compound suitable for use as a precursor. The silicon-containing precursor provided in this stage can be selected so that the amount of silicon-containing precursor that can be bound to the substrate surface is determined by the number of available junctions and the physical size of the chemisorbed species (including ligands). The chemisorbed silicon-containing monolayer formed by the silicon-containing precursor is self-terminated with a surface that does not react with the remaining chemicals used to form the silicon-containing monolayer.

[0129] Excess silicon-containing precursors, particularly silicon-containing precursors that have not been chemically adsorbed to the substrate surface, can then be removed from the reaction chamber with an inert gas pulse. The inert gas can be nitrogen, argon, helium, neon, krypton, or xenon. Purging the reaction chamber can also remove volatile byproducts produced during the atomic layer deposition process. In some embodiments, the inert gas can be nitrogen. The inert gas can be introduced into the reaction chamber, for example, for about 10 seconds. After purging, the reaction chamber can be evacuated or "pumped" to remove gases, such as excess silicon-containing precursors or volatile byproducts. For example, the concentration of silicon-containing precursors can be purged from the reaction chamber by a technique including contacting the substrate, i.e., or the silicon-containing monolayer, with an inert gas and / or reducing the pressure in the reaction chamber to below the deposition pressure, but not limited thereto, to reduce the concentration of silicon-containing precursors that contact the substrate and / or the chemically adsorbed species. In addition, purging can include contacting the silicon-containing monolayer with any substance that allows desorption of chemically adsorbed byproducts and reduces the concentration of the silicon-containing precursor before introducing the oxygen-containing precursor. The appropriate amount of purge to remove the silicon-containing precursor and volatile byproducts can be determined by experimentation. The pump and purge sequence can be repeated multiple times. The pump and purge sequence can begin or end with a pump or purge action. The time and parameters during the pump and purge action, such as gas flow, pressure, and temperature, can be varied during the pump and purge sequence. Reduction in purge and / or pump time can increase the amount of silicon oxide deposited per minute. And it may lead to an increase in the growth rate of the layer of interstitial material 713 .

[0130] The second reaction of the atomic layer deposition process can introduce an oxygen-containing precursor and pyridine into the reaction chamber to form an oxygen-containing monolayer on the silicon-containing monolayer. The oxygen-containing monolayer and the silicon-containing monolayer react to form a silicon oxide film (i.e., the layer of spacer material 713). Reaction byproducts and excess oxygen-containing precursor can be removed from the reaction chamber by using the evacuation and purge sequence described above. For example, the purge can be performed by introducing an inert gas into the reaction chamber. Generally speaking, the precursor pulse time ranges from about 0.5 seconds to about 30 seconds. The layer of spacer material 713 can be deposited on the word line cap layer 207 by continuous or repeated cycles, wherein each cycle deposits a monolayer of silicon oxide. The thickness of the layer of spacer material 713 can be achieved by exposing the intermediate semiconductor element to multiple repeated cycles.

[0131] In some embodiments, after performing an atomic layer deposition process to form the layer of spacer material 713 but before removing the intermediate semiconductor element from the reaction chamber, a post-deposition treatment can be performed on the intermediate semiconductor element, which produces a substantially defect-free silicon oxide surface. Therefore, as used herein, the term "post-deposition treatment" or its grammatical equivalent; "atomic layer deposition process" means and includes a process performed after an atomic layer deposition process, such as a process performed after the formation of the layer of spacer material 713 is substantially completed.

[0132] In detail, for example, after forming the layer of interstitial material 713, the intermediate semiconductor element can be subjected to post-deposition treatment so that the surface of the layer of interstitial material 713 can be substantially free of defects. The post-deposition treatment can include, for example, at least one of a pumping / purge cycle and water exposure, and can be performed after the atomic layer deposition process is completed. As used herein, the term "water exposure" means and includes subjecting the intermediate semiconductor element to water. As a non-limiting example, the water can be deionized water or reagent grade water. The water can contact or react with the layer of interstitial material 713, or react with gaseous byproducts formed during the atomic layer deposition process. In some embodiments, the post-deposition treatment can include a pumping / purge cycle and water exposure. For example, the post-deposition treatment can include at least one pumping action, at least one water exposure action, and at least one purge action, which can be performed in the reaction chamber after forming the layer of interstitial material 713.

[0133] The cleaning action may include introducing an inert gas into the reaction chamber. For example, nitrogen may be pulsed into the reaction chamber for about 5 seconds to about 60 seconds. However, other inert gases, such as Ar, He, Ne, Kr and Xe and combinations thereof, may be used. The temperature and flow rate of the inert gas may be adjusted during the cleaning action of the post-deposition process to control the formation of defects on the surface of the layer of interstitial material 713. The temperature of the inert gas introduced into the reaction chamber may be in the range of about 50°C to about 200°C or in the range of about 75°C to about 150°C. As a non-limiting example, a container such as an ampoule or a heated delivery line or an inline heater for supplying the inert gas to the container may be used to maintain the temperature of the inert gas at greater than about 75°C. The reaction chamber. The elevated temperature of the inert gas during the post-deposition process may significantly reduce the formation of defects, which may be due to better removal of byproducts from the reaction chamber. In order to further reduce the growth of defects on the layer of interstitial material 713, an inert gas may be introduced into the reaction chamber at a flow rate greater than about 0.5slm. The flow rate may depend on the type of reaction chamber used, and the size and number of holes in the reaction chamber through which the inert gas may pass. As a non-limiting example, the inert gas may be introduced into the reaction chamber at a flow rate in the range of about 0.5 slm to about 100 slm.

[0134] As a non-limiting example, post-deposition processing may include the pumping action, a water exposure action, a pumping action, and a cleaning action performed in sequence. However, these actions may be performed any number of times. Water introduced into the reaction chamber during post-deposition processing may contact or react with the layer of interstitial material 713. In addition, post-deposition processing may remove unreacted gases and byproducts from the reaction chamber.

[0135] The post-deposition process may be repeated to obtain a substantially defect-free surface of the layer of interstitial material 713. As a non-limiting example, the post-deposition process may be repeated one to ten times. The total time for one post-deposition process may be in the range of about 0.5 minutes to about 6 minutes.

[0136] The conditions in the reaction chamber during the post-deposition process may be controlled to further reduce the formation of defects on the layer of spacer material 713. For example, the temperature of the reaction chamber may be controlled to reduce the formation of defects on the layer of spacer material 713. As a non-limiting example, during the post-deposition process, the temperature within the reaction chamber (i.e., the process temperature of the post-deposition process) may be increased by about 10° C. to about 50° C. relative to the temperature of the reaction chamber during the deposition of the layer of spacer material 713. During the post-deposition process, the temperature within the reaction chamber may be in a non-steady state, but higher than the temperature of the reaction chamber during the deposition of the layer of spacer material 713 (i.e., the process temperature of forming the layer of spacer material 713).

[0137] Alternatively, in other embodiments, the post-deposition process may include a pumping / cleaning cycle after forming the layer of interstitial material 713 to reduce the formation of defects. The pumping / cleaning cycle may include only a pumping action and a cleaning action. As a non-limiting example, the pumping / cleaning cycle may use an inert gas to remove volatile materials from the reaction chamber in the cleaning action. For example, the pumping / cleaning cycle may include a pumping action to at least partially remove the gas contained in the reaction chamber, followed by a cleaning action to introduce an inert gas into the reaction chamber. The pumping action may include at least partially removing excess precursor gas, catalyst, inert gas, and byproducts from the reaction chamber. The reaction chamber may be evacuated for an amount of time in the range of about 5 seconds to about 60 seconds. The cleaning action may include introducing an inert gas into the reaction chamber for a time in the range of about 5 seconds to about 60 seconds. During the cleaning action, an inert gas may be introduced into the reaction chamber at a temperature greater than about 50°C or at a temperature in the range of about 75°C to about 150°C. As a non-limiting example, the inert gas can be nitrogen and can be stored in an ampoule or passed through a delivery line maintained at a temperature of about 150°C. The inert gas can be introduced into the reaction chamber at a flow rate greater than about 0.5 slm or about 30 slm. The pumping / purge cycle can include more than one pumping action and purge action. If multiple pumping actions and purge actions are used, each pumping action and purge action can be different from each other. In addition, the conditions during each pumping action and purge action, such as time, temperature and flow rate, can change during the pumping / purge cycle. The pumping / purge cycle can be repeated continuously to remove byproducts from the reaction chamber. In general, increasing the pumping / purge cycle time during post-deposition processing can further reduce the formation of crystal growth after depositing the layer of interstitial material 713.

[0138] As a non-limiting example, the pumping / purge cycle may include a 60-second pumping action for removing volatile gases and a 60-second purge action for introducing an inert gas by 60 seconds. As another example, the pumping / purge cycle may include a 30-second pumping action and a 30-second purge action. The purge action may include pulsing an inert gas into the reaction chamber at a flow rate greater than about 0.5slm. Therefore, if the pumping / purge cycle is repeated twice in a row, the total time of the pumping / purge cycle may be in the range of about 2 to 4 minutes. As a non-limiting example, the pumping / purge purge cycle may be repeated one to eight times in a row. In addition, other post-deposition actions, such as water exposure, may be performed between multiple cycles of the pumping / purge cycle.

[0139] During the pumping / purge cycle, the temperature of the reaction chamber may be controlled or maintained at a temperature in the range of about 5°C to about 50°C higher than the deposition temperature, as previously described. As a non-limiting example, if the formation of the layer of interstitial material 713 is performed at a temperature of about 75°C, the reaction chamber may be heated to a temperature in the range of about 85°C to about 125°C or in the range of about 90°C to about 100°C to reduce the formation of defects on the layer of interstitial material 713 during the post-deposition process. However, during certain portions of the pumping / purge cycle, the temperature of the reaction chamber may also be in a non-steady state, but the temperature is higher than the deposition temperature. For example, during the pumping / purge cycle, the temperature in the reaction chamber may be increased to a desired temperature for the post-deposition process. However, after the post-deposition process begins, the temperature in the reaction chamber may not reach the desired temperature within a period of about 5 minutes to about 10 minutes. Therefore, when the temperature changes, the temperature of the reaction chamber is in a non-steady state.

[0140] Please refer to Fig.12 , a spacer etch process may be performed to remove a portion of the spacer material 713. After the spacer etch process, the remaining spacer material 713 may be referred to as a plurality of sacrificial spacers 515. In some embodiments, the spacer etch process may be an anisotropic etch process, such as an anisotropic dry etch process. In some embodiments, during the spacer etch process, an etch rate ratio of the spacer material 713 to the mandrel layer 723 may be between about 100:1 and about 5:1, between about 15:1 and about 5:1, or between about 10:1 and about 5:1. In some embodiments, during the spacer etch process, an etch rate ratio of the spacer material 713 to the word line cap layer 207 may be between about 100:1 and about 5:1, between about 15:1 and about 5:1, or between about 10:1 and about 5:1.

[0141] Please refer to Fig.12 , multiple sacrificial spacers 515 can be formed on the side (or sidewall) 723S of the mandrel layer 723. In some embodiments, the widths W1 of the multiple sacrificial spacers 515 can be substantially the same. In some embodiments, the distances D1 between consecutive sacrificial spacers 515 can be consistent. In some embodiments, the distances D1 between consecutive sacrificial spacers 515 can be different. It is worth noting that adjacent sacrificial spacers 515 may not be positioned against the same section of the mandrel layer 723.

[0142] Please refer to Fig.13, the lower layer 531 can be formed on the word line cap layer 207 and cover the mandrel layer 723 and multiple sacrificial spacers 515. The gaps between consecutive sacrificial spacers 515 can be completely filled by the lower layer 531. In some embodiments, a planarization process can be performed to remove excess material and provide a substantially flat surface for subsequent processing steps. In some embodiments, the lower layer 531 can include a self-planarizing material, such as spin-on glass or spin-on low-k dielectric material. The use of self-planarizing dielectric materials can avoid the need to perform subsequent planarization steps. In some embodiments, the lower layer 531 can be configured as an anti-reflective layer. In some embodiments, the lower layer 531 can be composed of a thin film structure of alternating layers with contrasting refractive indices. The thickness T1 of the lower layer 531 can be selected to produce destructive interference in the light beam reflected from the interface and constructive interference in the corresponding penetrating light beam. As an example, but not limited to this, for example, the lower layer 531 can include an oxide, a sulfide, a fluoride, a nitride, a selenide or a combination thereof. In some embodiments, the lower layer 531 can improve the resolution of the lithography process. In some embodiments, the manufacturing technology of the lower layer 531 can include a deposition process, for example, including chemical vapor deposition, plasma enhanced chemical vapor deposition, evaporation, spin coating or other applicable deposition processes.

[0143] Please refer to Figure 1 as well as Figures 14 to 20 In step S15 , the lower layer 531 may be recessed to expose the plurality of sacrificial spacers 515 , the plurality of sacrificial spacers 515 may be selectively removed to expose the first peripheral region PR1 , and a plurality of gate recesses GR may be formed in the first peripheral region PR1 of the substrate 101 .

[0144] Please refer to Fig.14 , a recess process may be performed to lower the upper surface of the lower layer 531. In some embodiments, the recess process may be an etching process having etching selectivity to the lower layer 531. In some embodiments, the recess process may be an isotropic etching process, such as a wet etching process. In some embodiments, during the recess process, an etching rate ratio of the lower layer 531 to the plurality of sacrificial spacers 515 may be between about 100:1 and about 5:1, between about 15:1 and about 5:1, or between about 10:1 and about 5:1. In some embodiments, during the recess process, an etching rate ratio of the lower layer 531 to the mandrel layer 723 may be between about 100:1 and about 5:1, between about 15:1 and about 5:1, or between about 10:1 and about 5:1. In some embodiments, an endpoint of the recess process may be determined by signals of the plurality of sacrificial spacers 515 and the mandrel layer 723. After the recess process, upper surfaces of the plurality of sacrificial spacers 515 and the mandrel layer 723 may be exposed.

[0145] Please refer to Fig.15 , a selective removal process may be performed to selectively remove the plurality of sacrificial spacers 515. In some embodiments, the selective removal process may be an etching process having etching selectivity to the plurality of sacrificial spacers 515. In some embodiments, the selective removal process may be an isotropic etching process, such as an isotropic wet etching process. In some embodiments, during the selective removal process, an etching rate ratio of the spacer material 713 to the lower layer 531 may be between about 100:1 and about 5:1, between about 15:1 and about 5:1, or between about 10:1 and about 5:1. In some embodiments, during the selective removal process, an etching rate ratio of the spacer material 713 to the mandrel layer 723 may be between about 100:1 and about 5:1, between about 15:1 and about 5:1, or between about 10:1 and about 5:1. In some embodiments, during the selective removal process, the etch rate ratio of the spacer material 713 to the word line capping layer 207 may be between about 100:1 and about 5:1, between about 15:1 and about 5:1, or between about 10:1 and about 5:1. After the selective removal process, a plurality of openings 533 may be formed along the lower layer 531, adjacent to the mandrel layer 723, and above the first peripheral region PR1 of the substrate 101. The plurality of openings 533 may replace positions previously occupied by the sacrificial spacers 515. Portions of the word line capping layer 207 may be exposed through the plurality of openings 533.

[0146] Please refer to Fig.16 , an etching process can be performed using the lower layer 531 and the mandrel layer 723 as masks to remove the word line cap layer 207, the first insulating material 711, and the unmasked portion of the first hard mask layer 511. In some embodiments, the etching process can be a multi-stage etching process. For example, the etching process can be a three-stage anisotropic dry etching process. The etching chemistry in each stage can be different to provide different etching selectivities.

[0147] In some embodiments, during the first stage of the etching process, the etching rate ratio of the word line capping layer 207 to the lower layer 531 may be between about 100:1 and about 5:1, between about 15:1 and about 5:1, or between about 10:1 and about 5:1. In some embodiments, during the first stage of the etching process, the etching rate ratio of the word line capping layer 207 to the mandrel layer 723 may be between about 100:1 and about 5:1, between about 15:1 and about 5:1, or between about 10:1 and about 5:1.

[0148] In some embodiments, during the second stage of the etching process, the etching rate ratio of the first insulating material 711 to the lower layer 531 may be between about 100:1 and about 5:1, between about 15:1 and about 5:1, or between about 10:1 and about 5:1. In some embodiments, during the second stage of the etching process, the etching rate ratio of the first insulating material 711 to the mandrel layer 723 may be between about 100:1 and about 5:1, between about 15:1 and about 5:1, or between about 10:1 and about 5:1.

[0149] In some embodiments, during the third stage of the etching process, the etching rate ratio of the first hard mask layer 511 to the lower layer 531 may be between about 100:1 and about 5:1, between about 15:1 and about 5:1, or between about 10:1 and about 5:1. In some embodiments, during the third stage of the etching process, the etching rate ratio of the first hard mask layer 511 to the mandrel layer 723 may be between about 100:1 and about 5:1, between about 15:1 and about 5:1, or between about 10:1 and about 5:1.

[0150] The etching process may expand the plurality of openings 533 to the word line capping layer 207 , the layer of first insulating material 711 , and the first hard mask layer 511 , so as to expose portions of the upper surface 101TS of the first peripheral region PR1 of the substrate 101 .

[0151] Please refer to Fig.17 , the lower layer 531 and the mandrel layer 723 can be removed by a removal process. In some embodiments, the removal process can be an etching process that has etching selectivity to the lower layer 531 or the mandrel layer 723. For example, the removal process can be an isotropic wet etching process. In some embodiments, the removal process can be an ashing process.

[0152] Please refer to Fig.18 A second mask layer 725 may be formed on the word line cap layer 207 and above the array region AR of the substrate 101. In some embodiments, the second mask layer 725 may be a photoresist layer. The second mask layer 725 may mask the array region AR of the substrate 101.

[0153] Please refer to Fig.19, a gate recess etching process may be performed to remove portions of the first peripheral region PR1 of the substrate 101. In some embodiments, the gate recess etching process may be an anisotropic etching process having etching selectivity to the substrate 101. For example, the gate recess etching process may be an anisotropic dry etching process. In some embodiments, during the gate recess etching process, an etching rate ratio of the substrate 101 to the word line capping layer 207 (the first insulating material 711 or the first hard mask layer 511) may be between about 100:1 and about 5:1, between about 15:1 and about 15:1, or between about 10:1 and about 5:1. After the gate recess etching process, a plurality of gate recesses GR may be formed in the first peripheral region PR1 of the substrate 101.

[0154] Please refer to Fig. 20 , an etching process may be performed using the second mask layer 725 as a mask to remove the word line capping layer 207, the first insulating material 711, and some portions of the first hard mask layer 511 that are not masked by the second mask layer 725 (i.e., the first peripheral region PR1 and the second peripheral region PR2). After the etching process, the remaining first insulating material 711 may be referred to as a word line dielectric layer 201. The word line dielectric layer 201, the plurality of word line lower conductive layers 203, the plurality of word line upper conductive layers 205, and the word line capping layer 207 are together configured into a plurality of word line structures 200. After the etching process, the second mask layer 725 may be removed. In some embodiments, the second mask layer 725 may be retained until a gate structure is formed on the first peripheral region PR1 and the second peripheral region PR2, which will be described later.

[0155] Please refer to Figure 1 as well as Figure 21 to Figure 27 In step S17 , a plurality of recessed gates 400 may be formed on the plurality of gate recesses GR, and a peripheral gate structure 300 may be formed on the second peripheral region PR2 of the substrate 101 .

[0156] Please refer to Fig.21, a layer of gate dielectric material 731 can be conformally formed on the upper surface 101TS of the first peripheral region PR1 and the second peripheral region PR2 of the substrate 101 and on the multiple gate recesses GR. In some embodiments, for example, the gate dielectric material 731 may include oxides, nitrides, oxynitrides, silicates (e.g., metal silicates), aluminates, titanates, nitrides, high-k dielectric materials, or combinations thereof. In some embodiments, for example, the manufacturing technology of the layer of gate dielectric material 731 may include a suitable deposition process, such as atomic layer deposition, chemical vapor deposition, plasma enhanced chemical vapor deposition, evaporation, chemical solution deposition, or other suitable deposition processes. In some embodiments, the manufacturing technology of the layer of gate dielectric material 731 may include oxidizing the upper surface 101TS of the first peripheral region PR1 and the second peripheral region PR2 of the substrate 101 and the multiple gate recesses GR. In some embodiments, the thickness of the layer of gate dielectric material 731 may be about to approximately In some embodiments, the gate dielectric material 731 may include a multi-layer structure. For example, the gate dielectric material 731 may be an oxide-nitride-oxide (ONO) structure. As another example, the gate dielectric material 731 may include a lower layer formed of silicon oxide and an upper layer formed of a high-k dielectric material.

[0157] Examples of high-k dielectric materials (dielectric constant greater than 7.0) include metal oxides such as hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, zirconium silicon oxynitride, tantalum oxide, titanium oxide, barium strontium titanate, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate, but are not limited thereto. For example, the high-k dielectric material may also include dopants such as lanthanum and aluminum.

[0158] Please refer to Fig.21 The layer of gate dielectric material 731 formed in the plurality of gate recesses GR may include a valley-shaped, a U-shaped, or a V-shaped cross-sectional profile.

[0159] Please refer to Fig. 22, a layer of first conductive material 733 may be conformally formed above the surface of the layer of gate dielectric material 731. When the first conductive material 733 partially fills the plurality of gate recesses GR, it forms a valley facing upward (referred to as a first valley VY1) in the plurality of gate recesses GR. In some embodiments, for example, the first conductive material 733 may include polysilicon, polycrystalline germanium, polycrystalline silicon germanium, doped polysilicon, doped polycrystalline germanium, doped polycrystalline silicon germanium, or other suitable conductive materials, but is not limited thereto. In some embodiments, the layer of first conductive material 733 may be doped with a p-type dopant or an n-type dopant. In some embodiments, the layer of first conductive material 733 formed in the plurality of gate recesses GR may include a valley-shaped, a U-shaped, or a V-shaped cross-sectional profile.

[0160] Please refer to Fig.23 , a layer of second conductive material 735 may be conformally formed on the surface of the layer of first conductive material 733. When the second conductive material 735 partially fills the first valley VY1, it forms an upward-facing valley (referred to as a second valley VY2) in the plurality of gate recesses GR. In some embodiments, for example, the second conductive material 735 may be, for example, tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbide (e.g., tantalum carbide, titanium carbide, tantalum magnesium carbide), metal nitride (e.g., titanium nitride), transition metal aluminide, or a combination thereof. In some embodiments, the layer of second conductive material 735 formed in the plurality of gate recesses GR may include a valley-shaped, a U-shaped, or a V-shaped cross-sectional profile. In some embodiments, the lower surface 735BS of the layer of second conductive material 735 (or the lower portion of the second valley VY2) may be at a vertical plane VL1, which is lower than the upper surface 101TS of the substrate 101.

[0161] Please refer to Fig.24 , a layer of upper insulating material 737 can be formed on the layer of second conductive material 735 and can completely fill the second valley VY2. In some embodiments, for example, the upper insulating material 737 can include silicon nitride, silicon oxynitride, silicon oxynitride or other applicable dielectric materials. In some embodiments, for example, the manufacturing technology of the layer of upper insulating material layer 737 can include chemical vapor deposition, plasma enhanced chemical vapor deposition or other applicable deposition processes. A planarization process, such as chemical mechanical polishing, can be performed to remove excess material and provide a substantially flat surface for subsequent processing steps. In some embodiments, the lower surface 737BS (or lower portion) of the layer of upper insulating material 737 can be at a vertical plane VL2, which is lower than the upper surface 101TS of the substrate 101.

[0162] Please refer to Fig.25A gate mask layer 727 may be formed on the insulating material 737 . In some embodiments, the gate mask layer 727 may be a photoresist layer and may include a pattern of a peripheral gate structure 300 and a plurality of recessed gates 400 .

[0163] Please refer to Fig.26 , a gate etching process may be performed to remove the insulating material 737 on the layer, the second conductive material 735 on the layer, the first conductive material 733 on the layer, and the portion of the gate dielectric material 731 not masked by the gate mask layer 727. In some embodiments, the gate etching process may be a multi-stage etching process. For example, the gate etching process may be a four-stage anisotropic dry etching process. The etching chemistry in each stage may be different to provide different etching selectivities.

[0164] Please refer to Fig.26 , the remaining gate dielectric material 731 can become a plurality of recessed gate dielectric layers 401 and a gate dielectric layer 301. For the sake of brevity, clarity and convenience of description, only one recessed gate dielectric layer 401 is described. The recessed gate dielectric layer 401 can be conformally formed on the gate recess GR and can include a U-shaped, a valley-shaped or a V-shaped cross-sectional profile. The two ends of the recessed gate dielectric layer 401 can extend in opposite directions and align with the upper surface 101TS of the substrate 101. The gate dielectric layer 301 can be formed on the second peripheral region PR2. In some embodiments, the width W2 of the recessed gate dielectric layer 401 can be less than the width W3 of the gate dielectric layer 301.

[0165] Please refer to Fig.26 , the remaining first conductive material 733 may be transformed into a plurality of recessed gate lower conductive layers 403 and a gate lower conductive layer 303. For the sake of brevity, clarity and convenience of description, only one recessed gate lower conductive layer 403 is described. The recessed gate lower conductive layer 403 may be conformally formed on the recessed gate dielectric layer 401. The recessed gate lower conductive layer 403 may present a valley-shaped, V-shaped or U-shaped cross-sectional profile. Its lower portion 403BP may be disposed in the gate recess GR to form a first valley VY1. Both ends of the recessed gate lower conductive layer 403 may protrude above the upper surface 101TS of the substrate 101. The upper portion of the upper surface 403TS of the recessed gate lower conductive layer 403 may be at a vertical plane VL3, which is higher than the upper surface 101TS of the substrate 101. The gate lower conductive layer 303 may be formed on the gate dielectric layer 301 and above the second peripheral region PR2.

[0166] Please refer to Fig.26, the remaining second conductive material 735 can be transformed into a plurality of recessed gate upper conductive layers 405 and a gate upper conductive layer 305. For the sake of brevity, clarity and convenience of description, only one recessed gate upper conductive layer 405 is described. The recessed gate upper conductive layer 405 can be conformally formed on the recessed gate lower conductive layer 403. The recessed gate upper conductive layer 405 can present a valley-shaped, V-shaped or U-shaped cross-sectional profile. Its lower portion can be arranged in the gate recess GR to form a second valley VY2. Both ends of the recessed gate upper conductive layer 405 can protrude above the upper surface 101TS of the substrate 101. The upper portion of the upper surface 405TS of the recessed gate upper conductive layer 405 can be at a vertical level VL4, which is higher than the upper surface 101TS of the substrate 101. On the contrary, the lower surface 405BS of the recessed gate upper conductive layer 405 can be at a vertical level VL1, which is lower than the upper surface 101TS of the substrate 101. The gate upper conductive layer 305 may be formed on the gate lower conductive layer 303 and over the second peripheral region PR2 .

[0167] Please refer to Fig.26 , the remaining upper insulating material 737 may become a plurality of recessed gate capping layers 407 and a gate capping layer 307. For the sake of brevity, clarity and convenience of description, only one recessed gate capping layer 407 is described. The recessed gate capping layer 407 may be formed on the recessed gate upper conductive layer 405. The lower portion 407BP of the recessed gate capping layer 407 may have an inverted triangle cross-sectional profile. The lower portion 407BP (or lower surface) of the recessed gate capping layer 407 may be at a vertical level VL2, which is lower than the upper surface 101TS of the substrate 101. The gate capping layer 307 may be formed on the gate upper conductive layer 305. The recessed gate dielectric layer 401, the recessed gate lower conductive layer 403, the recessed gate upper conductive layer 405 and the recessed gate capping layer 407 together configure the recessed gate 400. The gate dielectric layer 301 , the gate lower conductive layer 303 , the gate upper conductive layer 305 and the gate cap layer 307 together form a peripheral gate structure 300 . In some embodiments, the width W2 of the recessed gate 400 may be smaller than the width W3 of the peripheral gate structure 300 .

[0168] Compared to a gate structure having the same width W2 as the recessed gate 400 but having a planar gate dielectric layer (similar to the gate dielectric layer 301), the U-shaped cross-sectional profile of the recessed gate dielectric layer 401 can provide a longer channel length. Therefore, this can potentially alleviate or reduce leakage problems in the semiconductor device 1A including the recessed gate 400. Improved leakage control may be beneficial to miniaturization of the gate.

[0169] Please refer to Fig.26, the gate dielectric layer 301 may have a width W3 that is greater than the recessed gate dielectric layer 401. This increased width allows the surrounding gate structure 300 to have a longer channel length, making it easier to support a larger drive current. This feature may be particularly advantageous for power-related circuits. In some embodiments, the surrounding gate structure 300 and the recessed gate 400 may be provided for core circuits.

[0170] Please refer to Fig. 27 The gate mask layer 727 may be removed by ashing or other suitable semiconductor processes. It should be understood that for the sake of clarity, Fig. 27 The gate dielectric layer 301 and the recessed gate dielectric layer 401 are omitted. In some embodiments, the component density (or pattern density) of the first peripheral region PR1 may be greater than the component density of the second peripheral region PR2. The component density may be a value defined by the number of components (e.g., recessed gate 400 or surrounding gate structure 300) formed on the first peripheral region PR1 (or the second peripheral region PR2) divided by the surface area of ​​the first peripheral region PR1 (or the second peripheral region PR2 viewed from a top view). In some embodiments, from a cross-sectional perspective, a larger component density may mean a smaller distance between adjacent pairs of components. In other words, the component density of a component may be inversely proportional to the critical dimension of the component. As Fig. 27 As shown, more recessed gates 400 are shown to emphasize that the first peripheral region PR1 has a greater device density than the second peripheral region PR2. It should be understood that Fig. 27 The number of recessed gates 400 or surrounding gate structures 300 shown is merely illustrative.

[0171] Leakage issues associated with smaller gate sizes can be effectively controlled using the recessed gate dielectric layer 401. In addition, recessed gates (such as the recessed gate 400) and planar gates (such as the surrounding gate structure 300) can be manufactured simultaneously, potentially leading to reduced manufacturing costs.

[0172] Figure 28 to Figure 31 1 is a cross-sectional schematic diagram illustrating a partial process of preparing a semiconductor element 1B according to another embodiment of the present disclosure.

[0173] Please refer to Fig.28 , can be used with Figures 2 to 11 The intermediate semiconductor element can be manufactured by a procedure similar to that shown in FIG. 1 , and its description will not be repeated here. Fig.13 The process shown forms the lower layer 531 to cover the layer of spacer material 713, and will not be described again herein.

[0174] Please refer to Fig.29, a recess process can be performed to lower the upper surface of the lower layer 531. In some embodiments, the recess process can be an etching process that has etching selectivity to the lower layer 531. In some embodiments, the recess process can be an isotropic etching process, such as a wet etching process. In some embodiments, during the recess process, the etching rate ratio of the lower layer 531 to the spacer material 713 can be between about 100:1 and about 5:1, between about 15:1 and about 5:1, or between about 10:1 and about 5:1. In some embodiments, the endpoint of the recess process can be determined by a signal of the spacer material 713. After the recess process, the upper surface of the layer of spacer material 713 can be exposed. Fig.14 In comparison, the surface area of ​​the upper surface of the layer of spacer material 713 is greater than the total surface area of ​​the plurality of sacrificial spacers 515. The increase in surface area can simplify endpoint detection in this embodiment.

[0175] Please refer to Fig.30 , a selective removal process may be performed to selectively remove portions of the interstitial material 713 to form a plurality of openings 533. Fig.15 The selective removal process is performed by a similar procedure as shown, and its description will not be repeated here.

[0176] Please refer to Fig.31 The surrounding gate structure 300 and the recessed gate 400 can be used in conjunction with Figures 16 to 27 The same procedure as shown is formed, and its description will not be repeated here.

[0177] One embodiment of the present disclosure provides a method for preparing a semiconductor element, including providing a substrate including a first peripheral region and a second peripheral region; forming a core axis layer on the first peripheral region; conformally forming a layer of spacer material on the substrate and covering the core axis layer; performing a spacer etching process to transform the layer of spacer material into a plurality of sacrificial spacers on each side of the core axis layer; forming a lower layer on the substrate and covering the core axis layer and the plurality of sacrificial spacers; recessing the lower layer to expose the core axis layer and the plurality of sacrificial spacers; selectively removing the plurality of sacrificial spacers to expose the first peripheral region; forming a plurality of gate recesses in the first peripheral region; and forming a plurality of recessed gates on the plurality of gate recesses.

[0178] Due to the design of the semiconductor device disclosed herein, leakage problems associated with smaller gate sizes can be effectively controlled by utilizing the recessed gate dielectric layer 401. In addition, multiple recessed gates (such as the recessed gate 400) and multiple planar gates (such as the surrounding gate structure 300) can be manufactured simultaneously, resulting in a possible reduction in manufacturing costs.

[0179] Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and replacements may be made without departing from the spirit and scope of the present disclosure as defined in the claims. For example, many of the above processes may be implemented in different ways, and other processes or combinations thereof may be used to replace many of the above processes.

[0180] Furthermore, the scope of the present application is not limited to the specific embodiments of the processes, machines, manufactures, compositions of matter, means, methods, and steps described in the specification. A person skilled in the art can understand from the disclosure of the present disclosure that existing or future developed processes, machines, manufactures, compositions of matter, means, methods, or steps that have the same functions or achieve substantially the same results as the corresponding embodiments described herein can be used according to the present disclosure. Accordingly, such processes, machines, manufactures, compositions of matter, means, methods, or steps are included in the claims of the present application.

Claims

1. A method for preparing a semiconductor element, comprising: Providing a substrate including a first peripheral region and a second peripheral region; forming a mandrel layer on the first peripheral region; conformally forming a layer of spacer material on the substrate and covering the mandrel layer; performing a spacer etch process to convert the layer of spacer material into a plurality of sacrificial spacers on each side of the mandrel layer; forming a lower layer on the substrate and covering the mandrel layer and the plurality of sacrificial spacers; recessing the lower layer to expose the mandrel layer and the plurality of sacrificial spacers; selectively removing the plurality of sacrificial spacers to expose the first peripheral region; forming a plurality of gate recesses in the first peripheral region; and A plurality of recessed gates are formed on the plurality of gate recesses. 2 . The preparation method as claimed in claim 1 , wherein the interlayer sub-material is formed by atomic layer deposition.

3. The method of claim 2 , wherein forming the plurality of recessed gates on the plurality of gate recesses comprises: conformally forming a layer of gate dielectric material on the substrate and in the plurality of gate recesses; Forming a layer of first conductive material on the layer of gate dielectric material to form a plurality of first valleys, wherein the plurality of first valleys are respectively and correspondingly in the plurality of gate recesses; Conformally forming a layer of second conductive material on the layer of first conductive material so as to form a plurality of second valleys, wherein the plurality of second valleys are respectively and correspondingly in the plurality of gate recesses; forming a layer of top insulating material on the layer of second conductive material and completely filling the plurality of second valleys; as well as The gate dielectric material layer, the first conductive material layer, the second conductive material layer and the top insulating material layer are patterned to respectively and correspondingly form a plurality of recessed gate dielectric layers, a plurality of recessed gate bottom conductive layers, a plurality of recessed gate top conductive layers and a plurality of recessed gate capping layers, The plurality of gate dielectric layers, the plurality of recessed gate bottom conductive layers, the plurality of recessed gate top conductive layers and the plurality of recessed gate capping layers are collectively configured to form a plurality of recessed gates. 4 . The method of claim 3 , wherein the gate dielectric material layer comprises oxide, nitride, oxynitride, metal silicate, aluminate, titanate, high-k dielectric material or a combination thereof. 5 . The method of claim 4 , wherein the first conductive material layer comprises polysilicon, polycrystalline germanium, polycrystalline silicon germanium, doped polysilicon, doped polycrystalline germanium or doped polycrystalline silicon germanium. 6 . The method of claim 5 , wherein the second conductive material layer comprises tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbide, metal nitride, transition metal aluminide, or a combination thereof. 7 . The method of claim 6 , wherein the top insulating material layer comprises silicon nitride, silicon nitride oxide or silicon nitride oxide.

8. The preparation method according to claim 7, further comprising: A peripheral gate structure is formed on the second peripheral region. 9 . The manufacturing method as claimed in claim 8 , wherein the plurality of recessed gates and the surrounding gate structure are formed simultaneously. 10 . The manufacturing method as claimed in claim 9 , wherein a device density of the first peripheral region is greater than a device density of the second peripheral region. 11 . The method of claim 10 , wherein a process temperature for forming the layer of spacer material is between about 320° C. and about 530° C. 12 . The method of claim 11 , wherein the atomic layer deposition of the spacer material comprises using a silicon-containing precursor and an oxygen-containing precursor. 13 . The method of claim 12 , wherein the atomic layer deposition of the interstitial material comprises using pyridine. 14 . The preparation method as claimed in claim 13 , wherein the silicon-containing precursor comprises hexachlorodisilane, dichlorosilane, silane, disilane, trichlorosilane or a combination thereof. The preparation method as claimed in claim 14 , wherein the oxygen-containing precursor comprises water.

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