Semiconductor element with recessed gate and preparation method thereof

Abstract

The invention discloses a semiconductor element and a preparation method thereof. The semiconductor device includes a substrate, a plurality of recessed gates and a peripheral gate structure. The substrate comprises a first peripheral area and a second peripheral area. The plurality of recessed gates each include a recessed gate dielectric layer disposed inwardly in the first peripheral region and including a U-shaped cross-sectional profile; a recessed gate bottom conductive layer disposed on the recessed gate dielectric layer and including a valley-shaped cross-sectional profile so as to form a first valley; a recessed gate top conductive layer conformally disposed on the first valley of the recessed gate bottom conductive layer; and a recessed gate cap layer disposed on the recessed gate top conductive layer. The peripheral gate structure is disposed on the second peripheral region. The element density of the first peripheral region is greater than the element density of the second peripheral region.

Description

Technical Field

[0001] This application claims priority to U.S. patent application No. 18 / 239,874 (i.e., the priority date is "August 30, 2023"), the contents of which are incorporated herein by reference in their entirety.

[0002] The present disclosure relates to a semiconductor element and a manufacturing method thereof, and in particular to a semiconductor element with a recessed gate and a manufacturing method thereof. Background Art

[0003] Semiconductor components are widely used in various electronic products, such as personal computers, mobile phones, digital cameras and other electronic devices. In order to meet the growing demand for computing power, the size of semiconductor components continues to shrink. However, various problems arise in the process of shrinking size, and these problems continue to increase. Therefore, there are still challenges in improving quality, yield, performance and reliability, and reducing complexity.

[0004] The above “prior art” description is only to provide background technology, and does not admit that the above “prior art” description reveals the subject matter of the present disclosure, does not constitute the prior art of the present disclosure, and any description of the above “prior art” should not be regarded as any part of this case. Summary of the invention

[0005] One aspect of the present disclosure provides a semiconductor element, which includes a substrate, a plurality of recessed gates, and a peripheral gate structure. The substrate includes a first peripheral region and a second peripheral region. The plurality of recessed gates respectively include a recessed gate dielectric layer, which is disposed inwardly in the first peripheral region and includes a U-shaped cross-sectional profile; a recessed gate bottom conductive layer, which is disposed on the recessed gate dielectric layer and includes a valley-shaped cross-sectional profile to form a first concave valley; a recessed gate top conductive layer, which is conformally disposed on the first concave valley of the recessed gate bottom conductive layer; and a recessed gate cap layer, which is disposed on the recessed gate top conductive layer. The peripheral gate structure is disposed on the second peripheral region. The component density of the first peripheral region is greater than the component density of the second peripheral region.

[0006] Another aspect of the present disclosure provides a method for preparing a semiconductor element, including: providing a substrate, including a first peripheral region and a second peripheral region; forming a bottom hard mask layer on the substrate; forming a mandrel layer on the bottom hard mask layer and above the first peripheral region; conformally forming a spacer material layer on the bottom hard mask layer and covering the mandrel layer; performing a spacer etching process to convert the spacer material layer into a plurality of sacrificial spacers on both sides of the mandrel layer; forming a bottom layer on the bottom hard mask layer and covering the mandrel layer and the plurality of sacrificial spacers; recessing the bottom layer to expose the mandrel layer and the plurality of sacrificial spacers; selectively removing the plurality of sacrificial spacers to form a plurality of openings exposing the bottom hard mask layer; deepening the plurality of openings to expose the first peripheral region; forming a plurality of gate recesses in the first peripheral region; and forming a plurality of recessed gates on the plurality of gate recesses.

[0007] Another aspect of the present disclosure provides a method for preparing a semiconductor element, including providing a substrate, the substrate including a first peripheral region and a second peripheral region; forming a bottom hard mask layer on the substrate; forming a core axis layer on the bottom hard mask layer and above the first peripheral region; conformally forming a gap material layer on the bottom hard mask layer and covering the core axis layer; forming a bottom layer on the bottom hard mask layer and covering the gap material layer; recessing the bottom layer to expose the gap material layer; selectively removing the gap material layer on the core axis layer to form a plurality of openings exposing the bottom hard mask layer; deepening the plurality of openings to expose the first peripheral region; forming a plurality of gate digs in the first peripheral region; and forming a plurality of recessed gates on the plurality of gate digs.

[0008] Due to the design of the semiconductor device disclosed herein, the use of a recessed gate dielectric layer can effectively control leakage problems associated with smaller gate sizes. In addition, a recessed gate (e.g., a recessed gate) and a planar gate (e.g., a peripheral gate structure) can be prepared at the same time, thereby reducing preparation costs.

[0009] The above has been a fairly broad overview of the technical features and advantages of the present disclosure, so that the detailed description of the present disclosure below can be better understood. Other technical features and advantages that constitute the subject matter of the claims of the present disclosure will be described below. It should be understood by those with ordinary knowledge in the technical field to which the present disclosure belongs that the concepts and specific embodiments disclosed below can be used to modify or design other structures or processes to achieve the same purpose as the present disclosure. It should also be understood by those with ordinary knowledge in the technical field to which the present disclosure belongs that such equivalent constructions cannot depart from the spirit and scope of the present disclosure as defined by the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] A more complete understanding of the disclosure of this application will be obtained by referring to the detailed description and claims in conjunction with the drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of various features may be arbitrarily increased or decreased for clarity of discussion.

[0011] Figure 1 is a flow chart illustrating a method for preparing a semiconductor element according to an embodiment of the present disclosure;

[0012] Figures 2 to 24 is a cross-sectional view illustrating a partial preparation process of a semiconductor element according to an embodiment of the present disclosure;

[0013] Figures 25 to 30 is a close-up cross-sectional view illustrating a partial manufacturing process of a semiconductor element according to an embodiment of the present disclosure;

[0014] Fig.31 is a cross-sectional view illustrating a partial manufacturing process of a semiconductor element according to an embodiment of the present disclosure; and

[0015] Figure 32 to Figure 35 is a cross-sectional view illustrating a process for preparing a semiconductor element according to another embodiment of the present disclosure.

[0016] The reference numerals are described as follows:

[0017] 1A: Semiconductor components

[0018] 1B: Semiconductor components

[0019] 10: Preparation method

[0020] 101: Base

[0021] 101TS: Top

[0022] 103-1: Character Line Ditch

[0023] 103-3: Character Line Ditch

[0024] 107: Isolation layer

[0025] 200: Character line structure

[0026] 201: word line dielectric layer

[0027] 203: word line bottom conductive layer

[0028] 205: word line top conductive layer

[0029] 207: Character line cover

[0030] 300: Peripheral gate structure

[0031] 301: Gate dielectric layer

[0032] 303: Gate bottom conductive layer

[0033] 305: Gate top conductive layer

[0034] 307: Gate capping layer

[0035] 400: Recessed gate

[0036] 401: Recessed gate dielectric layer

[0037] 403: Recessed gate bottom conductive layer

[0038] 403BP: Bottom

[0039] 403TS: Top

[0040] 405: Recessed gate top conductive layer

[0041] 405BS: bottom surface

[0042] 405TS: Top

[0043] 407: Recessed gate cap

[0044] 407BP: Bottom

[0045] 511: First hard mask layer

[0046] 513: The First Pattern

[0047] 515: Sacrificial Interstitial

[0048] 517: Bottom hard mask layer

[0049] 531: Bottom

[0050] 533: Opening

[0051] 535: First auxiliary layer

[0052] 711: First insulation material

[0053] 713: Interstitial Materials

[0054] 721: First mask layer

[0055] 723: Mandrel layer

[0056] 723S: Side

[0057] 725: Second mask layer

[0058] 727: Gate mask layer

[0059] 731: Gate dielectric materials

[0060] 733: First conductive material

[0061] 735: Second conductive material

[0062] 735BS: bottom surface

[0063] 737: Top layer insulation material

[0064] AR: Array Area

[0065] D1: Distance

[0066] GR: Gate Digging

[0067] PR1: First peripheral area

[0068] PR2: Second peripheral area

[0069] S11: Steps

[0070] S13: Steps

[0071] S15: Steps

[0072] S17: Steps

[0073] T1: Thickness

[0074] VL1: Vertical Horizontal

[0075] VL2: Vertical Horizontal

[0076] VL3: Vertical Horizontal

[0077] VL4: Vertical Horizontal

[0078] VY1: First valley

[0079] VY2: Second valley

[0080] W1: Width

[0081] W2: Width

[0082] W3: Width

[0083] Z: Direction DETAILED DESCRIPTION

[0084] The following disclosure provides many different embodiments, or examples, for implementing the different features of the provided claims. In order to simplify the present disclosure, specific examples of components and arrangements are described below. Of course, these are just examples and are not intended to be limiting. For example, in the following description, the formation of a first feature on or above a second feature may include an embodiment in which the first and second features are directly in contact with each other, and may also include an embodiment in which additional features can be formed between the first and second features, so that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numbers and / or letters in various embodiments. This repetition is for simplicity and clarity, and does not itself determine the relationship between the various embodiments and / or configurations discussed.

[0085] In addition, spatially relative terms, such as "lower", "below", "below", "upper", "above", etc., may be used herein to describe the relationship of one element or feature to another element or feature shown in the figure for ease of description. Spatially relative terms are intended to include different orientations of the element in use or operation, as well as the orientation depicted in the figure. The element may have other orientations (rotated 90 degrees or other orientations), and the spatially relative descriptors used herein may be interpreted accordingly.

[0086] It will be understood that when an element or layer is referred to as being “connected to” or “coupled to” another element or layer, it can be directly connected or coupled to the other element or layer or intervening elements or layers may be present.

[0087] It should be understood that although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. Unless otherwise specified, these terms are only used to distinguish one element from another element. Thus, for example, the first element, first component, or first part discussed below may be referred to as the second element, second component, or second part without departing from the teachings of the present disclosure.

[0088] Unless the context indicates otherwise, terms such as "same," "equal," "planar," or "coplanar" used herein in reference to orientation, layout, position, shape, size, quantity, or other measures do not necessarily mean exactly the same orientation, layout, position, shape, size, quantity, or other measures, but rather, nearly the same orientation, layout, position, shape, size, quantity, or other measures within an acceptable range of variation that may occur, such as due to the manufacturing process. The term "substantially" may be used herein to reflect this meaning. For example, items described as "substantially the same," "substantially equal," or "substantially planar" may be exactly the same, equal, or planar, or they may be the same, equal, or planar within an acceptable range of variation, such as due to the manufacturing process.

[0089] In the present disclosure, semiconductor elements generally refer to elements that can function by utilizing semiconductor characteristics, and optoelectronic elements, light-emitting display elements, semiconductor circuits and electronic elements are all included in the category of semiconductor elements.

[0090] It should be noted that in the description of the present disclosure, above (or over) corresponds to the direction of the arrow of direction Z, and below (or under) corresponds to the opposite direction of the arrow of direction Z.

[0091] It should be noted that in the description of the present disclosure, the terms "to form", "formed" and "formation" may refer to and include any method of creating, constructing, patterning, implanting or depositing elements, dopants or materials. Examples of formation methods may include, but are not limited to, atomic layer deposition, chemical vapor deposition, physical vapor deposition, sputtering, co-sputtering, spin coating, diffusion, deposition, growth, implantation, optical lithography, dry etching and wet etching.

[0092] It should be noted that, in the description of the present disclosure, the functions or steps indicated here may occur in a different order than that indicated in the figures. For example, two figures shown in succession may in fact be performed simultaneously in essence, or may sometimes be performed in a reverse order, depending on the functions or steps involved.

[0093] Figure 1 1 is a flowchart illustrating a method 10 for manufacturing a semiconductor device 1A according to an embodiment of the present disclosure. Figures 2 to 24 1 is a cross-sectional view illustrating a partial manufacturing process of a semiconductor device 1A according to an embodiment of the present disclosure. Figures 25 to 30 1 is a close-up cross-sectional view illustrating a partial manufacturing process of a semiconductor device 1A according to an embodiment of the present disclosure. Fig.31 1 is a cross-sectional view illustrating a partial manufacturing process of a semiconductor device 1A according to an embodiment of the present disclosure.

[0094] Reference Figures 1 to 11 In step S11, a substrate 101 including an array region AR, a first peripheral region PR1 and a second peripheral region PR2 may be provided, a plurality of word line trenches 103-1, 103-3 may be formed in the array region AR, and a plurality of word line structures 200 may be formed in the plurality of word line trenches 103-1, 103-3.

[0095] Reference Figure 2, in some embodiments, the array region AR and the first peripheral region PR1 may be adjacent to each other. For example, in a top view (not shown), the array region AR may be surrounded by the first peripheral region PR1. In some embodiments, the first peripheral region PR1 and the second peripheral region PR2 may be adjacent to each other. For example, in a top view (not shown), the first peripheral region PR1 may be surrounded by the second peripheral region PR2. In some embodiments, the first peripheral region PR1 and the second peripheral region PR2 may be separated from each other.

[0096] It should be noted that the array area AR may include a portion of the substrate 101 and a space above the portion of the substrate 101. Disposing an element on the array area AR means that the element is disposed on the top surface of the portion of the substrate 101. Describing an element as being disposed in the array area AR means that the element is disposed in the portion of the substrate 101; however, the top surface of the element may be flush with the top surface of the portion of the substrate 101. Describing an element as being disposed above the array area AR means that the element is disposed above the top surface of the portion of the substrate 101. Therefore, the first peripheral region PR1 and the second peripheral region PR2 may include the other portion of the substrate 101 and the space above the other portion of the substrate 101, respectively.

[0097] Reference Figure 2 The substrate 101 may be a bulk semiconductor substrate. The bulk semiconductor substrate may include, for example, an elementary semiconductor or a compound semiconductor. The elementary semiconductor may be silicon or germanium, and the compound semiconductor may be silicon germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, or other III-V compound semiconductors or II-VI compound semiconductors.

[0098] Reference Figure 2 , an isolation layer 107 may be formed in the substrate 101. For example, the isolation layer 107 may be formed in the array region AR of the substrate 101. A series of deposition processes may be performed to deposit a pad oxide layer (not shown) and a pad nitride layer (not shown) on the substrate 101. A photolithography process and a subsequent etching process, such as an anisotropic dry etching process, may be performed to form a trench that penetrates the pad oxide layer, the pad nitride layer and extends to the substrate 101. An insulating material may be deposited into the trench, and a planarization process, such as chemical mechanical polishing, may be subsequently performed until the top surface 101TS of the substrate 101 is exposed to remove excess filling material, provide a substantially flat surface for subsequent process steps, and simultaneously form the isolation layer 107. The insulating material may be, for example, silicon oxide or other suitable insulating materials.

[0099] Reference Figure 3, a first hard mask layer 511 may be formed on the substrate 101. In some embodiments, the first hard mask layer 511 may include a material having an etching selectivity to the substrate 101. In some embodiments, the first hard mask layer 511 may include a material having an etching selectivity to the substrate 101 and the isolation layer 107. In some embodiments, the first hard mask layer 511 may include, for example, silicon nitride, boron nitride, silicon boron nitride, phosphorus boron nitride, or boron carbon silicon nitride. In some embodiments, the manufacturing technology of the first hard mask layer 511 may include, for example, atomic layer deposition, chemical vapor deposition, or other applicable deposition processes.

[0100] Reference Figure 3 , a first mask layer 721 may be formed on the first hard mask layer 511 . In some embodiments, the first mask layer 721 may be a photoresist layer and may include a pattern of a plurality of word line structures 200 .

[0101] Reference Figure 4 , an etching process may be performed to remove a portion of the first hard mask layer 511. In some embodiments, during the etching process, an etching rate ratio of the first hard mask layer 511 to the substrate 101 may be between about 100:1 and about 2:1, between about 15:1 and about 2:1, or between about 10:1 and about 2:1. In some embodiments, during the etching process, an etching rate ratio of the first hard mask layer 511 to the isolation layer 107 may be between about 100:1 and about 2:1, between about 15:1 and about 2:1, or between about 10:1 and about 2:1. The pattern of the first mask layer 721 may be transferred to the first hard mask layer 511 and may be referred to as a first pattern 513. Portions of the isolation layer 107 and portions of the substrate 101 may be exposed through the first pattern 513. After the etching process, the first mask layer 721 may be removed by ashing or other applicable semiconductor processes.

[0102] Reference Figure 5 , a trench etching process may be performed using the first hard mask layer 511 as a mask to remove portions of the isolation layer 107 and portions of the substrate 101 and simultaneously form a plurality of word line trenches 103-1, 103-3. In some embodiments, the plurality of word line trenches 103-1 formed in the substrate 101 may be shallower than the plurality of word line trenches 103-3 formed in the isolation layer 107. In some embodiments, during the trench etching process, an etching rate ratio of the isolation layer 107 to the first hard mask layer 511 may be between about 100:1 and about 5:1, between about 15:1 and about 5:1, or between about 10:1 and about 5:1. In some embodiments, during the trench etching process, an etching rate ratio of the substrate 101 to the first hard mask layer 511 may be between about 80:1 and about 5:1, between about 10:1 and about 5:1, or between about 8:1 and about 5:1.

[0103] Reference Figure 6 , the first insulating material 711 layer may be conformally formed on the first hard mask layer 511 and in the plurality of word line trenches 103-1, 103-3. In the plurality of word line trenches 103-1, 103-3, the first insulating material 711 layer may have a U-shaped cross-sectional profile. In some embodiments, the first insulating material 711 layer may have a thickness in a range of about 1 nanometer to about 7 nanometers, including about 1 nanometer, about 2 nanometers, about 3 nanometers, about 4 nanometers, about 5 nanometers, about 6 nanometers, or about 7 nanometers.

[0104] In some embodiments, the manufacturing technique of the first insulating material 711 layer may include a thermal oxidation process. For example, the first insulating material 711 layer may be formed by oxidizing the surfaces of the plurality of word line trenches 103-1, 103-3. In some embodiments, the manufacturing technique of the first insulating material 711 layer may include a deposition process such as chemical vapor deposition or atomic layer deposition. The first insulating material 711 may include a high-k material, an oxide, a nitride, an oxynitride, or a combination thereof. In some embodiments, after depositing a pad polysilicon layer (not shown for clarity), the manufacturing technique of the first insulating material 711 layer may include free radical oxidation of the pad polysilicon layer. In some embodiments, after forming a pad silicon nitride layer (not shown for clarity), the manufacturing technique of the first insulating material 711 layer may include free radical oxidation of the pad silicon nitride layer.

[0105] In some embodiments, the high-k dielectric material may include a hafnium-containing material. For example, the hafnium-containing material may be hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, or a combination thereof. In some embodiments, the high-k dielectric material may be, for example, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, zirconium silicon oxynitride, aluminum oxide, or a combination thereof.

[0106] Reference Figure 7 , a plurality of word line bottom conductive layers 203 may be formed in the plurality of word line trenches 103-1, 103-3 respectively and correspondingly. For example, a conductive material (not shown) may be formed to fill the plurality of word line trenches 103-1, 103-3. An etching back process may then be performed to partially remove the conductive material formed in the plurality of word line trenches 103-1, 103-3 and simultaneously form a plurality of word line bottom conductive layers 203. In some embodiments, the conductive material may be a work function material, such as titanium, titanium nitride, silicon, silicon germanium, or a combination thereof. It should be noted that the term "work function" refers to the bulk chemical potential of a material (such as a metal) relative to a vacuum degree.

[0107] For example, in the present embodiment, the conductive material is titanium nitride, and its manufacturing technology may include chemical vapor deposition. In some embodiments, the deposition of the conductive material may include a source gas introduction step, a first purge step, a reactant flow step, and a second purge step. The source gas introduction step, the first purge step, the reactant flow step, and the second purge step may be referred to as a cycle. Multiple cycles may be performed to fill multiple word line trenches 103-1, 103-3.

[0108] In detail, Figure 6 The intermediate semiconductor element shown can be loaded into a reaction chamber. In the source gas introduction step, a source gas containing a precursor and a reactant can be introduced into the reaction chamber containing the intermediate semiconductor element. The precursor and the reactant can diffuse through the boundary layer and reach the surface of the intermediate semiconductor element. The precursor and the reactant can be adsorbed on the above surface and then migrate. The adsorbed precursor and the adsorbed reactant can react on the above surface and form solid by-products. The solid by-products can form crystal nuclei on the above surface. These nuclei can grow into islands, and the islands can merge into a continuous film on the above surface. In the first purification step, a purification gas such as argon can be injected into the reaction chamber to remove gaseous by-products, unreacted precursors and unreacted reactants.

[0109] In the reactant flow step, the reactants can be completely introduced into the reaction chamber to convert the continuous film into a titanium nitride layer. In the second purge step, a purge gas such as argon can be injected into the reaction chamber to remove gaseous byproducts and unreacted reactants.

[0110] In some embodiments, when the conductive material is deposited using chemical vapor deposition, plasma may be used. For example, the source of the plasma may be argon, hydrogen, or a combination thereof.

[0111] For example, the precursor may be titanium tetrachloride. The reactant may be ammonia. Due to the incomplete reaction of titanium tetrachloride and ammonia, titanium tetrachloride and ammonia may react on the surface and form a titanium nitride layer, which includes high chloride contamination. The ammonia in the reactant flow step can reduce the chlorine content of the titanium nitride layer.

[0112] In some embodiments, the etching rate ratio of the wordline bottom conductive layer 203 to the first insulating material 711 during the etch-back process may be between about 100:1 and about 5:1, between about 15:1 and about 5:1, or between about 10:1 and about 5:1.

[0113] Reference Figure 8, a plurality of word line top conductive layers 205 may be formed in the plurality of word line trenches 103-1, 103-3. In some embodiments, the plurality of word line portion top conductive layers 205 may include, for example, polysilicon, polycrystalline germanium, polycrystalline silicon germanium, doped polysilicon, doped polycrystalline germanium, doped polycrystalline silicon germanium, or a combination thereof. In some embodiments, the plurality of word line top conductive layers 205 may be doped with a p-type dopant or an n-type dopant. In some embodiments, a conductive material such as polysilicon, polycrystalline germanium, or polycrystalline silicon germanium may be deposited into the plurality of word line trenches 103-1, 103-3. An etch-back process may then be performed to remove a portion of the conductive layer to form the plurality of word line top conductive layers 205. In some embodiments, a dopant may be added during the deposition of the conductive material. In some embodiments, the dopant may be doped using an implantation process after the etch-back process.

[0114] The term "p-type dopant" refers to an impurity that is added to an intrinsic semiconductor material to produce a valence electron defect. In silicon-containing semiconductor materials, examples of p-type dopants include, but are not limited to, boron, aluminum, gallium, or indium. The term "n-type dopant" refers to an impurity that is added to an intrinsic semiconductor material to provide free electrons to the intrinsic semiconductor material. In silicon-containing materials, examples of n-type dopants include, but are not limited to, antimony, arsenic, or phosphorus.

[0115] refer to Fig. 9 , a word line capping layer 207 may be formed on the first hard mask layer 511 to completely fill the plurality of word line trenches 103-1, 103-3. In some embodiments, the word line capping layer 207 may include, for example, silicon nitride, silicon oxynitride, silicon nitride oxide, or other applicable dielectric materials. In some embodiments, the word line capping layer 207 may be fabricated using, for example, chemical vapor deposition, plasma enhanced chemical vapor deposition, or other applicable deposition processes. A planarization process such as chemical mechanical polishing may be performed to remove excess material and provide a substantially flat surface for subsequent process steps.

[0116] It should be noted that in the present disclosure, silicon oxynitride refers to a substance containing silicon, nitrogen and oxygen, wherein the proportion of oxygen is greater than the proportion of nitrogen. Silicon nitride oxide refers to a substance containing silicon, oxygen and nitrogen, wherein the proportion of nitrogen is greater than the proportion of oxygen.

[0117] refer to Fig. 9 The second mask layer 725 may be formed on the word line cap layer 207 and above the array region AR of the substrate 101. In some embodiments, the second mask layer 725 may be a photoresist layer. The second mask layer 725 may mask the array region AR of the substrate 101.

[0118] Reference Fig.10, the etching process can be performed using the second mask layer 725 as a mask to remove the word line capping layer 207, the first insulating material 711 layer, and the first hard mask layer 511 that are not masked by the second mask layer 725 (i.e., the first peripheral region PR1 and the second peripheral region PR2). After the etching process is completed, the remaining first insulating material 711 can be referred to as the word line dielectric layer 201. The word line dielectric layer 201, the plurality of word line bottom conductive layers 203, the plurality of word line top conductive layers 205, and the word line capping layer 207 together constitute a plurality of word line structures 200.

[0119] Reference Fig.11 After the etching process, the second mask layer 725 may be removed by an ashing process or other applicable semiconductor processes.

[0120] Reference Figure 1 and Figures 12 to 17 In step S13, a bottom hard mask layer 517 may be formed on the substrate 101, a first auxiliary layer 535 may be formed on the bottom hard mask layer 517, a mandrel layer 723 may be formed on the first auxiliary layer 535 and above the first peripheral region PR1, a plurality of sacrificial spacers 515 may be formed on the side 723S of the mandrel layer 723, and a bottom layer 531 may be formed on the first auxiliary layer 535.

[0121] refer to Fig.12 , a bottom hard mask layer 517 may be formed on the substrate 101 to cover the first peripheral region PR1, the second peripheral region PR2, and the word line capping layer 207. A planarization process such as chemical mechanical polishing may be performed to provide a substantially flat surface for subsequent process steps. In some embodiments, the bottom hard mask layer 517 may include a material having an etch selectivity to the word line capping layer 207.

[0122] In some embodiments, the bottom hard mask layer 517 may include materials such as boron nitride, silicon boron nitride, phosphorus boron nitride, or boron carbon silicon nitride. In some embodiments, the manufacturing technology of the bottom hard mask layer 517 may include, for example, atomic layer deposition, chemical vapor deposition, or other applicable deposition processes. In some embodiments, the manufacturing technology of the bottom hard mask layer 517 may include a film forming process and a treatment process. In detail, during the film forming process, a first precursor (which may be a boron-based precursor) may be introduced onto the substrate 101 to form a boron-based layer. Subsequently, during the treatment process, a second precursor (which may be a nitrogen-based precursor) may be introduced to react with the boron-based layer to convert the boron-based layer into the bottom hard mask layer 517.

[0123] In some embodiments, the first precursor may be, for example, diborane, borazine, or an alkyl substituted derivative of borazine. In some embodiments, the first precursor may be introduced at a flow rate of about 5 sccm to about 50 slm (standard liters per minute) or about 10 sccm to about 1 slm. In some embodiments, the first precursor may be introduced by a diluent gas such as nitrogen, hydrogen, argon, or a combination thereof. The introduction flow rate of the diluent gas may be between about 5 sccm and about 50 slm or between about 1 slm and about 10 slm.

[0124] In some embodiments, the film forming process may be performed without plasma assistance. In this case, the substrate temperature of the film forming process may be between about 100° C. and about 1000° C. For example, the substrate temperature of the film forming process may be between about 300° C. and about 500° C. The process pressure of the film forming process may be between about 10 mTorr and about 760 Torr. For example, the process pressure of the film forming process may be between about 2 Torr and about 10 Torr.

[0125] In some embodiments, the film forming process may be performed in the presence of plasma. In this case, the substrate temperature of the film forming process may be between about 100°C and about 1000°C. For example, the substrate temperature of the film forming process may be between about 300°C and about 500°C. The process pressure of the film forming process may be between about 10mTorr and about 760Torr. For example, the process pressure of the film forming process may be between about 2 Torr and about 10 Torr. The plasma may be generated by a radio frequency power of 2W to 5000W.

[0126] In some embodiments, the second precursor may be ammonia or hydrazine, etc. In some embodiments, the introduction flow rate of the second precursor may be between about 5 sccm and about 50 slm or between about 10 sccm and about 1 slm.

[0127] In some embodiments, the oxygen-based precursor may be introduced into the process along with the second precursor. For example, the oxygen-based precursor may be oxygen, nitric oxide, nitrous oxide, carbon dioxide, or water.

[0128] In some embodiments, a silicon-based precursor may be introduced into the process together with the second precursor. The silicon-based precursor may be silane, trisilane, trimethylsilane, or silazane (eg, hexamethylcyclotrisilazane), among others.

[0129] In some embodiments, a phosphorus-based precursor may be introduced into the process together with a second precursor. The phosphorus-based precursor may be phosphine or the like.

[0130] In some embodiments, an oxygen-based precursor, a silicon-based precursor, or a phosphorus-based precursor may be introduced during processing along with a second precursor.

[0131] In some embodiments, the curing process may be assisted by a plasma process, a UV curing process, a thermal annealing process, or a combination thereof.

[0132] When the treatment is performed with the aid of a plasma process, the plasma of the plasma process may be generated by radio frequency power. In some embodiments, the radio frequency power may be between about 2 W and about 5000 W, with a single low frequency between about 100 kHz and about 1 MHz. In some embodiments, the radio frequency power may be between about 30 W and about 1000 W at a single high frequency greater than about 13.6 MHz. In this case, the substrate temperature of the treatment process may be between about 20° C. and about 1000° C. The pressure of the treatment process may be between about 10 mTorr and about 760 Torr.

[0133] When the treatment is performed with the assistance of an ultraviolet curing process, in this case, the substrate temperature of the treatment process can be between about 20°C and about 1000°C. The pressure of the treatment process can be between about 10mTorr and about 760Torr. The ultraviolet curing can be provided by any ultraviolet source, such as a mercury microwave arc lamp, a pulsed xenon flash lamp, or an array of high-efficiency ultraviolet light emitting diodes. The wavelength of the ultraviolet source can be between about 170 nanometers and about 400 nanometers. The ultraviolet source can provide a photon energy between about 0.5eV and about 10eV, or between about 1eV and about 6eV. The assistance of the ultraviolet curing process can remove hydrogen from the first hard mask layer 511. Since hydrogen may diffuse to other areas of the semiconductor element 1A and may reduce the reliability of the semiconductor element 1A, removing hydrogen with the assistance of the ultraviolet curing process can improve the reliability of the semiconductor element 1A. In addition, the ultraviolet curing process can increase the density of the bottom hard mask layer 517.

[0134] When the treatment is performed with the aid of a thermal annealing process, in this case, the substrate temperature of the treatment process may be between about 20° C. and about 1000° C. The pressure of the treatment process may be between about 10 mTorr and about 760 Torr.

[0135] In some embodiments, the bottom hard mask layer 517 may be a carbon film. The term "carbon film" is used herein to describe a material whose mass is primarily carbon, whose structure is primarily defined by carbon atoms, or whose physical and chemical properties are primarily determined by the carbon content. The term "carbon film" is intended to exclude materials that are mixtures or compounds that include only carbon, such as dielectric materials such as carbon-doped silicon oxynitride, carbon-doped silicon oxide, or carbon-doped polysilicon. In some embodiments, the bottom hard mask layer 517 may be composed of carbon and hydrogen. In some embodiments, the bottom hard mask layer 517 may be composed of carbon, hydrogen, and oxygen. In some embodiments, the bottom hard mask layer 517 may be composed of carbon, hydrogen, and fluorine.

[0136] In some embodiments, the carbon film may be deposited by a process that includes introducing a process gas mixture consisting of one or more hydrocarbon compounds into a process chamber. The chemical formula of the hydrocarbon compound is C x H y , wherein x ranges from 2 to 4, and y ranges from 2 to 10. For example, the hydrocarbon compound may be propylene, propyne, propane, butane, butene, butadiene, or acetylene, or a combination thereof.

[0137] Reference Fig.13 , the first auxiliary layer 535 can be formed on the bottom hard mask layer 517. In some embodiments, the first auxiliary layer 535 can be an anti-reflective coating layer, such as a bottom anti-reflective coating layer. In some embodiments, the first auxiliary layer 535 can include a polymer-based material, etc., and can include a chromophore to further absorb ultraviolet or deep ultraviolet light. In some embodiments, the first auxiliary layer 535 can include silicon oxynitride and silicon nitride, etc. In some embodiments, the manufacturing technology of the first auxiliary layer 535 can include, for example, spin coating, chemical vapor deposition or other applicable deposition processes.

[0138] Reference Fig.14 , the mandrel layer 723 can be formed on the first auxiliary layer 535 and above the first peripheral region PR1. In some embodiments, the mandrel layer 723 can be a photoresist layer. The mandrel layer 723 can be a photoresist layer in some embodiments, having a pattern of multiple gate recesses GR (described later). The layer can be composed of a plurality of segments, and depending on the specific embodiment, the segments can have different widths or substantially the same width. Similarly, the distance between adjacent pairs of segments can remain the same or vary.

[0139] Reference Fig.15 , a layer of interstitial material 713 may be conformally formed on the first auxiliary layer 535, and may cover the mandrel layer 723. In some embodiments, the interstitial material 713 may be silicon oxide or the like. In some embodiments, the manufacturing technology of the interstitial material 713 layer may include a deposition process such as an atomic layer deposition process. Generally, the atomic layer deposition process may alternately provide two (or more) different source gases to the process object (i.e., the first auxiliary layer 535) one by one under predetermined process conditions, thereby causing chemical species to be adsorbed onto the process object at the single atomic level and deposited onto the process object through surface reactions. For example, the first and second source gases are alternately provided to the process object so that they flow along the surface of the process object, thereby causing the molecules contained in the first source gas to be adsorbed onto the surface, and the molecules contained in the second source gas react with the adsorbed molecules from the first source gas to form a thin film with a thickness of a single molecular layer. Repeating the above process steps may form a high-quality thin film on the process object.

[0140] In some embodiments, the spacer material 713 layer may be formed by an atomic layer deposition process at a temperature of about 320° C. to about 530° C. by sequentially exposing the first auxiliary layer 535 to a gaseous silicon-containing precursor (e.g., tetrachlorosilane) and an oxygen-containing precursor (e.g., water). In some embodiments, forming the spacer material 713 layer may include: Fig.14 The intermediate semiconductor element shown in the reaction chamber is exposed to a silicon-containing precursor to achieve chemical adsorption of silicon species on the intermediate semiconductor element. In theory, the chemical adsorption will form a uniform silicon-containing monolayer of one atom or molecule thickness over the entire exposed substrate. Excess silicon-containing precursor is exhausted from the reaction chamber, and the intermediate semiconductor element can be exposed to an oxygen-containing precursor. The oxygen-containing precursor chemically adsorbs on the silicon-containing monolayer to form an oxygen-containing monolayer. Excess oxygen-containing precursor is then exhausted from the reaction chamber. The above steps are repeated to form silicon dioxide of the desired thickness. The silicon-containing and oxygen-containing precursors can be mixed with a catalyst (such as pyridine) to accelerate the deposition rate while reducing the reaction temperature (about 50°C to about 100°C). Depositing the interstitial material 713 layer at a low temperature can be advantageous in many cases because the substrate or the material deposited on the substrate is heat sensitive.

[0141] In detail, in the first reaction of the atomic layer deposition process, a silicon-containing precursor can be introduced into the reaction chamber along with pyridine and chemically adsorbed to the substrate surface. In some embodiments, the silicon-containing precursor can include silicon hydride or silane, such as hexachlorodisilane, dichlorosilane, silane, disilane, trisilane or any other silicon-containing compound suitable as a precursor. The silicon-containing precursor provided at this stage can be selected based on the number of available binding sites and the physical size of the chemically adsorbed species (including ligands), thereby determining the amount of silicon-containing precursor that can be bound to the substrate surface. The chemically adsorbed silicon-containing monolayer formed by the silicon-containing precursor is self-terminating, and its surface does not react with the remaining chemicals used to form the silicon-containing monolayer.

[0142] Subsequent pulses of inert gas can purge the reaction chamber of excess silicon-containing precursor, particularly silicon-containing precursor that is not chemically adsorbed to the surface of the substrate. The inert gas can be nitrogen, argon, helium, neon, krypton, or xenon. Purging the reaction chamber can also remove volatile byproducts produced during the atomic layer deposition process. In some embodiments, the inert gas can be nitrogen. For example, the inert gas can be introduced into the reaction chamber for about 10 seconds. After purging, the reaction chamber can be evacuated or "pumped" to remove gases, such as excess silicon-containing precursor or volatile byproducts. For example, the silicon-containing precursor can be purged from the reaction chamber by the following techniques, including but not limited to: contacting the substrate and / or the silicon-containing monolayer with an inert gas, and / or reducing the pressure in the reaction chamber to below the deposition pressure of the silicon-containing precursor to reduce the concentration of the silicon-containing precursor in contact with the substrate and / or the chemically adsorbed species. In addition, purging can also include contacting the silicon-containing monolayer with any substance that can desorb chemically adsorbed byproducts and reduce the concentration of the silicon-containing precursor before introducing the oxygen-containing precursor. The appropriate amount of purge to remove silicon-containing precursors and volatile byproducts can be determined experimentally. The pumping and purge sequence can be repeated multiple times. The pumping and purge sequence can start or end with a pumping or purge. During the pumping and purge process, the time and parameters such as gas flow, pressure and temperature can be changed. Reducing the purge and / or pumping time can increase the amount of silicon oxide deposited per minute (angstroms / minute) and can increase the growth rate of the spacer material 713 layer.

[0143] The second reaction of the atomic layer deposition process can introduce an oxygen-containing precursor and pyridine into the reaction chamber to form an oxygen-containing monolayer on the silicon-containing monolayer. The oxygen-containing monolayer and the silicon-containing monolayer react to form a silicon oxide film (i.e., the interstitial material 713 layer). Reaction byproducts and excess oxygen-containing precursors can be removed from the reaction chamber by the above-mentioned pumping and purging sequence. For example, an inert gas can be introduced into the reaction chamber for purification. Typically, the precursor pulse time is between 0.5 seconds and 30 seconds. The interstitial material 713 layer can be deposited on the first auxiliary layer 535 by continuous or repeated cycles, wherein each cycle deposits a monolayer of silicon oxide. The thickness of the interstitial material 713 layer can be achieved by exposing the intermediate semiconductor element to multiple repeated cycles.

[0144] Reference Fig.16, a gapper etching process may be performed to remove a portion of the gapper material 713. After the gapper etching process, the remaining gapper material 713 may be referred to as a plurality of sacrificial gappers 515. In some embodiments, the gapper etching process may be an anisotropic etching process, such as an anisotropic dry etching process. In some embodiments, during the gapper etching process, an etch rate ratio of the gapper material 713 to the mandrel layer 723 may be between about 100:1 and about 5:1, between about 15:1 and about 5:1, or between about 10:1 and about 5:1. In some embodiments, during the gapper etching process, an etch rate ratio of the gapper material 713 to the first auxiliary layer 535 may be between about 100:1 and about 5:1, between about 15:1 and about 5:1, or between about 10:1 and about 5:1.

[0145] Reference Fig.16 , multiple sacrificial spacers 515 may be formed on the side (or sidewall) 723S of the mandrel layer 723. In some embodiments, the widths W1 of the multiple sacrificial spacers 515 may be substantially the same. In some embodiments, the distances D1 between consecutive sacrificial spacers 515 may be consistent. In some embodiments, the distances D1 between consecutive sacrificial spacers 515 may be different. It is worth noting that adjacent sacrificial spacers 515 may not be disposed on the same section of the mandrel layer 723.

[0146] Reference Fig.17 , a bottom layer 531 may be formed on the first auxiliary layer 535 and cover the mandrel layer 723 and a plurality of sacrificial spacers 515. The gaps between consecutive sacrificial spacers 515 may be completely filled by the bottom layer 531. In some embodiments, a planarization process may be performed to remove excess material and provide a substantially flat surface for subsequent process steps. In some embodiments, the bottom layer 531 may include a self-planarizing material, such as spin-on glass or spin-on low-k dielectric material. The use of a self-planarizing dielectric material may avoid performing a subsequent planarization step. In some embodiments, the bottom layer 531 may be configured as an anti-reflective layer. In some embodiments, the bottom layer 531 may include a thin film structure having alternating layers of contrasting refractive indices. The thickness T1 of the bottom layer 531 may be selected so as to produce destructive interference in a light beam reflected from an interface and constructive interference in a corresponding transmitted light beam. For example, the bottom layer 531 may include, for example, an oxide, a sulfide, a fluoride, a nitride, a selenide, or a combination thereof, but this is by no means limiting. In some embodiments, the bottom layer 531 may improve the resolution of the lithography process. In some embodiments, the manufacturing technology of the bottom layer 531 may include a deposition process, such as chemical vapor deposition, plasma enhanced chemical vapor deposition, evaporation, spin coating or other applicable deposition processes.

[0147] Reference Figure 1 and Figures 18 to 24In step S15 , the bottom layer 531 may be recessed to expose the plurality of sacrificial spacers 515 , the plurality of sacrificial spacers 515 may be selectively removed to expose the first peripheral region PR1 , and a plurality of gate trenches GR may be formed in the first peripheral region PR1 of the substrate 101 .

[0148] Reference Fig.18 , a recessing process may be performed to lower the top surface of the bottom layer 531. In some embodiments, the recessing process may be an etching process having etching selectivity to the bottom layer 531. In some embodiments, the recessing process may be an isotropic etching process, such as a wet etching process. In some embodiments, during the recessing process, an etching rate ratio of the bottom layer 531 to the plurality of sacrificial spacers 515 may be between about 100:1 and about 5:1, between about 15:1 and about 5:1, or between about 10:1 and about 5:1. In some embodiments, during the recessing process, an etching rate ratio of the bottom layer 531 to the mandrel layer 723 may be between about 100:1 and about 5:1, between about 15:1 and about 5:1, or between about 10:1 and about 5:1. In some embodiments, an end point of the recessing process may be determined by signals of the plurality of sacrificial spacers 515 and the mandrel layer 723. After the recessing process, the top surfaces of the plurality of sacrificial spacers 515 and the mandrel layer 723 may be exposed.

[0149] Reference Fig.19 , a selective removal process may be performed to selectively remove the plurality of sacrificial spacers 515. In some embodiments, the selective removal process may be an etching process having etching selectivity to the plurality of sacrificial spacers 515. In some embodiments, the selective removal process may be an isotropic etching process, such as an isotropic wet etching process. In some embodiments, during the selective removal process, an etching rate ratio of the spacer material 713 to the bottom layer 531 may be between about 100:1 and about 5:1, between about 15:1 and about 5:1, or between about 10:1 and about 5:1. In some embodiments, during the selective removal process, an etching rate ratio of the spacer material 713 to the mandrel layer 723 may be between about 100:1 and about 5:1, between about 15:1 and about 5:1, or between about 10:1 and about 5:1. In some embodiments, during the selective removal process, an etching rate ratio of the spacer material 713 to the first auxiliary layer 535 may be between about 100:1 and about 5:1, between about 15:1 and about 5:1, or between about 10:1 and about 5:1. After the selective removal process, a plurality of openings 533 may be formed along the bottom layer 531, adjacent to the mandrel layer 723, and over the first peripheral region PR1 of the substrate 101. The plurality of openings 533 may replace positions previously occupied by the sacrificial spacers 515. Portions of the first auxiliary layer 535 may be exposed through the plurality of openings 533.

[0150] Reference Fig. 20 and Fig.21 , an etching process can be performed using the bottom layer 531 and the mandrel layer 723 as masks to remove the unmasked portions of the first auxiliary layer 535 and the bottom hard mask layer 517. In some embodiments, the etching process can be a multi-stage etching process. For example, the etching process can be a two-stage anisotropic dry etching process. The etching chemical composition of each stage can be different to provide different etching selectivities.

[0151] Reference Fig. 20 In some embodiments, in the first stage of the etching process, the etching rate ratio of the first auxiliary layer 535 to the bottom layer 531 may be between about 100:1 and about 5:1, between about 15:1 and about 5:1, or between about 10:1 and about 5:1. In some embodiments, in the first stage of the etching process, the etching rate ratio of the first auxiliary layer 535 to the mandrel layer 723 may be between about 100:1 and about 5:1, between about 15:1 and about 5:1, or between about 10:1 and about 5:1.

[0152] Reference Fig.21 In some embodiments, in the second stage of the etching process, the etching rate ratio of the bottom hard mask layer 517 to the bottom layer 531 may be between about 100:1 and about 5:1, between about 15:1 and about 5:1, or between about 10:1 and about 5:1. In some embodiments, in the second stage of the etching process, the etching rate ratio of the bottom hard mask layer 517 to the mandrel layer 723 may be between about 100:1 and about 5:1, between about 15:1 and about 5:1, or between about 10:1 and about 5:1.

[0153] The etching process may expand the plurality of openings 533 to the first auxiliary layer 535 and the bottom hard mask layer 517 , thereby exposing a portion of the top surface 101TS of the first peripheral region PR1 of the substrate 101 .

[0154] Reference Fig. 22 , the bottom layer 531, the mandrel layer 723, and the first auxiliary layer 535 can be removed by a removal process. In some embodiments, the removal process can be an etching process having etching selectivity to the bottom layer 531 or the mandrel layer 723. For example, the removal process can be an isotropic wet etching process. In some embodiments, the removal process can be an ashing process.

[0155] Reference Fig.23, a gate-recess etching process may be performed to remove a portion of the first peripheral region PR1 of the substrate 101. In some embodiments, the gate-recess etching process may be an anisotropic etching process having etching selectivity to the substrate 101. For example, the gate-recess etching process may be an anisotropic dry etching process. In some embodiments, during the gate-recess etching process, an etching rate ratio of the substrate 101 to the bottom hard mask layer 517 may be between about 100:1 and about 5:1, between about 15:1 and about 5:1, or between about 10:1 and about 5:1. After the gate-recess etching process, a plurality of gate recesses GR may be formed in the first peripheral region PR1 of the substrate 101. Another advantage of using the bottom hard mask layer 517 is that it facilitates operating the etching selectivity during the gate-recess etching process.

[0156] Reference Fig.24 , the bottom hard mask layer 517 can be removed to expose the first peripheral region PR1 , the second peripheral region PR2 , the plurality of gate trenches GR and the word line capping layer 207 .

[0157] Reference Figure 1 and Figures 25 to 31 In step S17 , a plurality of recessed gates 400 may be formed on the plurality of gate recesses GR, and a peripheral gate structure 300 may be formed on the second peripheral region PR2 of the substrate 101 .

[0158] Reference Fig.25 , a gate dielectric material 731 layer may be conformally formed on the top surface 101TS of the first peripheral region PR1 and the second peripheral region PR2 of the substrate 101 and on the plurality of gate digs GR. In some embodiments, the gate dielectric material 731 may include, for example, oxides, nitrides, oxynitrides, silicates (e.g., metal silicates), aluminates, titanates, nitrides, high-k dielectric materials, or combinations thereof. In some embodiments, the manufacturing technique of the gate dielectric material 731 layer may include a suitable deposition process, such as atomic layer deposition, chemical vapor deposition, plasma enhanced chemical vapor deposition, evaporation, chemical solution deposition, or other suitable deposition processes. In some embodiments, the manufacturing technique of the gate dielectric material 731 layer may include oxidizing the top surface 101TS of the first peripheral region PR1 and the second peripheral region PR2 of the substrate 101 and the plurality of gate digs GR. In some embodiments, the thickness of the gate dielectric material 731 layer may be between about 10 angstroms and about 50 angstroms. In some embodiments, the gate dielectric material 731 layer may include a multilayer structure. For example, the gate dielectric material 731 layer may be an oxide-nitride-oxide (ONO) structure. For example, the gate dielectric material 731 layer may include a bottom layer including silicon oxide and a top layer including a high-k dielectric material.

[0159] High-k dielectric materials (dielectric constant greater than 7.0) include, but are not limited to, metal oxides such as hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, zirconium silicon oxynitride, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, scandium tantalum lead oxide, and lead zinc niobate. High-k dielectric materials may further include dopants such as lanthanum and aluminum.

[0160] Reference Fig.25 , the gate dielectric material 731 layer formed within the plurality of gate trenches GR may include a valley-shaped, U-shaped, or V-shaped cross-sectional profile.

[0161] Reference Fig.26 , a first conductive material 733 layer may be conformally formed on the surface of the gate dielectric material 731 layer. When the first conductive material 733 partially fills the plurality of gate digs GR, an upward valley (referred to as a first valley VY1) may be formed in the plurality of gate digs GR. In some embodiments, the first conductive material 733 may include, for example, polysilicon, polycrystalline germanium, polycrystalline silicon germanium, doped polysilicon, doped polycrystalline germanium, doped polycrystalline silicon germanium, or other suitable conductive materials. In some embodiments, the first conductive material 733 layer may be doped with a p-type dopant or an n-type dopant. In some embodiments, the first conductive material 733 layer formed in the plurality of gate digs GR may include a valley-shaped, U-shaped, or V-shaped cross-sectional profile.

[0162] Reference Fig. 27 , a second conductive material 735 layer may be conformally formed on the surface of the first conductive material 733 layer. When the second conductive material 735 partially fills the first valley VY1, an upward valley (referred to as a second valley VY2) is formed in the plurality of gate diggings GR. In some embodiments, the second conductive material 735 may be, for example, tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides (such as tantalum carbide, titanium carbide, tantalum magnesium carbide), metal nitrides (such as titanium nitride), transition metal aluminides, or combinations thereof. In some embodiments, the second conductive material 735 layer formed in the plurality of gate diggings GR may include a valley-shaped, U-shaped, or V-shaped cross-sectional profile. In some embodiments, the bottom surface 735BS of the second conductive material layer 735 (or the bottom portion of the second valley VY2) may be at a vertical level VL1 that is lower than the top surface 101TS of the substrate 101.

[0163] Reference Fig.28, a top insulating material 737 layer may be formed on the second conductive material 735 layer, and the second valley VY2 may be completely filled. In some embodiments, the top insulating material 737 may include silicon nitride, silicon oxynitride, silicon nitride oxide, or other applicable dielectric materials. In some embodiments, the manufacturing technology of the top insulating material 737 layer may include, for example, chemical vapor deposition, plasma enhanced chemical vapor deposition, or other applicable deposition processes. A planarization process such as chemical mechanical polishing may be performed to remove excess material and provide a substantially flat surface for subsequent process steps. In some embodiments, the bottom surface 737BS (or bottom portion) of the top insulating material 737 layer may have a vertical level VL2 lower than the top surface 101TS of the substrate 101.

[0164] Reference Fig.29 A gate mask layer 727 may be formed on the top insulating material layer 737. In some embodiments, the gate mask layer 727 may be a photoresist layer and may include a pattern of a peripheral gate structure 300 and a plurality of recessed gates 400.

[0165] Reference Fig.30 , a gate etching process may be performed to remove portions of the top insulating material 737 layer, the second conductive material 735 layer, the first conductive material 733 layer, and the gate dielectric material 731 layer that are not masked by the gate mask layer 727. In some embodiments, the gate etching process may be a multi-stage etching process. For example, the gate etching process may be a four-stage anisotropic dry etching process. The etching chemical composition of each stage may be different to provide different etching selectivities.

[0166] refer to Fig.30 , the remaining gate dielectric material 731 can become a plurality of recessed gate dielectric layers 401 and a gate dielectric layer 301. For the sake of brevity, clarity and convenience of description, only one recessed gate dielectric layer 401 is described here. The recessed gate dielectric layer 401 can be conformally formed on the gate trench GR and may include a U-shaped, valley-shaped or V-shaped cross-sectional profile. The two ends of the recessed gate dielectric layer 401 may extend in opposite directions and be aligned with the top surface 101TS of the substrate 101. The gate dielectric layer 301 may be formed on the second peripheral region PR2. In some embodiments, the width W2 of the recessed gate dielectric layer 401 may be less than the width W3 of the gate dielectric layer 301.

[0167] Reference Fig.30, the remaining first conductive material 733 layer can be transformed into a plurality of recessed gate bottom conductive layers 403 and gate bottom conductive layers 303. For the sake of brevity, clarity and convenience of description, only one recessed gate bottom conductive layer 403 is described here. The recessed gate bottom conductive layer 403 can be conformally formed on the recessed gate dielectric layer 401. The cross-sectional profile of the recessed gate bottom conductive layer 403 can be valley-shaped, V-shaped or U-shaped. Its bottom 403BP can be disposed in the gate digging GR to form a first valley VY1. Both ends of the recessed gate bottom conductive layer 403 can protrude from the top surface 101TS of the substrate 101. The top portion of the top surface 403TS of the recessed gate bottom conductive layer 403 can be located on a vertical level VL3, which is elevated compared to the top surface 101TS of the substrate 101. The gate bottom conductive layer 303 can be formed on the gate dielectric layer 301 and located above the second peripheral region PR2.

[0168] Reference Fig.30 , the remaining second conductive material 735 can become a plurality of recessed gate top conductive layers 405 and gate top conductive layer 305. For the sake of brevity, clarity and convenience of description, only one recessed gate top conductive layer 405 is described here. The recessed gate top conductive layer 405 can be conformally formed on the recessed gate bottom conductive layer 403. The cross-sectional profile of the recessed gate top conductive layer 405 can be valley-shaped, V-shaped or U-shaped. Its bottom can be located in the gate digging GR to form a second recessed valley VY2. Both ends of the recessed gate top conductive layer 405 can protrude from the top surface 101TS of the substrate 101. The top portion of the top surface 405TS of the recessed gate top conductive layer 405 can be located on the vertical level VL4, which is at a higher position than the top surface 101TS of the substrate 101. On the contrary, the bottom surface 405BS of the recessed gate top conductive layer 405 can be located at the vertical level VL1, which is lower than the top surface 101TS of the substrate 101. The gate top conductive layer 305 may be formed on the gate bottom conductive layer 303 and over the second peripheral region PR2 .

[0169] Reference Fig.30, the remaining top insulating material 737 can become a plurality of recessed gate capping layers 407 and a gate capping layer 307. For the sake of brevity, clarity and convenience of description, only one recessed gate capping layer 407 is described here. The recessed gate capping layer 407 can be formed on the recessed gate top conductive layer 405. The bottom 407BP of the recessed gate capping layer 407 can have an inverted triangular cross-sectional profile. The bottom 407BP (or bottom surface) of the recessed gate capping layer 407 can be located at a vertical level VL2 lower than the top surface 101TS of the substrate 101. The gate capping layer 307 can be formed on the gate top conductive layer 305. The recessed gate dielectric layer 401, the recessed gate bottom conductive layer 403, the recessed gate top conductive layer 405 and the recessed gate capping layer 407 together constitute the recessed gate 400. The gate dielectric layer 301 , the gate bottom conductive layer 303 , the gate top conductive layer 305 and the gate cap layer 307 together constitute the peripheral gate structure 300 . In some embodiments, the width W2 of the recessed gate 400 may be smaller than the width W3 of the peripheral gate structure 300 .

[0170] Compared to a gate structure having the same width W2 as the recessed gate 400 but having a planar gate dielectric layer (similar to the gate dielectric layer 301), the U-shaped cross-sectional profile of the recessed gate dielectric layer 401 can provide a longer channel length. Therefore, this can alleviate or reduce the leakage problem in the semiconductor device 1A including the recessed gate 400. The improvement of leakage control can be beneficial to the miniaturization of the gate.

[0171] Reference Fig.30 , the width W3 of the gate dielectric layer 301 may be greater than the width of the recessed gate dielectric layer 401. The increase in width allows the peripheral gate structure 300 to have a longer channel length, making it suitable for supporting a larger drive current. This feature is particularly advantageous for power-related circuits. In some embodiments, the peripheral gate structure 300 and the recessed gate 400 can be used for core circuits.

[0172] Reference Fig.31 , the gate mask layer 727 can be removed by ashing or other applicable semiconductor processes. It should be noted that for the sake of clarity, Fig.31The gate dielectric layer 301 and the recessed gate dielectric layer 401 are omitted. In some embodiments, the component density (or pattern density) of the first peripheral region PR1 may be greater than the component density of the second peripheral region PR2. The component density may be a value defined by the components (e.g., the recessed gate 400 or the peripheral gate structure 300) formed on the first peripheral region PR1 (or the second peripheral region PR2) divided by the surface area of ​​the first peripheral region PR1 (or the second peripheral region PR2 in a top view). In some embodiments, in a cross-sectional view, a greater component density means a smaller distance between a pair of adjacent components. In other words, the component density of a component may be inversely proportional to the critical dimension of the component. As Fig.31 As shown, more recessed gates 400 are shown to emphasize that the device density of the first peripheral region PR1 is greater than that of the second peripheral region PR2. Fig.31 The number of recessed gates 400 or peripheral gate structures 300 shown is for reference only.

[0173] The use of the recessed gate dielectric layer 401 can effectively control leakage problems associated with smaller gate sizes. In addition, the recessed gate (such as the recessed gate 400) and the planar gate (such as the peripheral gate structure 300) can be fabricated simultaneously, thereby reducing fabrication costs.

[0174] Figure 32 to Figure 35 1 is a cross-sectional view illustrating a process of manufacturing a semiconductor element 1B according to another embodiment of the present disclosure.

[0175] Reference Fig.32 , you can use something like Figures 2 to 15 The steps shown in the figure are used to prepare the intermediate semiconductor element, which will not be described in detail here. The bottom layer 531 can be made similar to Fig.17 The steps shown are formed to cover the spacer material 713 layer, and its description is not repeated here.

[0176] Reference Fig.33 , a recess process can be performed to lower the top surface of the bottom layer 531. In some embodiments, the recess process can be an etching process that has etching selectivity to the bottom layer 531. In some embodiments, the recess process can be an isotropic etching process, such as a wet etching process. In some embodiments, during the recess process, the etching rate ratio of the bottom layer 531 to the spacer material 713 can be between about 100:1 and about 5:1, between about 15:1 and about 5:1, or between about 10:1 and about 5:1. In some embodiments, the endpoint of the recess process can be determined by the signal of the spacer material 713. After the recess process, the top surface of the spacer material 713 layer can be exposed. Fig.18In comparison, the surface area of ​​the top surface of the spacer material 713 layer is greater than the total surface area of ​​the plurality of sacrificial spacers 515. The increase in surface area can simplify endpoint detection in this embodiment.

[0177] Reference Fig.34 , a selective removal process may be performed to selectively remove portions of the interstitial material 713, thereby forming a plurality of openings 533. In some embodiments, the selective removal process may be an anisotropic etching process, such as an anisotropic dry etching process. The selective removal process may be performed using a process similar to Fig.15 The procedures shown will not be repeated here.

[0178] Reference Fig.35 The formation process of the peripheral gate structure 300 and the recessed gate 400 may be similar to Figures 20 to 31 As shown, no further description is given here.

[0179] One aspect of the present disclosure provides a semiconductor element, which includes a substrate, a plurality of recessed gates, and a peripheral gate structure. The substrate includes a first peripheral region and a second peripheral region. The plurality of recessed gates respectively include a recessed gate dielectric layer, which is disposed inwardly in the first peripheral region and includes a U-shaped cross-sectional profile; a recessed gate bottom conductive layer, which is disposed on the recessed gate dielectric layer and includes a valley-shaped cross-sectional profile to form a first concave valley; a recessed gate top conductive layer, which is conformally disposed on the first concave valley of the recessed gate bottom conductive layer; and a recessed gate cap layer, which is disposed on the recessed gate top conductive layer. The peripheral gate structure is disposed on the second peripheral region. The component density of the first peripheral region is greater than the component density of the second peripheral region.

[0180] Another aspect of the present disclosure provides a method for preparing a semiconductor element, including: providing a substrate, including a first peripheral region and a second peripheral region; forming a bottom hard mask layer on the substrate; forming a mandrel layer on the bottom hard mask layer and above the first peripheral region; conformally forming a spacer material layer on the bottom hard mask layer and covering the mandrel layer; performing a spacer etching process to convert the spacer material layer into a plurality of sacrificial spacers on both sides of the mandrel layer; forming a bottom layer on the bottom hard mask layer and covering the mandrel layer and the plurality of sacrificial spacers; recessing the bottom layer to expose the mandrel layer and the plurality of sacrificial spacers; selectively removing the plurality of sacrificial spacers to form a plurality of openings exposing the bottom hard mask layer; deepening the plurality of openings to expose the first peripheral region; forming a plurality of gate recesses in the first peripheral region; and forming a plurality of recessed gates on the plurality of gate recesses.

[0181] Another aspect of the present disclosure provides a method for preparing a semiconductor element, including providing a substrate, the substrate including a first peripheral region and a second peripheral region; forming a bottom hard mask layer on the substrate; forming a core axis layer on the bottom hard mask layer and above the first peripheral region; conformally forming a gap material layer on the bottom hard mask layer and covering the core axis layer; forming a bottom layer on the bottom hard mask layer and covering the gap material layer; recessing the bottom layer to expose the gap material layer; selectively removing the gap material layer on the core axis layer to form a plurality of openings exposing the bottom hard mask layer; deepening the plurality of openings to expose the first peripheral region; forming a plurality of gate digs in the first peripheral region; and forming a plurality of recessed gates on the plurality of gate digs.

[0182] Due to the design of the semiconductor device disclosed in the present invention, the leakage problem associated with the smaller gate size can be effectively controlled by using the recessed gate dielectric layer 401. In addition, the recessed gate (such as the recessed gate 400) and the planar gate (such as the peripheral gate structure 300) can be prepared at the same time, thereby reducing the preparation cost.

[0183] Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and replacements can be made without departing from the spirit and scope of the present disclosure defined by the claims. For example, many of the above processes can be implemented in different ways, and other processes, or combinations thereof, can be used to replace many of the above processes.

[0184] Furthermore, the scope of the present application is not limited to the specific embodiments of the processes, machines, manufactures, compositions of matter, means, methods, and steps described in the specification. A person skilled in the art can understand from the disclosure of the present disclosure that existing or future developed processes, machines, manufactures, compositions of matter, means, methods, or steps that have the same functions or achieve substantially the same results as the corresponding embodiments described herein can be used according to the present disclosure. Accordingly, such processes, machines, manufactures, compositions of matter, means, methods, or steps are included in the claims of the present application.

Claims

1. A semiconductor element, comprising: A substrate, comprising a first peripheral region and a second peripheral region; A plurality of recessed gates respectively include: a recessed gate dielectric layer disposed inwardly of the first peripheral region and comprising a U-shaped cross-sectional profile; a recessed gate bottom conductive layer disposed on the recessed gate dielectric layer and comprising a valley-shaped cross-sectional profile, thereby forming a first recessed valley; a recessed gate top conductive layer, conformally disposed on the first valley of the recessed gate bottom conductive layer; and A recessed gate cap layer is disposed on the recessed gate top conductive layer; and a peripheral gate structure is disposed on the second peripheral region; The component density of the first peripheral area is greater than the component density of the second peripheral area.

2. The semiconductor device as claimed in claim 1, wherein the peripheral gate structure comprises: a gate dielectric layer disposed on the second peripheral region; A gate bottom conductive layer is disposed on the gate dielectric layer; a gate top conductive layer disposed on the gate bottom conductive layer; and A gate cap layer is disposed on the gate top conductive layer. 3 . The semiconductor device as claimed in claim 2 , wherein a width of the gate dielectric layer is greater than a width of the recessed gate dielectric layer. 4 . The semiconductor device as claimed in claim 3 , wherein the gate dielectric layer and the recessed gate dielectric layer comprise the same material. 5 . The semiconductor device as claimed in claim 3 , wherein the gate bottom conductive layer and the recessed gate bottom conductive layer comprise the same material. 6 . The semiconductor device as claimed in claim 3 , wherein the gate top conductive layer and the recessed gate top conductive layer comprise the same material. 7 . The semiconductor device as claimed in claim 3 , wherein the gate cap layer and the recessed gate cap layer comprise the same material.

8. A method for preparing a semiconductor element, comprising: Providing a substrate, including a first peripheral region and a second peripheral region; forming a bottom hard mask layer on the substrate; forming a mandrel layer on the bottom hard mask layer and above the first peripheral region; Conformally forming a spacer material layer on the bottom hard mask layer and covering the mandrel layer; Performing a spacer etching process to convert the spacer material layer into a plurality of sacrificial spacers on both sides of the mandrel layer; forming a bottom layer on the bottom hard mask layer and covering the mandrel layer and the plurality of sacrificial spacers; recessing the bottom layer to expose the mandrel layer and the plurality of sacrificial spacers; selectively removing the plurality of sacrificial spacers to form a plurality of openings exposing the bottom hard mask layer; deepening the plurality of openings to expose the first peripheral area; forming a plurality of gate digs in the first peripheral region; as well as A plurality of recessed gates are formed on the plurality of gate digs. 9 . The method for manufacturing a semiconductor device as claimed in claim 8 , wherein the manufacturing technology of the spacer material layer comprises atomic layer deposition. 10 . The method for manufacturing a semiconductor device as claimed in claim 9 , further comprising removing the bottom hard mask layer before forming the plurality of recessed gates, thereby exposing the first peripheral region and the second peripheral region of the substrate.

11. The method for manufacturing a semiconductor device as claimed in claim 10, wherein forming the plurality of recessed gates on the plurality of gate diggings comprises: Conformally forming a gate dielectric material layer on the substrate and within the plurality of gates; Forming a first conductive material layer on the gate dielectric material layer, thereby forming a plurality of first valleys in the plurality of gate digs respectively; Conformally forming a second conductive material layer on the first conductive material layer, thereby correspondingly forming a plurality of second valleys in the plurality of gate holes; forming a top insulating material layer on the second conductive material layer to completely fill the plurality of second valleys; as well as The gate dielectric material layer, the first conductive material layer, the second conductive material layer and the top insulating material layer are patterned to respectively form a plurality of recessed gate dielectric layers, a plurality of recessed gate bottom conductive layers, a plurality of recessed gate top conductive layers and a plurality of recessed gate capping layers in the plurality of gate excavations to together constitute a plurality of recessed gates. 12 . The method for preparing a semiconductor device as claimed in claim 11 , wherein the gate dielectric material comprises oxide, nitride, oxynitride, metal silicate, aluminate, titanate, nitride, high-k dielectric material or a combination thereof. 13 . The method for manufacturing a semiconductor device as claimed in claim 12 , wherein the first conductive material comprises polysilicon, polysilicon germanium, polysilicon germanium, doped polysilicon, doped polycrystalline germanium or doped polysilicon germanium.

14. The method for preparing a semiconductor device as claimed in claim 13, wherein the second conductive material comprises tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbide, metal nitride, transition metal aluminide or a combination thereof. 15 . The method for manufacturing a semiconductor device as claimed in claim 14 , wherein the top insulating material comprises silicon nitride, silicon nitride oxide or silicon nitride oxide. 16 . The method for manufacturing a semiconductor device as claimed in claim 15 , further comprising forming a peripheral gate structure on the second peripheral region. 17 . The method for manufacturing a semiconductor device as claimed in claim 16 , wherein the plurality of recessed gates and the peripheral gate structure are formed simultaneously. 18 . The method for manufacturing a semiconductor device as claimed in claim 17 , wherein a device density in the first peripheral region is greater than a device density in the second peripheral region. 19 . The method for fabricating a semiconductor device as claimed in claim 18 , wherein a temperature of forming the spacer material is between about 320° C. and about 530° C. 20 . The method for fabricating a semiconductor device as claimed in claim 19 , wherein the atomic layer deposition for forming the spacer material layer comprises a silicon-containing precursor and an oxygen-containing precursor.

Images