Semiconductor material etching method and etching machine control method

Abstract

The embodiment of the invention discloses an etching method of a semiconductor material and a control method of an etching machine, and the etching method comprises the steps: providing a semiconductor layer, and carrying out the first etching and the second etching of the semiconductor layer to form a recess; the first etching and the second etching at least comprise the step of bombarding the semiconductor layer by using plasma bias; the plasma bias power in the second etching is smaller than the plasma bias power in the first etching; performing an etching post-processing step, including introducing oxygen-containing gas into the recess to oxidize at least part of the inner wall of the recess; and forming a barrier layer on the inner wall of the recess.

Description

Technical Field

[0001] The disclosed embodiments relate to the field of semiconductor technology, and more particularly to a method for etching semiconductor materials and a method for controlling an etching machine. Background Art

[0002] In the field of semiconductor manufacturing technology, especially in the field of 2.5D & 3D packaging, it is usually necessary to apply Through Silicon Via (TSV), which is a technology that interconnects chips by making vertical conductions between chips, between chips and wafers, and between wafers. Through Silicon Via technology has the advantages of short interconnection distance and high integration. It can maximize the stacking density of chips in three-dimensional space, improve chip performance, reduce power consumption, and reduce size. Therefore, it is widely used in 2.5D / 3D ICs. When making through silicon vias, it is necessary to etch holes in the silicon layer. When the aspect ratio of the opening becomes higher and higher, how to improve the etching morphology of the deep hole becomes an urgent problem to be solved. Summary of the invention

[0003] In view of this, embodiments of the present disclosure provide a semiconductor material etching method and an etching machine control method.

[0004] According to some aspects of the embodiments of the present disclosure, a method for etching a semiconductor material is provided, comprising:

[0005] Providing a semiconductor layer, performing a first etching and a second etching on the semiconductor layer to form a recess; the first etching and the second etching at least include bombarding the semiconductor layer with a plasma bias; the plasma bias power in the second etching is less than the plasma bias power in the first etching;

[0006] Performing a post-etching treatment step, including introducing a gas containing an oxygen element into the cavity to oxidize at least a portion of an inner wall of the cavity;

[0007] A barrier layer is formed on the inner wall of the recess.

[0008] In some embodiments, the first etching cycle includes: performing the first etching and the second etching in sequence, and the etching method further includes:

[0009] When the number of times the first etching cycle is executed is less than the target number, executing the post-etching processing step and forming the barrier layer until the number of times the first etching cycle is executed is equal to the target number;

[0010] When the number of times the first etching cycle is executed is equal to the target number, the etching method is stopped.

[0011] In some embodiments, the etching method further comprises:

[0012] performing the first etching cycle on the semiconductor layer to form a first recess;

[0013] performing the post-etching processing step on the first cavity to form a first barrier layer on an inner wall of the first cavity;

[0014] Performing the first etching cycle on the semiconductor layer for the next time to remove the first barrier layer on the sidewall of the first recess and form a second recess below the first recess, wherein the second recess is connected to the first recess;

[0015] The post-etching treatment step is performed on the first cavity and the second cavity, and a second barrier layer is formed on the sidewall of the first cavity and the inner wall of the second cavity.

[0016] In some embodiments, a protrusion is provided at a connection between the first cavity and the second cavity, and the protrusion protrudes at least part of a side wall of the second cavity in a first direction; the first direction intersects with a thickness direction of the semiconductor layer; and the step of performing post-etching processing further includes:

[0017] oxidizing at least a portion of the protrusion to form an oxide layer;

[0018] The etching method further comprises:

[0019] When the first etching cycle is performed to form a third recess below the second recess, the second barrier layer and the oxide layer are etched away.

[0020] In some embodiments, when the first etching cycle is performed to the target number of times, the recess penetrates through the semiconductor layer.

[0021] In some embodiments, the method of determining the target number of times includes:

[0022] When or after executing the first etching cycle, spectrum information of the gas atmosphere in which the semiconductor layer is located is acquired; and according to the spectrum information, it is determined that the number of times the first etching cycle is executed is equal to the target number.

[0023] According to some aspects of the embodiments of the present disclosure, a control method for an etching machine is provided, the control method comprising:

[0024] transferring a wafer including a semiconductor layer to an etching chamber;

[0025] Performing a first etching and a second etching on the semiconductor layer to form a cavity; the first etching and the second etching at least include: introducing an etching gas into the etching chamber, using a plasma generating device to plasmaize the etching gas; using a plasma bias device to bombard the semiconductor layer with plasma; wherein the plasma bias power in the second etching is less than the plasma bias power in the first etching;

[0026] Introducing a gas containing oxygen elements into the etching chamber to perform a post-etching treatment step to oxidize the inner wall of the recess;

[0027] A passivation gas is introduced into the etching chamber to form a barrier layer on the inner wall of the recess.

[0028] In some embodiments, the first etching cycle includes: performing the first etching and the second etching in sequence, and the control method includes:

[0029] determining a number of executions of the first etching cycle;

[0030] In response to the number of times the first etching cycle is performed being less than a target number, performing the post-etching treatment step and forming the barrier layer until the number of times the first etching cycle is performed is equal to the target number;

[0031] In response to the first etching cycle being performed a number of times equal to the target number, the etching method is stopped.

[0032] In some embodiments, the control method includes:

[0033] When or after executing the first etching cycle, obtaining spectrum information of the gas inside the etching chamber by using an optical signal sensor inside the etching chamber;

[0034] Determine, based on the spectral information, that the number of times the first etching cycle is performed is equal to the target number.

[0035] In some embodiments,

[0036] The etching gas includes: at least one of sulfur hexafluoride or nitrogen trifluoride;

[0037] The oxygen-containing element gas in the post-etching treatment step may include: at least one of oxygen or carbon monoxide;

[0038] The passivation gas includes: tetracarbon octafluoride.

[0039] The embodiment of the present disclosure provides an etching method for semiconductor materials, performing a first etching and a second etching on a semiconductor layer to form a recess, wherein the first etching and the second etching at least include bombarding the semiconductor layer with a plasma bias, wherein the bias power of the plasma in the second etching is less than the bias power of the plasma in the first etching, thereby reducing the over-etching phenomenon of the sidewalls and the bottom of the recess caused by excessive bias power; performing a post-etching treatment step on the recess to oxidize the semiconductor material exposed on the inner wall of the recess; forming a barrier layer on the sidewall and / or the bottom of the recess, wherein the oxide layer on the inner wall and the barrier layer can be removed as an etching buffer layer or a sacrificial layer during subsequent first etching and second etching cycles, thereby reducing the lateral etching of the sidewalls of the recess and maintaining good uniformity of the recess etching morphology. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 is a schematic flow chart of an etching method according to an exemplary embodiment;

[0041] Figures 2 to 8 is a schematic diagram of a method for etching a semiconductor material according to an exemplary embodiment;

[0042] Figures 9 to 16 is a schematic diagram of a semiconductor material etching method according to an embodiment of the present disclosure;

[0043] Fig.17 It is a flow chart of a control method of an exemplary etching machine according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0044] The exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments set forth herein. On the contrary, these embodiments are provided in order to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0045] In the following description, a large number of specific details are given to provide a more thorough understanding of the present disclosure. However, it is obvious to those skilled in the art that the present disclosure can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present disclosure, some technical features known in the art are not described; that is, all features of actual embodiments are not described here, and well-known functions and structures are not described in detail.

[0046] It should be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected or coupled to the other element or layer, or intervening elements or layers may be present.

[0047] Spatially relative terms such as "under", "beneath", "below", "under", "above", "above", etc., may be used here for convenience of description to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientation shown in the figure, the spatial relationship terms are intended to also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, then the elements or features described as "under other elements" or "under it" or "under it" will be oriented as "on" other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0048] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be a limitation of the present disclosure. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0049] It should be understood that the "some embodiments" or "an embodiment" mentioned throughout the specification means that specific features, structures or characteristics related to the embodiments are included in at least one embodiment of the present disclosure. Therefore, "in some embodiments" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present disclosure, the size of the sequence number of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure.

[0050] When packaging a semiconductor structure, multiple semiconductor structures can be stacked in the vertical direction or in the thickness direction of the device; a vertical connection structure is formed to vertically interconnect the semiconductor structures, such as for power supply, data transmission and communication interaction. The connection structure may include a conductive channel, a conductive plug, a conductive wire, a through silicon via (TSV) or other structures. The connection structure may penetrate the corresponding semiconductor structure in the vertical direction. Multiple connection structures are aligned and coupled in the vertical direction. Each connection structure leads out the electrical signal of its corresponding semiconductor structure and couples and interconnects. The semiconductor structure may include a chip, a die, or a wafer. For example, a conductive channel may be made between chips, between chips and wafers, and between wafers to realize vertical interconnection of upper and lower semiconductor structures. If chips and wafers are stacked, or wafers are stacked, they can be cut according to the cutting path on the wafer after stacking to obtain multiple packaging structures. The packaging structure is coupled to a PCB board or an intermediate substrate by means of bumps or leads. In some embodiments, multiple semiconductor structures can be hybrid-bonded in the vertical direction to exchange electrical signals through bonding contacts; the connection structures corresponding to each semiconductor structure are coupled through bonding contacts, and the bonding contacts are located between two connection structures in the vertical direction.

[0051] In some embodiments, the semiconductor structure is etched to form an opening that penetrates the semiconductor layer in a vertical direction. The opening may penetrate other dielectric layers of the semiconductor structure in a vertical direction. The opening does not damage the interconnection layer of the semiconductor structure and the device structure such as transistors, and a conductive material is filled in the opening to form a connection structure. The connection structure may be a single-layer conductive structure or a multi-layer structure; for example, the connection structure may include a conductive core and a dielectric material surrounding the core. Exemplarily, the constituent materials of the connection structure may include, but are not limited to, conductive materials such as tungsten, copper, aluminum, titanium, nickel, gold, silver, platinum, titanium nitride, and tungsten nitride. The semiconductor layer may include a semiconductor substrate (or, a semiconductor wafer) or a semiconductor material epitaxially grown on a semiconductor substrate, and the semiconductor substrate may be thinned. The constituent materials of the semiconductor layer may include, but are not limited to: may include any semiconductor material in the field, including, but not limited to: single-element semiconductor materials (such as silicon, germanium), III-V compound semiconductor materials, II-VI compound semiconductor materials, organic semiconductor materials, or other semiconductor materials known in the art; for example, materials such as single crystal silicon, polycrystalline silicon, germanium, silicon carbide, or indium gallium zinc oxide IGZO. The semiconductor layer can be doped to form an active region, which can be used as a channel, source or drain of a transistor. Other device structures can be formed on one side of the semiconductor layer, including but not limited to: an interconnect layer, a transistor or a storage structure; a pad can be formed on the other side of the semiconductor layer, which can be used as an IO pad for signal interconnection and power supply.

[0052] In some embodiments, the through silicon via fabrication technology for some semiconductor layers 100 may adopt a cyclic process of etching, depositing a film layer, re-etching the film layer, opening a hole, and re-depositing a film layer, thereby reducing the etching load effect and improving the uniformity of the morphology and size of the etched opening. Figure 1 A method for etching a semiconductor material is provided, comprising:

[0053] Providing a semiconductor layer; the semiconductor layer may be doped to include an active region, and the semiconductor layer may include a device structure;

[0054] Performing a first etching step on the semiconductor layer to form a cavity; the etching mask may include a patterned photoresist, or a patterned hard mask, an anti-reflective coating or other film layer;

[0055] determining whether the number of cycles of the first etching step reaches a target number of cycles;

[0056] If the target number of cycles is reached, etching is stopped, and a mask removal step is performed, including but not limited to removing the mask including the photoresist using gases such as oxygen and argon, and removing etching byproducts in the recesses, the byproducts including but not limited to organic polymers; the photoresist removal step also includes etching or cleaning;

[0057] If the cycle has not reached this point, a deposition step is performed to form a passivation layer or a barrier layer on the sidewall and / or bottom of the recess;

[0058] The first etching step is performed on the recess having the passivation layer; in this first etching step, the etchant etches the barrier layer in the recess and etches the semiconductor layer at the bottom of the recess downward to increase the depth of the recess; it is determined again whether the number of cycles of the first etching step reaches the target number, so as to determine whether to perform the photoresist removal step or the deposition step. Exemplarily, the recess may include a recessed structure such as an opening, a groove, a trench, or a hole formed by etching away a portion of the semiconductor material.

[0059] In some embodiments, one etching step plus one deposition step is one cycle unit, and the etching stops after reaching the specified etching depth after multiple cycles. When the etching step reaches the target number of cycles, the deposition step will no longer be performed, and finally the silicon deep via etching is completed after the mask removal step. For the target number of cycles, the etching rate can be adjusted according to the etching time and gas volume of an etching step, and can be preset according to the etching rate and the thickness of the semiconductor layer (or silicon layer) to be etched, and calibrated by testing experiments, or an etching stop layer can be set under the semiconductor layer, which can increase the number of cycles to a certain extent to fully penetrate the semiconductor layer.

[0060] Taking the plasma dry etching of silicon material as an example, the etching gas of the first etching step may include fluorine-containing gas or chlorine-containing gas, including but not limited to: carbon tetrafluoride (CF4), sulfur hexafluoride (SF6), nitrogen trifluoride (NF3) or other fluorine-containing gas. In order to maintain a high etching rate, at least one of SF6 or NF3 can be selected, and hydrogen, oxygen, argon, etc. can also be introduced to adjust the etching rate. When etching, the etching gas is ionized by a plasma generator to form a plasma or plasma composed of reactive free radicals, and the plasma contacts the silicon material for etching to form a cavity; a bias device can be used to generate a downward electric field to accelerate the plasma to bombard the surface of the silicon material, which can break the polymer residue in the cavity, so that the reactive free radicals contact the silicon material for reaction, and the biased bombardment plasma can be provided by argon or oxygen. Exemplary, the plasma generator may include but is not limited to: a capacitively coupled plasma generator (CCP) and an inductively coupled plasma generator (ICP).

[0061] When performing the deposition step, octafluorocarbon (C4F8) gas is introduced into the recesses to deposit a carbon-containing polymer film on the sidewalls and / or bottom of the etched recesses. After the C4F8 gas is introduced into the recesses, the C4F8 decomposes into ionic CF x + Base, CF x - Base and active F - Base, where CF x + Base and CF x - The base reacts with the silicon surface to form a nCF2 polymer passivation film. When the next first etching step is performed, SF6 gas is introduced to increase the F - Ion dissociation, F - Reacts with nCF2 to etch away the passivation film and generate volatile gas CF2; F -The ions react with silicon to generate volatile gas SiF4 to etch silicon. In the next first etching step, the passivation film (or barrier layer) blocks the etchant from etching the sidewalls of the cavity, reducing the etching of the silicon material in the cavity and causing the expansion of the lateral size of the cavity, and the passivation film can be removed by the etching gas as a sacrificial layer to reduce the introduction of other film layers, providing a larger space and better landing sidewalls for the subsequent formation of other structures inside the cavity. In some other embodiments, an oxidizing gas such as oxygen can be introduced to oxidize the sidewalls of the cavity to form silicon oxide, or other film-forming process gases can be introduced to form other barrier layers, which may not be removed by the etching gas. Perform multiple first etching steps to form multiple cavities, such as forming a first cavity, a second cavity, and a third cavity, and multiple cavities are connected to form a cavity that penetrates the semiconductor layer or a cavity of greater depth; the first etching step of this time can remove the barrier layer formed in the previous deposition step.

[0062] Specifically, refer to Figure 2 As shown, a semiconductor layer 100 or a semiconductor substrate is provided. The semiconductor layer 100 can be doped to include an active area. The semiconductor layer 100 can include a device structure. A patterned mask layer is formed on one side surface of the semiconductor layer 100. The mask layer may include a patterned photoresist 101. The photoresist 101 can be formed on the front or back side of the semiconductor layer 100 having the device structure. The semiconductor layer 100 can be thinned.

[0063] Reference Figure 3 As shown, a first etching step is performed on the semiconductor layer 100 to form a first cavity 111. The cross-sectional shape of the first cavity 111 in the xoz plane may include a circle, an ellipse or other regular / irregular arcs; as shown in the scallop shape or ellipse, the etching gas may be SF6 and / or NF3, and the etching gas is plasmatized, and a bias device generates a bias electric field to accelerate the plasma to bombard the etching material; at this time, the first etching step does not reach the target number of cycles. Figure 4 As shown, a deposition step is performed to introduce C4F8 into the cavity to form a first barrier layer 121 (or a passivation layer) on the inner wall (ie, the side wall and the bottom) of the first cavity 111. Figure 5 As shown, the first etching step is performed for the second time on the first cavity 111, the first barrier layer 121 on the sidewall and the bottom of the first cavity 111 is etched away, and the semiconductor material at the bottom of the first cavity 111 is etched to form a second cavity 112, and the second cavity 112 is connected to the first cavity 111; at this time, the first etching step has been performed twice and has not reached the target cycle number, and the second deposition step needs to be performed, refer to Figure 6As shown, a second barrier layer 122 is formed on the sidewall of the first cavity 111 and the inner wall of the second cavity 112, and then the third first etching step and the third deposition step are performed. Exemplarily, the cavity 110 may include the first cavity 111 and the second cavity 112, and the nth cavity. When the cumulative number of executions of a certain first etching step performed subsequently reaches the target number of cycles, the deposition step will no longer be performed, the etching method of the cavity 110 is completed, and the step of removing the photoresist 101 can be performed.

[0064] The etching method of the recess 110 provided in the embodiment of the present disclosure finally ends with a certain first etching step. A certain deposition step needs to be followed by a first etching step. If the first etching step is performed n-1 times cumulatively and still does not reach the target number of cycles, the n-1th deposition step is performed to form a barrier layer on the inner wall of the recess 110 formed; the nth first etching step is performed to remove the barrier layer on the inner wall of the recess 110, and the semiconductor material is etched downward to deepen the depth of the recess 110; at this time, the first etching step is performed n times cumulatively, the target number of cycles is reached, the depth of the recess 110 reaches the target etching depth, or the recess 110 penetrates the semiconductor layer 100. Figure 7 As shown, the deposition step and the first etching step may not be performed subsequently. In some embodiments, after performing the first etching step multiple times to reach the target number of cycles, the cavity 110 extends in the semiconductor layer 100, and the cavity 110 does not completely penetrate the semiconductor layer 100. Subsequently, the surface of the semiconductor layer 100 on one side of the bottom of the cavity 110 may be thinned to expose the bottom of the cavity 110. At this time, the cavity penetrates the thinned semiconductor layer 100.

[0065] In some embodiments, reference Figure 5 and Figure 7 As shown, when etching is performed using an etching gas with a high etching rate such as SF6 or NF3, the semiconductor material on the sidewall of the cavity 110 will also be partially etched, and each first etching step forms a portion of the entire cavity 110, and each first etching step can form a scallop-like morphology, where the size of the top and bottom of the scallop in the x direction is smaller than the size of the middle part in the x direction. For example, after two first etching steps, the first cavity 111 and the second cavity 112 near the top of the semiconductor material are formed, and the size of the first cavity 111 at both ends in the x direction is smaller than the size of the middle part of the first cavity 111 at both ends in the x direction, and the morphology of the second cavity 112 is similar to that of the first cavity 111; the connection between the first cavity 111 and the second cavity 112 has a protrusion 141 protruding from the middle part along the x direction, and the existence of the protrusion 141 makes it difficult to subsequently deposit materials (such as silicon oxide) on the sidewall of the cavity, resulting in leakage between the connection structure formed in the cavity 110 and the semiconductor layer 100, thereby reducing the stability of the device.

[0066] In some embodiments, due to the high etching rate of the etching gas SF6 or NF3, even if a barrier layer including a carbon-containing polymer is deposited on the sidewall of the cavity 110, the barrier layer may continue to dig out the semiconductor material along the x direction after being etched, which may easily cause Figure 8 The morphology of the concave cavity 110 is small at both ends and large in the middle, which reduces the uniformity of the size of the concave cavity 110 and reduces the conductivity of the subsequent connection structure formed in the concave cavity 110. In view of this, the embodiment of the present disclosure provides an etching method for semiconductor materials to improve the anisotropy during the etching process of the concave cavity 110 and improve the morphology and size uniformity of the concave cavity 110.

[0067] According to some aspects of the embodiments of the present disclosure, Fig. 9 A method for etching a semiconductor material is provided, comprising:

[0068] Providing a semiconductor layer, performing a first etching and a second etching on the semiconductor layer to form a recess; the first etching and the second etching at least include bombarding the semiconductor layer with a plasma bias; the plasma bias power in the second etching is less than the plasma bias power in the first etching;

[0069] Performing a post-etching treatment step, including introducing a gas containing an oxygen element into the cavity to oxidize at least a portion of an inner wall of the cavity;

[0070] A deposition step is performed to form a barrier layer on the inner wall of the recess.

[0071] Reference Figure 3 As shown, a semiconductor layer 100 or a semiconductor substrate is subjected to a first etching and a second etching using a mask layer including a patterned photoresist 101. The etchants for the first etching and the second etching may be the same, such as etching gas SF6 or NF3. The first etching and the second etching both utilize a plasma generator to plasmatize the etching gas to generate free radicals, and the free radicals react with the semiconductor material to generate volatile byproduct gases. The first etching and the second etching may both utilize a plasma bias device to accelerate the plasma to bombard the semiconductor material, and the plasma bias device may include a bias electrode. A cavity of a certain depth will be formed during the first etching. The bias power during the second etching may be less than the bias power configured during the first etching, so as to reduce over-etching of the semiconductor material caused by excessive bias power, and reduce sputtering bombardment of the cavity sidewalls when the plasma with excessive energy bombards the bottom of the cavity, which is beneficial to maintaining good uniformity of the cavity etching morphology. After the first etching and the second etching, a cavity is formed, and the cavity may include Figure 3 The first cavities 111 are shown. The first etching and the second etching may constitute a first etching cycle, which may be performed in a cycle to gradually deepen the depth of the cavities to penetrate the semiconductor layer 100 or reach a target etching depth.

[0072] Reference Fig.10 As shown, the inner wall of the first cavity 111 is oxidized by oxygen, carbon monoxide or other oxygen-containing gas to form an oxide layer 131, that is, a post-etching treatment step is performed. In the post-etching treatment step, O2 will dissociate into O free radicals and O 2- ions, O radicals will oxidize the sidewall of the first cavity 111 into an oxide layer 131, and the oxide layer 131 extends into a portion of the thickness of the sidewall along the x direction; the oxide layer 131 can be continuous or discontinuous, and can exist in a portion of the sidewall. For example, Si on the sidewall is oxidized to SiO2. CO gas will dissociate into CO radicals under the action of the electric field of the chamber, and the CO radicals will react with the F - The COF gas generated by ions is pumped away by the molecular pump, reducing the residual F - The ions continue to consume the SiO2 on the sidewalls and the silicon on the sidewalls, reducing overetching and slow diffusion etching of residual etchant to cause defects.

[0073] Reference Fig.11 As described above, the deposition step is performed, C4F8 is introduced, and Fig.10 On the inner wall of the first recess 111, or Fig.10 A barrier layer is formed on the oxide layer 131 on the inner wall of the first recess 111, and the barrier layer may include a carbon-containing polymer, and the barrier layer may include a first barrier layer 121. The oxide layer 131 and the first barrier layer 121 may be removed as an etching buffer layer or a sacrificial layer in the next first etching cycle to reduce the lateral sidewall of the recess and maintain good uniformity of the recess etching morphology. The thickness of the oxide layer 131 may be less than or equal to the thickness of the first barrier layer 121.

[0074] In some embodiments, reference Fig.12 As shown, the first etching cycle includes: performing the first etching and the second etching in sequence, and the etching method also includes:

[0075] When the number of times the first etching cycle is executed is less than the target number, executing the post-etching processing step and forming the barrier layer until the number of times the first etching cycle is executed is equal to the target number;

[0076] When the number of times the first etching cycle is executed is equal to the target number, the etching method is stopped; and a mask removal step is performed.

[0077] Executing a first etching and a second etching is a first etching cycle. After executing a first etching cycle, it is determined whether the cumulative number of executions of the first etching cycle reaches the target number. If the target number is reached, the etching post-processing operation and the deposition step will no longer be executed. If the current first etching cycle has not reached the target number, the etching post-processing operation is executed, O2 and CO are introduced to oxidize the sidewall of the cavity to form an oxide layer 131; the deposition step is executed, and C4F8 is introduced to form a barrier layer; the next first etching cycle is executed to remove the oxide layer 131 and the barrier layer formed in the last etching post-processing operation; it is determined again whether the cumulative number of executions of the first etching cycle reaches the target number, and the first etching cycle, the determination of the cumulative number of etchings reaches the target number, the etching post-processing step, and the deposition step are executed in sequence until the first etching cycle reaches the target number. When the cumulative number of executions of a subsequent first etching step reaches the target number of cycles, the deposition step will no longer be executed, the etching method of the cavity is completed, and the step of removing the photoresist 101 can be executed.

[0078] The recess etching method provided by the embodiment of the present disclosure ultimately ends with a first etching cycle step. A first etching step needs to be followed by a deposition step. If the first etching step has been performed n-1 times cumulatively and the target number of cycles has not been reached, n-1 first etching post-processing steps are performed, and the n-1th deposition step is performed to form an oxide layer 131 and a barrier layer on the inner wall of the formed recess; the nth first etching cycle step is performed to remove the barrier layer and the oxide layer 131 on the inner wall of the recess, and the semiconductor material is etched downward to deepen the depth of the recess; at this time, the first etching step has been performed n times cumulatively, reaching the target number of cycles, the recess depth reaches the target etching depth, or the recess penetrates the semiconductor layer 100. The oxide layer 131 formed by the post-etching processing operation can be a discontinuous film layer with uneven thickness, for example, a thicker oxide layer 131 is formed at the protrusion 141 on the side wall of the cavity; the first etching cycle can remove the oxide layer 131 at some positions, for example, the oxide layer 131 of the protrusion 141 on the side wall of the cavity can be removed, and multiple etching-oxidation cycles can grind the protrusion 141 to form a smooth sidewall morphology.

[0079] In some embodiments, the etching method further comprises:

[0080] Reference Figure 3 As shown, the first etching cycle is performed on the semiconductor layer 100 to form a first cavity 111; it is determined that the cumulative number of executions of the current first etching cycle has not reached the target number, and the first etching cycle needs to be performed again later;

[0081] Reference Fig.10As shown, a post-etching treatment step is performed on the first cavity 111. The post-etching treatment step can oxidize the inner wall of the first cavity 111 to form an oxide layer 131, or in other embodiments can be used to remove residual F in the etchant. - ion; reference Fig.11 As shown, a first barrier layer 121 is formed on the inner wall of the first cavity 111;

[0082] Reference Fig.13 As shown, the semiconductor layer 100 is subjected to the next first etching cycle, the first barrier layer 121 on the sidewall of the first recess 111 is removed, and a second recess 112 is formed under the first recess 111, and the second recess 112 is connected to the first recess 111; the first etching cycle may etch away at least a portion of the oxide layer 131 on the sidewall of the first recess 111, or the oxide layer 131 may not be removed, and the oxide layer 131 may be used as an insulating isolation from the semiconductor layer 100; if the accumulated number of first etching cycles currently being executed is equal to the target number, the entire etching cycle will be stopped, as well as the subsequent post-etching processing steps and deposition steps;

[0083] If the first etching cycle number has not reached the target number after the first cavity 111 and the second cavity 112 are formed, etching needs to be continued to deepen the cavity depth; Fig.14 As shown, the first cavity 111 and the second cavity 112 are subjected to a post-etching treatment step to form a second barrier layer 122 and an oxide layer 131 on the sidewalls of the first cavity 111 and the inner wall of the second cavity 112; Fig.15 The first etching cycle is executed to remove the barrier layer and the oxide layer 131 on the sidewall of the first cavity 111, and to form the third cavity 113 under the second cavity 112. If the etching depth has reached the target depth after the third cavity 113 is formed, the number of executions of the first etching cycle has reached the target number, and the subsequent operation is no longer executed, and the mask removal step of removing the mask such as the photoresist 101 is executed; the formed cavities include the first cavity 111, the second cavity 112, and the third cavity 113.

[0084] In some embodiments, executing Fig.12 The etching method steps shown in the figure are to cyclically execute the first etching cycle, determine whether the etching cycle execution times reach the target times, perform the etching post-processing steps and the deposition steps, until the first etching cycle reaches the target times, no longer perform the subsequent etching post-processing steps and the deposition steps, end the etching method cycle and perform the mask removal step, and form Fig.16 The shown recesses include a first recess 111 , a second recess 112 , and a third recess 113 , which are recesses of greater depth. Fig.16In the embodiment, each etching cycle step can form a portion of the cavity 110 , such as performing the first three first etching cycles to form the first cavity 111 , the second cavity 112 , and the third cavity 113 .

[0085] In some embodiments, when it is determined that the number of first etching cycles has reached the target number, a post-etching treatment step may be performed after the last first etching cycle, with less O2 and CO introduced or with less execution time; that is, the gas used and the processing time of the post-etching treatment operation immediately following the last first etching cycle are less than the post-etching treatment step when the target number of etching cycles has not been reached; to remove the residual F - ions, or a thinner oxide layer 131 can be formed, which does not affect the subsequent formation of the sidewall insulating layer and the filling of the conductive material.

[0086] In some embodiments, reference Fig.14 As shown, a protrusion 141 is provided at a connection between the first cavity 111 and the second cavity 112, and the protrusion 141 protrudes from at least a portion of the sidewall of the second cavity 112 in the x direction; the x direction intersects with the thickness direction (z direction) of the semiconductor layer 100; and performing the post-etching processing step further includes:

[0087] Reference Fig.14 As shown, at least a portion of the protrusion 141 is oxidized to form an oxide layer 131;

[0088] The etching method also includes:

[0089] Reference Fig.15 As shown, when the first etching cycle is performed to form the third cavity 113 under the second cavity 112 , the second barrier layer 122 and the oxide layer 131 are etched away.

[0090] The cross-sectional shapes of the first cavity 111 and the second cavity 112 in the xoz plane may include but are not limited to: oval, bowl, egg, and scallop. Taking the first cavity 111 as an example, the middle part of the first cavity 111 is larger in the x direction and smaller in the two ends in the x direction. The second cavity 112 is similar to the first cavity 111; a protrusion 141 protruding along the x direction is formed at the connection between the first cavity 111 and the second cavity 112. The protrusion 141 protrudes along the x direction and is easier to be etched and removed, which is conducive to forming a smooth side wall and improving the uniformity of the cavity etching morphology.

[0091] In some embodiments, in the post-etching treatment step, the processing gases used are O2 and CO. O2 will dissociate into O free radicals and O under the action of the electric field of the chamber. 2- ions, O radicals will oxidize the Si of the sidewall scallop into SiO2. The part of the scallop morphology protrusion 141 is affected by O 2-The incident angle of ion bombardment is larger, which makes it easier to accept O 2- Due to the bombardment of ions, Si-Si bonds are more likely to break and be oxidized to generate SiO2. In addition, the protrusion 141 has a larger specific surface area and a larger area in contact with O radicals. Therefore, the oxidation rate of the protrusion 141 is faster and the oxidation thickness is thicker. The oxide layer 131 will be etched away by SF6 or NF3 in the subsequent etching step. After multiple etching-oxidation cycles, the protrusion 141 of the cavity 110 will be slowly polished to obtain a relatively smooth sidewall morphology; CO gas will dissociate into CO radicals under the action of the electric field of the cavity, and the CO radicals will react with the residual F ions in the previous etching step to generate COF gas, which will be pumped away by the molecular pump, reducing the residual F ions from continuing to consume the SiO2 on the sidewall. Due to the presence of CO gas, the SiO2 film generated by oxidation on the upper and lower sidewalls of the protrusion 141 can continue to be retained, and the retention of part of the SiO2 film can reduce the consumption of sidewall Si in the subsequent etching steps, that is, the anisotropy of the etching process of the cavity 110 is improved.

[0092] In some embodiments, when the first etching cycle is performed to the target number of times, the cavity 110 penetrates the semiconductor layer 100. Alternatively, the cavity 110 does not penetrate the semiconductor layer 100, and the semiconductor layer 100 is subsequently thinned to expose the bottom of the cavity 110, so that the cavity 110 penetrates the remaining semiconductor layer 100; the thinning process may include but is not limited to chemical mechanical polishing.

[0093] In some embodiments, the target number of the first etching cycle can be determined by experimental testing and calibration according to the thickness of the semiconductor layer 100 to be etched, and the etching rates of the first etching and the second etching in the first etching cycle on the semiconductor layer 100 are tested respectively to determine the theoretical total etching time of the first etching and the second etching; the theoretical total etching time of the first etching is divided by the single first etching time to obtain the target number of the first etching, and the second etching is similar to the first etching; the total etching time of multiple first etchings and multiple second etchings is greater than or equal to the theoretical total etching time required. After determining the target number of the first etching cycle according to the etching time, multiple tests and adjustments are performed to obtain the optimal target number that is suitable for the depth of the semiconductor layer 100 to be etched. The target number can be stored in the storage device of the etching machine for the control unit of the etching machine to call, and the control unit records the cumulative number of executions of the first etching cycle and compares it with the preset target number to determine whether the target number is reached.

[0094] In some embodiments, an etching stop layer made of a material different from the semiconductor layer 100 is disposed under the semiconductor layer 100. Multiple first etching cycles may be performed to perform over-etching to a certain extent. The cavity 110 penetrates the semiconductor layer 100. The cavity 110 may stop at the stop layer or extend into part of the stop layer.

[0095] In some other embodiments, the method for determining the target number of times includes:

[0096] When or after executing the first etching cycle, spectrum information of the gas atmosphere where the semiconductor layer 100 is located is obtained; and it is determined that the number of first etching cycles executed is equal to the target number according to the spectrum information.

[0097] During the etching process of the semiconductor layer 100, the semiconductor layer 100 contacts and reacts with the plasma etchant to generate polymers and volatile gases, or is etched by plasma bombardment; as the semiconductor material is continuously etched, the gas phase components inside the etching chamber will continue to change, the concentration of each component will also continue to change, and the emission spectra of the gas phase components will be different. The spectral information inside the etching chamber can be obtained to determine that the semiconductor layer 100 has reached the etching end point, that is, the number of executions of the first etching cycle has reached the target number. For example, at the beginning of etching, the reaction is more intense, and the emission spectrum of a certain target component detected has a signal peak. As the reaction proceeds and the etching end point is about to be reached, the emission spectrum of the target component gradually moves to a low intensity, weakens after crossing the peak and tends to a straight line, and finally disappears; according to this principle, after testing and calibration, a certain time when the collected spectral signal tends to a straight line is used as the etching end point.

[0098] In some embodiments, the optical signal sensor provided inside the etching chamber obtains the gas phase emission light signal in the etching chamber during the first etching cycle, and feeds the data back to the corresponding spectrum processing module. The spectrum processing module draws the spectrum conversion curve of the target component according to the acquisition time, light intensity, and the spectrum wavelength range of the target component, compares the curve with the standard curve in the machine storage device, obtains the moment when the characteristic waveform or characteristic band of the spectrum conversion curve of the target component appears, and determines whether the current first etching cycle has reached the target number of cycles or not. For example, if a characteristic peak appears n times in the spectrum curve, and then the characteristic peak disappears and the spectrum curve tends to be stable, or disappears, then the nth first etching cycle has reached the target number of cycles.

[0099] In some other embodiments, the second-to-last first etching cycle is easily misjudged as having reached the target number of cycles, and the last first etching cycle is easily misjudged as not reaching the etching endpoint and causing over-etching. Spectral information can be detected after the second-to-last first etching cycle is completed or during execution to determine whether the second-to-last first etching cycle has reached the target number of cycles; subsequently, spectral information is detected during the last first etching cycle to confirm that the last first etching cycle has been completed and the cumulative number of executions of the last first etching cycle has reached the target number of cycles.

[0100] In some embodiments, Fig.16The recess 110 shown is filled with a conductive material to form a connection structure, which may be a single-layer conductive structure or a multi-layer structure; for example, the connection structure may include a conductive core and a dielectric material surrounding the core. In some embodiments, a dielectric material is formed on the sidewall of the recess 110, and then the connection structure is formed, and the dielectric material provides electrical isolation between the connection structure and the semiconductor layer 100.

[0101] According to some aspects of the embodiments of the present disclosure, Fig.17 A control method for an etching machine is provided, the control method comprising:

[0102] transferring a wafer including a semiconductor layer to an etching chamber;

[0103] Performing a first etching and a second etching on the semiconductor layer to form a cavity; the first etching and the second etching at least include: introducing an etching gas into the etching chamber, using a plasma generating device to plasmaize the etching gas; using a plasma bias device to bombard the semiconductor layer with plasma; wherein the plasma bias power in the second etching is less than the plasma bias power in the first etching;

[0104] Introducing a gas containing oxygen elements into the etching chamber to perform a post-etching treatment step to oxidize the inner wall of the recess;

[0105] A passivation gas is introduced into the etching chamber to form a barrier layer on the inner wall of the recess.

[0106] The etching machine may include but is not limited to: a loading platform, a transfer chamber, a robot arm, an etching chamber, a plasma generator, a plasma bias device, a gas distribution device, various electric control valves and a gas flow meter, a control unit, etc. The control unit controls the robot arm to extract the wafers in the wafer box on the loading platform, and the robot arm carries the wafers through the transfer chamber to the inside of the etching chamber isolated from the atmosphere; the control unit controls the gas distribution device to transmit gas, and controls the corresponding electric control valve to open or close, and receives the gas flow signal fed back by the gas flow meter to control the target volume of gas to enter the etching chamber; the control unit controls the plasma generator to start so that the gas is ionized to generate plasma, and controls the plasma bias device to start so that the plasma bombards the wafer surface, and the chemical reaction is combined with the physical bombardment to complete the etching. The etching gas may include but is not limited to SF6 or NF3. The control unit records the number of times the first etching and the second etching are performed. After the first etching and the second etching steps are completed, the control unit determines whether the target number of times is reached. If the target number of times is reached, the control unit controls the robotic arm to transfer the wafer and perform the subsequent mask removal step; if the target number of times is not reached, the control unit controls the introduction of O2 and CO to perform the post-etching processing step, and the introduction of C4F8 to perform the deposition step to form a barrier layer; then the etching gas corresponding to the first etching is introduced to perform etching again, and the etching gas corresponding to the second etching is introduced to perform etching again, until the etching number reaches the target number of times.

[0107] In some embodiments, the first etching cycle includes: executing the first etching and the second etching in sequence, and the control method includes: determining the number of executions of the first etching cycle; in response to the number of executions of the first etching cycle being less than the target number, executing the post-etching processing steps and forming the barrier layer until the number of executions of the first etching cycle is equal to the target number; in response to the number of executions of the first etching cycle being equal to the target number, stopping execution of the etching method.

[0108] In some embodiments, the control method includes: when executing the first etching cycle or after executing the first etching cycle, obtaining spectral information of the gas inside the etching chamber using an optical signal sensor inside the etching chamber;

[0109] Determine, based on the spectral information, that the number of times the first etching cycle is performed is equal to the target number.

[0110] After the first etching cycle or the first etching cycle is completed, the gas phase emission light signal in the etching chamber is obtained, and the data is fed back to the corresponding spectrum processing module. The spectrum processing module draws the spectrum conversion curve of the target component according to the acquisition time, light intensity, and the spectral wavelength range of the target component; the control unit or the spectrum processing module compares the curve with the standard curve in the machine storage device, obtains the etching of the characteristic waveform of the spectrum conversion curve of the target component or the characteristic band, and determines whether the current first etching cycle has reached the target number of cycles or not. For example, a characteristic peak appears n times in the spectrum curve graph, and then the characteristic peak disappears and the spectrum curve tends to be stable, or disappears, then the nth first etching cycle has reached the target number of cycles. The control unit controls the post-etching processing step according to whether the cumulative number of executions of the current first etching cycle reaches the target number. Deposition step, or the wafer is transferred out.

[0111] In some embodiments, the etching gas includes: at least one of sulfur hexafluoride (SF6) or nitrogen trifluoride (NF3); the oxygen-containing element gas in the post-etching treatment step may include: at least one of oxygen (O2) or carbon monoxide (CO); the passivation gas includes: tetracarbon octafluoride (C4F8).

[0112] The above description is only a specific implementation mode of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure.

Claims

1. A method for etching a semiconductor material, characterized in that: include: Providing a semiconductor layer, performing a first etching and a second etching on the semiconductor layer to form a recess; The first etching and the second etching at least include bombarding the semiconductor layer with a plasma bias; the plasma bias power in the second etching is less than the plasma bias power in the first etching; Performing a post-etching treatment step, including introducing a gas containing an oxygen element into the cavity to oxidize at least a portion of an inner wall of the cavity; A barrier layer is formed on the inner wall of the recess.

2. The etching method according to claim 1, characterized in that: The first etching cycle includes: performing the first etching and the second etching in sequence, and the etching method further includes: When the number of times the first etching cycle is executed is less than the target number, executing the post-etching processing step and forming the barrier layer until the number of times the first etching cycle is executed is equal to the target number; When the number of times the first etching cycle is executed is equal to the target number, the etching method is stopped.

3. The etching method according to claim 2, characterized in that: The etching method further comprises: performing the first etching cycle on the semiconductor layer to form a first recess; performing the post-etching processing step on the first cavity to form a first barrier layer on an inner wall of the first cavity; Performing the first etching cycle on the semiconductor layer for the next time to remove the first barrier layer on the sidewall of the first recess and form a second recess below the first recess, wherein the second recess is connected to the first recess; The post-etching treatment step is performed on the first cavity and the second cavity, and a second barrier layer is formed on the sidewall of the first cavity and the inner wall of the second cavity.

4. The etching method according to claim 3, characterized in that: A protrusion is provided at the connection between the first cavity and the second cavity, and the protrusion protrudes at least part of the side wall of the second cavity in the first direction; The first direction intersects with the thickness direction of the semiconductor layer; The post-etching processing step further comprises: oxidizing at least a portion of the protrusion to form an oxide layer; The etching method further comprises: When the first etching cycle is performed to form a third recess below the second recess, the second barrier layer and the oxide layer are etched away.

5. The etching method according to claim 2, characterized in that: When the first etching cycle is performed to the target number of times, the recess penetrates the semiconductor layer.

6. The etching method according to claim 2, characterized in that: Methods for determining the target number of times include: When or after executing the first etching cycle, spectrum information of the gas atmosphere in which the semiconductor layer is located is acquired; and according to the spectrum information, it is determined that the number of times the first etching cycle is executed is equal to the target number.

7. A control method for an etching machine, characterized in that: The control method comprises: transferring a wafer including a semiconductor layer to an etching chamber; Performing a first etching and a second etching on the semiconductor layer to form a cavity; the first etching and the second etching at least include: introducing an etching gas into the etching chamber, using a plasma generating device to plasmaize the etching gas; using a plasma bias device to bombard the semiconductor layer with plasma; wherein the plasma bias power in the second etching is less than the plasma bias power in the first etching; Introducing a gas containing oxygen elements into the etching chamber to perform a post-etching treatment step to oxidize the inner wall of the recess; A passivation gas is introduced into the etching chamber to form a barrier layer on the inner wall of the recess.

8. The control method according to claim 7, characterized in that: The first etching cycle includes: performing the first etching and the second etching in sequence, and the control method includes: determining a number of executions of the first etching cycle; In response to the number of times the first etching cycle is performed being less than a target number, performing the post-etching treatment step and forming the barrier layer until the number of times the first etching cycle is performed is equal to the target number; In response to the first etching cycle being performed a number of times equal to the target number, the etching method is stopped.

9. The control method according to claim 8, characterized in that: The control method comprises: When or after executing the first etching cycle, obtaining spectrum information of the gas inside the etching chamber by using an optical signal sensor inside the etching chamber; Determine, based on the spectral information, that the number of times the first etching cycle is performed is equal to the target number.

10. The control method according to claim 7, characterized in that: The etching gas includes: at least one of sulfur hexafluoride or nitrogen trifluoride; The oxygen-containing element gas in the post-etching treatment step may include: at least one of oxygen or carbon monoxide; The passivation gas includes: tetracarbon octafluoride.

Images