Method for preparing ultrathin SiC / diamond composite wafer through Van der Waals force bonding

Abstract

The invention provides a method for preparing an ultrathin SiC / diamond composite wafer by Van der Waals force bonding. The method comprises the following steps: forming a graphene layer on one surface of a polycrystalline diamond wafer to obtain a diamond / graphene wafer; forming a graphene layer on one surface of the SiC wafer to obtain a SiC / graphene wafer; h < + > ions are injected into the SiC surface of the SiC / graphene wafer through ion injection; bonding the polycrystalline diamond and the SiC by virtue of the graphene layers of the polycrystalline diamond and the SiC through Van der Waals force bonding to obtain a bonded wafer; stripping the SiC layer of the bonded wafer at high temperature to obtain an ultrathin SiC / diamond composite wafer; and polishing the surface of the SiC layer of the ultrathin SiC / diamond composite wafer. According to the method for preparing the ultrathin SiC / diamond composite wafer through Van der Waals force bonding, low voidage and large-size bonding of diamond and silicon carbide can be achieved, the interface thermal resistance between the diamond and a device can be reduced, and the output power density of the device can be improved.

Description

Technical Field

[0001] The invention relates to the technical field of semiconductor material preparation, and in particular to a method for preparing an ultra-thin SiC / diamond composite wafer by van der Waals bonding. Background Art

[0002] At present, high-power GaN devices generally use silicon carbide substrates. However, with the further improvement of the power density of GaN microwave power devices, the thermal conductivity of silicon carbide is 390W / m·K. Therefore, silicon carbide substrates will be difficult to meet the heat dissipation problem of GaN devices, and substrate materials with higher thermal conductivity are urgently needed.

[0003] The thermal conductivity of diamond is as high as 2000W / m·K, which is the material with the second highest thermal conductivity in nature after graphene. Therefore, diamond has gradually become the first choice for GaN device packaging materials. In recent years, the technology and application of diamond as a heat sink material and substrate material for GaN devices have made great progress. However, it is difficult to make breakthroughs in the technology of large-size, high-quality diamond single crystals, and the use of diamond single crystals as substrate materials for GaN devices is still a great challenge.

[0004] After years of research, the thermal conductivity of polycrystalline diamond has approached that of single-crystal diamond, making it possible to prepare large-size wafers of 6 inches or larger, and can play an important role in the heat sink of GaN devices.

[0005] By preparing polycrystalline diamond / silicon carbide composite wafers, on the one hand, the problem of low thermal conductivity and insufficient heat dissipation capacity of silicon carbide can be solved. On the other hand, it can also solve the problem that the diamond wafer is small in size and cannot be used to prepare large-size microwave devices. However, there are large thermal mismatch and lattice mismatch problems between diamond and silicon carbide materials, which makes the composite wafer easy to fall off and the risk of wafer breakage during the preparation process. These factors are technical difficulties that restrict the application of diamond / silicon carbide composite wafers.

[0006] At present, a few researchers have achieved heterogeneous bonding of diamond and silicon carbide on a small scale (less than 2 inches) through bonding process technology. 3 N 4 、Al 2 O 3 Bonding layer dielectrics such as polymers and metals reduce the interface thermal resistance, but the bonding void rate is high and large-size bonding cannot be achieved.

[0007] Therefore, there is an urgent need for a method for preparing a large-sized and high-bonding-rate polycrystalline diamond / silicon carbide composite wafer, which can not only solve the problem of low thermal conductivity and insufficient heat dissipation capacity of silicon carbide as a substrate for high-power GaN devices, but also solve the problem in the prior art that large-sized polycrystalline diamond and silicon carbide composite wafers cannot be bonded due to the low bonding rate of polycrystalline diamond / silicon carbide composite wafers. Summary of the invention

[0008] The purpose of the present invention is to provide a method for preparing an ultra-thin SiC / diamond composite wafer by van der Waals bonding, so as to achieve low void rate and large-size bonding between diamond and silicon carbide, and to achieve reliable thinning of silicon carbide, so as to reduce the interface thermal resistance between diamond and the device, increase the output power density of the device, and enhance the performance and reliability of the device.

[0009] In order to solve the above technical problems, the present invention provides a method for preparing an ultra-thin SiC / diamond composite wafer by van der Waals bonding, comprising the following steps:

[0010] A diamond / graphene wafer is obtained by forming a graphene layer on a surface of a polycrystalline diamond sheet through vacuum annealing;

[0011] A SiC / graphene wafer is obtained by forming a graphene layer on one surface of a SiC wafer through vacuum annealing;

[0012] H is implanted on the SiC surface of the SiC / graphene wafer by ion implantation. + ion;

[0013] The diamond / graphene wafer and the H-implanted + ion bonding of the graphene layer of the SiC / graphene wafer to obtain a bonded wafer;

[0014] The SiC layer of the bonded wafer is peeled off at high temperature to obtain an ultra-thin SiC / diamond composite wafer;

[0015] Polishing of SiC layer surface of ultra-thin SiC / diamond composite wafer.

[0016] Furthermore, the vacuum annealing temperature of the polycrystalline diamond sheet is 600-950° C., the thickness of the graphene layer formed on the surface of the polycrystalline diamond sheet is 100-300 nm, and the surface flatness is 1-3 nm.

[0017] Furthermore, the vacuum annealing temperature of the SiC wafer is 1000-1200° C., the thickness of the graphene formed on the surface of the SiC wafer is 100-300 nm, and the surface flatness is 1-3 nm.

[0018] Furthermore, the ion implantation depth is 1 to 10 μm, and the implantation dose is 1016 ~10 20 cm -3 , the injection energy is 90~200keV.

[0019] Furthermore, the bonding temperature during the van der Waals bonding is 100-200° C., and the thickness of the bonding layer formed by the van der Waals bonding is 5-100 nm.

[0020] Furthermore, before the van der Waals bonding, the diamond / graphene wafer and the H-implanted + The SiC / graphene wafers with ions were subjected to surface polishing, surface cleaning and chemical wet activation treatment respectively.

[0021] Furthermore, the surface flatness of the polished diamond / graphene wafer is 1 to 3 nm, and the H + The surface flatness of the ion-polished SiC / graphene wafer is 0.1-3 nm;

[0022] The diamond / graphene wafer and the H-implanted + The surface cleaning of ionic SiC / graphene wafers adopts organic / RCA cleaning method, and SC3 (SPM), SC2 (HPM), SC1 (APM), and BOE solutions are used for cleaning in sequence;

[0023] The chemical wet activation treatment uses plasma or RIE to respectively activate the diamond / graphene wafer and the H-implanted + The SiC / graphene wafer surface is plasma treated with ions.

[0024] Furthermore, the high temperature stripping of the SiC layer of the bonded wafer is to place the bonded wafer in a vacuum high temperature environment and + The high temperature treatment of the SiC layer by ions causes the SiC layer to be peeled off.

[0025] Furthermore, the vacuum degree during high temperature peeling of the SiC layer of the bonded wafer is controlled to be 10 2 ~10 6 Pa, the temperature is controlled at 1000-1200° C., and the SiC layer is peeled off to a thickness of 1-10 μm.

[0026] Furthermore, the surface polishing of the SiC layer of the ultra-thin SiC / diamond composite wafer is performed by polishing the surface of the peeled SiC layer using a wafer polisher, and the surface flatness of the SiC layer after the polishing is 1 to 3 nm.

[0027] The present invention provides a method for preparing an ultra-thin SiC / diamond composite wafer by van der Waals bonding, wherein a graphene layer formed by pyrolysis of polycrystalline diamond and a graphene layer formed by pyrolysis of SiC are bonded by van der Waals force, so that the bonding void rate between the bonded polycrystalline diamond and the SiC wafer is low, thereby achieving large-scale bonding of polycrystalline diamond and SiC wafer. In addition, since the prepared composite wafer is a composite of polycrystalline diamond and SiC wafer, the prepared composite wafer not only has the high thermal conductivity and corrosion resistance of diamond, but also has the large size and oxidation resistance of silicon carbide, and can be used as a high thermal conductivity substrate or packaging heat sink material. The ultra-thin SiC / diamond composite wafer prepared by the present invention is used as an epitaxial substrate for GaN HEMT devices, which can effectively solve the heat dissipation problem of high-power GaN HEMT devices.

[0028] Specifically, the method for preparing an ultra-thin SiC / diamond composite wafer by van der Waals bonding provided by the present invention can achieve the following technical effects:

[0029] ① Since the thermal conductivity of SiC wafer is 490, while the thermal conductivity of polycrystalline diamond is 1500, the ultra-thin SiC / diamond composite wafer prepared by the present invention can increase the thermal conductivity to 2-3 times according to the thickness of SiC in the composite wafer, thereby solving the problem of low thermal conductivity and insufficient heat dissipation of SiC. On the other hand, the present invention adopts polycrystalline diamond to prepare ultra-thin SiC / diamond composite wafer, and the bonding size can be increased from 2 inches to 8 inches at most, solving the problem that the size of diamond single crystal wafer is small and large-size microwave power devices cannot be prepared. At the same time, the ultra-thin SiC / diamond composite wafer prepared by the present invention is applied to silicon carbide power electronic devices, which can improve the heat dissipation level of silicon carbide power devices.

[0030] ② Other bonding methods or bonding media have the problems of poor bonding performance, easy falling off of bonding media, and difficult control of surface flatness. The present invention adopts the graphene-graphene van der Waals bonding method, which belongs to intermolecular force bonding. Compared with the covalent bond bonding force, the interface stress can be reduced by 3 orders of magnitude, which greatly reduces the interface stress and can effectively prevent the problem of easy falling off of the composite wafer. In addition, it also avoids the problem of low thermal conductivity bonding layer (such as Si 3 N 4 、Al 2 O 3 The use of materials such as silicon carbide, etc. can further reduce the thermal resistance at the interface between diamond and SiC.

[0031] ③ The present invention adopts intelligent stripping technology to thin the SiC layer, injects hydrogen ions into the SiC layer through ion implantation, and then strips the thick SiC layer at high temperature, which can effectively avoid the risk of SiC wafer breakage during the stripping process. At the same time, the thickness of SiC can be controlled within 10μm, and the interface thermal resistance between diamond and GaN devices can be reduced by 30%-40%.

[0032] ④ The ultra-thin SiC / diamond composite wafer prepared by the present invention has a bonding rate of more than 95%, strong lateral bonding force, high thermal conductivity of polycrystalline diamond, controllable thickness and wafer size, good continuity, and is suitable for high-efficiency heat dissipation substrates for high-power microwave devices and highly integrated digital chips.

[0033] Therefore, the method for preparing ultra-thin SiC / diamond composite wafers by van der Waals bonding provided by the present invention improves the bonding rate and bonding size between diamond and SiC, improves the heat dissipation performance of power devices, and reduces the interface thermal resistance between diamond and GaN devices, providing a process flow and solution ideas for the design and manufacture of new diamond-based GaN devices, and has a relatively broad application prospect. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 A flow chart of a method for preparing an ultra-thin SiC / diamond composite wafer by van der Waals bonding provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0035] See also Figure 1 The embodiment of the present invention provides a method for preparing an ultra-thin SiC / diamond composite wafer by van der Waals bonding, comprising the following steps:

[0036] Step 1) forming a graphene layer on a surface of a polycrystalline diamond sheet by vacuum annealing to obtain a diamond / graphene wafer;

[0037] Step 2) forming a graphene layer on a surface of a SiC wafer by vacuum annealing to obtain a SiC / graphene wafer;

[0038] Step 3) H is implanted on the SiC surface of the SiC / graphene wafer by ion implantation. + ion;

[0039] Step 4) Bond the diamond / graphene wafer and the H-implanted + ion bonding of the graphene layer of the SiC / graphene wafer to obtain a bonded wafer;

[0040] Step 5) high temperature stripping of the SiC layer of the bonded wafer to obtain an ultra-thin SiC / diamond composite wafer;

[0041] Step 6) polishing the surface of the SiC layer of the ultra-thin SiC / diamond composite wafer.

[0042] Wherein, the polycrystalline diamond sheet has a thickness of 150 to 300 μm and a size of 4 inches, 6 inches or 8 inches;

[0043] The vacuum annealing temperature of polycrystalline diamond sheet is 600~950℃ and the vacuum degree is 10 -4 ~10 -7 Pa, annealing time is 1 to 2 h, and the catalytic medium is Fe, Ni or Cu;

[0044] The graphene layer formed on the surface of the polycrystalline diamond sheet has a thickness of 100 to 300 nm and a surface flatness of 1 to 3 nm.

[0045] Wherein, the SiC wafer has a thickness of 300-500 μm and a size of 4 inches, 6 inches or 8 inches;

[0046] The vacuum annealing temperature of SiC wafer is 1000~1200℃ and the vacuum degree is 10 -4 ~10 -7 Pa, annealing time is 1 to 2 h, and the catalytic medium is Fe, Ni or Cu;

[0047] The graphene formed on the surface of the SiC wafer has a thickness of 100 to 300 nm and a surface flatness of 1 to 3 nm.

[0048] Among them, H is injected into the SiC surface of the SiC / graphene wafer. + The ion implantation depth is 1 to 10 μm and the implantation dose is 10 16 ~10 20 cm -3 , the injection energy is 90~200keV.

[0049] The bonding temperature during the van der Waals bonding is 100-200° C., and the thickness of the bonding layer is 5-100 nm.

[0050] Since the bonding medium of polycrystalline diamond / graphene wafer and SiC / graphene wafer is graphene slurry when the graphene layer is bonded by van der Waals force, compared with Si 3 N 4 、Al 2 O 3, polymers, metals, etc. as bonding layer media can not only further reduce the interfacial thermal resistance between diamond and SiC, but also greatly reduce the bonding void rate of polycrystalline diamond / graphene wafers and SiC / graphene wafers during bonding, so that the bonding rate of diamond and SiC can reach more than 95%, which is beneficial to the bonding of large-sized polycrystalline diamond and SiC, thereby producing large-sized SiC / diamond composite wafers.

[0051] Furthermore, the diamond / graphene wafer and the H-implanted + Before bonding the graphene layer of the SiC / graphene wafer with ions, the diamond / graphene wafer and the H-implanted + The SiC / graphene wafers with ions were subjected to surface polishing, surface cleaning and chemical wet activation treatment respectively.

[0052] The surface flatness of the polished diamond / graphene wafer is 1-3 nm, and the H injected + The surface flatness of the ion-polished SiC / graphene wafer is 0.1-3 nm;

[0053] Diamond / graphene wafer and H implantation + The surface cleaning of ionic SiC / graphene wafers adopts organic / RCA cleaning method, and SC3 (SPM), SC2 (HPM), SC1 (APM), and BOE solutions are used for cleaning in sequence;

[0054] Chemical wet activation treatment uses plasma or RIE to treat diamond / graphene wafers and implant H + The SiC / graphene wafer surface is plasma treated with ions.

[0055] The high temperature stripping of the SiC layer of the bonded wafer is to place the bonded wafer in a vacuum high temperature environment and inject H + The SiC layer is subjected to high temperature treatment by ionization to peel off the SiC layer. The vacuum degree during high temperature peeling of the SiC layer of the bonded wafer is controlled to be 10 2 ~10 6 Pa, the temperature is controlled at 1000-1200° C., and the SiC layer is peeled off to a thickness of 1-10 μm.

[0056] Since the SiC surface of the SiC / graphene wafer is implanted with a layer of H + ions, therefore, when H + When the SiC / graphene wafer with ions is placed in a vacuum high temperature environment for peeling, H is injected into the SiC layer. +The SiC part outside the ions can be easily peeled off to make the SiC layer thinner, thereby obtaining an ultra-thin SiC / diamond composite wafer, avoiding the risk of wafer breakage during SiC wafer peeling. And through this intelligent peeling method, the SiC thickness of the obtained ultra-thin SiC / diamond composite wafer can be controlled within 1 to 10 μm.

[0057] The ultra-thin SiC / diamond composite wafer prepared by the present invention is used as the epitaxial substrate of the GaN HEMT device, which can greatly reduce the interface thermal resistance between the diamond and the GaN device. Compared with the SiC wafer as the epitaxial substrate of the GaN HEMT device, the thermal resistance of the device can be reduced by 30%-40%, and the power density of the device can be increased by 3-5 times, which effectively solves the heat dissipation problem of the high-power GaN HEMT device.

[0058] The surface polishing of the SiC layer of the ultra-thin SiC / diamond composite wafer is to polish the surface of the peeled SiC layer using a wafer polisher, and to implant H ions into the SiC layer. + The SiC part of the ions is removed, and the surface flatness of the SiC layer after polishing is 1 to 3 nm.

[0059] Since the thermal conductivity of SiC wafer is 490, while the thermal conductivity of polycrystalline diamond is 1500, the ultra-thin SiC / diamond composite wafer prepared by the present invention can increase the thermal conductivity of the composite wafer to 2-3 times, thereby solving the problem of low thermal conductivity and insufficient heat dissipation of SiC. Therefore, the ultra-thin SiC / diamond composite wafer prepared by the present invention is applied to silicon carbide power electronic devices, which can greatly improve the heat dissipation level of silicon carbide power devices.

[0060] In addition, the present invention uses polycrystalline diamond to prepare ultra-thin SiC / diamond composite wafers, and the wafer size of polycrystalline diamond can reach 6 inches and above. Therefore, the ultra-thin SiC / diamond composite wafer prepared by the present invention can increase the bonding size from 2 inches to 8 inches at most, solving the problem that the size of diamond single crystal wafers is small and large-sized microwave power devices cannot be prepared.

[0061] At the same time, the present invention adopts a graphene-graphene van der Waals bonding method, and its bonding belongs to the bonding of intermolecular forces. Compared with the covalent bond force, it can reduce the interface stress by 3 orders of magnitude, greatly reducing the interface stress, and can effectively prevent the problem of easy falling off of the composite wafer.

[0062] The following is a detailed description of a method for preparing an ultra-thin SiC / diamond composite wafer by van der Waals bonding provided by the present invention through examples.

[0063] Example 1

[0064] (1) Pyrolysis of graphene on diamond surface

[0065] A polycrystalline diamond / graphene wafer is obtained by pyrolyzing a surface of a polycrystalline diamond to form a graphene layer by high temperature vacuum annealing. The thickness of the polycrystalline diamond is 150 μm and the size can be 4 inches. The high temperature vacuum annealing temperature is 600°C and the vacuum degree is 10 -4 Pa, the annealing time is 1h, and the catalytic medium is Fe. The thickness of the graphene layer formed by pyrolysis on the surface of polycrystalline diamond is 100nm, and the surface flatness of the formed graphene layer is 1nm.

[0066] (2) Pyrolysis of graphene on SiC surface

[0067] A graphene layer is formed on one surface of a semi-insulating SiC wafer by pyrolysis using a high temperature vacuum annealing method to obtain a SiC / graphene wafer. The thickness of the semi-insulating SiC wafer is 300 μm and the size can be 4 inches. The temperature of the high temperature vacuum annealing is 1000°C and the vacuum degree is 10 -4 Pa, the annealing time is 1h, and the catalytic medium is Fe. The thickness of the graphene layer formed by pyrolysis on the surface of the semi-insulating SiC wafer is 100nm, and the surface flatness of the formed graphene layer is 1nm.

[0068] (3) SiC / graphene surface ion implantation

[0069] H was implanted into the SiC surface of the SiC / graphene wafer by ion implantation. + ions. The ion implantation depth is 1 μm and the implantation dose is 10 16 cm -3 , the injection energy is 90keV.

[0070] (4) Diamond / graphene and SiC / graphene van der Waals bonding

[0071] The polycrystalline diamond / graphene wafer and the SiC / graphene wafer are firstly surface polished respectively. The surface flatness of the diamond / graphene wafer after surface polishing is 1 nm, and the surface flatness of the SiC / graphene wafer after surface polishing is 0.1 nm.

[0072] Then, the surfaces of the polycrystalline diamond / graphene wafer and SiC / graphene wafer after surface polishing were cleaned respectively. The surface cleaning process used an organic / RCA cleaning method, and SC3 (SPM), SC2 (HPM), SC1 (APM), and BOE solutions were used to clean the surfaces of the two wafers respectively.

[0073] The cleaned polycrystalline diamond / graphene wafer and SiC / graphene wafer are then subjected to chemical wet activation treatment, wherein the chemical wet activation treatment process uses plasma to perform plasma treatment on the sample surface.

[0074] Finally, under certain conditions, the activated polycrystalline diamond / graphene wafer and the graphene layer of the SiC / graphene wafer are bonded together by van der Waals bonding to obtain a SiC / diamond composite wafer. The bonding temperature of the graphene layers of the two wafers when bonding together is 100°C, and the bonding layer thickness is 5nm.

[0075] Since the bonding medium of polycrystalline diamond / graphene wafer and SiC / graphene wafer is graphene slurry when the graphene layer is bonded by van der Waals force, compared with Si 3 N 4 、Al 2 O 3 , polymers, metals, etc. as bonding layer media can not only further reduce the interfacial thermal resistance between diamond and SiC, but also greatly reduce the bonding void rate of polycrystalline diamond / graphene wafers and SiC / graphene wafers during bonding, so that the bonding rate of diamond and SiC can reach 97%, which is beneficial to the bonding of large-size polycrystalline diamond and SiC, thereby producing a large-size SiC / diamond composite wafer with a size of 4 inches.

[0076] Moreover, the bonding between the polycrystalline diamond and the SiC wafer in the embodiment of the present invention is the van der Waals bonding of graphene-graphene, which is a bonding through intermolecular forces. Compared with the covalent bonding force, the van der Waals bonding between the polycrystalline diamond / graphene and SiC / graphene in the embodiment of the present invention can reduce the interface stress by 3 orders of magnitude, greatly reducing the interface stress and effectively solving the problem of easy detachment of the composite wafer.

[0077] (5) High temperature peeling of SiC layer

[0078] The SiC / diamond composite wafer is placed in a vacuum high temperature environment to peel off the SiC layer to obtain an ultra-thin SiC / diamond composite wafer. The vacuum degree during vacuum high temperature peeling of the SiC layer of the SiC / diamond composite wafer is 10 2 Pa, temperature 1000° C. The SiC thickness of the obtained ultra-thin SiC / diamond composite wafer can be controlled at 10 μm.

[0079] Since the SiC surface of the SiC / graphene wafer is implanted with a layer of H + ions, therefore, when H + When the SiC / graphene wafer with ions is placed in a vacuum high temperature environment for processing, H is injected into the SiC layer.+ The SiC part outside the ions can be easily stripped off to make the SiC layer thinner, thereby obtaining an ultra-thin SiC / diamond composite wafer, avoiding the risk of wafer breakage during SiC wafer stripping. Moreover, through this intelligent stripping method, the SiC thickness of the obtained ultra-thin SiC / diamond composite wafer can be controlled below 10μm. The ultra-thin SiC / diamond composite wafer can be used as an epitaxial substrate for GaN HEMT devices, which can greatly reduce the interface thermal resistance between diamond and GaN devices, solving the heat dissipation problem of high-power GaN HEMT devices.

[0080] (6) SiC surface polishing

[0081] The SiC layer surface of the ultra-thin SiC / diamond composite wafer after peeling was polished by a wafer polisher, and H ions were implanted into the SiC layer. + The SiC part of the ions is removed, and the polishing flatness of the SiC layer surface of the ultra-thin SiC / diamond composite wafer is 1nm after polishing.

[0082] Since the thermal conductivity of polycrystalline diamond is as high as 1500, the ultra-thin SiC / diamond composite wafer prepared in the embodiment of the present invention can increase the thermal conductivity by 3 times, thereby solving the problem of low thermal conductivity of SiC and insufficient heat dissipation.

[0083] The ultra-thin SiC / diamond composite wafer prepared in the embodiment of the present invention is used as the epitaxial substrate of the GaN HEMT device. Compared with the SiC wafer as the epitaxial substrate of the GaN HEMT device, the thermal resistance of the device can be reduced by 30%, and the power density of the device can be increased by 3 times, which greatly reduces the interface thermal resistance between the diamond and GaN devices and effectively solves the heat dissipation problem of the high-power GaN HEMT device.

[0084] Example 2

[0085] (1) Pyrolysis of graphene on diamond surface

[0086] A polycrystalline diamond / graphene wafer is obtained by pyrolyzing a surface of polycrystalline diamond to form a graphene layer by high temperature vacuum annealing. The thickness of the polycrystalline diamond is 300 μm and the optional size is 8 inches. The high temperature vacuum annealing temperature is 950°C and the vacuum degree is 10 -7 Pa, the annealing time is 2h, and the catalytic medium is Cu. The thickness of the graphene layer formed by pyrolysis on the surface of polycrystalline diamond is 300nm, and the surface flatness of the formed graphene layer is 3nm.

[0087] (2) Pyrolysis of graphene on SiC surface

[0088] A graphene layer is formed on one surface of a semi-insulating SiC wafer by pyrolysis using a high-temperature vacuum annealing method to obtain a SiC / graphene wafer. The thickness of the semi-insulating SiC wafer is 500 μm and the size can be 8 inches. The temperature of the high-temperature vacuum annealing is 1200°C and the vacuum degree is 10 -7 Pa, the annealing time is 2h, and the catalytic medium is Cu. The thickness of the graphene layer formed by pyrolysis on the surface of the semi-insulating SiC wafer is 300nm, and the surface flatness of the formed graphene layer is 3nm.

[0089] (3) SiC / graphene surface ion implantation

[0090] H was implanted into the SiC surface of the SiC / graphene wafer by ion implantation. + ions. The ion implantation depth is 10 μm and the implantation dose is 10 20 cm -3 , the injection energy is 200keV.

[0091] (4) Diamond / graphene and SiC / graphene van der Waals bonding

[0092] The polycrystalline diamond / graphene wafer and the SiC / graphene wafer are first surface polished respectively. The surface flatness of the diamond / graphene wafer after surface polishing is 3 nm, and the surface flatness of the SiC / graphene wafer after surface polishing is 3 nm.

[0093] Then, the surfaces of the polycrystalline diamond / graphene wafer and SiC / graphene wafer after surface polishing were cleaned respectively. The surface cleaning process used an organic / RCA cleaning method, and SC3 (SPM), SC2 (HPM), SC1 (APM), and BOE solutions were used to clean the surfaces of the two wafers respectively.

[0094] The cleaned polycrystalline diamond / graphene wafer and SiC / graphene wafer are then subjected to chemical wet activation treatment, wherein the chemical wet activation treatment process uses RIE to perform plasma treatment on the sample surface.

[0095] Finally, under certain conditions, the activated polycrystalline diamond / graphene wafer and the graphene layer of the SiC / graphene wafer are bonded together by van der Waals bonding to obtain a SiC / diamond composite wafer. The bonding temperature of the graphene layers of the two wafers when bonding together is 200°C, and the bonding layer thickness is 100nm.

[0096] Since the bonding medium of polycrystalline diamond / graphene wafer and SiC / graphene wafer is graphene slurry when the graphene layer is bonded by van der Waals force, compared with Si 3 N 4、Al 2 O 3 , polymers, metals, etc. as bonding layer media can not only further reduce the interfacial thermal resistance between diamond and SiC, but also greatly reduce the bonding void rate of polycrystalline diamond / graphene wafers and SiC / graphene wafers during bonding, and can make the bonding rate of diamond and SiC reach 96%, which is beneficial to the bonding of large-size polycrystalline diamond and SiC, thereby producing large-size SiC / diamond composite wafers with a size of 8 inches.

[0097] Moreover, the bonding between the polycrystalline diamond and the SiC wafer in the embodiment of the present invention is the van der Waals bonding of graphene-graphene, which is a bonding through intermolecular forces. Compared with the covalent bonding force, the van der Waals bonding between the polycrystalline diamond / graphene and SiC / graphene in the embodiment of the present invention can reduce the interface stress by 3 orders of magnitude, greatly reducing the interface stress and effectively solving the problem of easy detachment of the composite wafer.

[0098] (5) High temperature peeling of SiC layer

[0099] The SiC / diamond composite wafer is placed in a vacuum high temperature environment to peel off the SiC layer to obtain an ultra-thin SiC / diamond composite wafer. The vacuum degree during vacuum high temperature peeling of the SiC layer of the SiC / diamond composite wafer is 10 6 Pa, temperature 1200° C. The SiC thickness of the obtained ultra-thin SiC / diamond composite wafer can be controlled at 1 μm.

[0100] Since the SiC surface of the SiC / graphene wafer is implanted with a layer of H + ions, therefore, when H + When the SiC / graphene wafer with ions is placed in a vacuum high temperature environment for peeling, H is injected into the SiC layer. + The SiC part outside the ions can be easily stripped off to make the SiC layer thinner, thereby obtaining an ultra-thin SiC / diamond composite wafer, avoiding the risk of wafer breakage during SiC wafer stripping. Moreover, through this intelligent stripping method, the SiC thickness of the obtained ultra-thin SiC / diamond composite wafer can be controlled below 10μm. The ultra-thin SiC / diamond composite wafer can be used as an epitaxial substrate for GaN HEMT devices, which can greatly reduce the interface thermal resistance between diamond and GaN devices, solving the heat dissipation problem of high-power GaN HEMT devices.

[0101] (6) SiC surface polishing

[0102] The SiC layer surface of the ultra-thin SiC / diamond composite wafer after peeling was polished by a wafer polisher, and H ions were implanted into the SiC layer. +The SiC part of the ions is removed, and the polishing flatness of the SiC layer surface of the ultra-thin SiC / diamond composite wafer is 3nm after polishing.

[0103] Since the thermal conductivity of polycrystalline diamond is as high as 1500, the ultra-thin SiC / diamond composite wafer prepared in the embodiment of the present invention can increase the thermal conductivity to 2.5 times, thereby solving the problem of low thermal conductivity of SiC and insufficient heat dissipation.

[0104] The ultra-thin SiC / diamond composite wafer prepared in the embodiment of the present invention is used as the epitaxial substrate of the GaN HEMT device. Compared with the SiC wafer as the epitaxial substrate of the GaN HEMT device, the thermal resistance of the device can be reduced by 40%, and the power density of the device can be increased by 5 times, which greatly reduces the interface thermal resistance between the diamond and GaN devices and effectively solves the heat dissipation problem of the high-power GaN HEMT device.

[0105] Example 3

[0106] (1) Pyrolysis of graphene on diamond surface

[0107] A polycrystalline diamond / graphene wafer is obtained by pyrolyzing a surface of polycrystalline diamond to form a graphene layer by high temperature vacuum annealing. The thickness of the polycrystalline diamond is 200 μm and the optional size is 6 inches. The high temperature vacuum annealing temperature is 800°C and the vacuum degree is 10 -6 Pa, the annealing time is 1.5h, and the catalytic medium is Ni. The thickness of the graphene layer formed by pyrolysis on the surface of polycrystalline diamond is 200nm, and the surface flatness of the formed graphene layer is 2nm.

[0108] (2) Pyrolysis of graphene on SiC surface

[0109] A graphene layer is formed on one surface of a semi-insulating SiC wafer by pyrolysis using a high-temperature vacuum annealing method to obtain a SiC / graphene wafer. The thickness of the semi-insulating SiC wafer is 300-500 μm, and the size can be 6 inches. The temperature of the high-temperature vacuum annealing is 1100°C, and the vacuum degree is 10 -6 Pa, annealing time is 1.5h, catalytic medium is Ni. The thickness of the graphene layer formed by pyrolysis on the surface of the semi-insulating SiC wafer is 200nm, and the surface flatness of the formed graphene layer is 2nm.

[0110] (3) SiC / graphene surface ion implantation

[0111] H was implanted into the SiC surface of the SiC / graphene wafer by ion implantation. + The ion implantation depth is 5 μm and the implantation dose is 10 18 cm -3 , the injection energy is 150keV.

[0112] (4) Diamond / graphene and SiC / graphene van der Waals bonding

[0113] The polycrystalline diamond / graphene wafer and the SiC / graphene wafer are firstly surface polished respectively. The surface flatness of the diamond / graphene wafer after surface polishing is 2 nm, and the surface flatness of the SiC / graphene wafer after surface polishing is 1 nm.

[0114] Then, the surfaces of the polycrystalline diamond / graphene wafer and SiC / graphene wafer after surface polishing were cleaned respectively. The surface cleaning process used an organic / RCA cleaning method, and SC3 (SPM), SC2 (HPM), SC1 (APM), and BOE solutions were used to clean the surfaces of the two wafers respectively.

[0115] The cleaned polycrystalline diamond / graphene wafer and SiC / graphene wafer are then subjected to chemical wet activation treatment, wherein the chemical wet activation treatment process uses plasma to perform plasma treatment on the sample surface.

[0116] Finally, under certain conditions, the activated polycrystalline diamond / graphene wafer and the graphene layer of the SiC / graphene wafer are bonded together by van der Waals bonding to obtain a SiC / diamond composite wafer. The bonding temperature of the graphene layers of the two wafers when bonding together is 150°C, and the bonding layer thickness is 60nm.

[0117] Since the bonding medium of polycrystalline diamond / graphene wafer and SiC / graphene wafer is graphene slurry when the graphene layer is bonded by van der Waals force, compared with Si 3 N 4 、Al 2 O 3 , polymers, metals, etc. as bonding layer media can not only further reduce the interface thermal resistance between diamond and SiC, but also greatly reduce the bonding void rate of polycrystalline diamond / graphene wafers and SiC / graphene wafers during bonding, so that the bonding rate of diamond and SiC can reach 96%, which is beneficial to the bonding of large-size polycrystalline diamond and SiC, thereby producing a large-size SiC / diamond composite wafer with a size of 6 inches.

[0118] Moreover, the bonding between the polycrystalline diamond and the SiC wafer in the embodiment of the present invention is the van der Waals bonding of graphene-graphene, which is a bonding through intermolecular forces. Compared with the covalent bonding force, the van der Waals bonding between the polycrystalline diamond / graphene and SiC / graphene in the embodiment of the present invention can reduce the interface stress by 3 orders of magnitude, greatly reducing the interface stress and effectively solving the problem of easy detachment of the composite wafer.

[0119] (5) High temperature peeling of SiC layer

[0120] The SiC / diamond composite wafer is placed in a vacuum high temperature environment to peel off the SiC layer to obtain an ultra-thin SiC / diamond composite wafer. The vacuum degree during vacuum high temperature peeling of the SiC layer of the SiC / diamond composite wafer is 10 4 Pa, temperature 1100° C. The SiC thickness of the obtained ultra-thin SiC / diamond composite wafer can be controlled at 5 μm.

[0121] Since the SiC surface of the SiC / graphene wafer is implanted with a layer of H + ions, therefore, when H + When the SiC / graphene wafer with ions is placed in a vacuum high temperature environment for peeling, H is injected into the SiC layer. + The SiC part outside the ions can be easily stripped off to make the SiC layer thinner, thereby obtaining an ultra-thin SiC / diamond composite wafer, avoiding the risk of wafer breakage during SiC wafer stripping. Moreover, through this intelligent stripping method, the SiC thickness of the obtained ultra-thin SiC / diamond composite wafer can be controlled below 10μm. The ultra-thin SiC / diamond composite wafer can be used as an epitaxial substrate for GaN HEMT devices, which can greatly reduce the interface thermal resistance between diamond and GaN devices, solving the heat dissipation problem of high-power GaN HEMT devices.

[0122] (6) SiC surface polishing

[0123] The SiC layer surface of the ultra-thin SiC / diamond composite wafer after peeling was polished by a wafer polisher, and H ions were implanted into the SiC layer. + The SiC part of the ions is removed, and the polishing flatness of the SiC layer surface of the ultra-thin SiC / diamond composite wafer is 2nm after polishing.

[0124] Since the thermal conductivity of polycrystalline diamond is as high as 1500, the ultra-thin SiC / diamond composite wafer prepared in the embodiment of the present invention can increase the thermal conductivity by 2 times, thereby solving the problem of low thermal conductivity of SiC and insufficient heat dissipation.

[0125] The ultra-thin SiC / diamond composite wafer prepared in the embodiment of the present invention is used as the epitaxial substrate of the GaN HEMT device. Compared with the SiC wafer as the epitaxial substrate of the GaN HEMT device, the thermal resistance of the device can be reduced by 35%, and the power density of the device can be increased by 4 times, which greatly reduces the interface thermal resistance between the diamond and GaN devices and effectively solves the heat dissipation problem of the high-power GaN HEMT device.

[0126] Finally, it should be noted that the above specific implementation methods are only used to illustrate the technical solution of the present invention rather than to limit it. Although the present invention has been described in detail with reference to examples, those skilled in the art should understand that the technical solution of the present invention can be modified or replaced by equivalents without departing from the spirit and scope of the technical solution of the present invention, which should be included in the scope of the claims of the present invention.

Claims

1. A method for preparing ultra-thin SiC / diamond composite wafers by van der Waals bonding, characterized in that: The steps include: A diamond / graphene wafer is obtained by forming a graphene layer on a surface of a polycrystalline diamond sheet through vacuum annealing; A SiC / graphene wafer is obtained by forming a graphene layer on one surface of a SiC wafer through vacuum annealing; H is implanted on the SiC surface of the SiC / graphene wafer by ion implantation. + ion; The diamond / graphene wafer and the H-implanted + ion bonding of the graphene layer of the SiC / graphene wafer to obtain a bonded wafer; The SiC layer of the bonded wafer is peeled off at high temperature to obtain an ultra-thin SiC / diamond composite wafer; Polishing of SiC layer surface of ultra-thin SiC / diamond composite wafer.

2. The method for preparing an ultra-thin SiC / diamond composite wafer by van der Waals bonding according to claim 1, characterized in that The vacuum annealing temperature of the polycrystalline diamond sheet is 600-950° C., the graphene layer formed on the surface of the polycrystalline diamond sheet has a thickness of 100-300 nm, and a surface flatness of 1-3 nm.

3. The method for preparing an ultra-thin SiC / diamond composite wafer by van der Waals bonding according to claim 1, characterized in that: The vacuum annealing temperature of the SiC wafer is 1000-1200° C., the graphene formed on the surface of the SiC wafer has a thickness of 100-300 nm, and a surface flatness of 1-3 nm.

4. The method for preparing an ultra-thin SiC / diamond composite wafer by van der Waals bonding according to claim 1, characterized in that: The ion implantation depth is 1 to 10 μm, and the implantation dose is 10 16 ~10 20 cm -3 , the injection energy is 90~200keV.

5. The method for preparing an ultra-thin SiC / diamond composite wafer by van der Waals bonding according to claim 1, characterized in that: The bonding temperature during the van der Waals bonding is 100-200° C., and the thickness of the bonding layer formed by the van der Waals bonding is 5-100 nm.

6. The method for preparing ultra-thin SiC / diamond composite wafer by van der Waals bonding according to claim 5, characterized in that: Before the van der Waals bonding, the diamond / graphene wafer and the H- + The SiC / graphene wafers with ions were subjected to surface polishing, surface cleaning and chemical wet activation treatment respectively.

7. The method for preparing an ultra-thin SiC / diamond composite wafer by van der Waals bonding according to claim 6, characterized in that: The surface flatness of the diamond / graphene wafer after polishing is 1-3 nm, and the H injected + The surface flatness of the ion-polished SiC / graphene wafer is 0.1 to 3 nm.

8. The method for preparing ultra-thin SiC / diamond composite wafer by van der Waals bonding according to claim 1, characterized in that: The high temperature stripping of the SiC layer of the bonded wafer is to place the bonded wafer in a vacuum high temperature environment and inject H + The high temperature treatment of the SiC layer by ions causes the SiC layer to be peeled off.

9. The method for preparing an ultra-thin SiC / diamond composite wafer by van der Waals bonding according to claim 8, characterized in that: The vacuum degree of the SiC layer of the bonded wafer is controlled to be 10 2 ~10 6 Pa, the temperature is controlled at 1000-1200° C., and the SiC layer is peeled off to a thickness of 1-10 μm.

10. The method for preparing an ultra-thin SiC / diamond composite wafer by van der Waals bonding according to claim 9, characterized in that: The SiC layer surface polishing treatment of the ultra-thin SiC / diamond composite wafer is to polish the surface of the peeled SiC layer using a wafer polishing machine, and the surface flatness of the SiC layer after the polishing treatment is 1-3nm.

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