Memory

Abstract

The embodiment of the invention discloses a memory, and the memory comprises a substrate which is internally provided with a heat dissipation structure; and the semiconductor structure is positioned on the substrate.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a memory. Background Art

[0002] With the continuous development of semiconductor process technology, the critical dimension (CD) of devices is getting smaller and smaller, and the integration of chips is getting higher and higher. The high integration makes the chip generate a lot of heat when working, and the temperature rise caused by the heat will affect the performance of the chip. For highly integrated chips, heat dissipation becomes very difficult. The common multi-layer stacked structure has more chips, and the density of the chip working area is more concentrated. If the heat generated during operation cannot be dissipated in time and effectively, it will gradually accumulate, accelerate chip aging, and even cause chip failure in severe cases. Summary of the invention

[0003] In view of this, an embodiment of the present disclosure provides a memory.

[0004] An embodiment of the present disclosure provides a memory, comprising: a substrate, in which a heat dissipation structure is arranged; and a semiconductor structure located on the substrate.

[0005] In an optional embodiment, the substrate includes a first region and a second region, the operating temperature of the semiconductor structure in the first region is higher than the operating temperature in the second region, and the arrangement density of the heat dissipation structure in the first region is greater than the arrangement density in the second region.

[0006] In an optional implementation, the intervals between the heat dissipation structures in the first region are smaller than the intervals in the second region, and / or the size of the heat dissipation structure in the first region is larger than the size in the second region.

[0007] In an optional embodiment, the heat dissipation channel includes a first sub-channel and a second sub-channel alternately connected to each other; wherein, a plurality of the first sub-channels are arranged parallel to each other along a first direction parallel to the surface of the substrate; and an angle between the first sub-channel and the second sub-channel is greater than or equal to 90 degrees.

[0008] In an optional embodiment, the spacing between adjacent first sub-channels located in the first region is smaller than the spacing between adjacent first sub-channels located in the second region, and / or, along a second direction parallel to the substrate surface, the size of the first sub-channel located in the first region is larger than the size of the first sub-channel located in the second region; wherein the first direction intersects with the second direction.

[0009] In an optional embodiment, the heat dissipation structure includes at least one heat dissipation channel; wherein the inlet end and the outlet end of the heat dissipation channel are located on the same side or different sides of the substrate along a first direction parallel to the surface of the substrate.

[0010] In an optional embodiment, the heat dissipation structure includes a first heat dissipation channel and a second heat dissipation channel; wherein, the outlet end of the first heat dissipation channel and the inlet end of the second heat dissipation channel are located on the first side of the substrate along the first direction, and the inlet end of the first heat dissipation channel and the outlet end of the second heat dissipation channel are located on the second side of the substrate along the first direction.

[0011] In an optional embodiment, in a cross section parallel to the surface of the substrate, the cross-sectional shape of the heat dissipation structure is at least one of a bow-shaped structure, a wave-shaped structure or a U-shaped structure.

[0012] In an optional implementation, the memory further includes: an interconnection layer located between the heat dissipation structure and the semiconductor structure.

[0013] In an optional embodiment, the heat dissipation structure is used to conduct the heat in the memory to the outside of the memory by using a coolant; wherein the coolant is a cooling gas or a cooling liquid.

[0014] In the technical solution provided in the embodiment of the present disclosure, a heat dissipation structure is provided in the substrate to dissipate heat. On the one hand, the heat dissipation effect inside the memory is effectively improved to avoid the influence of overheating on the performance and life of the memory. On the other hand, the heat dissipation structure is embedded in the substrate and does not occupy additional space, which is conducive to improving the integration of the memory.

[0015] The details of one or more embodiments of the present disclosure are set forth in the accompanying drawings and the description below. Other features and advantages of the present disclosure will become apparent from the description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0017] Figure 1 is a schematic diagram of a chip packaging structure according to an exemplary embodiment;

[0018] Figure 2A A cross-sectional view of a memory device according to an embodiment of the present disclosure Figure 1 ;

[0019] Figure 2B A second cross-sectional schematic diagram of a memory provided in accordance with an embodiment of the present disclosure;

[0020] Figure 2C A schematic top view of a memory device according to an embodiment of the present disclosure Figure 1 ;

[0021] Figure 3 A second schematic top view of a memory provided in an embodiment of the present disclosure;

[0022] Figure 4 A schematic top view of a memory device according to an embodiment of the present disclosure Figure 3 ;

[0023] Figure 5 A schematic top view of a memory device according to an embodiment of the present disclosure Figure 4 ;

[0024] Figure 6 A schematic top view of a memory device according to an embodiment of the present disclosure Figure 5 ;

[0025] Fig. 7A A schematic top view of a memory device according to another embodiment of the present disclosure Figure 6 ;

[0026] Figure 7B A cross-sectional view of a memory device according to another embodiment of the present disclosure Figure 1 ;

[0027] Figure 7C A second cross-sectional schematic diagram of a memory provided in accordance with another embodiment of the present disclosure;

[0028] Fig.7D A schematic top view of a memory device according to another embodiment of the present disclosure is shown in FIG7;

[0029] Fig. 8A FIG8 is a top view schematic diagram of a memory provided by another embodiment of the present disclosure;

[0030] Figure 8B A cross-sectional view of a memory provided in another embodiment of the present disclosure Figure 1 ;

[0031] Figure 8C A second cross-sectional schematic diagram of a memory provided in yet another embodiment of the present disclosure;

[0032] Fig.8D A schematic top view of a memory device according to another embodiment of the present disclosure Figure 9 ;

[0033] Fig. 9A schematic diagram of a specific implementation flow of a method for forming a memory provided in an embodiment of the present disclosure;

[0034] Fig.10 A schematic diagram of a memory system according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0035] The technical solution of the present disclosure will be further described in detail below in conjunction with the accompanying drawings and embodiments. Although the exemplary implementation methods of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the implementation methods described here. On the contrary, these implementation methods are provided in order to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0036] The present disclosure is described in more detail in the following paragraphs by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will become clearer from the following description. It should be noted that the accompanying drawings are in a very simplified form and are not in exact proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present disclosure.

[0037] It should be understood that spatial relationship terms such as "under", "below", "below", "under", "above", "above", etc., may be used here for convenience of description to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientation shown in the figure, the spatial relationship terms are intended to also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, then the elements or features described as "under other elements" or "under it" or "under it" will be oriented as "on" other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0038] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be a limitation of the present disclosure. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0039] It should be noted that the technical solutions described in the embodiments of the present disclosure can be arbitrarily combined without conflict.

[0040] The commonly used heat dissipation technology at present is to install heat sinks, cooling fans, etc. on the packaging shell of the chip after packaging to promote heat dissipation. However, with the continuous increase in chip integration, the heat dissipation efficiency of the above method is low. When the chip is used for a long time, it may still cause overheating and damage to the chip.

[0041] Figure 1 FIG. 1 is a schematic diagram of a chip packaging structure according to an exemplary embodiment. Figure 1 As shown, the chip packaging structure includes a substrate 100 , solder balls 101 , a chip 102 , a first thermal interface material (TIM) 103 , a heat sink 104 , a second thermal interface material 105 and a heat sink (HS) 106 .

[0042] In some embodiments, the heat sink 106 is used to prevent the chip package structure from overheating. Exemplarily, the material of the heat sink 106 includes but is not limited to copper (Cu) or copper alloy.

[0043] In some embodiments, the first thermal interface material 103 and the second thermal interface material 105 are used to fill the micro gaps and holes on the uneven surface generated when the two materials are joined or contacted, reduce the impedance of heat transfer, and improve heat dissipation. Exemplarily, the first thermal interface material 103 and the second thermal interface material 105 include but are not limited to thermal grease or thermal adhesive.

[0044] like Figure 1 As shown in the figure, the heat conduction on the chip surface needs to pass through a large number of intermediate thermal resistors such as thermal grease and heat sinks, and because a variety of heterogeneous materials are integrated, a large number of parasitic problems such as thermal mismatch are easily generated. Due to the existence of a large number of interface thermal resistances, the heat dissipation performance is seriously affected. In addition, the above heat dissipation method is to dissipate heat for the entire chip, and the heat dissipation effect inside the chip is very limited. It cannot effectively solve the uneven heat distribution inside the chip due to the existence of high heat flux density points, as well as the performance degradation and reliability problems caused by the uneven heat distribution.

[0045] In this regard, the present disclosure proposes the following implementation modes.

[0046] The present disclosure provides a memory device, such as Figure 2A and Figure 2B As shown, the memory includes: a substrate 200 , in which a heat dissipation structure 201 is arranged; and a semiconductor structure 203 located on the substrate 200 .

[0047] Exemplarily, the material of the substrate 200 may include a single semiconductor material, such as silicon (Si), germanium (Ge), etc., or a compound semiconductor material, such as gallium nitride (GaN), gallium arsenide (GaAs) or indium phosphide (InP), etc. The substrate may include doping, or include doped regions and undoped regions in the substrate. The substrate may also include silicon-on-insulator (SOI), germanium-on-insulator (GOI), silicon-germanium-on-insulator (SGOI,) or a combination thereof. Other substrates that may also be used include multilayer substrates, gradient substrates or mixed direction substrates.

[0048] In some embodiments, the heat dissipation structure 201 is used to conduct heat in the memory to the outside of the memory using a coolant.

[0049] In some embodiments, the coolant is a cooling gas or a cooling liquid.

[0050] In some embodiments, the cooling gas includes one or more of helium, argon, nitrogen, and sulfur hexafluoride.

[0051] In some embodiments, the cooling liquid may include one or more of deionized water, liquid metal, chlorofluorocarbons (CFC), hydrochlorofluorocarbons (HCFC), hydrofluorocarbons (HFC), perfluorocarbons (PFC), hydrofluoroethers (HFE), and perfluoropolyethers (PFPE).

[0052] The liquid metal includes but is not limited to gallium, gallium-indium alloy or gallium-indium-tin alloy that is liquid at room temperature.

[0053] In some embodiments, Figure 2A and Figure 2B As shown, the memory further includes an interconnect layer 202 located between the heat dissipation structure 201 and the semiconductor structure 203. The interconnect layer 202 can be used to transmit electrical signals between the components of the semiconductor structure, and can also be used to further conduct the heat generated by the semiconductor structure to the heat dissipation structure in the substrate to improve the overall heat dissipation effect, and can also be used to play a supporting role to enhance the stability of the memory structure.

[0054] In some specific embodiments, the material of the interconnection layer 202 includes, but is not limited to, metal materials such as copper, aluminum, nickel, tungsten, silver, gold, and titanium.

[0055] In some embodiments, the projection of the semiconductor structure in a plane parallel to the substrate is located within the projection of the heat dissipation structure in a plane parallel to the substrate. In this way, the corresponding relationship between the semiconductor structure and the heat dissipation structure can ensure that there is enough heat dissipation structure to dissipate the heat generated by the semiconductor structure.

[0056] In some embodiments, the substrate includes a first region and a second region, the operating temperature of the semiconductor structure in the first region is higher than that in the second region, and the arrangement density of the heat dissipation structure in the first region is greater than that in the second region.

[0057] like Figure 2A As shown, the substrate 200 includes a first region 200-1 and a second region 200-2, the operating temperature of the semiconductor structure in the first region 200-1 is higher than the operating temperature in the second region 200-2, and the setting density of the heat dissipation structure 201 in the first region 200-1 is greater than the setting density in the second region 200-2. It can be understood that, based on the fact that the heat dissipation demand of the first region 200-1 is greater than the heat dissipation demand of the second region 200-2, the setting densities of the heat dissipation structure 201 in the first region 200-1 and the second region 200-2 are differentiated to avoid using too many resources in areas with low heat dissipation demand, so as to meet the heat dissipation requirements of different regions in an efficient and energy-saving manner. It should be noted that the substrate can be divided into regions according to the differences in the operating temperatures of device structures (such as semiconductor structures) in different regions of the substrate in actual situations. Here Figure 2A The division of the first area 200 - 1 and the second area 200 - 2 is only an example and should not overly limit the protection scope of the present disclosure.

[0058] In some embodiments, the spacing of the heat dissipation structures in the first region is smaller than that in the second region, and / or the size of the heat dissipation structures in the first region is larger than that in the second region.

[0059] In some embodiments, Figure 2A As shown, the spacing of the heat dissipation structures 201 in the first region is smaller than that in the second region.

[0060] In some embodiments, the size of the heat dissipation structure in the first region is larger than the size in the second region. Figure 5 As shown, the heat dissipation structure includes a heat dissipation channel 206. Along a second direction (Y direction) parallel to the surface of the substrate 200, the heat dissipation channel 206 of the heat dissipation structure has a larger size in the first area 200-1 than in the second area 200-2.

[0061] In some embodiments, the spacing of the heat dissipation structures in the first region is smaller than the spacing in the second region, and the size of the heat dissipation structures in the first region is larger than the size in the second region. Figure 6 As shown, the heat dissipation structure includes a heat dissipation channel 206, the interval between the heat dissipation channels 206 of the heat dissipation structure in the first area 200-1 is smaller than the interval in the second area 200-2, and the size of the heat dissipation channel 206 of the heat dissipation structure in the first area 200-1 along the second direction is larger than the size in the second area 200-2.

[0062] In each embodiment of the present disclosure, the term "setting density" can be understood as the proportion of the area of ​​the heat dissipation structure within a unit area. If the size of the heat dissipation structure within a unit area is larger or the interval is smaller, it can be considered that the setting density of the heat dissipation structure is larger.

[0063] In some embodiments, the memory includes but is not limited to selector only memory (SOM), phase change memory (PCM), ferroelectric random access memory (FeRAM), magnetic memory (MRAM), resistive random access memory (RRAM), NAND memory, etc.

[0064] Among them, selector-only memory has the advantages of simple structure, high miniaturization, fast data read and write speed, good cycle life, vertical stacking, low write crosstalk caused by thermal effects, etc. It has obvious advantages and good application prospects in the fields of high-speed interconnect technology (Compute Express Link, CXL), high-bandwidth memory (High Bandwidth Memory, HBM), etc. Since selector-only memory has a large current density after being turned on and has a high storage density, it has a high heat dissipation requirement.

[0065] In some embodiments, the memory is a selector-only memory; the semiconductor structure includes a first storage array structure located in the first area and a second storage array structure located in the second area. Exemplarily, the first storage array structure undertakes high-speed, high-frequency storage operations, and is commonly used for cache storage, real-time data processing, high-performance storage areas, and storage of operating system applications. It focuses on providing high-speed read and write capabilities and is suitable for processing data with high access frequency. The second storage array structure undertakes low-frequency, low-speed storage tasks and is mainly used in scenarios such as cold data storage, long-term archiving, configuration storage, and logging. It focuses on data reliability and stability and is suitable for processing data with low access frequency and long-term storage.

[0066] In some embodiments, the storage cells of the first storage array structure are arranged more densely and undertake high-frequency, high-speed storage tasks, which leads to more frequent heat generation. Therefore, the operating temperature of the first storage array structure is higher than the operating temperature of the second storage array structure.

[0067] In some embodiments, the memory is a selector-only memory; the semiconductor structure includes a memory array structure located in a first region and a peripheral circuit structure located in a second region.

[0068] In some embodiments, the first area can be understood as the array area, and the second area can be understood as the peripheral area. The structure in the array area (e.g., storage array structure) operates at a higher frequency than the structure in the peripheral area (e.g., peripheral circuit structure) and undertakes core computing or storage tasks, with a greater load, and thus generates higher heat. In addition, due to its dense arrangement of devices in the array area, the heat dissipation conditions are relatively poor, making it more difficult to effectively dissipate heat, while the peripheral area usually has fewer devices and more space for heat dissipation. Therefore, the operating temperature of the semiconductor structure in the first area is higher than the operating temperature in the second area.

[0069] like Figure 2A As shown, the semiconductor structure 203 includes a memory array structure 203 - 1 in a first region 200 - 1 and a peripheral circuit structure 203 - 2 in a second region 200 - 2 .

[0070] In some embodiments, the memory cell in the memory array structure 203 - 1 includes a first electrode 212 , a gating layer 214 , and a second electrode 216 that are sequentially stacked along a direction perpendicular to the surface of the substrate 200 .

[0071] In some embodiments, the bit line 210 contacts the first electrode 212 , and the word line 218 contacts the second electrode 216 .

[0072] In some embodiments, the peripheral circuit 203-2 may include any suitable digital, analog and / or mixed signal circuits for facilitating the operation of the memory. For example, the peripheral circuit 203-2 may include control logic, a data buffer, a decoder (a decoder may also be referred to as a decoder), a driver, and a read / write circuit. When the control logic receives a read / write operation command and address data, under the action of the control logic, the decoder may apply the corresponding voltage generated by the driver to the corresponding word line and bit line based on the decoded address to implement the data read operation or write operation, and perform data interaction with the outside through the data buffer. Exemplarily, after receiving the read operation or write operation command and address data, the control logic may determine the selected word line and the selected bit line corresponding to the selected storage cell in the plurality of storage cells under the action of the decoder. Exemplarily, the storage cell may be controlled by a row decoder and a column decoder. Specifically: the row decoder may receive a row address from the controller and activate the appropriate word line based on the received row address. The column decoder may receive a column address from the controller and activate the appropriate bit line, and may activate the storage cell at the intersection of the word line and the bit line.

[0073] In some embodiments, only the selector memory has both storage and switching functions, that is, the material of the selection layer 214 of the selector memory is a dual-function material (DFM). Exemplarily, the material of the selection layer 214 may include any appropriate bidirectional threshold switch (OTS) material, which may include chalcogenide alloys such as germanium (Ge), arsenic (As) and selenium (Se) and their compounds; the first electrode 212 and the second electrode 216 may be the same material or different materials, and the materials of the first electrode and the second electrode include but are not limited to copper (Cu), aluminum (Al), gold (Au), tungsten (W), carbon (C) and its compounds, conductive doped semiconductors, etc.

[0074] In some embodiments, when a memory such as a SOM device performs a write operation, each memory cell can be programmed to store two storage states represented as logic "1" (low resistance state, SET state) and logic "0" (high resistance state, RESET state). A forward pulse is applied to the selected memory cell to cause the elements in the OTS material to achieve forward migration or forward polarization. This process is called a SET process, or a SET operation. A reverse pulse (or negative pulse) is applied to the selected memory cell to cause the elements in the OTS material to achieve reverse migration or reverse polarization. This process is called a RESET process, or a RESET operation. In other devices, more than two states can be stored, which will not be described in detail here.

[0075] In some embodiments, during the read operation, the SOM device can obtain data by applying a pulse voltage between the SET and RESET state threshold transition voltages, i.e., a read voltage VRead, to the memory cell to measure the resistance values ​​of the two states of the OTS material in the memory cell. It should be understood that the storage state of the SOM device is generally not changed if the read voltage is read a small number of times.

[0076] It should be noted that Figure 2A The number of layers of the storage unit in the figure is only an example and should not overly limit the protection scope of the present disclosure. The higher the integration of the memory, the more layers of the storage unit.

[0077] The disclosed embodiments allow the heat generated by the semiconductor structure to be dissipated not only through conductive lines (such as bit lines or word lines) and surrounding dielectric materials, but also through a heat dissipation structure provided within the substrate, thereby effectively increasing the heat dissipation path within the memory.

[0078] In addition, the setting of the heat dissipation structure in the embodiment of the present disclosure is conducive to effective heat dissipation of the substrate or the lower layer of the multi-layer stacked structure, reducing the temperature difference between the upper storage unit and the bottom storage unit, thereby improving the device consistency, and effectively improving the problem of uneven heat distribution caused by the large temperature difference between the storage array structure located on the upper layer and the storage array located on the lower layer when the number of storage units of the memory is large.

[0079] In some embodiments, the heat dissipation structure includes at least one heat dissipation channel; wherein an inlet end and an outlet end of the heat dissipation channel are located on the same side or different sides of the substrate along a first direction parallel to a surface of the substrate.

[0080] In some embodiments, Figure 2C As shown, the heat dissipation structure includes a heat dissipation channel 206. The inlet end 204 and the outlet end 205 of the heat dissipation channel 206 are located on different sides of the substrate 200 along a first direction (X direction) parallel to the substrate surface.

[0081] here, Figure 2C for Figure 2A A top view of the memory shown, Figure 2C Other structures except the substrate and heat dissipation structure are omitted. Figure 2C Designed to showcase Figure 2A The inlet and outlet locations of the heat dissipation channel of the heat dissipation structure are not shown. Figure 2A The changes in the spacing of the heat dissipation structures in different areas. Please refer to Figure 2A, in order to better understand the interval change of the heat dissipation structure in the first area and the second area. It should be noted that in actual use, the setting density of the heat dissipation channel can be adjusted according to the working temperature of different areas to meet the heat dissipation requirements of different areas. Figure 2A The setting density of the heat dissipation structure in is only an example, and the protection scope of the present disclosure should not be excessively limited here.

[0082] It should be noted that, here and below, the first direction and the second direction are parallel to the substrate surface, the third direction is perpendicular to the substrate surface, the first direction and the second direction intersect each other, and in some specific embodiments, the first direction is perpendicular to the second direction. Exemplarily, the first direction may be the extension direction of the X-axis shown in the drawings, the second direction may be the extension direction of the Y-axis shown in the drawings, and the third direction may be the extension direction of the Z-axis shown in the drawings.

[0083] In the disclosed embodiment, the inlet and outlet of the heat dissipation channel are located on different sides of the substrate along the first direction (X direction), so that the coolant flows evenly throughout the heat dissipation channel, reducing local heat accumulation, preventing overheating, and helping to improve the problem of uneven heat distribution. In addition, the flow path of the coolant can be optimized to avoid backflow or blockage, enhance the airflow circulation in the heat dissipation channel, and improve the heat dissipation performance.

[0084] In some embodiments, the heat dissipation channel includes a first sub-channel and a second sub-channel alternately connected to each other; wherein a plurality of the first sub-channels are arranged parallel to each other along a first direction parallel to the surface of the substrate; and an angle between the first sub-channel and the second sub-channel is greater than or equal to 90 degrees.

[0085] In some embodiments, the angle between the first sub-channel and the second sub-channel may be 120 degrees, 110 degrees, 100 degrees or 90 degrees.

[0086] In some embodiments, Figure 2C As shown, the heat dissipation channel 206 includes first sub-channels 206-1 and second sub-channels 206-2 that are alternately connected to each other; wherein a plurality of first sub-channels 206-1 are arranged parallel to each other along a first direction; and an angle between the first sub-channels 206-1 and the second sub-channels 206-2 is equal to 90 degrees.

[0087] In other embodiments, Figure 3 As shown, the inlet end 204 and the outlet end 205 of the heat dissipation channel 206 are located on different sides of the substrate 200 along the first direction (X direction) parallel to the substrate surface, and the angle α between the first sub-channel 206-1 and the second sub-channel 206-2 of the heat dissipation channel 206 is greater than 90 degrees.

[0088] Here, the angle between the first sub-channel and the second sub-channel is greater than or equal to 90 degrees. The larger angle between the first sub-channel and the second sub-channel reduces the resistance and eddy current during the flow of the coolant, ensuring that the flow of the coolant is smoother, thereby improving the cooling efficiency. At the same time, a higher integration level can be achieved in a limited space, thereby ensuring the compactness of the heat dissipation structure.

[0089] In the disclosed embodiment, Figure 2C The dotted line shown in the heat dissipation channel 206 in FIG. 1 is only used to distinguish the first sub-channel 206 - 1 from the second sub-channel 206 - 2 of the heat dissipation channel 206 . It should be emphasized that the dotted line does not exist in an actual memory.

[0090] In some embodiments, the spacing between adjacent first sub-channels located in the first region is smaller than the spacing between adjacent first sub-channels located in the second region, and / or, along a second direction parallel to the substrate surface, the size of the first sub-channel located in the first region is larger than the size of the first sub-channel located in the second region; wherein the first direction intersects with the second direction.

[0091] In some embodiments, Figure 4 As shown, the interval w1 between adjacent first sub-channels 206-1 located in the first area 200-1 is smaller than the interval w2 between adjacent first sub-channels 206-1 located in the second area 200-2. In this way, more first sub-channels can be arranged within a unit area of ​​the first area, thereby increasing the contact area between the coolant and the heat source and improving the heat exchange efficiency to meet the heat dissipation demand of the first area.

[0092] In some embodiments, Figure 5 As shown, along the second direction (Y direction) parallel to the surface of the substrate 200, the size of the adjacent first sub-channels 206-1 located in the first region 200-1 is larger than the size of the adjacent first sub-channels 206-1 located in the second region 200-2. In this way, the flow path of the coolant in the first region is extended, so that the contact time between the coolant and the heat source is increased, more heat can be taken away, and the heat dissipation effect is improved to meet the heat dissipation requirements of the first region.

[0093] In some embodiments, Figure 6As shown, the interval w1 between adjacent first sub-channels 206-1 in the first region 200-1 is smaller than the interval w2 between adjacent first sub-channels 206-1 in the second region 200-2, and the size of adjacent first sub-channels 206-1 in the first region 200-1 along the second direction is larger than the size of adjacent first sub-channels 206-1 in the second region 200-2. By simultaneously changing the length of the first sub-channels in the first region and the intervals between the first sub-channels, the heat dissipation effect is further improved to meet the heat dissipation requirements of the first region.

[0094] The embodiment of the present disclosure meets the different heat dissipation requirements of the first area and the second area by designing the structure of the heat dissipation channel according to the different operating temperatures of the semiconductor structure in different areas. While avoiding the impact of uneven heat distribution on memory performance, it also avoids waste of resources and achieves heat dissipation effect in a highly efficient and energy-saving manner.

[0095] Figure 7B for Fig. 7A Schematic diagram of the cross section along the AA' tangent direction, Figure 7C for Fig. 7A Schematic diagram of the cross section along the BB' tangent direction. Fig. 7A As shown, the heat dissipation structure includes a heat dissipation channel 206 having an inlet end 204 and an outlet end 205. The inlet end 204 and the outlet end 205 are located on the same side of the substrate 200 along a first direction (X direction) parallel to the substrate surface.

[0096] Figure 8B for Fig. 8A Schematic diagram of the cross section along the CC' tangent direction, Figure 8C for Fig. 8A Schematic diagram of the cross section along the DD' tangent direction. Fig. 8A As shown, the heat dissipation structure includes a heat dissipation channel 206 having an inlet end 204 and an outlet end 205. The inlet end 204 and the outlet end 205 are located on the same side of the substrate 200 along a first direction (X direction) parallel to the substrate surface.

[0097] In some embodiments, a heat dissipation condenser is disposed outside the storage device to connect the outlet end of the heat dissipation channel with the inlet end to achieve internal circulation.

[0098] In the embodiment of the present disclosure, the inlet and outlet ends of the heat dissipation channel are located on the same side of the substrate along the first direction (X direction), which can save space, facilitate effective heat dissipation management in a limited space, and help to better control the flow path of the coolant, improve fluid dynamics efficiency, ensure that heat is quickly removed, and enhance the heat dissipation effect.

[0099] In some embodiments, the heat dissipation structure includes a first heat dissipation channel and a second heat dissipation channel; wherein, the outlet end of the first heat dissipation channel and the inlet end of the second heat dissipation channel are located on the first side of the substrate along the first direction, and the inlet end of the first heat dissipation channel and the outlet end of the second heat dissipation channel are located on the second side of the substrate along the first direction.

[0100] For example, Fig.7D As shown, the heat dissipation structure includes a first heat dissipation channel and a second heat dissipation channel; wherein the outlet end 205-1 of the first heat dissipation channel and the inlet end 204-2 of the second heat dissipation channel are located on the first side of the substrate 200 along the first direction, and the inlet end 204-1 of the first heat dissipation channel and the outlet end 205-2 of the second heat dissipation channel are located on the second side of the substrate 200 along the first direction. Here, the first side refers to the left side of the substrate 200 along the first direction, and the second side refers to the right side of the substrate 200 along the first direction.

[0101] like Fig.8D As shown, the heat dissipation structure includes a first heat dissipation channel and a second heat dissipation channel; wherein the outlet end 205-1 of the first heat dissipation channel and the inlet end 204-2 of the second heat dissipation channel are located on the first side of the substrate 200 along the first direction, and the inlet end 204-1 of the first heat dissipation channel and the outlet end 205-2 of the second heat dissipation channel are located on the second side of the substrate 200 along the first direction. Here, the first side refers to the middle side of the substrate 200 along the first direction (the position close to the tangent line DD'), and the second side refers to the right side of the substrate 200 along the first direction.

[0102] In some embodiments, a heat dissipation condenser is provided outside the storage device for connecting the outlet end of the first heat dissipation channel with the inlet end of the second heat dissipation channel and connecting the inlet end of the first heat dissipation channel with the outlet end of the second heat dissipation channel to realize internal circulation.

[0103] It should be noted that, in order to facilitate the description of the arrangement of the heat dissipation channel of the heat dissipation structure, Fig. 7A , Fig.7D , Fig. 8A and Fig.8D The interconnection layer and semiconductor structure are omitted. FIG. 2A to FIG. 2C The interconnection layer and the semiconductor structure can be understood by referring to the related description, which will not be repeated here.

[0104] Figure 7B and Figure 7C as well as FIG. 8B to FIG. 8C For other structures (such as substrate, interconnect layer, semiconductor structure, etc.) FIG. 2A to FIG. 2C Please refer to the relevant description for understanding, and no further details will be given here.

[0105] It should be noted that in Figure 3 , Figure 4 , Figure 5 , Figure 6 , Fig. 7A , Fig.7D , Fig. 8A and Fig.8D In the figure, the first subchannel and the second subchannel are simplified to be shown as solid lines (straight lines).

[0106] In some embodiments, in a cross section perpendicular to the substrate surface, the cross-sectional shape of the first sub-channel and the second sub-channel is at least one of a square, a circular, an elliptical, or a V-shape.

[0107] For example, Figure 2A As shown, in the XZ plane, the cross-sectional shape of the first sub-channel and the second sub-channel is a square.

[0108] In some embodiments, in a cross section parallel to the surface of the substrate, the cross-sectional shape of the heat dissipation structure is at least one of a bow-shaped structure, a wave-shaped structure, or a U-shaped structure.

[0109] In some embodiments, Figure 2C As shown, in the cross section parallel to the XY plane, the cross section shape of the heat dissipation structure is a bow-shaped structure.

[0110] In some embodiments, Figure 3 As shown, in the cross section parallel to the XY plane, the cross section shape of the heat dissipation structure is a wavy structure.

[0111] In some embodiments, Fig. 8A As shown, in the cross section parallel to the XY plane, the cross section shape of the heat dissipation structure is a U-shaped structure.

[0112] The heat dissipation channel is designed as a bow-shaped structure, a wave-shaped structure or a U-shaped structure, which increases the flow path of the coolant, allows the heat to be more fully transferred to the outside of the memory, and improves the heat dissipation effect. It can also be compact in structure, optimize space utilization, and improve the integration of the memory.

[0113] The disclosed embodiment disposes a heat dissipation structure in the substrate to dissipate heat. On the one hand, it effectively improves the heat dissipation effect inside the memory and avoids the impact of overheating on the performance and life of the memory. On the other hand, the heat dissipation structure is embedded in the substrate and does not occupy additional space, which is conducive to improving the integration of the memory.

[0114] The disclosed embodiment also provides a method for forming a memory. Fig. 9 The following is a schematic diagram of a specific implementation flow of a method for forming a memory provided by an embodiment of the present disclosure. Fig. 9As shown, the specific steps of the method for forming the memory include:

[0115] Step S10: providing a substrate;

[0116] Step S20: forming a heat dissipation structure in the substrate;

[0117] Step S30: forming a semiconductor structure on a substrate.

[0118] In some implementations, the heat dissipation structure is used to conduct heat in the memory to the outside of the memory using a coolant.

[0119] In some embodiments, forming a heat dissipation structure in the substrate includes: etching the substrate to form a groove; forming a cover layer on the groove to close the top opening of the groove to form a heat dissipation channel with an inlet end and an outlet end.

[0120] In some embodiments, the substrate is etched using a patterned mask to form a groove. In some embodiments, a capping layer is formed by plasma enhanced chemical vapor deposition (PECVD) or physical vapor deposition (PVD). The capping layer seals the top opening of the groove so that the groove forms a closed heat dissipation channel or heat dissipation cavity.

[0121] It should be noted that the cover layer only closes the top opening of the groove and does not cover the inlet and outlet reserved on the groove.

[0122] In some embodiments, the inlet port and the outlet port are located at the same side or different sides of the substrate along a first direction parallel to a surface of the substrate.

[0123] In some embodiments, Figure 2C As shown, the inlet port 204 and the outlet port 205 are located on different sides of the substrate 200 along a first direction (X direction) parallel to the substrate surface.

[0124] In some embodiments, Fig. 7A and Fig. 8A As shown, the inlet port 204 and the outlet port 205 are located on the same side of the substrate 200 along a first direction (X direction) parallel to the substrate surface.

[0125] In some embodiments, in a cross section parallel to the surface of the substrate, a cross-sectional shape of the groove is at least one of a bow-shaped structure, a wave-shaped structure, or a U-shaped structure.

[0126] Here, in the cross section parallel to the substrate surface, the cross-sectional shape of the groove can be referred to as Figure 2C , Figure 3 and Fig. 8A The cross-sectional shape of the heat dissipation channel is shown for understanding.

[0127] In some embodiments, the method further includes: forming an interconnection layer at least covering the heat dissipation structure; and forming the semiconductor structure on the interconnection layer.

[0128] In some embodiments, the interconnect layer 202 can be used to transmit electrical signals between various elements of the semiconductor structure, and can also be used to further conduct the heat generated by the semiconductor structure to the heat dissipation structure in the substrate to improve the overall heat dissipation effect, and can also be used to play a supporting role to enhance the stability of the memory structure.

[0129] Here, the process of forming the interconnection layer 202 may include any process known in the art, including but not limited to chemical vapor deposition (CVD), physical vapor deposition, sputtering, and atomic layer deposition (ALD).

[0130] In the embodiment of the present disclosure, the heat dissipation structure located in the substrate and the semiconductor structure located on the substrate are independently arranged and can be designed in coordination according to actual needs to optimize the heat dissipation performance and circuit performance.

[0131] The memory formed by the memory forming method provided in the embodiment of the present disclosure is similar to the memory in the above-mentioned embodiments. For the technical features not fully disclosed in the embodiment of the present disclosure, please refer to the above-mentioned embodiments for understanding, and no further details will be given here.

[0132] An embodiment of the present disclosure further provides a memory system, comprising: at least one memory as described in the aforementioned embodiment; and a controller, wherein the controller is configured to control the memory.

[0133] Fig.10 FIG. 1 is a schematic diagram of a memory system according to an embodiment of the present disclosure. Fig.10 As shown, the memory system 1000 includes at least one memory as above; and a memory controller coupled to the memory and configured to control the memory.

[0134] The memory system 1000 includes a mobile phone, a smart phone, a desktop computer, a laptop computer, a tablet computer, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital camera, a camcorder, a personal computer (PC), a server computer, a workstation, a digital TV, a set-top box, a portable game console, a navigation system, a wearable electronic device, an Internet of Things (IoT) device, an Internet of Everything (IoE) device, an e-book, a Virtual Reality (VR) device, an Augmented Reality (AR) device, or any other suitable electronic device having a memory therein.

[0135] like Fig.10 As shown, the memory system 1000 may include a host 1008 and a storage subsystem 1002, the storage subsystem 1002 having one or more memories 1004, and the storage subsystem 1002 further including a controller 1006. The host 1008 may be a processor (e.g., a central processing unit (CPU)) or a system on chip (SoC) (e.g., an application processor (AP)) of an electronic device. The host 1008 may access the storage subsystem 1002 in conjunction with or by running the execution of one or more applications 1012 of one or more operating systems 1010. The memory 1004 may be any memory disclosed in the present disclosure.

[0136] According to some embodiments, the controller 1006 is also coupled to the host 1008. The controller 1006 may provide an interface with respect to the memory 1004 to manage data stored in the memory 1004, and may communicate with the host 1008 through at least one of various interface protocols (e.g., USB, MMC, PCIe, Serial ATA, Parallel ATA, SCSI). The controller 1006 may be implemented as an independent chip, or may be integrated with the memory 1004. The controller 1006 may be implemented on a motherboard, and may be implemented as an integrated memory controller (IMC) included in a microprocessor.

[0137] In some embodiments, the controller 1006 may manage data stored in the memory 1004 and communicate with the host 1008 .

[0138] The controller 1006 may be configured to control operations of the memory 1004, such as read, erase, and program operations. The controller 1006 may also be configured to manage various functions regarding data stored or to be stored in the memory 1004, including but not limited to bad block management, garbage collection, logical to physical address translation, wear leveling, etc. In some embodiments, the controller 1006 is also configured to process error correction codes (ECC) regarding data read from or written to the memory 1004.

[0139] It should be understood that "one embodiment" or "some embodiments" mentioned throughout the specification means that specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present disclosure. Therefore, "in one embodiment" or "in some embodiments" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present disclosure, the size of the serial number of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The serial numbers of the embodiments of the present disclosure are for description only and do not represent the advantages and disadvantages of the embodiments.

[0140] The above description is only a specific implementation mode of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure.

Claims

1. A memory, characterized in that: include: A substrate, wherein a heat dissipation structure is disposed in the substrate; A semiconductor structure is located on the substrate.

2. The memory according to claim 1, characterized in that: The substrate includes a first region and a second region, the operating temperature of the semiconductor structure in the first region is higher than the operating temperature in the second region, and the arrangement density of the heat dissipation structure in the first region is higher than the arrangement density in the second region.

3. The memory according to claim 2, characterized in that: The intervals between the heat dissipation structures in the first region are smaller than the intervals between the heat dissipation structures in the second region, and / or the size of the heat dissipation structures in the first region is larger than the size in the second region.

4. The memory according to claim 3, characterized in that: The heat dissipation channel includes first sub-channels and second sub-channels alternately connected to each other; wherein a plurality of the first sub-channels are arranged parallel to each other along a first direction parallel to the surface of the substrate; and an angle between the first sub-channel and the second sub-channel is greater than or equal to 90 degrees.

5. The memory according to claim 4, characterized in that: The spacing between adjacent first sub-channels located in the first region is smaller than the spacing between adjacent first sub-channels located in the second region, and / or, along a second direction parallel to the substrate surface, the size of the first sub-channel located in the first region is larger than the size of the first sub-channel located in the second region; wherein the first direction intersects with the second direction.

6. The memory according to claim 1, characterized in that: The heat dissipation structure comprises at least one heat dissipation channel; wherein an inlet end and an outlet end of the heat dissipation channel are located on the same side or different sides of the substrate along a first direction parallel to a surface of the substrate.

7. The memory according to claim 6, characterized in that: The heat dissipation structure includes a first heat dissipation channel and a second heat dissipation channel; wherein the outlet end of the first heat dissipation channel and the inlet end of the second heat dissipation channel are located on the first side of the substrate along the first direction, and the inlet end of the first heat dissipation channel and the outlet end of the second heat dissipation channel are located on the second side of the substrate along the first direction.

8. The memory according to claim 1, characterized in that: In a cross section parallel to the surface of the substrate, the cross-sectional shape of the heat dissipation structure is at least one of a bow-shaped structure, a wave-shaped structure or a U-shaped structure.

9. The memory according to claim 1, characterized in that: The memory further comprises: an interconnection layer located between the heat dissipation structure and the semiconductor structure.

10. The memory according to claim 1, characterized in that: The heat dissipation structure is used to conduct the heat in the memory to the outside of the memory by using a coolant; wherein the coolant is a cooling gas or a cooling liquid.

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