Link error checking method, device and equipment and readable storage medium

Abstract

The invention discloses a link error checking method. The method comprises the following steps: acquiring switch identification information respectively corresponding to each switch; acquiring a line connection relationship between each switch and each uplink device and each downlink device; determining each port identification number corresponding to each switch identification information according to the line connection relationship; obtaining each index item state flag bit of the port corresponding to each port identification number; and performing link error check according to the state flag bit of each index item of each port. By applying the link error checking method provided by the invention, the error detection accuracy is improved, the system stability and reliability are enhanced, the troubleshooting time is shortened, and the maintenance cost is reduced. The invention further discloses a link error checking device and equipment and a storage medium, which have corresponding technical effects.

Description

Technical Field

[0001] The present invention relates to the field of computer application technology, and in particular to a link error checking method, device, equipment and computer-readable storage medium. Background Art

[0002] In computer and communication systems, the performance and reliability of switches are crucial. As a key channel for data transmission, the stability and accuracy of high-speed Peripheral Component Interconnect Express (PCIe) links directly affect the operation of the entire system.

[0003] However, the upstream and downstream high-speed peripheral component interconnect links with switch chips may often have errors due to various factors, such as electromagnetic interference, hardware failure, software errors, etc., which may lead to serious problems such as data loss and system crash.

[0004] In summary, how to effectively solve the serious problems such as data loss, system crash, etc. that high-speed peripheral component interconnect links often have errors due to various factors is an issue that technicians in this field urgently need to solve. Summary of the invention

[0005] The object of the present invention is to provide a link error checking method, which improves the error detection accuracy, enhances the system stability and reliability, shortens the troubleshooting time, and reduces the maintenance cost; another object of the present invention is to provide a link error checking device, equipment and computer-readable storage medium.

[0006] In order to solve the above technical problems, the present invention provides the following technical solutions:

[0007] A link error checking method, comprising:

[0008] Obtaining switch identification information corresponding to each switch;

[0009] Obtaining the line connection relationship between each switch and each upstream device and each downstream device;

[0010] Determine the port identification numbers corresponding to the switch identification information according to the line connection relationship;

[0011] Obtain the status flag bits of each indicator item of the port corresponding to each port identification number;

[0012] Perform link error check based on the status flag bits of each indicator item of each port.

[0013] In a specific implementation of the present invention, obtaining the status flag bits of each indicator item of the port corresponding to each port identification number includes:

[0014] Obtain the receiving port status flag bit, transport layer status flag bit, data link layer status flag bit, receiver status flag bit, physical link status flag bit and serial transceiver status flag bit of the port corresponding to each port identification number;

[0015] Accordingly, link error checking is performed based on the status flag bits of each indicator item of each port, including:

[0016] Link error checking is performed based on the receiving port status flag bit, transport layer status flag bit, data link layer status flag bit, receiver status flag bit, physical link status flag bit and serial transceiver status flag bit of each port.

[0017] In a specific implementation of the present invention, link error checking is performed according to the receiving port status flag bit, the transport layer status flag bit, the data link layer status flag bit, the receiver status flag bit, the physical link status flag bit and the serial transceiver status flag bit of each port, including:

[0018] When it is determined that the receiving port status flag, transport layer status flag, data link layer status flag, receiver status flag and serial transceiver status flag of each port are all 0, and all bits of the physical link status flag except the last bit are also all 0, it is determined that the link is normal.

[0019] In a specific implementation of the present invention, link error checking is performed according to the receiving port status flag bit, the transport layer status flag bit, the data link layer status flag bit, the receiver status flag bit, the physical link status flag bit and the serial transceiver status flag bit of each port, including:

[0020] When there are non-zero bits in the other bits except the last bit in the physical link status flag, the receiving port status flag, the transport layer status flag, the data link layer status flag, the receiver status flag and the serial transceiver status flag, it is determined that the link is abnormal.

[0021] In a specific implementation of the present invention, when there are non-zero bits in the other bits except the last bit in the physical link status flag bit, the receiving port status flag bit, the transport layer status flag bit, the data link layer status flag bit, the receiver status flag bit, and the serial transceiver status flag bit, determining that the link is abnormal includes:

[0022] When the receiving port status flag has a non-zero bit, determining that the link to which the port corresponding to the receiving port status flag belongs is an abnormal receiving port;

[0023] When the transport layer status flag has a non-zero bit, determining that the link to which the port corresponding to the transport layer status flag belongs is abnormal in the transmission of the data packet at the physical layer;

[0024] When the data link layer status flag bit has a non-zero bit, determining that the link to which the port corresponding to the data link layer status flag bit belongs is a deserializer abnormality;

[0025] When there are non-zero bits in the bits other than the last bit in the receiver status flag bit, determining that the link to which the port corresponding to the receiver status flag bit belongs is a receiver abnormality;

[0026] When the serial transceiver status flag bit has a non-zero bit, determining that the link to which the port corresponding to the serial transceiver status flag bit belongs is a serial transceiver abnormality;

[0027] When a non-zero bit exists in the physical link status flag bit, it is determined that the link to which the port corresponding to the physical link status flag bit belongs is abnormal.

[0028] In a specific implementation of the present invention, obtaining the line connection relationship between each switch and each upstream device and each downstream device includes:

[0029] Obtain the uplink binding relationship between each switch and each uplink device;

[0030] Obtain the downstream binding relationship between each switch and each downstream device;

[0031] The line connection relationship is determined according to each uplink binding relationship and each downlink binding relationship.

[0032] In a specific implementation of the present invention, link error checking is performed according to the status flag bits of each indicator item of each port, including:

[0033] According to the status flag bits of each indicator item of each port, link error checks are performed on the links to which each port belongs respectively to obtain error detection results of each sub-link;

[0034] The overall link error detection result is determined based on the error detection results of each sub-link.

[0035] In a specific implementation of the present invention, link error checking is performed according to the status flag bits of each indicator item of each port, including:

[0036] If the current test scenario is a DC cycle test scenario or an AC cycle test scenario, the physical link status flag bit in each indicator item status flag bit corresponding to each port is used as the indicator item status flag bit with the highest priority to perform link error check;

[0037] If the current test scenario is a whole-machine voltage stabilization test scenario, the transport layer status flag bit and the data link layer status flag bit in each indicator item status flag bit corresponding to each port are used as the indicator item status flag bits with the top two priorities for link error check;

[0038] If the current test scenario is a big data impact test scenario, the serial transceiver status flag bit in each indicator item status flag bit corresponding to each port is used as the indicator item status flag bit with the highest priority to perform link error checking.

[0039] A link error checking device, comprising:

[0040] Memory for storing computer programs;

[0041] A processor is used to implement the steps of the link error checking method as described above when executing the computer program.

[0042] A computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the link error checking method described above are implemented.

[0043] The link error checking method provided by the present invention obtains the switch identification information corresponding to each switch; obtains the line connection relationship between each switch and each upstream device and each downstream device; determines the port identification number corresponding to each switch identification information according to the line connection relationship; obtains the status flag bits of each index item of the port corresponding to each port identification number; and performs link error checking according to the status flag bits of each index item of each port.

[0044] It can be seen from the above technical solution that, by obtaining the status flag bits of each index item of the port corresponding to each port identification number according to the line connection relationship between each switch and each upstream device and each downstream device, automatic link error checking is performed according to the status flag bits of each index item of each port. It can accurately capture various subtle and complex errors, reduce missed detection and false detection, and significantly improve the accuracy of error detection. It can timely discover and repair errors in the link, reduce the risk of system failure, enhance system stability and reliability, and ensure the continuity of key services. It realizes clear and accurate error reporting and positioning, can quickly lock the erroneous links and links, and shortens the troubleshooting time. It can prevent and solve errors in advance and in time, reduce the cost of hardware replacement and repair, reduce maintenance costs, and improve user experience.

[0045] Correspondingly, the present invention also provides a link error checking device, equipment and computer-readable storage medium corresponding to the above-mentioned link error checking method, which have the above-mentioned technical effects and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or related technologies, the drawings required for use in the embodiments or related technical descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0047] FIG1 is a flowchart of an implementation of a link error checking method according to an embodiment of the present invention;

[0048] FIG2 is another implementation flow chart of the link error checking method in an embodiment of the present invention;

[0049] FIG3 is a schematic diagram of a switch uplink and downlink connection structure according to an embodiment of the present invention;

[0050] FIG4 is a structural block diagram of a link error checking device according to an embodiment of the present invention;

[0051] 5 is a structural block diagram of a link error checking device according to an embodiment of the present invention;

[0052] FIG6 is a schematic diagram of the specific structure of a link error checking device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0053] In order to enable those skilled in the art to better understand the scheme of the present invention, the present invention is further described in detail below in conjunction with the accompanying drawings and specific implementation methods. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0054] Referring to FIG. 1 , FIG. 1 is a flowchart of an implementation of a link error checking method in an embodiment of the present invention. The method may include the following steps:

[0055] S101: Obtain switch identification information corresponding to each switch.

[0056] Each switch (Switch) in the system has its own corresponding switch identification information (Switch ID), and the switch identification information corresponding to each switch is obtained.

[0057] S102: Obtain the line connection relationship between each switch and each upstream device and each downstream device.

[0058] Each switch in the system has a corresponding upstream device and downstream device. There is a line connection between the switch, the upstream device, and the downstream device, and the corresponding relationship between each switch, each upstream device, and each downstream device can be pre-configured. Obtain the line connection relationship between each switch and each upstream device and each downstream device.

[0059] The upstream device can be set to a central processing unit (CPU), and the downstream device can be set to a graphics processing unit (GPU), hard disk, etc.

[0060] S103: Determine the port identification numbers corresponding to the identification information of each switch according to the line connection relationship.

[0061] Each upstream device and each downstream device has its own corresponding port. After obtaining the line connection relationship between each switch and each upstream device and each downstream device, the port identification number (port ID) corresponding to each switch identification information is determined according to the line connection relationship. For example, in a Linux system, in a PCIE link with a PCIE Switch, the port ID of the PCIE Switch is obtained through the system's built-in tool lspci.

[0062] S104: Obtain the status flag bits of each index item of the port corresponding to each port identification number.

[0063] Each port has an indicator item status flag bit that marks the status of each indicator item. After determining the port identification numbers corresponding to the switch identification information according to the line connection relationship, the indicator item status flag bits of the ports corresponding to the port identification numbers are obtained. For example, according to the judgment rules, the automatic identification script is edited, and the script will automatically scan the indicator item status flag bits of each port of the uplink and downlink according to the detection requirements.

[0064] S105: Perform link error check according to the status flag bit of each indicator item of each port.

[0065] Each indicator item status flag bit marks the corresponding indicator item status respectively. After obtaining each indicator item status flag bit of the port corresponding to each port identification number, a link error check is performed according to each indicator item status flag bit of each port. The setting state of the indicator item status flag bit can be pre-set to indicate the normal state of the indicator item and the abnormal state of the indicator item. Through each indicator item status flag bit, it is determined whether each indicator item is in a normal state, and then the link state is determined according to the indicator item state.

[0066] It can be seen from the above technical solution that, by obtaining the status flag bits of each index item of the port corresponding to each port identification number according to the line connection relationship between each switch and each upstream device and each downstream device, automatic link error checking is performed according to the status flag bits of each index item of each port. It can accurately capture various subtle and complex errors, reduce missed detection and false detection, and significantly improve the accuracy of error detection. It can timely discover and repair errors in the link, reduce the risk of system failure, enhance system stability and reliability, and ensure the continuity of key services. It realizes clear and accurate error reporting and positioning, can quickly lock the erroneous links and links, and shortens the troubleshooting time. It can prevent and solve errors in advance and in time, reduce the cost of hardware replacement and repair, reduce maintenance costs, and improve user experience.

[0067] It should be noted that, based on the above embodiment, the embodiment of the present invention also provides corresponding improved solutions. In the subsequent embodiments, the same steps or corresponding steps as those in the above embodiment can be referenced to each other, and the corresponding beneficial effects can also be referenced to each other, which will not be repeated one by one in the following improved embodiments.

[0068] Referring to FIG. 2 , FIG. 2 is another implementation flow chart of the link error checking method in an embodiment of the present invention. The method may include the following steps:

[0069] S201: Obtain switch identification information corresponding to each switch.

[0070] See Figure 3, which is a schematic diagram of a switch uplink and downlink connection structure in an embodiment of the present invention. Figure 3 is a 16-card 4-switch, and the switch identification information that can be obtained is 1, 3, 5, 7, etc.

[0071] S202: Acquire the line connection relationship between each switch and each upstream device and each downstream device.

[0072] S203: Determine the port identification numbers corresponding to the identification information of each switch according to the line connection relationship.

[0073] S204: Obtain the receiving port status flag bit, transport layer status flag bit, data link layer status flag bit, receiver status flag bit, physical link status flag bit and serial transceiver status flag bit of the port corresponding to each port identification number.

[0074] The status flags of each indicator item of the port include the receiving port status flag (PortRX), the transport layer status flag (BadTLP), the data link layer status flag (BadDLLP), the receiver status flag (RecDiag), the physical link status flag (LinkDown) and the serial transceiver status flag (SerdesError), etc. Get the receiving port status flag, transport layer status flag, data link layer status flag, receiver status flag, physical link status flag and serial transceiver status flag of the port corresponding to each port identification number.

[0075] S205: Perform link error check according to the receiving port status flag bit, the transport layer status flag bit, the data link layer status flag bit, the receiver status flag bit, the physical link status flag bit and the serial transceiver status flag bit of each port.

[0076] After obtaining the receiving port status flag bit, the transport layer status flag bit, the data link layer status flag bit, the receiver status flag bit, the physical link status flag bit and the serial transceiver status flag bit of the port corresponding to each port identification number, link error checking is performed according to the receiving port status flag bit, the transport layer status flag bit, the data link layer status flag bit, the receiver status flag bit, the physical link status flag bit and the serial transceiver status flag bit of each port. The receiving port status of the link to which the port belongs can be determined by the receiving port status flag bit, the transport layer status of the link to which the port belongs can be determined by the transport layer status flag bit, the data link layer status of the link to which the port belongs can be determined by the data link layer status flag bit, the receiver status of the link to which the port belongs can be determined by the receiver status flag bit, the physical link status of the link to which the port belongs can be determined by the physical link status flag bit, and the serial transceiver status of the link to which the port belongs can be determined by the serial transceiver status flag bit, and then the link status can be determined according to the receiving port status, the transport layer status, the data link layer status, the receiver status, the physical link status and the serial transceiver status, thereby improving the accuracy of link status checking.

[0077] Compared with traditional link error checking methods, it can detect more potential and difficult-to-detect errors. It reduces the cases of misjudgment and missed judgment, improves the credibility of the test results, optimizes the test process and algorithm, and shortens the test time. It can test multiple PCIe links at the same time, improving the parallelism of the test. It can comprehensively and accurately detect and identify various error types in the PCIe link, and effectively verify and analyze the test results. It can timely detect and repair errors in the PCIe link, reduce the risk of system failure, provide strong guarantee for the stable operation of the system, and improve user experience.

[0078] In a specific implementation of the present invention, step S205 may include the following steps:

[0079] When it is determined that the receiving port status flag, transport layer status flag, data link layer status flag, receiver status flag and serial transceiver status flag of each port are all 0, and all bits of the physical link status flag except the last bit are also all 0, it is determined that the link is normal.

[0080] The receiving port status flag, the transport layer status flag, the data link layer status flag, the receiver status flag, the physical link status flag and the serial transceiver status flag can be represented by a preset number of flags, such as 8-bit flags. When it is determined that the receiving port status flag, the transport layer status flag, the data link layer status flag, the receiver status flag and the serial transceiver status flag of each port are all 0, and the other bits of the physical link status flag except the last bit are all 0, it is determined that the link is normal. By using the receiving port status flag, the transport layer status flag, the data link layer status flag, the receiver status flag and the serial transceiver status flag to be all 0, and the other bits of the physical link status flag except the last bit are all 0 to indicate that the link is normal, the complexity of link status detection is greatly simplified.

[0081] In a specific implementation of the present invention, step S205 may include the following steps:

[0082] When there are non-zero bits in the bits other than the last bit in the physical link status flag, the receiving port status flag, the transport layer status flag, the data link layer status flag, the receiver status flag, and the serial transceiver status flag, the link is determined to be abnormal.

[0083] When there are non-zero bits in the bits other than the last bit in the physical link status flag, the receiving port status flag, the transport layer status flag, the data link layer status flag, the receiver status flag, and the serial transceiver status flag, the link is determined to be abnormal. By using the receiving port status flag, the transport layer status flag, the data link layer status flag, the receiver status flag, and the serial transceiver status flag, or the bits other than the last bit in the physical link status flag, as long as there are non-zero bits, it indicates that the link is abnormal, which greatly simplifies the complexity of link error checking.

[0084] In a specific implementation of the present invention, when there are non-zero bits in the bits other than the last bit in the physical link status flag bit, the receiving port status flag bit, the transport layer status flag bit, the data link layer status flag bit, the receiver status flag bit, and the serial transceiver status flag bit, determining that the link is abnormal may include the following steps:

[0085] Step 1: When the receiving port status flag has a non-zero bit, it is determined that the link to which the port corresponding to the receiving port status flag belongs is an abnormal receiving port;

[0086] Step 2: When the transport layer status flag bit is not 0, it is determined that the link to which the port corresponding to the transport layer status flag bit belongs is abnormal in the transmission of the data packet at the physical layer;

[0087] Step 3: When the data link layer status flag bit is not 0, it is determined that the link to which the port corresponding to the data link layer status flag bit belongs is a deserializer abnormality;

[0088] Step 4: When there are non-zero bits in the bits other than the last bit in the receiver status flag, it is determined that the link to which the port corresponding to the receiver status flag belongs is a receiver abnormality;

[0089] Step 5: When the serial transceiver status flag bit is not 0, it is determined that the link to which the port corresponding to the serial transceiver status flag bit belongs is a serial transceiver abnormality;

[0090] Step 6: When the physical link status flag bit is not 0, it is determined that the link to which the port corresponding to the physical link status flag bit belongs is a physical link abnormality.

[0091] For the convenience of description, the above six steps can be combined for explanation.

[0092] When there is a non-zero bit in the receiving port status flag, it is determined that the link to which the port corresponding to the receiving port status flag belongs is a receiving port abnormality; when there is a non-zero bit in the transport layer status flag, it is determined that the link to which the port corresponding to the transport layer status flag belongs is a data packet transmission abnormality in the physical layer; when there is a non-zero bit in the data link layer status flag, it is determined that the link to which the port corresponding to the data link layer status flag belongs is a deserializer abnormality; when there are non-zero bits in the receiver status flag except the last bit, it is determined that the link to which the port corresponding to the receiver status flag belongs is a receiver abnormality; when there is a non-zero bit in the serial transceiver status flag, it is determined that the link to which the port corresponding to the serial transceiver status flag belongs is a serial transceiver abnormality; when there is a non-zero bit in the physical link status flag, it is determined that the link to which the port corresponding to the physical link status flag belongs is a physical link abnormality. Through the corresponding set states of the receiving port status flag, the transport layer status flag, the data link layer status flag, the receiver status flag and the serial transceiver status flag, the cause of the link abnormality is accurately determined.

[0093] The embodiments of the present application can accurately capture various subtle and complex errors, reduce missed detections and false detections, and significantly improve the accuracy of error detection. It can promptly detect and repair errors in the link, reduce the risk of system failures, such as avoiding data loss or system crashes caused by PCIe link errors, ensure the continuity of key services, and enhance system stability and reliability. Through accurate error detection and processing, the efficiency and quality of data transmission are improved, for example, retransmissions and delays caused by errors are reduced, the overall response speed of the system is improved, and system performance is optimized. Stable and reliable system performance provides users with a better user experience. For example, in server scenarios, service interruptions caused by link errors are reduced, and users' high requirements for service quality are met, which improves user satisfaction.

[0094] The embodiments of the present invention can clearly and accurately report and locate errors, helping technicians quickly find the root cause of the problem. If a fault occurs, it is no longer necessary to spend a lot of time on step-by-step troubleshooting, and the erroneous links and links can be quickly locked, greatly shortening the troubleshooting time. It can prevent and solve errors in advance and in a timely manner, reducing the cost of hardware replacement and repair. For example, it can avoid damage to the entire Switch or related equipment due to serious errors, save hardware procurement costs, and reduce maintenance costs. It provides valuable data and experience for further optimizing PCIe link technology and related products. For example, through the analysis of test results, it promotes the research and development of new error correction algorithms and hardware designs, and promotes technological innovation and development.

[0095] As shown in Figure 3, the self-developed black box tool is used to scan the information under the port ID of the PCIE switch, and the reading values ​​of PortRX, BadTLP, BadDLLP, RecDiag, LinkDown, SerdesError, etc. under the port are captured, such as the number of PCIe errors of the four switches respectively;

[0096] . / Self-developed black box tool-i 1 counters;

[0097] . / Self-developed black box tool-i 3 counters;

[0098] . / Self-developed black box tool-i 5 counters;

[0099] . / Self-developed black box tool-i 7 counters;

[0100] The -i parameter stands for scan; 1, 3, 5, 7, etc. represent the port number of each switch and link; Counters stands for the scan count.

[0101] The following information about the PCIE link under each switch port number will be obtained:

[0102]

[0103] In a specific implementation of the present invention, obtaining the line connection relationship between each switch and each upstream device and each downstream device may include the following steps:

[0104] Step 1: Obtain the uplink binding relationship between each switch and each uplink device;

[0105] Step 2: Obtain the downstream binding relationship between each switch and each downstream device;

[0106] Step 3: Determine the line connection relationship according to each uplink binding relationship and each downlink binding relationship.

[0107] For the convenience of description, the above three steps can be combined for explanation.

[0108] The uplink binding relationship between each switch and each uplink device is obtained, and the downlink binding relationship between each switch and each downlink device is obtained, and the line connection relationship is determined according to each uplink binding relationship and each downlink binding relationship. The line connection relationship is accurately determined through each uplink binding relationship and each downlink binding relationship.

[0109] In a specific implementation of the present invention, performing link error checking according to the status flag bits of each indicator item of each port may include the following steps:

[0110] Step 1: Perform link error checks on the links to which each port belongs according to the status flag bits of each indicator item of each port, and obtain error detection results of each sub-link;

[0111] Step 2: Determine the overall link error detection result based on the error detection results of each sub-link.

[0112] For the convenience of description, the above two steps can be combined for explanation.

[0113] According to the status flag bits of each index item of each port, link error checks are performed on the links to which each port belongs, and the error detection results of each sub-link are obtained. The total link error detection result is determined according to the error detection results of each sub-link. By performing error checks on each sub-link, the error check results corresponding to each sub-link are obtained. When the error check results of each sub-link are all normal links, the total link error detection result is determined to be normal links; when there are error check results of sub-links that are abnormal links, the total link error detection result is determined to be abnormal links. Thus, the error check results of each sub-link are used to accurately determine the total link error detection result.

[0114] In a specific implementation of the present invention, performing link error checking according to the status flag bits of each indicator item of each port may include the following steps:

[0115] If the current test scenario is a DC cycle test scenario or an AC cycle test scenario, the physical link status flag bit in each indicator item status flag bit corresponding to each port is used as the indicator item status flag bit with the highest priority to perform link error check;

[0116] If the current test scenario is a whole-machine voltage stabilization test scenario, the transport layer status flag bit and the data link layer status flag bit in each indicator item status flag bit corresponding to each port are used as the indicator item status flag bits with the top two priorities for link error check;

[0117] If the current test scenario is a big data impact test scenario, the serial transceiver status flag bit in each indicator item status flag bit corresponding to each port is used as the indicator item status flag bit with the highest priority to perform link error checking.

[0118] The test scenario can be pre-set. If the current test scenario is a DC cycle test scenario or an AC cycle test scenario, since the link is involved in voltage impact, chip logic scheduling, and clock acquisition adaptation during the cold start process, when the physical link status flag is not all zero, it is generally a situation where the device is offline or lost. Therefore, the physical link status flag in each indicator item status flag corresponding to each port is used as the highest priority indicator item status flag for link error checking.

[0119] If the current test scenario is a whole-machine voltage stabilization test scenario, since the PCIE link already has stable chip logic scheduling and clock adaptation, it is only necessary to consider the reliability of the data link transmission layer under voltage stabilization conditions. When the transport layer status flag is not all zero, it is generally due to waveform jitter causing the high and low levels to be reset untimely. When the data link layer status flag is not all zero, it is generally due to a misjudgment of the data handshake protocol. Therefore, the transport layer status flag and the data link layer status flag in each indicator item status flag corresponding to each port are used as the indicator item status flags with the top two priorities for link error checking.

[0120] If the current test scenario is a big data impact test scenario, such as ticket grabbing or concentrated burst scenarios, due to the existence of a large amount of data exchange, probabilistic PCIE link problems can be screened out. Therefore, the serial transceiver status flag bit in each indicator item status flag bit corresponding to each port is used as the indicator item status flag bit with the highest priority for link error checking.

[0121] By adaptively setting the priority of link flag bit checking according to different test scenarios, the indicator item status flag bit that is more likely to be a link abnormality mark is checked first in the corresponding test scenario. As long as a link error is found, there is no need to check other indicator item status flag bits, which further improves the efficiency of link error checking. By obtaining different test scenarios and obtaining the indicator item status flag bits of each port in different test scenarios, the comprehensiveness of link error testing is improved.

[0122] After determining that the link is abnormal, the following steps are also performed:

[0123] Get the target port corresponding to the non-0 bit except the last bit of the physical link status flag bit;

[0124] Determine the link to which the target port belongs as an abnormal link;

[0125] Connect the abnormal link to an oscilloscope and use the oscilloscope to perform a waveform test on the abnormal link;

[0126] Compare the target waveform obtained from the test with the standard waveform, and troubleshoot the cause of the abnormality based on the comparison results.

[0127] After determining that the link is abnormal, obtain the target port corresponding to the non-0 bit except the last bit of the physical link status flag, determine the link to which the target port belongs as an abnormal link, connect the abnormal link to an oscilloscope, and use the oscilloscope to perform a waveform test on the abnormal link. Compare the target waveform obtained by the test with the standard waveform, and investigate the cause of the abnormality based on the comparison result. By performing a waveform test on the abnormal link after determining that the link is abnormal, and comparing the target waveform obtained by the test with the standard waveform, accurate and rapid investigation of the cause of the link abnormality is achieved.

[0128] Corresponding to the above method embodiment, the present invention further provides a link error checking device. The link error checking device described below and the link error checking method described above can be referred to each other.

[0129] Referring to FIG. 4 , FIG. 4 is a structural block diagram of a link error checking device according to an embodiment of the present invention. The device may include:

[0130] The switch identification information acquisition module 41 is used to acquire the switch identification information corresponding to each switch;

[0131] The line connection relationship acquisition module 42 is used to acquire the line connection relationship between each switch and each upstream device and each downstream device;

[0132] The port identification number determination module 43 is used to determine the port identification numbers corresponding to the identification information of each switch according to the line connection relationship;

[0133] The indicator item status flag bit acquisition module 44 is used to acquire the indicator item status flag bits of the ports corresponding to the port identification numbers;

[0134] The link error checking module 45 is used to perform link error checking according to the status flag bits of each indicator item of each port.

[0135] It can be seen from the above technical solution that, by obtaining the status flag bits of each index item of the port corresponding to each port identification number according to the line connection relationship between each switch and each upstream device and each downstream device, automatic link error checking is performed according to the status flag bits of each index item of each port. It can accurately capture various subtle and complex errors, reduce missed detection and false detection, and significantly improve the accuracy of error detection. It can timely discover and repair errors in the link, reduce the risk of system failure, enhance system stability and reliability, and ensure the continuity of key services. It realizes clear and accurate error reporting and positioning, can quickly lock the erroneous links and links, and shortens the troubleshooting time. It can prevent and solve errors in advance and in time, reduce the cost of hardware replacement and repair, reduce maintenance costs, and improve user experience.

[0136] In a specific embodiment of the present invention, the indicator item status flag bit acquisition module 44 is specifically a module for acquiring the receiving port status flag bit, the transport layer status flag bit, the data link layer status flag bit, the receiver status flag bit, the physical link status flag bit and the serial transceiver status flag bit of the port corresponding to each port identification number;

[0137] The link error checking module 45 specifically performs link error checking according to the receiving port status flag bit, transport layer status flag bit, data link layer status flag bit, receiver status flag bit, physical link status flag bit and serial transceiver status flag bit of each port.

[0138] In a specific embodiment of the present invention, the link error check module 45 is specifically a module that determines that the link is normal when it is determined that the receiving port status flag, transport layer status flag, data link layer status flag, receiver status flag and serial transceiver status flag of each port are all 0, and the physical link status flag bits except the last bit are also all 0.

[0139] In a specific embodiment of the present invention, the link error check module 45 is specifically a module that determines that the link is abnormal when there are non-zero bits in the bits other than the last bit in the physical link status flag, the receiving port status flag, the transport layer status flag, the data link layer status flag, the receiver status flag and the serial transceiver status flag.

[0140] In a specific implementation of the present invention, the link error checking module 45 includes:

[0141] A receiving port abnormality determination submodule, used for determining that the link to which the port corresponding to the receiving port status flag belongs is a receiving port abnormality when the receiving port status flag has a non-zero bit;

[0142] The physical layer transmission anomaly determination submodule is used to determine that when the transmission layer status flag bit is not 0, the link to which the port corresponding to the transmission layer status flag bit belongs is a data packet with physical layer transmission anomaly;

[0143] The deserializer abnormality determination submodule is used to determine that the link to which the port corresponding to the data link layer status flag belongs is a deserializer abnormality when the data link layer status flag has a non-zero bit;

[0144] A receiver abnormality determination submodule, used for determining that the link to which the port corresponding to the receiver status flag belongs is a receiver abnormality when there is a non-zero bit in the bits other than the last bit in the receiver status flag bit;

[0145] The physical link abnormality determination submodule is used to determine that the link to which the port corresponding to the serial transceiver status flag belongs is a serial transceiver abnormality when the serial transceiver status flag has a non-zero bit;

[0146] The physical link abnormality determination submodule is used to determine that the link to which the port corresponding to the physical link status flag belongs is a physical link abnormality when the physical link status flag has a non-zero bit.

[0147] In a specific implementation of the present invention, the line connection relationship acquisition module includes:

[0148] An uplink binding relationship acquisition submodule is used to acquire the uplink binding relationship between each switch and each uplink device;

[0149] A downstream binding relationship acquisition submodule is used to acquire the downstream binding relationship between each switch and each downstream device;

[0150] The line connection relationship determination submodule is used to determine the line connection relationship according to each uplink binding relationship and each downlink binding relationship.

[0151] In a specific implementation of the present invention, the link error checking module 45 includes:

[0152] The sub-link error detection result determination submodule is used to perform link error checks on the links to which each port belongs according to the status flag bits of each indicator item of each port, and obtain the error detection results of each sub-link;

[0153] The total link error detection result determination submodule is used to determine the total link error detection result according to the error detection results of each sub-link.

[0154] In a specific implementation of the present invention, the link error checking module 45 includes:

[0155] A first link error check submodule, for performing a link error check by taking the physical link status flag bit in each indicator item status flag bit corresponding to each port as the indicator item status flag bit with the highest priority if the current test scenario is a DC cycle test scenario or an AC cycle test scenario;

[0156] The second link error check submodule is used to perform link error check on the transport layer status flag bit and the data link layer status flag bit in each indicator item status flag bit corresponding to each port as the indicator item status flag bits ranked first two in priority if the current test scenario is the whole machine voltage stabilization test scenario;

[0157] The third link error check submodule is used to perform link error check on the serial transceiver status flag bit in each indicator item status flag bit corresponding to each port as the indicator item status flag bit with the highest priority if the current test scenario is a big data impact test scenario.

[0158] Corresponding to the above method embodiment, referring to FIG. 5 , FIG. 5 is a schematic diagram of a link error checking device provided by the present invention, and the device may include:

[0159] A memory 332, for storing computer programs;

[0160] The processor 322 is configured to implement the steps of the link error checking method of the above method embodiment when executing a computer program.

[0161] Specifically, please refer to FIG. 6 , which is a schematic diagram of the specific structure of a link error checking device provided in this embodiment. The link error checking device may have relatively large differences due to different configurations or performances, and may include a processor (central processing units, CPU) 322 (for example, one or more processors) and a memory 332, and the memory 332 stores one or more computer programs 342 or data 344. Among them, the memory 332 can be a temporary storage or a permanent storage. The program stored in the memory 332 may include one or more modules (not shown in the figure), and each module may include a series of instruction operations in the data processing device. Furthermore, the processor 322 may be configured to communicate with the memory 332, and execute a series of instruction operations in the memory 332 on the link error checking device 301.

[0162] The link error checking device 301 may further include one or more power supplies 326 , one or more wired or wireless network interfaces 350 , one or more input and output interfaces 358 , and / or one or more operating systems 341 .

[0163] The steps in the link error checking method described above can be implemented by the structure of a link error checking device.

[0164] Corresponding to the above method embodiment, the present invention further provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the following steps can be implemented:

[0165] Obtain the switch identification information corresponding to each switch; obtain the line connection relationship between each switch and each upstream device and each downstream device; determine the port identification number corresponding to each switch identification information according to the line connection relationship; obtain the status flag bits of each index item of the port corresponding to each port identification number; and perform link error check according to the status flag bits of each index item of each port.

[0166] The computer-readable storage medium may include: a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, and other media that can store program codes.

[0167] For an introduction to the computer-readable storage medium provided by the present invention, please refer to the above method embodiment, and the present invention will not be elaborated here.

[0168] Corresponding to the above method embodiment, the present invention also provides a computer program product, including a computer program, which implements the steps of the above link error checking method when executed by a processor.

[0169] In this specification, each embodiment is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the devices, equipment and computer-readable storage media disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the description is relatively simple, and the relevant parts can be referred to the method part description.

[0170] The principles and implementation methods of the present invention are described in this article using specific examples. The description of the above embodiments is only used to help understand the technical solution and core ideas of the present invention. It should be pointed out that for ordinary technicians in this technical field, without departing from the principles of the present invention, the present invention can also be improved and modified, and these improvements and modifications also fall within the scope of protection of the present invention.

Claims

1. A link error checking method, characterized in that: include: Obtaining switch identification information corresponding to each switch; Obtaining the line connection relationship between each switch and each upstream device and each downstream device; Determine the port identification numbers corresponding to the switch identification information according to the line connection relationship; Obtain the status flag bits of each indicator item of the port corresponding to each port identification number; Perform link error check based on the status flag bits of each indicator item of each port.

2. The link error checking method according to claim 1, characterized in that: Get the status flag bits of each indicator item of the port corresponding to each port identification number, including: Obtain the receiving port status flag bit, transport layer status flag bit, data link layer status flag bit, receiver status flag bit, physical link status flag bit and serial transceiver status flag bit of the port corresponding to each port identification number; Accordingly, link error checking is performed based on the status flag bits of each indicator item of each port, including: Link error checking is performed based on the receiving port status flag bit, transport layer status flag bit, data link layer status flag bit, receiver status flag bit, physical link status flag bit and serial transceiver status flag bit of each port.

3. The link error checking method according to claim 2, characterized in that: Perform link error checks based on the receive port status flag, transport layer status flag, data link layer status flag, receiver status flag, physical link status flag, and serial transceiver status flag of each port, including: When it is determined that the receiving port status flag, transport layer status flag, data link layer status flag, receiver status flag and serial transceiver status flag of each port are all 0, and all bits of the physical link status flag except the last bit are also all 0, it is determined that the link is normal.

4. The link error checking method according to claim 2, characterized in that: Perform link error checks based on the receive port status flag, transport layer status flag, data link layer status flag, receiver status flag, physical link status flag, and serial transceiver status flag of each port, including: When there are non-zero bits in the other bits except the last bit in the physical link status flag, the receiving port status flag, the transport layer status flag, the data link layer status flag, the receiver status flag and the serial transceiver status flag, it is determined that the link is abnormal.

5. The link error checking method according to claim 4, characterized in that: When there are non-zero bits in the bits other than the last bit in the physical link status flag bit, the receiving port status flag bit, the transport layer status flag bit, the data link layer status flag bit, the receiver status flag bit, and the serial transceiver status flag bit, determining that the link is abnormal includes: When the receiving port status flag has a non-zero bit, determining that the link to which the port corresponding to the receiving port status flag belongs is an abnormal receiving port; When the transport layer status flag has a non-zero bit, determining that the link to which the port corresponding to the transport layer status flag belongs is abnormal in the transmission of the data packet at the physical layer; When the data link layer status flag bit is not 0, determining that the link to which the port corresponding to the data link layer status flag bit belongs is a deserializer abnormality; When there are non-zero bits in the bits other than the last bit in the receiver status flag, it is determined that the link to which the port corresponding to the receiver status flag belongs is abnormal. When the serial transceiver status flag bit has a non-zero bit, determining that the link to which the port corresponding to the serial transceiver status flag bit belongs is a serial transceiver abnormality; When a non-zero bit exists in the physical link status flag bit, it is determined that the link to which the port corresponding to the physical link status flag bit belongs is abnormal.

6. The link error checking method according to claim 1, characterized in that: Obtain the line connection relationship between each switch and each upstream device and each downstream device, including: Obtain the uplink binding relationship between each switch and each uplink device; Obtain the downstream binding relationship between each switch and each downstream device; The line connection relationship is determined according to each uplink binding relationship and each downlink binding relationship.

7. The link error checking method according to any one of claims 1 to 6, characterized in that: Perform link error checks based on the status flags of each indicator item on each port, including: According to the status flag bits of each indicator item of each port, link error checks are performed on the links to which each port belongs respectively to obtain error detection results of each sub-link; The overall link error detection result is determined based on the error detection results of each sub-link.

8. The link error checking method according to claim 1, characterized in that: Perform link error checks based on the status flags of each indicator item on each port, including: If the current test scenario is a DC cycle test scenario or an AC cycle test scenario, the physical link status flag bit in each indicator item status flag bit corresponding to each port is used as the indicator item status flag bit with the highest priority to perform link error check; If the current test scenario is a whole machine voltage stabilization test scenario, the transport layer status flag bit and the data link layer status flag bit in each indicator item status flag bit corresponding to each port are used as the indicator item status flag bits with the top two priorities to perform link error check; If the current test scenario is a big data impact test scenario, the serial transceiver status flag bit in each indicator item status flag bit corresponding to each port is used as the indicator item status flag bit with the highest priority to perform link error checking.

9. A link error checking device, characterized in that: include: Memory for storing computer programs; A processor, configured to implement the steps of the link error checking method according to any one of claims 1 to 8 when executing the computer program.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the link error checking method according to any one of claims 1 to 8 are implemented.

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