Image sensor chip packaging structure for space navigation and packaging method thereof

Abstract

The image sensor chip packaging structure comprises a tube shell, a core cavity is formed in an opening in the upper end of the tube shell, a chip is arranged at the groove bottom of the core cavity, the chip is an image sensor, the chip is connected to the tube shell through a plurality of bonding wires, a plurality of pins are arranged at the lower end of the tube shell, and a glass cover plate is arranged at the core cavity of the tube shell. And the glass cover plate is adhered to the core cavity of the tube shell through the sealing rubber ring. And the chip is adhered to the bottom of the core cavity through insulating glue. The packaging method is used for packaging the packaging structure of the image sensor chip for space navigation. According to the packaging structure, the high-temperature co-fired ceramic substrate formed by sintering and pressing multiple layers of ceramic is adopted, so that a multi-layer circuit structure can be conveniently formed for a high-integration chip; the flatness, parallelism and roughness of the surface of the packaging substrate can be better controlled, and the chip mounting precision can meet the application requirement. The high-temperature co-fired ceramic is stable in structure and high in heat conductivity, heat dissipation of the chip is facilitated, and the requirement for high reliability of aerospace application can be met.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor packaging, and in particular to an aerospace image sensor chip packaging structure and a packaging method thereof. Background Art

[0002] Semiconductor packaging technology mainly involves packaging bare chips designed and manufactured by integrated circuits into a structure that has functions such as input and output signals, power supply, and mechanical support for bare chips, while ensuring the heat dissipation and stability of the chips. As a bridge for information transmission between chips and circuit boards, packaging technology directly affects the electrical, thermal, optical, and mechanical properties of devices and integrated circuits, and directly determines the size, weight, application, life, performance, and cost of electronic products. CMOS image sensor chips are widely used in mobile phone photography, digital cameras, medical treatment, automotive electronics, monitoring, and other fields because of their advantages such as low power consumption, high integration, random access, and fast imaging. With the rapid development of image sensors, they will play an important role in the aerospace field, such as space remote sensing, space technology, and other fields.

[0003] Due to the particularity of the application environment, the packaging design of aerospace electronics needs to develop in the direction of miniaturization, lightweight, high density, and high reliability. For image sensor products used in such fields, their technological advancement, process maturity, and product reliability are all crucial, and they influence and restrict each other. To achieve mass production and standardized production of aerospace image sensor chip products, it is necessary to consider both the design advancement and the process feasibility and maturity, to ensure that the product meets the application needs and application environment requirements.

[0004] At present, most image sensor chips are industrial-grade and consumer-grade devices, and most of the packaging forms use non-sealed plastic substrate packaging structures. In addition, the packaging materials do not have radiation resistance and cannot meet the reliability requirements of aerospace application environments. Summary of the invention

[0005] The present invention provides an aerospace image sensor chip packaging structure and a packaging method thereof to solve the deficiencies of the above-mentioned prior art, realize high-reliability packaging of image sensor chips for aerospace applications, and also meet the miniaturization and lightweight requirements of image sensor chips for aerospace applications.

[0006] In order to achieve the purpose of the present invention, the following technologies are proposed: On the one hand, a space image sensor chip packaging structure is proposed, including a tube shell, the upper end of the tube shell is opened to form a core cavity, a chip is arranged at the bottom of the groove of the core cavity, the chip is an image sensor, the chip is connected to the tube shell through a plurality of bonding wires, a plurality of pins are arranged at the lower end of the tube shell, and a glass cover is arranged at the core cavity of the tube shell. The glass cover is attached to the core cavity of the tube shell through a sealing rubber ring. The chip is attached to the bottom of the core cavity through an insulating adhesive.

[0007] Furthermore, the shell is formed by sintering and pressing multiple layers of alumina ceramic layers and multiple layers of tungsten metal conductor layers at 1600°C, and there are multiple metal vias on the ceramic layer. The metal conductor layers are connected to each other through the metal vias on the ceramic layer. The shell is made of ceramic because the material has many advantages such as high mechanical strength, high thermal conductivity, corrosion resistance, and stable chemical properties. Tungsten is used as the signal transmission line because it has a high melting point, which facilitates the sintering and pressing of the shell. Its structural characteristics will not change during the molding process. In addition, it has high hardness and strength, serving as the skeleton of the entire shell, thereby further enhancing the shell's impact resistance and other properties. In addition, it also has a low thermal expansion coefficient, thereby avoiding deformation or damage to the shell in space with large changes in high and low temperatures. In addition, it also has good electrical and thermal conductivity, making it the best material for the metal layer.

[0008] Furthermore, the pins are made of Kovar alloy so that the pins have a very low thermal expansion coefficient, which is close to the thermal expansion coefficient of the tube shell, thereby improving the reliability of use in high and low temperature environments.

[0009] Furthermore, a plurality of mounting holes are provided on the tube shell, some of which can be used for connection between the tube shell and the flange by means of screws, and the other parts are used for positioning the tube shell during installation.

[0010] Furthermore, in order to ensure the optical center accuracy of the image sensor chip after being packaged in a tube shell, the flatness of the area at the bottom of the core cavity for pasting the chip is 0.05mm, the roughness is 0.8μm, and the parallelism between the area at the bottom of the core cavity for pasting the chip and the bottom surface of the tube shell is 0.08mm. Furthermore, a plurality of identification pieces are provided on the tube shell, and the identification pieces are made of gold. Four identification pieces mark the geometric center of the tube shell and are used as alignment references when installing the glass cover plate.

[0011] Further, the tube shell includes, from top to bottom, a first ceramic layer, a second ceramic layer, a third ceramic layer, a fourth ceramic layer, a fifth ceramic layer, a sixth ceramic layer, a seventh ceramic layer, an eighth ceramic layer, a ninth ceramic layer, a tenth ceramic layer, an eleventh ceramic layer, a twelfth ceramic layer, a thirteenth ceramic layer and a fourteenth ceramic layer; a first metal layer is provided on the upper side of the second ceramic layer, a second metal layer is provided on the upper side of the third ceramic layer, a third metal layer is provided on the upper side of the fourth ceramic layer, a fourth metal layer is provided on the upper side of the fifth ceramic layer, a fifth metal layer is provided on the upper side of the sixth ceramic layer, a sixth metal layer is provided on the upper side of the seventh ceramic layer, a seventh metal layer is provided on the upper side of the eighth ceramic layer, an eighth metal layer is provided on the upper side of the ninth ceramic layer, a ninth metal layer is provided on the upper side of the tenth ceramic layer, a tenth metal layer is provided on the upper side of the eleventh ceramic layer, an eleventh metal layer is provided on the upper side of the twelfth ceramic layer, a twelfth metal layer is provided on the upper side of the thirteenth ceramic layer, a thirteenth metal layer is provided on the upper side of the fourteenth ceramic layer, and a fourteenth metal layer is provided on the lower side of the fourteenth ceramic layer; The first ceramic layer, the second ceramic layer, the third ceramic layer, the fourth ceramic layer, the fifth ceramic layer and the sixth ceramic layer are all provided with notches. After the tube shell is sintered and pressed into shape, the core cavity is formed by the combination of the notches.

[0012] Further: The first metal layer is the GNDA analog ground plane layer; The second metal layer has a plurality of connection pins and a portion of LVDS differential pair output signal lines, and the other end of the bonding wire is connected to the connection pin formed on the second metal layer; The third metal layer is the GNDD digital ground plane layer and the pixel control signal low level layer; The fourth metal layer is the GNDD digital ground plane layer, on which there are another part of LVDS differential pair signal routing and TANA analog output signal routing; The fifth metal layer is the GNDD digital ground plane layer, which has digital input signal routing and digital output signal routing; The sixth metal layer is the GNDA analog ground plane layer, which has the phase-locked loop power ground trace; The seventh metal layer is the VDDA analog power layer; The eighth metal layer is the GNDD digital ground plane layer and the pixel control signal high level layer; The ninth metal layer is the VDDD digital power layer; The tenth metal layer is a pixel control signal low level and high level layer; The eleventh metal layer is the GNDA analog ground plane layer and the pixel control signal low level and high level layer, which has a positive voltage LDO power supply; The twelfth metal layer is the GNDA analog ground plane layer, which has negative voltage LDO power supply, digital input signal high level signal routing and analog bias signal routing; The thirteenth metal layer is the VDDPIX pixel power layer; The fourteenth metal layer is a pad, and the pins are welded on the fourteenth metal layer.

[0013] Further: The first metal layer is connected to the second metal layer through the metal via on the second ceramic layer for transmitting the GNDA analog ground plane signal; The second metal layer is connected to the third metal layer through the metal via on the third ceramic layer, and is used for the transmission of the GNDD digital ground plane signal and the pixel control signal low level signal; The second metal layer is connected to the fourth metal layer through metal vias on the third ceramic layer and the fourth ceramic layer, and is used for transmitting a portion of the LVDS differential pair signals and the TANA analog output signals; The second metal layer is connected to the fifth metal layer through metal vias on the third ceramic layer, the fourth ceramic layer and the fifth ceramic layer, and is used for transmission of digital input signals and digital output signals; The second metal layer is connected to the sixth metal layer through metal vias on the third ceramic layer, the fourth ceramic layer, the fifth ceramic layer and the sixth ceramic layer, and is used for transmitting the GNDA analog ground plane signal and the phase-locked loop power ground signal; The second metal layer is connected to the seventh metal layer through metal vias on the third ceramic layer, the fourth ceramic layer, the fifth ceramic layer, the sixth ceramic layer and the seventh ceramic layer, and is used for transmitting the VDDA analog power signal; The second metal layer is connected to the eighth metal layer through metal vias on the third ceramic layer, the fourth ceramic layer, the fifth ceramic layer, the sixth ceramic layer, the seventh ceramic layer and the eighth ceramic layer, and is used for transmitting high-level signals of pixel control signals; The second metal layer is connected to the ninth metal layer through metal vias on the third ceramic layer, the fourth ceramic layer, the fifth ceramic layer, the sixth ceramic layer, the seventh ceramic layer, the eighth ceramic layer and the ninth ceramic layer, and is used for transmitting the VDDD digital power signal; The second metal layer is connected to the eleventh metal layer through metal vias on the third ceramic layer, the fourth ceramic layer, the fifth ceramic layer, the sixth ceramic layer, the seventh ceramic layer, the eighth ceramic layer, the ninth ceramic layer, the tenth ceramic layer and the eleventh ceramic layer, and is used for transmitting a positive voltage LDO power supply signal; The second metal layer is connected to the twelfth metal layer through metal vias on the third ceramic layer, the fourth ceramic layer, the fifth ceramic layer, the sixth ceramic layer, the seventh ceramic layer, the eighth ceramic layer, the ninth ceramic layer, the tenth ceramic layer, the eleventh ceramic layer and the twelfth ceramic layer, and is used for transmission of negative voltage LDO power supply signals, digital input signals and analog bias signals; The second metal layer is connected to the thirteenth metal layer through metal vias on the third ceramic layer, the fourth ceramic layer, the fifth ceramic layer, the sixth ceramic layer, the seventh ceramic layer, the eighth ceramic layer, the ninth ceramic layer, the tenth ceramic layer, the eleventh ceramic layer, the twelfth ceramic layer and the thirteenth ceramic layer for transmitting a VDDPIX pixel power signal; The third metal layer is connected to the fourth metal layer through a metal via on the fourth ceramic layer for transmission of the GNDD digital ground plane signal; The third metal layer is connected to the tenth metal layer through metal vias on the fourth ceramic layer, the fifth ceramic layer, the sixth ceramic layer, the seventh ceramic layer, the eighth ceramic layer, the ninth ceramic layer, and the tenth ceramic layer, and is used for transmitting low-level signals of pixel control signals; The fourth metal layer is connected to the fifth metal layer through a metal via on the fifth ceramic layer for transmitting a GNDD digital ground plane signal; The fourth metal layer is connected to the fourteenth metal layer through metal vias on the fifth ceramic layer, the sixth ceramic layer, the seventh ceramic layer, the eighth ceramic layer, the ninth ceramic layer, the tenth ceramic layer, the eleventh ceramic layer, the twelfth ceramic layer and the thirteenth ceramic layer, and is used for the transmission of LVDS differential pair signals and TANA analog output signals, and is led out through pins; The fifth metal layer is connected to the eighth metal layer through metal vias on the sixth ceramic layer, the seventh ceramic layer, and the eighth ceramic layer, and is used for transmission of the GNDD digital ground plane signal; The fifth metal layer is connected to the fourteenth metal layer through metal vias on the sixth ceramic layer, the seventh ceramic layer, the eighth ceramic layer, the ninth ceramic layer, the tenth ceramic layer, the eleventh ceramic layer, the twelfth ceramic layer and the thirteenth ceramic layer, and is used for transmission of the GNDD digital ground plane signal and is led out through pins; The sixth metal layer is connected to the eleventh metal layer through metal vias on the seventh ceramic layer, the eighth ceramic layer, the ninth ceramic layer, the tenth ceramic layer and the eleventh ceramic layer, and is used for transmission of GNDA analog ground plane signals; The sixth metal layer is connected to the fourteenth metal layer through metal vias on the seventh ceramic layer, the eighth ceramic layer, the ninth ceramic layer, the tenth ceramic layer, the eleventh ceramic layer, the twelfth ceramic layer and the thirteenth ceramic layer, and is used for transmitting the phase-locked loop power ground signal and is led out through the pins; The seventh metal layer is connected to the fourteenth metal layer through metal vias on the eighth ceramic layer, the ninth ceramic layer, the tenth ceramic layer, the eleventh ceramic layer, the twelfth ceramic layer and the thirteenth ceramic layer, and is used for transmitting the VDDA analog power supply signal and is led out through the pin; The eighth metal layer is connected to the tenth metal layer through metal vias on the ninth ceramic layer and the tenth ceramic layer, and is used for transmitting high-level signals of pixel control signals; The eighth metal layer is connected to the fourteenth metal layer through metal vias on the ninth ceramic layer, the tenth ceramic layer, the eleventh ceramic layer, the twelfth ceramic layer and the thirteenth ceramic layer, and is used for transmission of the GNDD digital ground plane signal, and is led out through pins; The ninth metal layer is connected to the fourteenth metal layer through metal vias on the tenth ceramic layer, the eleventh ceramic layer, the twelfth ceramic layer and the thirteenth ceramic layer, and is used for transmitting the VDDD digital power signal and is led out through the pins; The tenth metal layer is connected to the eleventh metal layer through the metal via on the eleventh ceramic layer, and is used for transmitting low-level pixel control signals and high-level pixel control signals; The eleventh metal layer is connected to the twelfth metal layer through a metal via on the twelfth ceramic layer for transmitting the GNDA analog ground plane signal; The eleventh metal layer is connected to the fourteenth metal layer through metal vias on the twelfth ceramic layer and the thirteenth ceramic layer, and is used for transmitting a positive voltage LDO power supply signal; The twelfth metal layer is connected to the fourteenth metal layer through the metal vias on the thirteenth ceramic layer, and is used for the transmission of GNDA analog ground plane signals, negative voltage LDO power supply signals, digital input signals, and analog bias signals, and is led out through pins; The thirteenth metal layer is connected to the fourteenth metal layer through a metal via on the thirteenth ceramic layer, is used for transmitting a VDDPIX pixel power supply signal, and is led out through a pin.

[0014] On the other hand, a method for packaging an aerospace image sensor chip is provided, which is used for packaging an aerospace image sensor chip packaging structure, comprising the steps of: Step 01: Perform microscopic inspection on the cut chips, and perform the requirements described in the GJB548C-2005 standard during microscopic inspection.

[0015] Step 02, use a chip mounter to stick the chip into the core cavity of the tube shell through insulating glue; When loading, the horizontal / vertical tolerance between the center of the chip and the center of the tube shell is less than ±20μm; The chip's pitch angle deviation error should be less than ±0.05°; The rotation angle deviation error of the chip should be less than ±0.3°; Step 03, curing the chip in the core cavity of the tube shell, the curing condition is baking at 150°C for 1 hour.

[0016] Step 04, test the chip mounting results, implement GJB548C-2005 standard during the test, use X-ray machine to test the porosity of the insulating glue, and test whether the position of the chip meets the set requirements.

[0017] Step 05: Bond the chip to the shell using gold wire bonding wire.

[0018] Step 06, the bonding results are tested by scanning electron microscopy. Before the test, high temperature storage at 300°C for 1-24 hours is required.

[0019] Step 07, stick the glass cover to the core cavity of the tube shell through the XZ-A sealing rubber ring. When sealing, the tube shell needs to be preheated first, and it is necessary to ensure that there is no debris and dust in the core cavity. The curing condition of the XZ-A sealing rubber ring is baking at 120°C for 1.5 hours.

[0020] Step 08, test the air tightness of the sealed core cavity, and the air tightness of the core cavity is ≤10 -8 Pa·m 3 / s, the detection standard is based on the GJB548C-2005 leak detection method.

[0021] Step 09, printing the circuit model, production cycle, and electrostatic discharge sensitivity level identification information on the back side of the tube shell by laser printing.

[0022] The advantages of the above technical solution are: Compared with the existing plastic-encapsulated substrate image sensor chip, the present invention adopts a high-temperature co-fired ceramic substrate formed by sintering and pressing multiple layers of ceramics, which is convenient for forming a multi-layer circuit structure for highly integrated chips; it can better control the flatness, parallelism and roughness of the packaging substrate surface, which is conducive to the chip mounting accuracy to meet application requirements. In addition, the high-temperature co-fired ceramic structure is stable, and the high thermal conductivity is conducive to chip heat dissipation, which can meet the high reliability requirements of aerospace applications.

[0023] The glass cover plate, a key raw material used in the packaging structure of the present invention, has radiation resistance, and after being irradiated with high-energy gamma rays, the optical properties such as internal transmittance have basically no obvious attenuation changes. In addition, by coating the glass cover plate with an anti-reflection film on both sides, the transmittance of the glass cover plate in the visible light band is guaranteed to be ≥97%, which can meet the application requirements of aerospace environment.

[0024] Existing image sensors usually have difficulty meeting the requirements for device sealing. In the ceramic tube shell of the present invention, the sealing portion is sealed by sticking an XZ-A sealing rubber ring to a glass cover plate, and the rubber ring is cured at high temperature to improve the airtightness of the tube shell sealing portion. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to make the objectives, technical solutions and advantages of the present invention more clear, the present invention will be further described in detail below with reference to the accompanying drawings.

[0026] Figure 1 The three-dimensional structure of the image sensor chip packaging structure for aerospace Figure 1 .

[0027] Figure 2 The three-dimensional structure of the image sensor chip packaging structure for aerospace Figure 2 .

[0028] Figure 3 The diagram shows the layering of the tube shell and the connection relationship between the layers.

[0029] Figure 4 The present invention shows a flow chart of a method for packaging an image sensor chip for aerospace use. DETAILED DESCRIPTION

[0030] Example 1 like Figure 1~Figure 2 As shown, a space image sensor chip packaging structure includes a tube shell 1, the upper end of the tube shell 1 is opened to form a core cavity 102, the groove bottom of the core cavity 102 is provided with a chip 4, the chip 4 is an image sensor, and the chip 4 is connected to the tube shell 1 through a plurality of bonding wires 5, the lower end of the tube shell 1 is provided with a plurality of pins 2, and the core cavity 102 of the tube shell 1 is provided with a glass cover plate 3. The glass cover plate 3 is attached to the core cavity 102 of the tube shell 1 through a sealing rubber ring. The chip 4 is attached to the bottom of the core cavity 102 through an insulating adhesive.

[0031] The shell 1 is formed by sintering and pressing multiple layers of alumina ceramic layers and multiple layers of tungsten metal conductor layers at 1600°C, and there are multiple metal vias on the ceramic layer. The metal conductor layers are connected by signals through the metal vias on the ceramic layer. The shell is made of ceramic because the material has many advantages such as high mechanical strength, high thermal conductivity, corrosion resistance, and stable chemical properties. Tungsten is used as the signal transmission line because it has a high melting point, which is convenient for sintering and pressing the shell 1. Its structural characteristics will not change during the molding process. In addition, it also has high hardness and strength, as the skeleton of the entire shell, thereby further enhancing the shell's impact resistance and other properties. In addition, it also has a low thermal expansion coefficient, thereby avoiding the problem of deformation or damage of the shell in space with large changes in high and low temperatures. In addition, it also has good electrical conductivity and thermal conductivity, making it the best material for the metal layer. The shell 1 is provided with multiple mounting holes 150, some of which can be used for connection between the shell and the flange through screws, and the other part is used for positioning when the shell is installed. In order to ensure the optical center accuracy of the image sensor chip after being packaged in the tube shell, the flatness of the area at the bottom of the core cavity 102 for pasting the chip 4 is 0.05mm, the roughness is 0.8μm, and the parallelism between the area at the bottom of the core cavity 102 for pasting the chip 4 and the ground of the tube shell 1 is 0.08mm. The tube shell 1 is provided with a plurality of identification members 101, which are made of gold and are used as alignment references when installing the glass cover.

[0032] Pin 2 is made of Kovar alloy so that the pin has a very low thermal expansion coefficient, which is close to the thermal expansion coefficient of the tube shell, thereby improving the reliability of use in high and low temperature environments.

[0033] like Figure 3As shown, the tube shell 1 includes, from top to bottom, a first ceramic layer 10, a second ceramic layer 20, a third ceramic layer 30, a fourth ceramic layer 40, a fifth ceramic layer 50, a sixth ceramic layer 60, a seventh ceramic layer 70, an eighth ceramic layer 80, a ninth ceramic layer 90, a tenth ceramic layer 100, an eleventh ceramic layer 110, a twelfth ceramic layer 120, a thirteenth ceramic layer 130 and a fourteenth ceramic layer 140. The identification part 101 is arranged on the first ceramic layer 10, the first metal layer is provided on the upper side of the second ceramic layer 20, the second metal layer is provided on the upper side of the third ceramic layer 30, the third metal layer is provided on the upper side of the fourth ceramic layer 40, the fourth metal layer is provided on the upper side of the fifth ceramic layer 50, the fifth metal layer is provided on the upper side of the sixth ceramic layer 60, the sixth metal layer is provided on the upper side of the seventh ceramic layer 70, the seventh metal layer is provided on the upper side of the eighth ceramic layer 80, the eighth metal layer is provided on the upper side of the ninth ceramic layer 90, the ninth metal layer is provided on the upper side of the tenth ceramic layer 100, the tenth metal layer is provided on the upper side of the eleventh ceramic layer 110, the eleventh metal layer is provided on the upper side of the twelfth ceramic layer 120, the twelfth metal layer is provided on the upper side of the thirteenth ceramic layer 130, the thirteenth metal layer is provided on the upper side of the fourteenth ceramic layer 140, and the fourteenth metal layer is provided on the lower side of the fourteenth ceramic layer 140.

[0034] The first ceramic layer 10 , the second ceramic layer 20 , the third ceramic layer 30 , the fourth ceramic layer 40 , the fifth ceramic layer 50 and the sixth ceramic layer 60 are all provided with notches. After the tube shell 1 is sintered and pressed into shape, the core cavity 102 is formed by the combination of the notches.

[0035] The first metal layer is the GNDA analog ground plane layer. The second metal layer has a plurality of connection pins and a part of the LVDS differential pair output signal lines, and the other end of the bonding wire 5 is connected to the connection pin formed by the second metal layer. The third metal layer is the GNDD digital ground plane layer and the pixel control signal low level layer. The fourth metal layer is the GNDD digital ground plane layer, which has another part of the LVDS differential pair signal routing and the TANA analog output signal routing. The fifth metal layer is the GNDD digital ground plane layer, which has the digital input signal routing and the digital output signal routing. The sixth metal layer is the GNDA analog ground plane layer, which has the phase-locked loop power ground routing. The seventh metal layer is the VDDA analog power layer. The eighth metal layer is the GNDD digital ground plane layer and the pixel control signal high level layer. The ninth metal layer is the VDDD digital power layer. The tenth metal layer is the pixel control signal low level and high level layer. The eleventh metal layer is the GNDA analog ground plane layer and the pixel control signal low level and high level layer, which has a positive voltage LDO power supply. The twelfth metal layer is the GNDA analog ground plane layer, which has negative voltage LDO power supply, digital input signal high level signal routing and analog bias signal routing. The thirteenth metal layer is the VDDPIX pixel power layer. The fourteenth metal layer is the pad, and pin 2 is welded on the fourteenth metal layer.

[0036] The first metal layer is connected to the second metal layer through the metal vias on the second ceramic layer 20 for transmitting the GNDA analog ground plane signal.

[0037] The second metal layer is connected to the third metal layer through the metal vias on the third ceramic layer 30 and is used for transmission of the GNDD digital ground plane signal and the low level signal of the pixel control signal.

[0038] The second metal layer is connected to the fourth metal layer through metal vias on the third ceramic layer 30 and the fourth ceramic layer 40 , and is used for transmitting a portion of the LVDS differential pair signals and the TANA analog output signals.

[0039] The second metal layer is connected to the fifth metal layer through metal vias on the third ceramic layer 30 , the fourth ceramic layer 40 and the fifth ceramic layer 50 , and is used for transmission of digital input signals and digital output signals.

[0040] The second metal layer is connected to the sixth metal layer through metal vias on the third ceramic layer 30 , the fourth ceramic layer 40 , the fifth ceramic layer 50 and the sixth ceramic layer 60 , and is used for transmitting the GNDA analog ground plane signal and the phase-locked loop power ground signal.

[0041] The second metal layer is connected to the seventh metal layer through metal vias on the third ceramic layer 30 , the fourth ceramic layer 40 , the fifth ceramic layer 50 , the sixth ceramic layer 60 and the seventh ceramic layer 70 for transmitting the VDDA analog power signal.

[0042] The second metal layer is connected to the eighth metal layer through metal vias on the third ceramic layer 30 , the fourth ceramic layer 40 , the fifth ceramic layer 50 , the sixth ceramic layer 60 , the seventh ceramic layer 70 and the eighth ceramic layer 80 for transmitting high-level pixel control signals.

[0043] The second metal layer is connected to the ninth metal layer through metal vias on the third ceramic layer 30 , the fourth ceramic layer 40 , the fifth ceramic layer 50 , the sixth ceramic layer 60 , the seventh ceramic layer 70 , the eighth ceramic layer 80 and the ninth ceramic layer 90 for transmitting the VDDD digital power signal.

[0044] The second metal layer is connected to the eleventh metal layer through metal vias on the third ceramic layer 30, the fourth ceramic layer 40, the fifth ceramic layer 50, the sixth ceramic layer 60, the seventh ceramic layer 70, the eighth ceramic layer 80, the ninth ceramic layer 90, the tenth ceramic layer 100 and the eleventh ceramic layer 110 for transmitting the positive voltage LDO power signal.

[0045] The second metal layer is connected to the twelfth metal layer through metal vias on the third ceramic layer 30, the fourth ceramic layer 40, the fifth ceramic layer 50, the sixth ceramic layer 60, the seventh ceramic layer 70, the eighth ceramic layer 80, the ninth ceramic layer 90, the tenth ceramic layer 100, the eleventh ceramic layer 110 and the twelfth ceramic layer 120, and is used for transmitting negative voltage LDO power signals, digital input signals and analog bias signals.

[0046] The second metal layer is connected to the thirteenth metal layer through metal vias on the third ceramic layer 30, the fourth ceramic layer 40, the fifth ceramic layer 50, the sixth ceramic layer 60, the seventh ceramic layer 70, the eighth ceramic layer 80, the ninth ceramic layer 90, the tenth ceramic layer 100, the eleventh ceramic layer 110, the twelfth ceramic layer 120 and the thirteenth ceramic layer 130 for transmission of the VDDPIX pixel power signal.

[0047] The third metal layer is connected to the fourth metal layer through the metal vias on the fourth ceramic layer 40 for transmission of the GNDD digital ground plane signal.

[0048] The third metal layer is connected to the tenth metal layer through metal vias on the fourth ceramic layer 40, the fifth ceramic layer 50, the sixth ceramic layer 60, the seventh ceramic layer 70, the eighth ceramic layer 80, the ninth ceramic layer 90 and the tenth ceramic layer 100 for transmitting low-level pixel control signals.

[0049] The fourth metal layer is connected to the fifth metal layer through the metal vias on the fifth ceramic layer 50 for transmission of the GNDD digital ground plane signal.

[0050] The fourth metal layer is connected to the fourteenth metal layer through metal vias on the fifth ceramic layer 50, the sixth ceramic layer 60, the seventh ceramic layer 70, the eighth ceramic layer 80, the ninth ceramic layer 90, the tenth ceramic layer 100, the eleventh ceramic layer 110, the twelfth ceramic layer 120 and the thirteenth ceramic layer 130, and is used for the transmission of LVDS differential pair signals and TANA analog output signals, and is brought out through pin 2.

[0051] The fifth metal layer is connected to the eighth metal layer through metal vias on the sixth ceramic layer 60 , the seventh ceramic layer 70 , and the eighth ceramic layer 80 for transmission of the GNDD digital ground plane signal.

[0052] The fifth metal layer is connected to the fourteenth metal layer through metal vias on the sixth ceramic layer 60 , the seventh ceramic layer 70 , the eighth ceramic layer 80 , the ninth ceramic layer 90 , the tenth ceramic layer 100 , the eleventh ceramic layer 110 , the twelfth ceramic layer 120 and the thirteenth ceramic layer 130 , and is used for transmission of the GNDD digital ground plane signal and is brought out through pin 2.

[0053] The sixth metal layer is connected to the eleventh metal layer through metal vias on the seventh ceramic layer 70 , the eighth ceramic layer 80 , the ninth ceramic layer 90 , the tenth ceramic layer 100 and the eleventh ceramic layer 110 for transmission of GNDA analog ground plane signals.

[0054] The sixth metal layer is connected to the fourteenth metal layer through metal vias on the seventh ceramic layer 70, the eighth ceramic layer 80, the ninth ceramic layer 90, the tenth ceramic layer 100, the eleventh ceramic layer 110, the twelfth ceramic layer 120 and the thirteenth ceramic layer 130, and is used for transmitting the phase-locked loop power ground signal and is led out through pin 2.

[0055] The seventh metal layer is connected to the fourteenth metal layer through metal vias on the eighth ceramic layer 80 , the ninth ceramic layer 90 , the tenth ceramic layer 100 , the eleventh ceramic layer 110 , the twelfth ceramic layer 120 and the thirteenth ceramic layer 130 for transmitting the VDDA analog power signal and leading out through pin 2.

[0056] The eighth metal layer is connected to the tenth metal layer through metal vias on the ninth ceramic layer 90 and the tenth ceramic layer 100 for transmitting high-level signals of pixel control signals.

[0057] The eighth metal layer is connected to the fourteenth metal layer through metal vias on the ninth ceramic layer 90 , the tenth ceramic layer 100 , the eleventh ceramic layer 110 , the twelfth ceramic layer 120 and the thirteenth ceramic layer 130 for transmitting the GNDD digital ground plane signal and is led out through pin 2 .

[0058] The ninth metal layer is connected to the fourteenth metal layer through metal vias on the tenth ceramic layer 100 , the eleventh ceramic layer 110 , the twelfth ceramic layer 120 and the thirteenth ceramic layer 130 for transmitting the VDDD digital power signal and is led out through pin 2 .

[0059] The tenth metal layer is connected to the eleventh metal layer through the metal via on the eleventh ceramic layer 110 , and is used for transmitting low-level pixel control signals and high-level pixel control signals.

[0060] The eleventh metal layer is connected to the twelfth metal layer through the metal via on the twelfth ceramic layer 120 for transmission of the GNDA analog ground plane signal.

[0061] The eleventh metal layer is connected to the fourteenth metal layer through metal vias on the twelfth ceramic layer 120 and the thirteenth ceramic layer 130 for transmitting a positive voltage LDO power signal.

[0062] The twelfth metal layer is connected to the fourteenth metal layer through the metal via on the thirteenth ceramic layer 130, and is used for the transmission of the GNDA analog ground plane signal, the negative voltage LDO power supply signal, the digital input signal, and the analog bias signal, and is led out through pin 2.

[0063] The thirteenth metal layer is connected to the fourteenth metal layer through a metal via on the thirteenth ceramic layer 130 , is used for transmitting a VDDPIX pixel power signal, and is led out through the pin 2 .

[0064] Specifically, the chip 4 is connected to the second metal layer through the bonding wire 5 , and finally the chip 4 is powered, inputted, and outputted through the pins 2 on the tube shell 1 .

[0065] Among them, the GNDA analog ground plane signal is transmitted through the first metal layer, the second metal layer, the sixth metal layer, the eleventh metal layer, the twelfth metal layer, and the fourteenth metal layer, and is finally turned on and led out through pin 2.

[0066] The GNDD digital ground plane signal is transmitted through the second metal layer, the third metal layer, the fourth metal layer, the fifth metal layer, the eighth metal layer, and the fourteenth metal layer, and is finally turned on and led out through pin 2.

[0067] The pixel control signal low level signal is transmitted through the second metal layer, the third metal layer, the tenth metal layer, the eleventh metal layer, and the fourteenth metal layer, and is finally turned on and led out through the pin 2.

[0068] The high-level signal of the pixel control signal is transmitted through the second metal layer, the eighth metal layer, the tenth metal layer, the eleventh metal layer, and the fourteenth metal layer, and is finally turned on and led out through the pin 2.

[0069] The LVDS differential pair signal is transmitted through the second metal layer, the fourth metal layer, and the fourteenth metal layer, and is finally conducted and led out through pin 2.

[0070] The TANA analog output signal is transmitted through the second metal layer, the fourth metal layer, and the fourteenth metal layer, and is finally turned on and led out through pin 2.

[0071] The digital input signal and the digital output signal are transmitted through the second metal layer, the fifth metal layer, the twelfth metal layer, and the fourteenth metal layer, and are finally conducted and led out through pin 2.

[0072] The VDDA analog power signal is transmitted through the second metal layer, the seventh metal layer, and the fourteenth metal layer, and is finally turned on and led out through pin 2.

[0073] The VDDD digital power signal is transmitted through the second metal layer, the ninth metal layer, and the fourteenth metal layer, and is finally turned on and led out through pin 2.

[0074] The positive voltage LDO power signal is transmitted through the second metal layer, the eleventh metal layer, and the fourteenth metal layer, and is finally turned on and led out through pin 2.

[0075] The negative voltage LDO power signal is transmitted through the second metal layer, the twelfth metal layer, and the fourteenth metal layer, and is finally turned on and led out through pin 2.

[0076] The analog bias signal is transmitted through the second metal layer, the twelfth metal layer and the fourteenth metal layer, and is finally conducted and led out through pin 2.

[0077] The VDDPIX pixel power signal is transmitted through the second metal layer, the thirteenth metal layer, and the fourteenth metal layer, and is finally turned on and led out through pin 2.

[0078] Example 2 like Figure 4 As shown, a method for packaging an aerospace image sensor chip is used for packaging an aerospace image sensor chip packaging structure, comprising the steps of: Step 01, perform microscopic inspection on the cut chip 4, and perform the requirements described in the GJB548C-2005 standard during the microscopic inspection.

[0079] Step 02, using a chip mounter to stick the chip 4 into the core cavity 102 of the tube shell 1 through insulating glue; When mounting, the horizontal / vertical tolerance between the center position of the chip 4 and the center of the tube shell 1 is less than ±20μm; The pitch angle deviation error of chip 4 should be less than ±0.05°; The rotation angle deviation error of chip 4 should be less than ±0.3°; Step 03, curing the chip 4 in the core cavity 102 on the tube shell 1, the curing condition is baking at 150° C. for 1 hour.

[0080] Step 04, the chip 4 mounting result is tested according to the GJB548C-2005 standard, the porosity of the insulating glue is tested by an X-ray machine, and the position of the chip is tested to see if it meets the set requirements.

[0081] Step 05, bonding the chip 4 and the tube shell 1 through the gold wire bonding wire 5.

[0082] Step 06, the bonding results are tested by scanning electron microscopy. Before the test, high temperature storage at 300°C for 1-24 hours is required.

[0083] Step 07, stick the glass cover plate 3 to the core cavity 102 of the tube shell 1 through the XZ-A sealing rubber ring. When sealing, the tube shell 1 needs to be preheated first, and it is necessary to ensure that there is no debris and dust in the core cavity 102. The curing condition of the XZ-A sealing rubber ring is baking at 120°C for 1.5 hours.

[0084] Step 08, the air tightness of the sealed core cavity 102 is tested, and the air tightness of the core cavity 102 is ≤10 - 8 Pa·m 3 / s, the detection standard is based on the GJB548C-2005 leak detection method.

[0085] Step 09, printing the circuit model, production cycle, and electrostatic discharge sensitivity level identification information on the back side of the tube shell 1 by laser printing.

[0086] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims

1. An aerospace image sensor chip packaging structure, characterized in that: The tube shell (1) comprises a tube shell (1), the upper end of the tube shell (1) is open and formed with a core cavity (102), a chip (4) is provided at the bottom of the groove of the core cavity (102), the chip (4) is connected to the tube shell (1) through a plurality of bonding wires (5), a plurality of pins (2) are provided at the lower end of the tube shell (1), and a glass cover plate (3) is provided at the core cavity (102) of the tube shell (1); The glass cover plate (3) is adhered to the core cavity (102) of the tube shell (1) via a sealing rubber ring; The chip (4) is adhered to the bottom of the core cavity (102) by means of insulating glue.

2. The aerospace image sensor chip packaging structure according to claim 1, characterized in that: The tube shell (1) is formed by sintering and pressing multiple ceramic layers and multiple metal conductor layers at 1600° C., and the ceramic layers are provided with multiple metal vias, and the metal conductor layers are electrically connected via the metal vias on the ceramic layers.

3. The aerospace image sensor chip packaging structure according to claim 1, characterized in that: The pins (2) are made of Kovar.

4. The aerospace image sensor chip packaging structure according to claim 1, characterized in that: A plurality of mounting holes (150) are provided on the tube shell (1).

5. The aerospace image sensor chip packaging structure according to claim 1, characterized in that: The flatness of the area at the bottom of the core cavity (102) for pasting the chip (4) is 0.05 mm, the roughness is 0.8 μm, and the parallelism between the area at the bottom of the core cavity (102) for pasting the chip (4) and the ground of the tube shell (1) is 0.08 mm.

6. The aerospace image sensor chip packaging structure according to claim 1, characterized in that: A plurality of identification pieces (101) are provided on the tube shell (1); the identification pieces (101) are made of gold, and the identification pieces (101) are used as alignment references during installation.

7. The aerospace image sensor chip packaging structure according to claim 2, characterized in that: The tube shell (1) comprises, from top to bottom, a first ceramic layer (10), a second ceramic layer (20), a third ceramic layer (30), a fourth ceramic layer (40), a fifth ceramic layer (50), a sixth ceramic layer (60), a seventh ceramic layer (70), an eighth ceramic layer (80), a ninth ceramic layer (90), a tenth ceramic layer (100), an eleventh ceramic layer (110), a twelfth ceramic layer (120), a thirteenth ceramic layer (130) and a fourteenth ceramic layer (140); A first metal layer is provided on the upper side of the second ceramic layer (20), a second metal layer is provided on the upper side of the third ceramic layer (30), a third metal layer is provided on the upper side of the fourth ceramic layer (40), a fourth metal layer is provided on the upper side of the fifth ceramic layer (50), a fifth metal layer is provided on the upper side of the sixth ceramic layer (60), a sixth metal layer is provided on the upper side of the seventh ceramic layer (70), a seventh metal layer is provided on the upper side of the eighth ceramic layer (80), an eighth metal layer is provided on the upper side of the ninth ceramic layer (90), a ninth metal layer is provided on the upper side of the tenth ceramic layer (100), a tenth metal layer is provided on the upper side of the eleventh ceramic layer (110), an eleventh metal layer is provided on the upper side of the twelfth ceramic layer (120), a twelfth metal layer is provided on the upper side of the thirteenth ceramic layer (130), a thirteenth metal layer is provided on the upper side of the fourteenth ceramic layer (140), and a fourteenth metal layer is provided on the lower side of the fourteenth ceramic layer (140); The first ceramic layer (10), the second ceramic layer (20), the third ceramic layer (30), the fourth ceramic layer (40), the fifth ceramic layer (50) and the sixth ceramic layer (60) are all provided with notches, and after the tube shell (1) is sintered and pressed into shape, the core cavity (102) is formed by combining the notches.

8. The aerospace image sensor chip packaging structure according to claim 7, characterized in that: The first metal layer is the GNDA analog ground plane layer; The second metal layer has a plurality of connection pins and a portion of LVDS differential pair output signal lines, and the other end of the bonding wire (5) is connected to the connection pin formed on the second metal layer; The third metal layer is the GNDD digital ground plane layer and the pixel control signal low level layer; The fourth metal layer is the GNDD digital ground plane layer, on which there are another part of LVDS differential pair signal routing and TANA analog output signal routing; The fifth metal layer is the GNDD digital ground plane layer, which has digital input signal routing and digital output signal routing; The sixth metal layer is the GNDA analog ground plane layer, which has the phase-locked loop power ground trace; The seventh metal layer is the VDDA analog power layer; The eighth metal layer is the GNDD digital ground plane layer and the pixel control signal high level layer; The ninth metal layer is the VDDD digital power layer; The tenth metal layer is a pixel control signal low level and high level layer; The eleventh metal layer is the GNDA analog ground plane layer and the pixel control signal low level and high level layer, which has a positive voltage LDO power supply; The twelfth metal layer is the GNDA analog ground plane layer, which has negative voltage LDO power supply, digital input signal high level signal routing and analog bias signal routing; The thirteenth metal layer is the VDDPIX pixel power layer; The fourteenth metal layer is a soldering pad, and the pin (2) is soldered on the fourteenth metal layer.

9. The aerospace image sensor chip packaging structure according to claim 8, characterized in that: The first metal layer is connected to the second metal layer through a metal via on the second ceramic layer (20) for transmitting a GNDA analog ground plane signal; The second metal layer is connected to the third metal layer through a metal via on the third ceramic layer (30) and is used for transmitting the GNDD digital ground plane signal and the pixel control signal low level signal; The second metal layer is connected to the fourth metal layer through metal vias on the third ceramic layer (30) and the fourth ceramic layer (40), and is used for transmitting a portion of the LVDS differential pair signals and the TANA analog output signals; The second metal layer is connected to the fifth metal layer through metal vias on the third ceramic layer (30), the fourth ceramic layer (40) and the fifth ceramic layer (50), and is used for transmission of digital input signals and digital output signals; The second metal layer is connected to the sixth metal layer through metal vias on the third ceramic layer (30), the fourth ceramic layer (40), the fifth ceramic layer (50) and the sixth ceramic layer (60), and is used for transmitting the GNDA analog ground plane signal and the phase-locked loop power ground signal; The second metal layer is connected to the seventh metal layer through metal vias on the third ceramic layer (30), the fourth ceramic layer (40), the fifth ceramic layer (50), the sixth ceramic layer (60) and the seventh ceramic layer (70), and is used for transmitting a VDDA analog power supply signal; The second metal layer is connected to the eighth metal layer through metal vias on the third ceramic layer (30), the fourth ceramic layer (40), the fifth ceramic layer (50), the sixth ceramic layer (60), the seventh ceramic layer (70) and the eighth ceramic layer (80), and is used for transmitting high-level signals of pixel control signals; The second metal layer is connected to the ninth metal layer through metal vias on the third ceramic layer (30), the fourth ceramic layer (40), the fifth ceramic layer (50), the sixth ceramic layer (60), the seventh ceramic layer (70), the eighth ceramic layer (80) and the ninth ceramic layer (90), and is used for transmitting a VDDD digital power signal; The second metal layer is connected to the eleventh metal layer through metal vias on the third ceramic layer (30), the fourth ceramic layer (40), the fifth ceramic layer (50), the sixth ceramic layer (60), the seventh ceramic layer (70), the eighth ceramic layer (80), the ninth ceramic layer (90), the tenth ceramic layer (100) and the eleventh ceramic layer (110), and is used for transmitting a positive voltage LDO power supply signal; The second metal layer is connected to the twelfth metal layer through metal vias on the third ceramic layer (30), the fourth ceramic layer (40), the fifth ceramic layer (50), the sixth ceramic layer (60), the seventh ceramic layer (70), the eighth ceramic layer (80), the ninth ceramic layer (90), the tenth ceramic layer (100), the eleventh ceramic layer (110) and the twelfth ceramic layer (120), and is used for transmitting negative voltage LDO power supply signals, digital output signals, digital input signals and analog bias signals; The second metal layer is connected to the thirteenth metal layer through metal vias on the third ceramic layer (30), the fourth ceramic layer (40), the fifth ceramic layer (50), the sixth ceramic layer (60), the seventh ceramic layer (70), the eighth ceramic layer (80), the ninth ceramic layer (90), the tenth ceramic layer (100), the eleventh ceramic layer (110), the twelfth ceramic layer (120) and the thirteenth ceramic layer (130), for transmitting a VDDPIX pixel power signal; The third metal layer is connected to the fourth metal layer through a metal via on the fourth ceramic layer (40) for transmitting a GNDD digital ground plane signal; The third metal layer is connected to the tenth metal layer through metal vias on the fourth ceramic layer (40), the fifth ceramic layer (50), the sixth ceramic layer (60), the seventh ceramic layer (70), the eighth ceramic layer (80), the ninth ceramic layer (90) and the tenth ceramic layer (100), and is used for transmitting low-level signals of pixel control signals; The fourth metal layer is connected to the fifth metal layer through a metal via on the fifth ceramic layer (50) for transmitting a GNDD digital ground plane signal; The fourth metal layer is connected to the fourteenth metal layer through metal vias on the fifth ceramic layer (50), the sixth ceramic layer (60), the seventh ceramic layer (70), the eighth ceramic layer (80), the ninth ceramic layer (90), the tenth ceramic layer (100), the eleventh ceramic layer (110), the twelfth ceramic layer (120) and the thirteenth ceramic layer (130), and is used for transmitting LVDS differential pair signals and TANA analog output signals, and is led out through the pin (2); The fifth metal layer is connected to the eighth metal layer through metal vias on the sixth ceramic layer (60), the seventh ceramic layer (70) and the eighth ceramic layer (80), and is used for transmission of GNDD digital ground plane signals; The fifth metal layer is connected to the fourteenth metal layer through metal vias on the sixth ceramic layer (60), the seventh ceramic layer (70), the eighth ceramic layer (80), the ninth ceramic layer (90), the tenth ceramic layer (100), the eleventh ceramic layer (110), the twelfth ceramic layer (120) and the thirteenth ceramic layer (130), and is used for transmitting the GNDD digital ground plane signal, and is led out through the pin (2); The sixth metal layer is connected to the eleventh metal layer through metal vias on the seventh ceramic layer (70), the eighth ceramic layer (80), the ninth ceramic layer (90), the tenth ceramic layer (100) and the eleventh ceramic layer (110), and is used for transmission of GNDA analog ground plane signals; The sixth metal layer is connected to the fourteenth metal layer through metal vias on the seventh ceramic layer (70), the eighth ceramic layer (80), the ninth ceramic layer (90), the tenth ceramic layer (100), the eleventh ceramic layer (110), the twelfth ceramic layer (120) and the thirteenth ceramic layer (130), and is used for transmitting a phase-locked loop power ground signal and is led out through the pin (2); The seventh metal layer is connected to the fourteenth metal layer through metal vias on the eighth ceramic layer (80), the ninth ceramic layer (90), the tenth ceramic layer (100), the eleventh ceramic layer (110), the twelfth ceramic layer (120) and the thirteenth ceramic layer (130), and is used for transmitting a VDDA analog power supply signal, and is led out through a pin (2); The eighth metal layer is connected to the tenth metal layer through metal vias on the ninth ceramic layer (90) and the tenth ceramic layer (100), and is used for transmitting high-level signals of pixel control signals; The eighth metal layer is connected to the fourteenth metal layer through metal vias on the ninth ceramic layer (90), the tenth ceramic layer (100), the eleventh ceramic layer (110), the twelfth ceramic layer (120) and the thirteenth ceramic layer (130), and is used for transmitting the GNDD digital ground plane signal, and is led out through the pin (2); The ninth metal layer is connected to the fourteenth metal layer through metal vias on the tenth ceramic layer (100), the eleventh ceramic layer (110), the twelfth ceramic layer (120) and the thirteenth ceramic layer (130), and is used for transmitting a VDDD digital power signal, and is led out through a pin (2); The tenth metal layer is connected to the eleventh metal layer through a metal via on the eleventh ceramic layer (110) and is used for transmitting low-level pixel control signals and high-level pixel control signals; The eleventh metal layer is connected to the twelfth metal layer through a metal via on the twelfth ceramic layer (120) for transmitting a GNDA analog ground plane signal; The eleventh metal layer is connected to the fourteenth metal layer through metal vias on the twelfth ceramic layer (120) and the thirteenth ceramic layer (130), and is used for transmitting positive voltage LDO power supply signals, pixel control signal low level signals and pixel control signal high level signals, and is led out through the pin (2); The twelfth metal layer is connected to the fourteenth metal layer through a metal via on the thirteenth ceramic layer (130), and is used for transmitting GNDA analog ground plane signals, negative voltage LDO power supply signals, digital output signals, digital input signals, and analog bias signals, and is led out through pins (2); The thirteenth metal layer is connected to the fourteenth metal layer through a metal via on the thirteenth ceramic layer (130), is used for transmitting a VDDPIX pixel power supply signal, and is led out through a pin (2).

10. A method for packaging an aerospace image sensor chip, characterized in that: The packaging method for the aerospace image sensor chip packaging structure according to any one of claims 1 to 9 comprises the steps of: Step 01, performing microscopic inspection on the cut chip (4); Step 02, using a chip mounter to adhere the chip (4) into the core cavity (102) of the tube shell (1) using insulating adhesive; When mounting the chip, the horizontal / vertical tolerance between the center position of the chip (4) and the center of the tube shell (1) is less than ±20 μm; The pitch angle deviation error of the chip (4) should be less than ±0.05°; The rotation angle deviation error of the chip (4) should be less than ±0.3°; Step 03, curing the chip (4) in the core cavity (102) of the tube shell (1); Step 04, testing the chip (4) loading result; Step 05, bonding the chip (4) and the tube shell (1) by means of gold wire; Step 06, detecting the bonding result by scanning electron microscope; Step 07, sticking the glass cover plate (3) to the core cavity (102) of the tube shell (1) through a sealing rubber ring; Step 08, testing the air tightness of the sealed core cavity (102); Step 09: Print identification information on the back side of the tube shell (1) by laser printing.

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