Vertical chip and manufacturing method thereof

Abstract

The invention provides a vertical chip and a manufacturing method thereof, and the method comprises the steps: providing an epitaxial wafer substrate which comprises a substrate, a metal bonding layer and an epitaxial layer, and the metal bonding layer and the epitaxial layer are sequentially stacked on the substrate; patterning the epitaxial layer to form a plurality of independent LED epitaxy on the metal bonding layer; depositing a first passivation layer, enabling the first passivation layer to at least wrap the side wall of the LED epitaxy, and enabling the metal bonding layer on the passage between the adjacent LED epitaxy to be exposed; etching the metal bonding layer exposed on the passage, so that the etched metal is adhered back to the first passivation layer to form an optical isolation layer; and depositing a second passivation layer to enable the second passivation layer to wrap the optical isolation layer. By etching the metal bonding layer exposed on the passage, the etched metal is adhered to the first passivation layer and surrounds the side wall of the LED epitaxy to form optical isolation, so that the manufacturing process of the optical isolation and the optical isolation material are saved, and the manufacturing cost of the chip is greatly reduced.

Description

Technical Field

[0001] The present application relates to the technical field of chip manufacturing, and in particular to a vertical chip and a manufacturing method thereof. Background Art

[0002] At present, the application scenarios of Micro-LED are mainly concentrated on AR glasses, and AR glasses need to prepare higher-resolution display screens in a small area. As the required display screen area becomes smaller and smaller, the spacing between chips also decreases, and the impact of light interference on pixels becomes more and more important. Therefore, it is necessary to fill light isolation materials between pixels to solve the problem of light interference.

[0003] However, the optical isolation materials in the prior art are mostly made of metal and vinyl (such as gold and vinyl), and the cost of metal and vinyl is extremely high, which will increase the manufacturing cost of the chip.

[0004] Therefore, the prior art still needs to be improved and developed. Summary of the invention

[0005] In view of the above-mentioned deficiencies in the prior art, the purpose of the present application is to provide a vertical chip and a method for manufacturing the same, by etching the metal on the substrate and sticking the etched metal back on the first passivation layer to form optical isolation, surrounding the side walls of the LED epitaxy, saving the optical isolation manufacturing process and optical isolation materials, and greatly reducing the chip manufacturing cost.

[0006] The technical solution of this application is as follows:

[0007] A method for manufacturing a vertical chip, wherein the method comprises the following steps:

[0008] Providing an epitaxial wafer substrate, the epitaxial wafer substrate comprising a substrate, and a metal bonding layer and an epitaxial layer sequentially stacked on the substrate;

[0009] Patterning the epitaxial layer to form a plurality of independent LED epitaxies on the metal bonding layer;

[0010] Depositing a first passivation layer, so that the first passivation layer at least covers the sidewalls of the LED epitaxy and exposes the metal bonding layer on the passages between adjacent LED epitaxys;

[0011] Etching the metal bonding layer exposed on the passage, so that the etched metal is re-adhered to the first passivation layer to form a light isolation layer;

[0012] A second passivation layer is deposited so that the second passivation layer covers the light isolation layer.

[0013] Through the above scheme, multiple independent LED epitaxies are connected to the substrate through the metal bonding layer. By etching the exposed metal bonding layer on the aisle, the etched metal is attached to the first passivation layer and surrounds the side wall of the LED epitaxy to form optical isolation, which saves the optical isolation production process and optical isolation materials, and greatly reduces the chip production cost.

[0014] In one embodiment, the step of etching the metal bonding layer exposed on the passage so that the etched metal is re-adhered to the first passivation layer to form a light isolation layer comprises:

[0015] Etching the metal bonding layer exposed on the passage through ion beam etching, so that the metal of the metal bonding layer is sputtered and re-stained on the first passivation layer;

[0016] The re-sticking metal of the first passivation layer is modified to form the light isolation layer on the first passivation layer.

[0017] Through the above scheme, the metal bonding layer exposed on the channel is etched by ion beam, so that the etched metal is re-attached to the first passivation layer of the LED epitaxy, and the re-attached metal is modified to achieve optical isolation on the first passivation layer of the LED epitaxy.

[0018] In one embodiment, the step of etching the metal bonding layer exposed on the passage by ion beam etching so that the metal of the metal bonding layer is sputtered and re-stained on the first passivation layer includes:

[0019] Install the epitaxial wafer substrate so that the epitaxial wafer substrate is placed on the etching stage of the ion beam etching;

[0020] Adjusting the tilt angle of the etching stage for the first time so that the ion beam of the ion beam etching has a first incident angle with the epitaxial wafer substrate;

[0021] The metal bonding layer exposed on the passage is etched by using the ion beam at the first incident angle, so that the etched metal is sputtered and re-attached to the first passivation layer.

[0022] Through the above scheme, the epitaxial wafer substrate is installed on the etching platform, and the inclination angle of the etching platform can be adjusted so that the ion beam and the epitaxial wafer substrate have a certain inclination angle, so that the ion beam can not only etch the metal bonding layer on the aisle, but also make the etched metal sputter back onto the first passivation layer.

[0023] In one embodiment, the step of modifying the re-sticking metal of the first passivation layer to form the optical isolation layer on the first passivation layer includes:

[0024] Adjusting the tilt angle of the etching stage for the second time so that the ion beam of the ion beam etching has a second incident angle with the epitaxial wafer substrate;

[0025] The re-sticking metal of the first passivation layer is modified by using the ion beam at the second incident angle, so that a flat and smooth optical isolation layer is formed on the first passivation layer.

[0026] Through the above solution, by adjusting the tilt angle of the etching stage, it is possible to facilitate the ion beam to modify the re-attached metal on the first passivation layer, so as to form a flat and smooth optical isolation layer around the LED epitaxy.

[0027] In one embodiment, in the step of etching the metal bonding layer exposed on the passageway using the ion beam at the first incident angle so that the etched metal is sputtered and re-stained on the first passivation layer, the metal bonding layer includes one of the following metals:

[0028] Cr, Pt, Ti, Au, Sn, Ni or Al;

[0029] And the thickness of the metal bonding layer is 0.5-0.9 um.

[0030] Through the above scheme, it can be ensured that the sputtered metal can form light isolation and make the light isolation reach a certain height. Among them, when the thickness of the metal bonding layer is 0.5-0.9um, it can be ensured that the height of the light isolation layer is between the multi-quantum well layer and the second semiconductor layer, so as to achieve a better light isolation effect.

[0031] In one embodiment, in the step of etching the metal bonding layer exposed on the passageway with the ion beam at the first incident angle so that the etched metal is sputtered and re-stained on the first passivation layer, the epitaxial layer at least includes a first semiconductor layer, a multi-quantum well layer, and a second semiconductor layer which are stacked in sequence;

[0032] The height of the optical isolation layer is at least not lower than that of the multi-quantum well layer, and the height of the optical isolation layer is not higher than that of the second semiconductor layer.

[0033] Through the above scheme, the metal bonding layer can be made of Cr, Pt, Ti, Au, Sn, Ni or Al, and the thickness of the metal bonding layer can be 0.5-0.9um; by using ion beam etching to etch the metal bonding layer on the aisle, the metal bonding layer can form optical isolation on the first passivation layer, and the height of the optical isolation cannot be lower than the multi-quantum well layer at least, and the height of the optical isolation is not higher than the height of the second semiconductor layer.

[0034] In one embodiment, the height of the light isolation layer is 0.7-1.3 um.

[0035] Through the above solution, the height of the optical isolation layer is 0.7-1.3 um, 0.7 um can be understood as the preferred height of the multi-quantum well layer, and 1.3 um can be understood as the preferred height of the second semiconductor layer.

[0036] In one embodiment, in the step of using the ion beam to modify the re-etched metal of the first passivation layer at the second incident angle so that a flat and smooth optical isolation layer is formed on the first passivation layer, the first incident angle range is 90-110° and the metal etching time of the ion beam is 25-35min; the second incident angle range is 150-170°, and the modification time of the ion beam is 4-6min.

[0037] Through the above scheme, by adjusting the inclination angle of the etching stage and making the inclination angle of the ion beam and the epitaxial wafer substrate to 90-110°, the ion beam can etch the metal bonding layer on the epitaxial wafer substrate, and the etched metal can be re-sticked on the first passivation layer; by adjusting the inclination angle of the etching stage and making the inclination angle of the ion beam and the epitaxial wafer substrate to 150-170°, the ion beam can modify the re-sticked metal.

[0038] In one embodiment, in the step of modifying the re-sticking metal of the first passivation layer at the second incident angle using the ion beam to form a flat and smooth optical isolation layer on the first passivation layer, the type of the ion beam includes one of the following:

[0039] Gallium ion beam, helium ion beam, neon ion beam or argon ion beam;

[0040] When the ion beam is an argon ion beam, the etching energy of the ion beam is 450-550 mj; the acceleration voltage of the ion beam is 280-320 V; and the current of the ion beam is 130-170 mA.

[0041] Through the above scheme, any one of gallium ion beams, helium ion beams, neon ion beams or argon ion beams can be used to etch metal. When using an argon ion beam, the above parameters are used to give it a certain energy and then shoot the ion beam toward the surface of the metal bonding layer to impact its surface atoms, causing the bonding metal atoms to be sputtered, thereby achieving the purpose of re-attachment, thereby forming a light isolation layer on the first passivation layer.

[0042] In one embodiment, after the step of depositing a second passivation layer so that the second passivation layer covers the light isolation layer, the step further includes:

[0043] Performing patterning on the second passivation layer so that the LED epitaxy exposes the electrode position;

[0044] An electrode is evaporated at the electrode position.

[0045] Through the above scheme, a coating can be formed on the periphery of the light isolation layer to expose the electrode position, and the individual LEDs can be epitaxially connected in parallel to form a parallel array by evaporating the electrode, which can improve the luminous efficiency and be used to produce a higher resolution display screen.

[0046] The present application also provides a vertical chip, which includes:

[0047] A substrate, wherein the substrate includes a plurality of independent light-emitting units;

[0048] The light-emitting unit comprises a metal bonding layer, an LED epitaxial layer, a first passivation layer, a light isolation layer, and a second passivation layer sequentially stacked on the substrate;

[0049] The metal bonding layer is located between the LED epitaxy and the substrate;

[0050] The first passivation layer at least covers the sidewalls of the LED epitaxial layer;

[0051] The optical isolation layer is connected to the metal bonding layer, surrounds the side wall of the LED epitaxial layer and adheres to the first passivation layer;

[0052] The second passivation layer covers the light isolation layer.

[0053] Through the above scheme, multiple independent LED epitaxies are connected to the substrate through the metal bonding layer. The metal bonding layer exposed on the etching aisle can be made to adhere to the first passivation layer and surround the side wall of the LED epitaxy to form optical isolation, which saves the optical isolation production process and optical isolation materials, and greatly reduces the chip production cost.

[0054] The present application proposes a vertical chip and a method for manufacturing the same, wherein the method comprises: providing an epitaxial wafer substrate, the epitaxial wafer substrate comprising a substrate, and a metal bonding layer and an epitaxial layer sequentially stacked on the substrate; patterning the epitaxial layer to form a plurality of independent LED epitaxies on the metal bonding layer; depositing a first passivation layer so that the first passivation layer at least covers the sidewalls of the LED epitaxies and exposes the metal bonding layer on the aisles between adjacent LED epitaxies; etching the metal bonding layer exposed on the aisles so that the etched metal sticks back to the first passivation layer to form a light isolation layer; depositing a second passivation layer so that the second passivation layer covers the light isolation layer. The present application etches the metal bonding layer exposed on the aisles so that the etched metal sticks to the first passivation layer and surrounds the sidewalls of the LED epitaxies to form light isolation, thereby saving the light isolation manufacturing process and light isolation materials, and greatly reducing the chip manufacturing cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] Figure 1 A schematic diagram of a manufacturing process of a vertical chip according to an embodiment of the present application;

[0056] Figure 2 A schematic diagram of the metal etching process of a vertical chip according to an embodiment of the present application;

[0057] Figure 3 A schematic diagram of a specific embodiment of a vertical chip according to an embodiment of the present application;

[0058] Figure 4 This is a schematic diagram of the structure of an epitaxial wafer substrate in a vertical chip according to an embodiment of the present application;

[0059] Figure 5 This is a schematic diagram of the structure of the LED epitaxy in the vertical chip of an embodiment of the present application;

[0060] Figure 6 A schematic diagram of the connection between the LED epitaxy and the first passivation layer in the vertical chip of an embodiment of the present application;

[0061] Figure 7 This is a schematic diagram of the assembly structure of the optical isolation layer and the first passivation layer in the vertical chip of an embodiment of the present application;

[0062] Figure 8 This is a schematic diagram of the assembly structure of the optical isolation layer and the LED epitaxy in the vertical chip of the embodiment of the present application;

[0063] Fig. 9 This is a schematic diagram of the connection between the LED epitaxy and the second passivation layer in the vertical chip of the embodiment of the present application;

[0064] Fig.10 This is a schematic diagram of the structure of a vertical chip according to an embodiment of the present application;

[0065] Fig.11 This is a schematic diagram of the connection between the Si substrate and the epitaxial wafer in the vertical chip of an embodiment of the present application;

[0066] Fig.12 Schematic diagram of the metal bonding state of the epitaxial wafer substrate in the vertical chip of an embodiment of the present application.

[0067] The numbers in the figure:

[0068] 10a, epitaxial wafer substrate; 10b, epitaxial wafer; 10, substrate; 20, metal bonding layer; 30, epitaxial layer; 40, LED epitaxy; 50, first passivation layer; 60, optical isolation layer; 70, second passivation layer; 80, electrode; 81, electrode position; 21, first metal layer; 22, second metal layer; 31, first semiconductor layer; 32, multi-quantum well layer; 33, second semiconductor layer; 34, third semiconductor layer; 41, aisle. DETAILED DESCRIPTION

[0069] The present application provides a vertical chip and a method for manufacturing the same. To make the purpose, technical solution and effect of the present application clearer and more specific, the present application is further described in detail with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0070] like Figure 1 As shown, this embodiment provides a method for manufacturing a vertical chip, the method comprising the following steps:

[0071] Step S100: Figure 4 As shown, an epitaxial wafer substrate 10 a is provided. The epitaxial wafer substrate 10 a includes a substrate 10 , and a metal bonding layer 20 and an epitaxial layer 30 sequentially stacked on the substrate 10 .

[0072] Step S200: Figure 5 As shown, the epitaxial layer 30 is patterned to form a plurality of independent LED epitaxies 40 on the metal bonding layer 20 .

[0073] Step S300: Figure 6 As shown, a first passivation layer 50 is deposited, so that the first passivation layer 50 at least covers the sidewalls of the LED epitaxy 40 and exposes the metal bonding layer 20 on the passages 41 between adjacent LED epitaxy 40;

[0074] Step S400: Figure 7 As shown, the metal bonding layer 20 exposed on the channel 41 is etched so that the etched metal is re-adhered to the first passivation layer 50 to form a light isolation layer 60;

[0075] Step S500: Figure 8 and Fig. 9 As shown, a second passivation layer 70 is deposited so that the second passivation layer 70 covers the optical isolation layer 60 .

[0076] In the present embodiment, the epitaxial wafer substrate 10a includes a substrate 10, a metal bonding layer 20 and an epitaxial layer 30. The epitaxial layer 30 is connected to the substrate 10 via the metal bonding layer 20. The epitaxial layer 30 is patterned to form a plurality of independent LED epitaxies 40 on the metal bonding layer 20. Then, a first passivation layer 50 is deposited on the sidewalls of the LED epitaxies 40, and the metal bonding layer 20 on the aisle 41 is exposed. Then, the exposed metal bonding layer 20 on the aisle 41 is etched, so that the etched metal is reattached to the first passivation layer 50 to form a light isolation layer 60. That is, the metal bonding layer 20 on the aisle 41 can be made into light isolation to solve the light interference problem of the light-emitting unit. Since the material of the light isolation layer 60 is taken from the metal bonding layer 20 on the etched aisle 41, the present embodiment does not need to use metal and black glue to make light isolation on the sidewalls of the LED epitaxy 40, which can save light isolation materials and save the process of making light isolation separately, and can greatly reduce the production cost of the chip.

[0077] Through the above scheme, multiple independent LED epitaxy 40 are connected to the substrate 10 through the metal bonding layer 20. By etching the exposed metal bonding layer 20 on the channel 41, the etched metal is attached to the first passivation layer 50 and surrounds the side wall of the LED epitaxy 40 to form optical isolation, which saves the optical isolation production process and optical isolation materials, and greatly reduces the chip production cost.

[0078] Furthermore, if Figure 1 As shown, after step S500, the following steps may also be included:

[0079] Step S600: Fig. 9 As shown, the second passivation layer 70 is patterned so that the LED epitaxy 40 exposes the electrode position 81 .

[0080] Step S700: Fig.10 As shown, electrode 80 is vapor deposited at electrode position 81 .

[0081] In this embodiment, after the second passivation layer 70 is deposited on the optical isolation layer 60, the second passivation layer 70 can be patterned so that the LED epitaxy 40 exposes the electrode position 81, and then the electrode 80 can be evaporated at the electrode position 81 so that each LED epitaxy 40 is connected in parallel, that is, each LED epitaxy 40 has a common N electrodes 80 to form a parallel array.

[0082] Through the above scheme, the second passivation layer 70 can be patterned and the electrode position 81 can be exposed on the LED epitaxy 40. By evaporating the electrode 80, each LED epitaxy 40 is connected in parallel to form a parallel array, which can improve the luminous efficiency and be used to make a higher resolution display screen.

[0083] Specifically, if Figure 2 As shown, step S400 may include the steps of:

[0084] Step S410 , etching the metal bonding layer 20 exposed on the passage 41 by ion beam etching, so that the metal of the metal bonding layer 20 is sputtered and re-attached to the first passivation layer 50 .

[0085] Step S420 , modifying the re-attached metal of the first passivation layer 50 to form a light isolation layer 60 on the first passivation layer 50 .

[0086] In this embodiment, the metal bonding layer 20 exposed on the channel 41 can be first etched by ion beam, so that the etched metal is re-attached to the first passivation layer 50 of the LED epitaxy 40, and then the re-attached metal can be modified by ion beam to form a smooth and flat optical isolation layer 60 on the first passivation layer 50.

[0087] Through the above scheme, the metal bonding layer 20 exposed on the channel 41 is ion beam etched so that the etched metal is re-attached to the first passivation layer 50 of the LED epitaxy 40, and the re-attached metal is modified to achieve optical isolation on the first passivation layer 50 of the LED epitaxy 40.

[0088] Specifically, if Figure 3 As shown, step S410 includes the steps of:

[0089] Step S411 , installing the epitaxial wafer substrate 10 a so as to place the epitaxial wafer substrate 10 a on an etching stage for ion beam etching.

[0090] Step S412: adjusting the tilt angle of the etching stage for the first time so that the ion beam of the ion beam etching has a first incident angle with the epitaxial wafer substrate 10a.

[0091] Step S413 , etching the exposed metal bonding layer 20 on the passage 41 using an ion beam at a first incident angle, so that the etched metal is sputtered and re-attached to the first passivation layer 50 .

[0092] Through the above scheme, the epitaxial wafer substrate 10a is installed on the etching platform, and the inclination angle of the etching platform can be adjusted so that the ion beam and the epitaxial wafer substrate 10a have a certain inclination angle, so that the ion beam can not only etch the metal bonding layer 20 on the aisle 41, but also make the etched metal sputter back onto the first passivation layer 50.

[0093] Specifically, if Figure 3 As shown, step S410 includes the steps of:

[0094] Step S421 , adjusting the tilt angle of the etching stage for the second time so that the ion beam of the ion beam etching has a second incident angle with the epitaxial wafer substrate 10 a .

[0095] Step S422 : modifying the re-attached metal of the first passivation layer 50 by using an ion beam at a second incident angle, so as to form a flat and smooth optical isolation layer 60 on the first passivation layer 50 .

[0096] Through the above solution, by adjusting the tilt angle of the etching stage, it is convenient for the ion beam to modify the re-attached metal on the first passivation layer 50 , so as to form a flat and smooth optical isolation layer 60 around the LED epitaxy 40 .

[0097] Optionally, the substrate 10 may be a driving substrate (eg, a CMOS substrate), or may be other temporary substrates, such as a silicon substrate or sapphire.

[0098] Optionally, the metal bonding layer 20 may include one of the following metals:

[0099] Cr, Pt, Ti, Au, Sn, Ni or Al.

[0100] For example, the metal bonding layer 20 can be Au, that is, the metal bonding layer 20 is made of gold to connect the substrate 10 and the epitaxial layer 30, and the gold exposed on the channel 41 can be etched by ion beam etching so that the sputtered gold is re-stained on the first passivation layer 50 to form optical isolation.

[0101] For example, the metal bonding layer 20 can be Ti, that is, the metal bonding layer 20 is made of metal titanium to connect the substrate 10 and the epitaxial layer 30, and the metal titanium exposed on the channel 41 can be etched by ion beam etching, so that the sputtered metal titanium is re-adsorbed on the first passivation layer 50 to form optical isolation. It should be understood that the metal of the metal bonding layer 20 is not limited to the above-mentioned Cr, Pt, Ti, Au, Sn, Ni or Al, and the metal of the metal bonding layer 20 can also be other situations, which are not limited here.

[0102] Optionally, the thickness of the metal bonding layer 20 is 0.5-0.9 um.

[0103] In this embodiment, in order to ensure that the sputtered metal can form light isolation and make the light isolation reach a certain height, it is necessary to set a reasonable thickness of the metal bonding layer 20. For example, the thickness of the metal bonding layer 20 is 0.5-0.9um, which can ensure that the height of the light isolation layer 60 is between the multi-quantum well layer 32 and the second semiconductor layer 33, so as to achieve a better light isolation effect.

[0104] Optionally, the epitaxial layer 30 at least includes a first semiconductor layer 31 , a multi-quantum well layer 32 , and a second semiconductor layer 33 which are stacked in sequence.

[0105] For example, the epitaxial wafer substrate 10a includes a substrate 10, a metal bonding layer 20 and an epitaxial layer 30, wherein the epitaxial layer 30 includes at least a first semiconductor layer 31, a multi-quantum well layer 32 and a second semiconductor layer 33 which are stacked in sequence, wherein the first semiconductor layer 31 may be a P-type GaN layer, and the second semiconductor layer 33 may be an N-type GaN layer, that is, the epitaxial layer 30 includes at least a P-type GaN layer, a multi-quantum well layer 32 and an N-type GaN layer which are stacked to form a light-emitting unit. For example, the epitaxial layer 30 also includes a first semiconductor layer 31, a multi-quantum well layer 32, a second semiconductor layer 33 and a third semiconductor layer 34 which are stacked in sequence, and for example, the third semiconductor layer 34 may be a U-type GaN layer.

[0106] Optionally, the height of the optical isolation layer 60 is at least not lower than that of the multi-quantum well layer 32 , and the height of the optical isolation layer 60 is not higher than that of the second semiconductor layer 33 .

[0107] For example, the height of the optical isolation layer 60 is not lower than the multi-quantum well layer 32, and the height of the optical isolation layer 60 is not higher than the height of the second semiconductor layer 33, so as to ensure the optical isolation effect of the optical isolation layer 60, thereby effectively solving the problem of optical interference of the light-emitting unit.

[0108] Through the above scheme, the metal bonding layer 20 can be made of Cr, Pt, Ti, Au, Sn, Ni or Al, and the thickness of the metal bonding layer 20 can be 0.5-0.9um; by using ion beam etching to etch the metal bonding layer 20 on the aisle 41, the metal bonding layer 20 can form optical isolation on the first passivation layer 50, and the height of the optical isolation cannot be lower than the multi-quantum well layer 32 at least, and the height of the optical isolation is not higher than the height of the second semiconductor layer 33, so as to ensure the optical isolation effect of the optical isolation layer 60, thereby effectively solving the problem of optical interference of the light-emitting unit.

[0109] Optionally, the height of the light isolation layer 60 is 0.7-1.3 um.

[0110] For example, the epitaxial wafer substrate 10a includes a substrate 10, a metal bonding layer 20, a P-type GaN layer, a multi-quantum well layer 32 and an N-type GaN layer.

[0111] Through the above scheme, the height of the light isolation layer 60 is 0.7-1.3um, 0.7um can be understood as the preferred height of the multi-quantum well layer 32, and 1.3um can be understood as the preferred height of the second semiconductor layer 33, so that the light isolation layer 60 can have a good light isolation effect and can effectively solve the problem of light interference of the light-emitting unit.

[0112] Preferably, the height of the light isolation layer 60 can be flush with the height of the second semiconductor layer 33, so that the light isolation layer 60 has a good light isolation effect and can effectively solve the problem of light interference of the light emitting unit. For example, the height of the light isolation layer 60 is flush with the height of the second semiconductor layer 33 of the epitaxial layer 30, and the height of the light isolation layer 60 can be set to 1.3um.

[0113] Optionally, in step S413, the first incident angle ranges from 90 to 110° and the metal etching time of the ion beam is 25 to 35 minutes.

[0114] Optionally, in step S422, the second incident angle range is 150-170°, and the modification time of the ion beam is 4-6 minutes.

[0115] Through the above scheme, by adjusting the inclination angle of the etching stage and making the inclination angle between the ion beam and the epitaxial wafer substrate 10a to 90-110°, the ion beam can etch the metal bonding layer 20 on the epitaxial wafer substrate 10a, and the etched metal can be re-attached to the first passivation layer 50; by adjusting the inclination angle of the etching stage and making the inclination angle between the ion beam and the epitaxial wafer substrate 10a to 150-170°, the ion beam can modify the re-attached metal.

[0116] The type of ion beam is one of the following:

[0117] Gallium ion beam, helium ion beam, neon ion beam or argon ion beam;

[0118] When the ion beam is an argon ion beam, the etching energy of the ion beam is 450-550 mj; the acceleration voltage of the ion beam is 280-320 V; and the ion beam current is 130-170 mA.

[0119] Through the above scheme, any one of gallium ion beams, helium ion beams, neon ion beams or argon ion beams can be used to etch metal. When using an argon ion beam, the above parameters are used to give it a certain energy and then shoot the ion beam toward the surface of the metal bonding layer 20 to impact its surface atoms, causing the bonding metal atoms to be sputtered to achieve the purpose of re-attachment, thereby forming a light isolation layer 60 on the first passivation layer 50.

[0120] In one embodiment, the method for manufacturing a vertical chip in the specific embodiment of the present application includes the following steps:

[0121] S11, such as Fig.11As shown, an epitaxial wafer 10b and a Si substrate are provided, and metal is evaporated on the surfaces of the epitaxial wafer 10b and the Si substrate, wherein the epitaxial wafer 10b may include a sapphire substrate, and a U-type GaN layer, an N-type GaN layer, a multi-quantum well layer 32 and a P-type GaN layer stacked in sequence on the sapphire substrate, that is, a first metal layer 21 can be evaporated to form on the surface of the Si substrate, and a second metal layer 22 can be evaporated to form on the P-type GaN layer of the epitaxial wafer 10b.

[0122] S12, such as Fig.12 As shown, metal bonding is performed on the epitaxial wafer 10b and the Si substrate, so that a first metal layer 21 on the surface of the Si substrate and a second metal layer 22 on the surface of the epitaxial wafer 10b form a metal bonding layer 20.

[0123] S13, such as Figure 4 As shown, the sapphire substrate on the epitaxial wafer 10b is peeled off. For example, the sapphire substrate on the epitaxial wafer 10b can be removed by laser peeling, so that the U-type GaN layer is exposed on the epitaxial wafer 10b.

[0124] For example, a solid laser lift-off device can be used to lift off a sapphire substrate, and a laser wavelength of 257.5 nm can be used to remove the non-conductive sapphire substrate and expose the U-type GaN layer.

[0125] S14, such as Figure 4 As shown, the U-type GaN layer on the epitaxial wafer 10b is removed, so that the N-type GaN layer is exposed, and the epitaxial wafer 10b and the Si substrate are metal-bonded and peeled off to form the epitaxial wafer substrate 10a.

[0126] Since the U-type GaN layer is used as a bottom buffer layer during epitaxial growth and has a large resistance, it is necessary to remove the U-type GaN layer so that the N-type GaN layer is exposed to ensure that the total thickness of the light-emitting layer is 1.2-1.6um (i.e., the total thickness of the P-type GaN layer, the multi-quantum well layer 32, and the N-type GaN layer is 1.2-1.6um). It can be seen that stripping the sapphire substrate and removing the U-type GaN layer can reduce the chip voltage, improve the chip stability, and expose the N-type GaN layer.

[0127] S15, such as Figure 5 As shown, the epitaxial layer 30 is patterned to form a plurality of independent LED epitaxy 40 on the metal bonding layer 20. For example, BCL 3 or Cl 2 The epitaxial layer 30 is etched to form a plurality of independent LED epitaxies 40 on the metal bonding layer 20. The LED epitaxies 40 form independent light-emitting units, so that light can be emitted uniformly at all locations. The LED epitaxies 40 can be set to an inclined shape so that the subsequent SiO 2The layer can slope up the sidewall of the LED epitaxy 40. For example, the sidewall of the LED epitaxy 40 can have an inclination angle of 50-75°.

[0128] S16, such as Figure 6 As shown, a first passivation layer 50 is deposited on the sidewalls of the LED epitaxy 40 .

[0129] Since a high-power ion beam is required for subsequent metal etching of the metal bonding layer 20 on the channel 41, a photoresist may be formed by using a photoresist mask, and the photoresist formed by the photoresist mask is difficult to remove. Therefore, a hard mask is preferably used for the first passivation layer 50. For example, the metal etching method of the metal bonding layer 20 may be IBE etching, ICP etching, or RIE etching. For example, SiO2 having the same thickness as the second semiconductor layer 33 may be deposited. 2 layer; then on SiO 2 The photoresist is coated on the layer to form the pattern of the MESA step and the channel 41, and the SiO2 layer of the channel 41 of the LED epitaxy 40 is exposed; then the SiO2 layer on the channel 41 is etched and etched to the metal bonding layer 20, so that the metal bonding layer 20 of the channel 41 is exposed; then the photoresist on the SiO2 layer is removed, that is, the side wall of the LED epitaxy 40 is covered by the SiO2 layer, and the SiO2 layer on the channel 41 is etched away, so that the metal bonding layer 20 of the channel 41 is exposed.

[0130] S17, such as Figure 7 As shown, the metal bonding layer 20 on the channel 41 is etched by ion beam, so that the etched metal is re-adhered to the first passivation layer 50 to form the optical isolation layer 60 .

[0131] For example, the LED epitaxial layer 40 can be fixed on the etching stage first; then the inclination angle of the etching stage is adjusted so that the metal bonding layer 20 on the passage 41 is inclined at an angle of 90-110° to the ion beam, and then the metal bonding layer 20 on the passage 41 can be etched with an argon ion beam, the etching energy of the argon ion beam can be 450-550mj; the acceleration voltage of the argon ion beam can be 280-320V; and the current of the argon ion beam can be 130-170mA. The metal bonding layer 20 on the passage 41 is sputtered and re-stained on the SiO 2 On the layer, ensure that the height of the back-sticking metal is between the multi-quantum well layer 32 and the second semiconductor layer 33, for example, the height of the back-sticking metal is 0.7-1.3um; then the tilt angle of the etching carrier can be adjusted to make the tilt angle of the epitaxial wafer substrate 10a and the ion beam 150-170°, and then the back-sticking metal is modified with an argon ion beam to form a smooth and flat optical isolation layer 60 on the SiO2 layer.

[0132] S18, such as Figure 8 As shown, the first passivation layer 50 is removed.

[0133] For example, the SiO2 on the side wall of the LED epitaxial 40 can be etched by soaking in BOE solution. 2 For example, aqueous HF and NH 4 F can be used to etch the SiO2 layer on the side wall of the LED epitaxial 40. The ratio of HF aqueous solution to NH4F can be 1:6. In this embodiment, the SiO2 layer can be chemically wet-etched by soaking in BOE solution to remove the SiO2 layer on the side wall of the LED epitaxial 40. 2 layer.

[0134] S19, such as Fig. 9 As shown, a second passivation layer 70 is deposited so that the second passivation layer 70 covers the optical isolation layer 60 .

[0135] For example, the LED epitaxy 40 and the optical isolation layer 60 may be insulated and coated by an ALD deposition method to form the second passivation layer 70 on the LED epitaxy 40 and the optical isolation layer 60 .

[0136] S20, such as Fig. 9 As shown, the second passivation layer 70 is patterned so that the LED epitaxy 40 exposes the electrode position 81 .

[0137] For example, the second passivation layer 70 may be photolithographically exposed and etched until the LED epitaxy 40 exposes the electrode position 81 , that is, a mounting space for the electrode 80 is etched out in the LED epitaxy 40 .

[0138] S21, such as Fig.10 As shown, an electrode 80 is evaporated at the electrode position 81 , and the LED epitaxy 40 is connected in parallel through the electrode 80 to form a common N electrode 80 .

[0139] For example, the electrode 80 may be evaporated on the N-type GaN layer of the LED epitaxy 40 , and the LED epitaxy 40 may be connected in parallel through the electrode 80 to form a common N-electrode 80 to form a parallel array of LED epitaxy 40 .

[0140] The present application also provides a vertical chip, such as Fig.10 As shown, it is manufactured by the above-mentioned vertical chip manufacturing method, which includes: a substrate 10, the substrate 10 includes a plurality of independent light-emitting units; the light-emitting unit includes a metal bonding layer 20, an LED epitaxy 40, a first passivation layer 50, a light isolation layer 60, and a second passivation layer 70 stacked in sequence on the substrate 10; the metal bonding layer 20 is located between the LED epitaxy 40 and the substrate 10; the first passivation layer 50 at least covers the side wall of the LED epitaxy 40; the light isolation layer 60 is connected to the metal bonding layer 20, surrounds the side wall of the LED epitaxy 40 and adheres to the first passivation layer 50; the second passivation layer 70 covers the light isolation layer 60.

[0141] In this embodiment, since the light isolation layer 60 of the light-emitting unit is formed by etching the metal bonding layer 20 on the channel 41, and the etched metal is attached to the first passivation layer 50 and surrounds the side wall of the LED epitaxy 40 to form light isolation, the problem of light interference is effectively solved, the light isolation production process and light isolation materials are saved, and the chip production cost is greatly reduced.

[0142] Through the above scheme, multiple independent LED epitaxy 40 are connected to the substrate 10 through the metal bonding layer 20. The metal bonding layer 20 exposed on the etching channel 41 can be made to adhere to the first passivation layer 50 and surround the side wall of the LED epitaxy 40 to form optical isolation. Optical isolation can effectively solve the problem of optical interference. This embodiment saves the production process of optical isolation and saves optical isolation materials, greatly reducing the chip production cost.

[0143] In summary, the present application proposes a vertical chip and a method for manufacturing the same, wherein the method comprises: providing an epitaxial wafer substrate, the epitaxial wafer substrate comprising a substrate, and a metal bonding layer and an epitaxial layer sequentially stacked on the substrate; patterning the epitaxial layer to form a plurality of independent LED epitaxies on the metal bonding layer; depositing a first passivation layer so that the first passivation layer at least covers the sidewalls of the LED epitaxies and exposes the metal bonding layer on the aisles between adjacent LED epitaxies; etching the metal bonding layer exposed on the aisles so that the etched metal sticks back to the first passivation layer to form a light isolation layer; depositing a second passivation layer so that the second passivation layer covers the light isolation layer. The present application etches the metal bonding layer exposed on the aisles so that the etched metal sticks to the first passivation layer and surrounds the sidewalls of the LED epitaxies to form light isolation, thereby saving the light isolation manufacturing process and light isolation materials, and greatly reducing the chip manufacturing cost.

[0144] It should be understood that the application of the present application is not limited to the above examples. For ordinary technicians in this field, improvements or changes can be made based on the above description. All these improvements and changes should fall within the scope of protection of the claims attached to this application.

Claims

1. A method for manufacturing a vertical chip, characterized in that: The method comprises the following steps: Providing an epitaxial wafer substrate, the epitaxial wafer substrate comprising a substrate, and a metal bonding layer and an epitaxial layer sequentially stacked on the substrate; Patterning the epitaxial layer to form a plurality of independent LED epitaxies on the metal bonding layer; Depositing a first passivation layer, so that the first passivation layer at least covers the sidewalls of the LED epitaxy and exposes the metal bonding layer on the passages between adjacent LED epitaxys; Etching the metal bonding layer exposed on the passage, so that the etched metal is re-adhered to the first passivation layer to form a light isolation layer; A second passivation layer is deposited so that the second passivation layer covers the light isolation layer.

2. The method for manufacturing a vertical chip according to claim 1, characterized in that: The step of etching the metal bonding layer exposed on the passage so that the etched metal is re-adhered to the first passivation layer to form a light isolation layer comprises: Etching the metal bonding layer exposed on the passage through ion beam etching, so that the metal of the metal bonding layer is sputtered and re-stained on the first passivation layer; The re-sticking metal of the first passivation layer is modified to form the light isolation layer on the first passivation layer.

3. The method for manufacturing a vertical chip according to claim 2, characterized in that: The step of etching the metal bonding layer exposed on the passage through ion beam etching so that the metal of the metal bonding layer is sputtered and re-stained on the first passivation layer comprises: Install the epitaxial wafer substrate so that the epitaxial wafer substrate is placed on the etching stage of the ion beam etching; Adjusting the tilt angle of the etching stage for the first time so that the ion beam of the ion beam etching has a first incident angle with the epitaxial wafer substrate; The metal bonding layer exposed on the passage is etched by using the ion beam at the first incident angle, so that the etched metal is sputtered and re-attached to the first passivation layer.

4. The method for manufacturing a vertical chip according to claim 3, characterized in that: The step of modifying the re-sticking metal of the first passivation layer to form the optical isolation layer on the first passivation layer includes: Adjusting the tilt angle of the etching stage for the second time so that the ion beam of the ion beam etching has a second incident angle with the epitaxial wafer substrate; The re-sticking metal of the first passivation layer is modified by using the ion beam at the second incident angle, so that a flat and smooth optical isolation layer is formed on the first passivation layer.

5. The method for manufacturing a vertical chip according to claim 3, characterized in that: In the step of etching the metal bonding layer exposed on the passageway by using the ion beam at the first incident angle so that the etched metal is sputtered and re-stained on the first passivation layer, the metal bonding layer includes one of the following metals: Cr, Pt, Ti, Au, Sn, Ni or Al; And the thickness of the metal bonding layer is 0.5-0.9 um.

6. The method for manufacturing a vertical chip according to claim 5, characterized in that: In the step of etching the metal bonding layer exposed on the passage with the ion beam at the first incident angle so that the etched metal is sputtered and re-stained on the first passivation layer, the epitaxial layer at least includes a first semiconductor layer, a multi-quantum well layer and a second semiconductor layer which are stacked in sequence; The height of the optical isolation layer is at least not lower than that of the multi-quantum well layer, and the height of the optical isolation layer is not higher than that of the second semiconductor layer.

7. The method for manufacturing a vertical chip according to claim 4, characterized in that: In the step of using the ion beam to modify the re-etched metal of the first passivation layer at the second incident angle to form a flat and smooth optical isolation layer on the first passivation layer, the first incident angle range is 90-110° and the metal etching time of the ion beam is 25-35min; the second incident angle range is 150-170°, and the modification time of the ion beam is 4-6min.

8. The method for manufacturing a vertical chip according to claim 4, characterized in that: In the step of modifying the re-sticking metal of the first passivation layer at the second incident angle using the ion beam to form a flat and smooth optical isolation layer on the first passivation layer, the type of the ion beam includes one of the following: Gallium ion beam, helium ion beam, neon ion beam or argon ion beam; When the ion beam is an argon ion beam, the etching energy of the ion beam is 450-550 mj; the acceleration voltage of the ion beam is 280-320 V; and the current of the ion beam is 130-170 mA.

9. The method for manufacturing a vertical chip according to claim 1, characterized in that: After the step of depositing a second passivation layer so that the second passivation layer covers the light isolation layer, the method further comprises: Performing patterning on the second passivation layer so that the LED epitaxy exposes the electrode position; An electrode is evaporated at the electrode position.

10. A vertical chip, characterized in that: include: A substrate, wherein the substrate includes a plurality of independent light-emitting units; The light-emitting unit comprises a metal bonding layer, an LED epitaxial layer, a first passivation layer, a light isolation layer, and a second passivation layer sequentially stacked on the substrate; The metal bonding layer is located between the LED epitaxy and the substrate; The first passivation layer at least covers the sidewalls of the LED epitaxial layer; The optical isolation layer is connected to the metal bonding layer, surrounds the side wall of the LED epitaxial layer and adheres to the first passivation layer; The second passivation layer covers the light isolation layer.

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