Semiconductor device

Abstract

The invention relates to a semiconductor device. At least one transistor is formed on the device layer. A plurality of bumps are provided on one surface of the device layer. An insulating layer is disposed on a surface of the device layer opposite to the surface on which the plurality of bumps are provided. The thermally conductive layer is in contact with a surface of the insulating layer on the opposite side from the surface on which the device layer is disposed. The thermally conductive layer is formed of an insulating material having a thermal conductivity higher than that of the insulating layer. One first transistor among the transistors includes a non-overlapping portion that does not overlap with the plurality of bumps in a plan view of the device layer, and the thermally conductive layer is disposed continuously from a portion overlapping with the non-overlapping portion to a portion overlapping with at least one of the plurality of bumps.

Description

Technical Field

[0001] The present invention relates to semiconductor devices. Background Art

[0002] In a device using an SOI substrate in which an insulating layer and a semiconductor layer are stacked on a supporting substrate composed of a semiconductor, the parasitic capacitance between the semiconductor layer and the supporting substrate sometimes hinders the improvement of device characteristics. A semiconductor module is known in which the parasitic capacitance is reduced by removing the supporting substrate after flip-chip mounting a device using an SOI substrate on a module substrate or the like (see Patent Document 1).

[0003] Patent Document 1: International Publication No. 2019 / 163580

[0004] It is believed that the heat generated in the transistor formed in the semiconductor layer is mainly conducted to the module substrate via the nearest bump. However, it is clear that in a semiconductor module with a structure in which the support substrate is removed after the device using the SOI substrate is flip-chip mounted on the module substrate, the temperature of the transistor is likely to rise when the transistor formed in the semiconductor layer is in operation, compared with a structure in which the support substrate remains. If the temperature of the transistor rises excessively, the characteristics of the transistor may deteriorate. For example, when a transistor is used as a switch, the insertion loss of the switch increases. Summary of the invention

[0005] An object of the present invention is to provide a semiconductor device capable of suppressing an increase in parasitic capacitance between a device layer including a semiconductor layer in which a transistor is formed and a multilayer wiring layer and other layers, and suppressing a temperature rise of the transistor.

[0006] According to one aspect of the present invention, there is provided a semiconductor device comprising:

[0007] A device layer, wherein at least one transistor is formed on the device layer;

[0008] A plurality of bumps, wherein the plurality of bumps are arranged on one surface of the device layer;

[0009] an insulating layer disposed on a surface of the device layer opposite to a surface on which the plurality of bumps are disposed; and

[0010] a heat-conducting layer that contacts a surface of the insulating layer opposite to a surface on which the device layer is disposed and is formed of an insulating material having a higher thermal conductivity than that of the insulating layer,

[0011] A first transistor among the transistors includes a non-overlapping portion which does not overlap with the plurality of bumps when the device layer is viewed from above, and the heat conductive layer is continuously arranged from a portion overlapping with the non-overlapping portion to a portion overlapping with at least one of the plurality of bumps.

[0012] The heat-conducting layer facing the device layer via the insulating layer is formed of an insulating material, so the parasitic capacitance generated in the device layer is reduced. In addition, the heat-conducting layer functions as a heat conduction path from the transistor to the bump, so the temperature rise of the transistor can be suppressed. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 It is a schematic diagram showing the planar positional relationship of components of the semiconductor device according to the first embodiment.

[0014] Figure 2 is a cross-sectional view of a portion of the semiconductor device according to the first embodiment.

[0015] Figure 3A , Figure 3B as well as Figure 3C It is a cross-sectional view of a semiconductor device in the middle of manufacturing according to the first embodiment.

[0016] Figure 4A is a diagram showing the positional relationship between a transistor and a plurality of bumps of the semiconductor device of the first embodiment when viewed from above, Figure 4B This is a schematic perspective view of a state where a semiconductor device is mounted on a module substrate.

[0017] Figure 5A is a schematic cross-sectional view of the semiconductor device and the module substrate of the first embodiment, Figure 5B It is a schematic cross-sectional view of a semiconductor device and a module substrate according to a comparative example.

[0018] Fig. 6A as well as Figure 6B Schematic diagrams showing the results of simulations of temperature distribution in a semiconductor device without a heat conduction layer and a semiconductor device with a heat conduction layer.

[0019] Fig. 7A as well as Figure 7B It is a diagram showing the planar positional relationship of a plurality of components of a semiconductor device according to a modification of the first embodiment.

[0020] Figure 8 It is a schematic cross-sectional view of a semiconductor device and a module substrate according to a second embodiment.

[0021] Fig. 9 This is a graph showing the simulation result of the relationship between the maximum temperature reached when the transistor of the semiconductor device according to the second embodiment is operated and the thickness of the heat conductive layer.

[0022] Fig.10 This is a graph showing the simulation results of the relationship between the maximum temperature reached when the transistor of the semiconductor device according to the second embodiment is operated and the thermal conductivity of the heat conductive layer.

[0023] Fig.11A is a diagram showing the positional relationship between a transistor and a plurality of bumps of the semiconductor device of the third embodiment when viewed from above, Fig. 11B FIG. 1 is a schematic cross-sectional view of a semiconductor device and a module substrate according to a third embodiment.

[0024] Fig.12 is a block diagram of a high-frequency module according to a fourth embodiment. DETAILED DESCRIPTION

[0025] [First embodiment]

[0026] Reference Figure 1 to Figure 6B The semiconductor device of the first embodiment is described with reference to the accompanying drawings.

[0027] Figure 1 Schematic diagram showing the planar positional relationship of the components of the semiconductor device 10 according to the first embodiment. The insulating layer 20 and the device layer 30 are arranged so as to substantially overlap each other in a plan view. A transistor 31 is arranged in a region inside the device layer 30 .

[0028] The transistor 31 is, for example, a multi-finger field effect transistor (FET), and includes a plurality of source regions 31S, a plurality of drain regions 31D, and a plurality of gate electrodes 31G. The plurality of source regions 31S and the plurality of drain regions 31D are arranged alternately in one direction in the active region. The surface parallel to the surface of the device layer 30 is defined as an xy plane, and the direction in which the plurality of source regions 31S and the plurality of drain regions 31D are arranged is defined as an xyz orthogonal coordinate system in the x direction. Gate electrodes 31G are respectively arranged between mutually adjacent source regions 31S and drain regions 31D.

[0029] In a plan view, a plurality of source contact regions 32S arranged along the y direction are defined inside each of the plurality of source regions 31S. Similarly, a plurality of drain contact regions 32D arranged along the y direction are defined inside each of the plurality of drain regions 31D. Here, the source contact region 32S refers to the connection between the source region 31S and the source contact electrode (see below). Figure 2 The drain contact region 32D refers to the region where the drain region 31D and the drain contact electrode (see below) are connected to each other. Figure 2 In addition, “when viewed from above” means when the device layer 30 in which the transistor 31 is arranged is viewed from above along the direction in which the insulating layer 20 and the device layer 30 are stacked.

[0030] Through the transistor 31 and the wiring ( Figure 1 Examples of the high-frequency circuit include a low-noise amplifier that amplifies a high-frequency signal, a switch that selects one of a plurality of duplexers and filters provided for each frequency band, and the like.

[0031] The rectangle with the smallest area that includes all of the plurality of source contact regions 32S and the plurality of drain contact regions 32D in a plan view is referred to as a minimum including rectangle 40. Figure 1 In FIG. 4 , the outer periphery of the minimum inclusion rectangle 40 is indicated by a dotted line, and the interior of the minimum inclusion rectangle 40 is hatched. The region within the minimum inclusion rectangle 40 can be considered as a region where the transistor 31 substantially operates.

[0032] A metal layer 37 is arranged slightly inside the outer circumference of the device layer 30 so as to surround the inner region of the device layer 30 when viewed from above. The metal layer 37 is also called a guard ring. The metal layer 37 is separated into a plurality of parts in the circumferential direction. In addition, the metal layer 37 may be provided as a structure continuous in the circumferential direction so that the metal layer 37 becomes a closed ring shape when viewed from above.

[0033] Figure 2 1 is a cross-sectional view of a portion of the semiconductor device 10 and a module substrate 80 on which the semiconductor device 10 is mounted according to the first embodiment.

[0034] The semiconductor device 10 of the first embodiment includes a device layer 30, an insulating layer 20, a heat conducting layer 50, and a plurality of bumps 70. Figure 2 , one of the plurality of bumps 70 is shown. The semiconductor device 10 is flip-chip mounted on a module substrate 80. A direction from the semiconductor device 10 toward the module substrate 80 is defined as an upward direction.

[0035] The device layer 30 is arranged on the upward surface of the insulating layer 20, and the heat conductive layer 50 is arranged on the downward surface. The device layer 30 includes an element forming layer 39 composed of a semiconductor in contact with the insulating layer 20, and a multi-layer wiring layer arranged on the element forming layer 39. The insulating layer 20 can be composed of a single layer or a multi-layer. For example, when the insulating layer 20 is composed of a single layer, silicon oxide is used as the material of the insulating layer 20. When the insulating layer 20 is composed of a multi-layer, as the material of each layer, for example, silicon oxide, silicon nitride, etc. are used. The element forming layer 39 is composed of an active region composed of silicon and an insulating element isolation region 39I surrounding the active region. In the active region of the element forming layer 39, multiple source regions 31S, multiple drain regions 31D, and multiple channel regions 31C of the transistor 31 are arranged.

[0036] The plurality of source regions 31S and the plurality of drain regions 31D are arranged in the x direction at intervals. The channel region 31C is defined between the mutually adjacent source regions 31S and drain regions 31D. The gate electrode 31G is arranged on the channel region 31C via a gate insulating film (not shown).

[0037] The multilayer wiring layer on the element formation layer 39 includes a plurality of insulating layers 60. For example, a low dielectric constant material (Low-k material) is used for the plurality of insulating layers 60. For example, SiN or an organic insulating material is used for the uppermost insulating layer 60.

[0038] A source contact electrode 33S and a drain contact electrode 33D are embedded in the through hole of the insulating layer 60 provided at the bottom of the multilayer wiring layer. The source contact electrode 33S is in ohmic contact with the source region 31S in the source contact region 32S, and the drain contact electrode 33D is in ohmic contact with the drain region 31D in the drain contact region 32D. The source contact electrode 33S and the drain contact electrode 33D are formed of, for example, W. It is also possible to configure a bonding layer such as TiN as needed for the purpose of improving the bonding. In addition, a film composed of a metal silicide such as CoSi or NiSi may be formed on the surface of each of the source region 31S and the drain region 31D to reduce the resistance of the contact portion.

[0039] A plurality of wirings 34 or a plurality of vias 35 are respectively arranged on the plurality of insulating layers 60 above the second layer. The wirings 34 or the vias 35 are formed by a damascene method, a dual damascene method or a subtractive method. A plurality of wirings 34T and a plurality of pads 34P are arranged on the uppermost wiring layer of the device layer 30. As an example, the wirings 34, 34T and the pads 34P are formed of Cu or Al, and the vias are formed of Cu or W. In addition, a bonding layer such as TiN may be arranged as required for the purpose of preventing diffusion and improving bonding. A metal layer 37 called a guard ring is arranged on the periphery of the multilayer wiring layer.

[0040] A protective film 61 made of an organic insulating material is disposed on the device layer 30 to cover the wiring 34T and the pad 34P of the uppermost layer. Examples of the organic insulating material used for the protective film 61 include polyimide, benzocyclobutene (BCB), etc. The protective film 61 is provided with a plurality of openings for exposing the upper surfaces of the plurality of pads 34P, and a bump 70 is disposed on the pad 34P in the opening. The bump 70 is composed of, for example, a lower bump metal layer, a Cu column, and a solder layer. As the bump 70, bumps of other structures may also be used.

[0041] The semiconductor device 10 is flip-chip mounted on the module substrate 80 by connecting the bumps 70 to the pads 81 of the module substrate 80. After the semiconductor device 10 is mounted on the module substrate 80, the semiconductor device 10 may be sealed with resin.

[0042] The heat-conducting layer 50 is formed of an insulating material having a higher thermal conductivity than that of the insulating layer 20, such as diamond-like carbon (DLC). When the heat-conducting layer 50 is formed of DLC, for example, when the surface of the insulating layer 20 facing downward (the surface in contact with the heat-conducting layer 50) is subjected to XPS analysis, the peak of sp3 is detected in the spectrum analysis of carbon. In addition, the heat-conducting layer 50 is thermally coupled with the insulating layer 20, and heat is efficiently conducted between the insulating layer 20 and the heat-conducting layer 50. In addition, the material of the heat-conducting layer 50 is not limited to DLC. For example, the heat-conducting layer 50 may also include materials such as aluminum oxide (including sapphire), aluminum nitride or boron nitride. The thermal conductivity of these materials is shown in the following table, for example.

[0043] [Table 1]

[0044] Material Thermal conductivity [W / m·K] DLC 1000 Alumina (including sapphire) 42 Aluminum Nitride 320 Boron Nitride 410

[0045] The thickness of the heat conductive layer 50 is, for example, 75 nm, the thickness of the device layer 30 is, for example, 75 nm, the thickness of the bump 70 is, for example, 160 μm, and the thickness of the insulating layer 20 is, for example, not less than 200 nm and not more than 800 nm.

[0046] Next, refer to Figure 3A , Figure 3B as well as Figure 3C A method for manufacturing the semiconductor device 10 according to the first embodiment will be described. Figure 3A , Figure 3B as well as Figure 3C 1 is a cross-sectional view of the semiconductor device 10 of the first embodiment at an intermediate stage of manufacturing.

[0047] like Figure 3A As shown in FIG. 1 , an SOI substrate 90 including a temporary support substrate 91 made of silicon, an insulating layer 20 made of silicon oxide, and an element formation layer 39 made of silicon is prepared. An element isolation region 39I is formed in a portion of the element formation layer 39, and a transistor 31 is formed in an active region. Figure 3A , a source region 31S, a drain region 31D, and a gate electrode 31G are each shown. Furthermore, a multilayer wiring layer of a device layer 30 is formed on the element formation layer 39. A protective film 61 made of an organic insulating material is formed on the device layer 30, and a bump 70 is further formed. These structures can be formed using a general semiconductor wafer process.

[0048] like Figure 3BAs shown, the temporary support substrate 91 is etched away. Before the temporary support substrate 91 is etched away, a protective material (not shown) or the like is previously attached to the surface opposite to the temporary support substrate 91. By removing the temporary support substrate 91, one surface of the insulating layer 20 is exposed. As an example, in Figure 3A In the illustrated state, the thickness of the insulating layer 20 is greater than or equal to 400 nm and less than or equal to 1000 nm. However, the exposed surface layer portion of the insulating layer 20 is also etched by etching the temporary support substrate 91, so that the thickness of the insulating layer 20 becomes greater than or equal to 200 nm and less than or equal to 800 nm.

[0049] like Figure 3C As shown, a heat conductive layer 50 is formed on the exposed surface of the insulating layer 20. The heat conductive layer 50 is formed of, for example, DLC. The heat conductive layer 50 can be formed by, for example, plasma chemical vapor deposition (P-CVD) using hydrocarbon gas, sputtering using a solid carbon target, or the like. After the heat conductive layer 50 is formed, the stacked structure from the heat conductive layer 50 to the protective film 61 is cut into individual pieces.

[0050] Figure 4A FIG. 1 is a diagram showing the positional relationship between the transistor 31 and a plurality of bumps 70 of the semiconductor device 10 according to the first embodiment when viewed from above. Figure 4B 8 is a schematic perspective view of a state where the semiconductor device 10 is mounted on the module substrate 80. Figure 2 ), a plurality of transistors are arranged in addition to the transistor 31. A heat conducting layer 50 is arranged over the entire region of the insulating layer 20 and the device layer 30 in a plan view.

[0051] The plurality of bumps 70 of the semiconductor device 10 are connected to the module substrate 80. When viewed from above, a portion of the transistor 31 overlaps with one bump 70, and the other portion does not overlap with any bump 70. When viewed from above, a portion of the transistor 31 overlaps with the other portion. Figure 1 The smallest enclosing rectangle 40 is shown overlapping with other parts.

[0052] The portion of transistor 31 that overlaps with bump 70 is called overlapping portion 31X, and the portion that does not overlap is called non-overlapping portion 31Y. In a plan view, the area of ​​non-overlapping portion 31Y is larger than the area of ​​overlapping portion 31X. When semiconductor device 10 is operated, transistor 31 becomes a main heat source.

[0053] Next, refer to Figure 5A to Figure 6B The excellent effects of the first embodiment are described with reference to the accompanying drawings.

[0054] Figure 5A is a schematic cross-sectional view of the semiconductor device 10 and the module substrate 80 of the first embodiment. Figure 5B 1 is a schematic cross-sectional view of a semiconductor device 10A and a module substrate 80 of a comparative example. In the semiconductor device 10A of the comparative example, the heat conducting layer 50 ( Figure 5A ). In either semiconductor device 10 or 10A, the semiconductor device 10 or 10A is connected to the module substrate 80 via a plurality of bumps 70 , so that the semiconductor device 10 or 10A is mounted on the module substrate 80 . Figure 5A as well as Figure 5B The arrows shown indicate main heat conduction paths through which heat generated in the transistor 31 is conducted to the module substrate 80 .

[0055] The support substrate 91 ( Figure 3A ) structure, the problem caused by the temperature rise of the transistor 31 is not significant. The heat generated in the transistor 31 is conducted to the module substrate 80 via the nearest bump 70, so it is considered that sufficient heat dissipation efficiency can be obtained.

[0056] However, if Figure 5B As shown, if the support substrate 91 ( Figure 3A ), the inventors' experiments have shown that the temperature of the transistor 31 rises significantly. The heat generated in the transistor 31 is transferred to the module substrate 80 via the nearest bump 70. Figure 5B This is also common in the comparative example shown. It is believed that sufficient heat dissipation efficiency is obtained in the structure in which the support substrate 91 remains because the support substrate 91 also functions as a heat conduction path. That is, the heat generated in the transistor 31 is diffused in the support substrate 91 in the in-plane direction through the support substrate 91 in contact with the insulating layer 20 and is conducted to the bump 70.

[0057] like Figure 5B As shown, if the support substrate 91 ( Figure 3A ), the heat generated in the transistor 31 is difficult to diffuse in the in-plane direction. The heat generated in the overlapping portion 31X of the transistor 31 is mainly conducted to the module substrate 80 via the bump 70 that overlaps the overlapping portion 31X of the transistor 31 when viewed from above. However, the heat generated in the non-overlapping portion 31Y of the transistor 31 is difficult to conduct to the nearest bump 70. As a result, it is considered that the temperature rise of the non-overlapping portion 31Y of the transistor 31 becomes significant.

[0058] exist Figure 5A In the semiconductor device 10 of the first embodiment shown, the heat generated in the non-overlapping portion 31Y of the transistor 31 is mainly conducted to the bump 70 having an overlap with the transistor 31 via the heat conductive layer 50. Furthermore, the heat generated in the transistor 31 is diffused in the in-plane direction via the heat conductive layer 50 and is also conducted to the bump 70 having no overlap with the transistor 31.

[0059] In the first embodiment, the heat conductive layer 50 having a higher thermal conductivity than the insulating layer 20 and the bump 70 which does not overlap with the transistor 31 in a plan view function as a heat conduction path from the transistor 31 to the module substrate 80. In addition, the heat generated in the non-overlapping portion 31Y of the transistor 31 is also diffused in the heat conductive layer 50 in the in-plane direction and conducted to the bump 70. Therefore, the heat dissipation efficiency from the transistor 31 is improved, and the temperature rise of the transistor 31 can be suppressed.

[0060] Thus, the heat conductive layer 50 has a function of reducing the thermal resistance from the non-overlapping portion 31Y of the transistor 31 to the bump 70. Therefore, when the area of ​​the non-overlapping portion 31Y of the transistor 31 is larger than the area of ​​the overlapping portion 31X, the effect of arranging the heat conductive layer 50 is further improved.

[0061] Furthermore, since the heat conductive layer 50 is formed of an insulating material, the parasitic capacitance generated in the device layer 30 is reduced compared to a structure using a support substrate such as silicon instead of the heat conductive layer 50. Therefore, the high frequency characteristics of the semiconductor device 10 are suppressed from being degraded.

[0062] Next, refer to Fig. 6A as well as Figure 6B , regarding the configuration of the heat conducting layer 50 ( Figure 5A ) and a structure in which the heat conductive layer 50 is not configured, and the results of simulation on the temperature distribution in the in-plane direction when the transistor 31 is used as a heat source are described. Fig. 6A as well as Figure 6B Schematic diagrams showing the results of simulations of temperature distribution in a semiconductor device without heat conduction layer 50 and a semiconductor device with heat conduction layer 50 .

[0063] A transistor 31, another transistor 41, and a plurality of transistors 42 are arranged in the device layer 30. The transistors 31 and 41 are multi-finger transistors of substantially the same shape. In addition, no bumps are provided in the semiconductor device of the simulation object. In addition, the thickness and thermal conductivity of the heat-conducting layer 50 are set to 50 nm and 1000 W / m·K, respectively. This thermal conductivity is equivalent to, for example, the thermal conductivity of diamond-like carbon. The thickness and thermal conductivity of the insulating layer 20 are set to 200 nm and 1.4 W / m·K, respectively. This thermal conductivity is equivalent to, for example, the thermal conductivity of silicon oxide. The thickness and thermal conductivity of the device layer 30 are set to 75 nm and 150 W / m·K, respectively. This thermal conductivity is equivalent to, for example, the thermal conductivity of silicon. A high-frequency signal of 0.1 W is supplied to the transistor 31.

[0064] In this simulation, the temperature distribution is calculated for the case where the transistor 31 is a heat source. Fig. 6A , Figure 6BIn the figure, the height of the highest temperature is indicated by the gray density, which means that the darker the gray area, the higher the temperature. Fig. 6A ) has a maximum reaching temperature TH of 120° C., and the semiconductor device ( Figure 6B ) is 102.7°C.

[0065] The temperature of the white area is below 30°C. That is, the boundary between the gray area and the white area represents an isotherm with a temperature of 30°C. It can be seen that if the heat conductive layer 50 is configured, the area with a temperature below 30°C becomes narrower. In addition, in the semiconductor device without the heat conductive layer 50, the outer shape of the darker gray area is roughly consistent with the outer shape of the transistor 31. This means that the heat generated in the transistor 31 stays in the transistor 31. In the semiconductor device with the heat conductive layer 50, the temperature of the area near the four corners of the transistor 31 is lower than that of the semiconductor device without the heat conductive layer 50. This means that the heat generated in the transistor 31 diffuses in the in-plane direction.

[0066] from Fig. 6A as well as Figure 6B The simulation results shown show that the maximum reaching temperature is lowered by providing the heat conductive layer 50 , and the heat generated in the transistor 31 is easily diffused in the in-plane direction.

[0067] Next, refer to Fig. 7A as well as Figure 7B , a semiconductor device according to a modified example of the first embodiment is described. Fig. 7A as well as Figure 7B FIG. 1 is a diagram showing the planar positional relationship of a plurality of components of a semiconductor device 10 according to a modified example of the first embodiment. Fig. 7A as well as Figure 7B In the figure, the area where the heat conducting layer 50 is arranged is shaded. Figure 4A ), the heat conducting layer 50 is arranged over the entire region of the device layer 30. Fig. 7A , Figure 7B In the illustrated modification, the heat conductive layer 50 is disposed only in a partial region of the device layer 30 .

[0068] exist Fig. 7A In the illustrated modification, the heat conductive layer 50 includes the transistor 31 and one bump 70 overlapping the transistor 31 in a plan view. The heat generated in the non-overlapping portion 31Y of the transistor 31 is transferred to the bump 70 overlapping the transistor 31 via the heat conductive layer 50. Therefore, the heat dissipation efficiency of the heat generated in the non-overlapping portion 31Y can be improved.

[0069] exist Figure 7BIn the modified example shown, the heat conducting layer 50 includes the transistor 31, the bump 70 that overlaps with the transistor 31, and one bump 70 that does not overlap with the transistor 31 when viewed from above. The heat generated in the overlapping portion 31X and the non-overlapping portion 31Y of the transistor 31 is transferred to the two bumps 70 via the heat conducting layer 50. Fig. 7A Compared with the modified example shown, the heat dissipation efficiency from the transistor 31 can be further improved.

[0070] like Fig. 7A as well as Figure 7B As shown in the modified example, the heat conductive layer 50 does not necessarily need to be arranged in the entire area of ​​the device layer 30. In particular, in order to improve the heat dissipation efficiency from the non-overlapping portion 31Y of the transistor 31, the heat conductive layer 50 may be arranged continuously from the area overlapping with the non-overlapping portion 31Y to the part overlapping with at least one of the plurality of bumps 70. Fig. 7A as well as Figure 7B In the embodiment, the heat conductive layer 50 includes one or two bumps 70 in a plan view, but the heat conductive layer 50 may be configured to overlap with a portion of each of one or more bumps 70. That is, the structure in which "the heat conductive layer 50 overlaps with the bump 70" includes a structure in which the heat conductive layer 50 includes at least one bump 70 in a plan view, and a structure in which the heat conductive layer 50 overlaps with a portion of one bump 70.

[0071] The transistor 31 ( Figure 2 ) is a MOSFET, but the transistor 31 may also be a bipolar transistor. In the case where the transistor 31 is a bipolar transistor, the smallest rectangle including the emitter region, the base region, and the collector region when viewed from above may be considered as the region where the transistor 31 is arranged.

[0072] [Second embodiment]

[0073] Next, refer to Figure 8 , Fig. 9 as well as Fig.10 , the semiconductor device of the second embodiment is described. Figure 1 to Figure 6B The same structures as the semiconductor device of the first embodiment described in the accompanying drawings are omitted in the description.

[0074] Figure 8 1 is a schematic cross-sectional view of the semiconductor device 10 and the module substrate 80 of the second embodiment. The structure including the heat conducting layer 50, the insulating layer 20, the device layer 30 and the plurality of bumps 70 is similar to the semiconductor device 10 of the first embodiment ( Figure 5AThe semiconductor device 10 of the second embodiment further includes a support substrate 51, which is arranged on the surface of the heat conductive layer 50 opposite to the surface facing the insulating layer 20. The support substrate 51 is formed of an insulating material having a lower thermal conductivity than the heat conductive layer 50.

[0075] The thickness of the support substrate 51 is thicker than the total thickness of the device layer 30, the insulating layer 20, and the thermal conductive layer 50. As the support substrate 51, for example, a resin substrate such as epoxy resin is used. The support substrate 51 is attached to the thermal conductive layer 50 by, for example, an adhesive. After the support substrate 51 is attached, it is diced to separate into individual pieces.

[0076] Next, the excellent effects of the second embodiment will be described.

[0077] In the second embodiment, as in the first embodiment, the heat generated in the transistor 31 is diffused in the in-plane direction via the heat conductive layer 50. Therefore, it is possible to improve the efficiency of heat dissipation from the transistor 31. In addition, in the second embodiment, the semiconductor device 10 is mechanically supported by the support substrate 51, so that the excellent effect of facilitating handling in the manufacturing process is obtained.

[0078] Next, refer to Fig. 9 A preferred thickness of the heat conductive layer 50 will be described.

[0079] Fig. 9 This is a graph showing the simulation results of the relationship between the maximum temperature reached when the transistor 31 is operated and the thickness of the heat-conducting layer 50. The horizontal axis represents the thickness of the heat-conducting layer 50 in units of [nm], and the vertical axis represents the maximum temperature reached by the transistor 31 in units of [°C]. As simulation conditions, the thermal conductivity of the support substrate 51 is set to 0.25 W / m·K, the thickness of the support substrate 51 is set to 200 μm, and the thermal conductivity of the heat-conducting layer 50 is set to 1000 W / m·K. In addition, the bump 70 is not provided in the semiconductor device of the simulation object. A 0.1 W high-frequency signal is supplied to the transistor 31.

[0080] In a semiconductor device without the heat-conducting layer 50, that is, a semiconductor device with a thickness of 0 nm of the heat-conducting layer 50, the maximum temperature reached is about 140°C. In contrast, if the heat-conducting layer 50 is slightly arranged, the maximum temperature reached is significantly reduced. In addition, as the heat-conducting layer 50 becomes thicker, the maximum temperature reached decreases. When the thickness of the heat-conducting layer 50 becomes 580 nm or more, the slope of the maximum temperature reached with respect to the thickness of the heat-conducting layer 50 becomes gentle.

[0081] In other words, in the range where the thickness of the heat conductive layer 50 is less than 580 nm, the maximum temperature reaches a large change with respect to the change in the thickness of the heat conductive layer 50, and in the range where the thickness of the heat conductive layer 50 is greater than 580 nm, the maximum temperature reaches a small change with respect to the change in the thickness of the heat conductive layer 50. In the structure where the thickness of the heat conductive layer 50 is less than 580 nm, if the thickness of the heat conductive layer 50 is thinner than the target thickness due to the variation in the manufacturing process, the maximum temperature reaches a large increase. If the thickness of the heat conductive layer 50 is set to be greater than 580 nm, even if the thickness of the heat conductive layer 50 varies in the manufacturing process, the maximum temperature reaches a small change. In order to make the maximum temperature less susceptible to the variation in the manufacturing process, it is preferable to set the thickness of the heat conductive layer 50 to be greater than 580 nm.

[0082] In addition, from Fig. 9 The simulation results shown confirm that when the thickness of the heat conductive layer 50 is within the range of 580 nm to 2000 nm, an effect is obtained in that the maximum reaching temperature is less susceptible to the influence of the variation in the manufacturing process.

[0083] Next, refer to Fig.10 , the range of the thermal conductivity of the support substrate 51 for obtaining a sufficient effect of providing the heat conductive layer 50 will be described.

[0084] Fig.10 This is a graph showing the simulation results of the relationship between the maximum temperature reached when the transistor 31 is operated and the thermal conductivity of the heat-conducting layer 50. The horizontal axis represents the thermal conductivity of the support substrate 51 in units of [W / m·K], and the vertical axis represents the difference in the maximum temperature reached between the semiconductor device with the heat-conducting layer 50 and the semiconductor device without the heat-conducting layer 50 in units of [°C]. As simulation conditions, the thickness of the support substrate 51 is set to 200 μm, the thickness of the heat-conducting layer 50 is set to 50 nm, and the thermal conductivity of the heat-conducting layer 50 is set to 1000 W / m·K.

[0085] In the range where the thermal conductivity of the support substrate 51 is higher than 30 W / m·K, even if the heat conductive layer 50 is inserted, the effect of reducing the maximum reachable temperature is hardly obtained. This is because the support substrate 51 functions as a heat conduction path. In the range where the thermal conductivity of the support substrate 51 is less than 30 W / m·K, the effect of reducing the maximum reachable temperature is exhibited by inserting the heat conductive layer 50. Therefore, in the case where the thermal conductivity of the support substrate 51 is 30 W / m·K, a sufficient effect of disposing the heat conductive layer 50 is obtained.

[0086] [Third embodiment]

[0087] Next, refer to Fig.11A as well as Fig. 11B , the semiconductor device of the third embodiment is described. Figure 1 to Figure 6BThe same structures as the semiconductor device of the first embodiment described in the accompanying drawings are omitted in the description.

[0088] Fig.11A FIG. 1 is a diagram showing the positional relationship between the transistor 31 and a plurality of bumps 70 of the semiconductor device 10 according to the third embodiment when viewed from above. Fig. 11B 1 is a schematic cross-sectional view of the semiconductor device 10 and the module substrate 80 of the third embodiment. Figure 4A ), the transistor 31 overlaps with the bump 70 when viewed from above. In contrast, in the third embodiment, the transistor 31 does not overlap with any bump 70 when viewed from above. Fig. 11B As shown, the heat generated in the transistor 31 is conducted to the bump 70 via the heat conductive layer 50 .

[0089] Next, the excellent effects of the third embodiment will be described.

[0090] The heat conducting layer 50 functions as a heat conducting path, so that the heat generated in the transistor 31 is dissipated as follows. Fig. 11B As indicated by the middle arrow, heat is dissipated through the bumps 70 that do not overlap with the transistor 31 in a plan view. Therefore, even in a structure in which the transistor 31 does not overlap with any bump 70 in a plan view, a temperature rise of the transistor 31 can be suppressed.

[0091] If the bump 70 is arranged at a position overlapping with the transistor 31 when viewed from above, parasitic capacitance is generated between the transistor 31 and the bump 70. For example, when the transistor 31 is used for a high-frequency switch or a high-frequency low-noise amplifier, the characteristics of the high-frequency switch or the high-frequency low-noise amplifier are degraded due to the parasitic capacitance. In the third embodiment, the transistor 31 does not overlap with the bump 70 when viewed from above, so almost no parasitic capacitance is generated between the two. Therefore, the degradation of the characteristics of the high-frequency switch or the high-frequency low-noise amplifier due to the parasitic capacitance is suppressed.

[0092] [Fourth embodiment]

[0093] Next, refer to Fig.12 , a high frequency module according to a fourth embodiment will be described. The high frequency module according to the fourth embodiment includes a semiconductor device 10 of any one of the first to third embodiments.

[0094] Fig.12This is a block diagram of a high-frequency module of the fourth embodiment. The high-frequency module of the fourth embodiment includes a semiconductor device 10, a driver-stage amplifier circuit 110, a power-stage amplifier circuit 111, and a plurality of duplexers 112. The semiconductor device 10 includes: an input switch 101, a frequency band selection switch 102 for transmission, an antenna switch 104, a frequency band selection switch 105 for reception, a low-noise amplifier 106, a power amplifier control circuit 107, a low-noise amplifier control circuit 108, and an output terminal selection switch 109 for reception. The high-frequency module has the function of transmitting and receiving in a frequency division duplex (FDD) manner. In addition, Fig.12 In the figure, the description of the impedance matching circuit inserted as needed is omitted.

[0095] The two input side contacts of the input switch 101 are connected to the high-frequency signal input terminals IN1 and IN2, respectively. A high-frequency signal is input from the two high-frequency signal input terminals IN1 and IN2. When the input switch 101 selects one of the two input side contacts, the high-frequency signal input to the selected contact is input to the driver stage amplifier circuit 110.

[0096] The high-frequency signal amplified by the driver stage amplifier circuit 110 is input to the power stage amplifier circuit 111. The high-frequency signal amplified by the power stage amplifier circuit 111 is input to the contact point on the input side of the band selection switch 102. When the band selection switch 102 selects one contact point from a plurality of contacts on the output side, the high-frequency signal amplified by the power stage amplifier circuit 111 is output from the selected contact point.

[0097] The plurality of contacts on the output side of the band selection switch 102 are respectively connected to the transmission input nodes of the plurality of duplexers 112 prepared for each frequency band. A high-frequency signal is input to the duplexer 112 connected to the contact on the output side selected by the band selection switch 102. The band selection switch 102 has a function of selecting one duplexer 112 from the plurality of duplexers 112 prepared for each frequency band.

[0098] The antenna switch 104 has a plurality of contacts on the circuit side and two contacts on the antenna side. The plurality of contacts on the circuit side of the antenna switch 104 are respectively connected to the input / output common nodes of the plurality of duplexers 112. The two contacts on the antenna side are respectively connected to the antenna terminals ANT1 and ANT2. The antenna terminals ANT1 and ANT2 are respectively connected to antennas.

[0099] The antenna switch 104 connects the two antenna-side contacts to two contacts selected from a plurality of circuit-side contacts. When one frequency band is used for communication, the antenna switch 104 connects one circuit-side contact to one antenna-side contact. The high-frequency signal amplified by the power stage amplifier circuit 111 and passed through the duplexer 112 for the corresponding frequency band is transmitted from the antenna connected to the selected antenna-side contact.

[0100] The receiving band selection switch 105 has six input-side contacts. The six input-side contacts of the band selection switch 105 are respectively connected to the receiving output nodes of the duplexer 112. The output-side contacts of the band selection switch 105 are connected to the low-noise amplifier 106. The reception signal that has passed through the duplexer 112 connected to the input-side contacts selected by the band selection switch 105 is input to the low-noise amplifier 106.

[0101] The circuit-side contact of the output terminal selection switch 109 is connected to the output node of the low noise amplifier 106. The three terminal-side contacts of the output terminal selection switch 109 are respectively connected to the reception signal output terminals LNAOUT1, LNAOUT2, and LNAOUT3. The reception signal amplified by the low noise amplifier 106 is output from the reception signal output terminal selected by the output terminal selection switch 109.

[0102] Power supply voltages are applied from power supply terminals Vcc1 and Vcc2 to the driver stage amplifier circuit 110 and the power stage amplifier circuit 111, respectively. The power amplifier control circuit 107 is connected to the power supply terminal VIO1, the control signal terminal SDATA1, and the clock terminal SCLK1. The power amplifier control circuit 107 controls the driver stage amplifier circuit 110 and the power stage amplifier circuit 111 based on a digital control signal given to the control signal terminal SDATA1.

[0103] The low noise amplifier control circuit 108 is connected to the power supply terminal VIO2, the control signal terminal SDATA2, and the clock terminal SCLK2. The low noise amplifier control circuit 108 controls the low noise amplifier 106 based on the digital control signal given to the control signal terminal SDATA2.

[0104] The input switch 101, the transmission band selection switch 102, the antenna switch 104, the reception band selection switch 105, and the output terminal selection switch 109 are formed in the device layer 30 ( Figure 2 The band selection switch 102 and the antenna switch 104 for transmitting high-power high-frequency signals become the main heat sources.

[0105] Next, the excellent effects of the fourth embodiment will be described.

[0106] The high-frequency module of the fourth embodiment is equipped with the semiconductor device 10 of the first embodiment, the second embodiment, or the third embodiment. Therefore, the heat dissipation efficiency of the transistors constituting the transmission band selection switch 102 and the antenna switch 104, which are the main heat sources, is improved, and the temperature rise of the transistors can be suppressed. In addition, the degradation of the high-frequency characteristics of the transmission band selection switch 102 and the antenna switch 104 caused by parasitic capacitance is suppressed.

[0107] The heat generated by the transistors constituting the input switch 101, the low noise amplifier 106, and the output terminal selection switch 109, which do not allow high-power high-frequency signals to pass, is less than the heat generated by the transistors constituting the transmission band selection switch 102 and the antenna switch 104. Therefore, the transistors constituting the input switch 101, the low noise amplifier 106, and the output terminal selection switch 109 do not necessarily need to be aligned with the bump 70 and the heat conductive layer 50 ( Figure 4A ) have overlap, but these transistors may also overlap with the bump 70 and the thermal conductive layer 50.

[0108] The above-mentioned embodiments are for illustration only, and it is of course possible to replace or combine parts of the structures shown in different embodiments. The same effects brought about by the same structures of multiple embodiments are not mentioned in sequence in each embodiment. Moreover, the present invention is not limited to the above-mentioned embodiments. For example, it is clear that a person skilled in the art can make various changes, improvements, combinations, etc.

[0109] For example, in each of the above-mentioned embodiments, the heat conductive layer 50 is composed of a single layer, but the heat conductive layer 50 may be composed of a plurality of layers. In other words, the heat conductive layer 50 may include a plurality of layers on the side opposite to the device layer 30 as viewed from the insulating layer 20, and the plurality of layers are formed of an insulating material having a higher thermal conductivity than the insulating layer 20. Here, each of the plurality of layers constituting the heat conductive layer 50 may be continuously arranged from a portion overlapping with the non-overlapping portion 31Y of the transistor 31 to a portion overlapping with at least one of the plurality of bumps 70.

[0110] In this case, the plurality of layers constituting the heat conductive layer 50 may be formed of different materials. For example, the thermal conductivity of the insulating material of the layer disposed relatively close to the insulating layer 20 among the plurality of layers constituting the heat conductive layer 50 may be higher than the thermal conductivity of the insulating material of the layer disposed relatively far from the insulating layer 20. In this case, the heat dissipation efficiency of the semiconductor device 10 can be improved.

[0111] Explanation of reference numerals: 10... semiconductor device; 10A... semiconductor device of a comparative example; 20... insulating layer; 30... device layer; 31... transistor; 31C... channel region; 31D... drain region; 31G... gate electrode; 31S... source region; 31X... overlapping portion with bump; 31Y... non-overlapping portion with bump; 32D... drain contact region; 32S... source contact region; 33D... drain contact electrode; 33S... source contact electrode; 34... wiring; 34P... pad; 34T... uppermost wiring; 35... via hole; 37... metal layer of peripheral portion; 39... element formation layer; 39I... element separation region; 40... minimum containing rectangle; 41... Transistor; 41X... overlapping portion with the bump; 41Y... non-overlapping portion with the bump; 42... transistor; 50... heat conductive layer; 51... supporting substrate; 60... insulating layer; 61... protective film; 70... bump; 80... module substrate; 81... solder pad; 90... SOI substrate; 91... supporting substrate; 101... input switch; 102... frequency band selection switch for transmission; 104... antenna switch; 105... frequency band selection switch for reception; 106... low noise amplifier; 107... power amplifier control circuit; 108... low noise amplifier control circuit; 109... output terminal selection switch; 110... driver stage amplifier circuit; 111... power stage amplifier circuit; 112... duplexer.

Claims

1. A semiconductor device, wherein: have: a device layer, wherein at least one transistor is formed on the device layer; A plurality of bumps, wherein the plurality of bumps are arranged on one surface of the device layer; an insulating layer disposed on a surface of the device layer opposite to a surface on which the plurality of bumps are disposed; as well as a heat-conducting layer that contacts a surface of the insulating layer opposite to a surface on which the device layer is arranged and is formed of an insulating material having a higher thermal conductivity than that of the insulating layer, A first transistor among the transistors includes a portion that does not overlap with the plurality of bumps when the device layer is viewed from above, that is, a non-overlapping portion, and the heat conductive layer is continuously arranged from a portion overlapping with the non-overlapping portion to a portion overlapping with at least one of the plurality of bumps.

2. The semiconductor device according to claim 1, wherein The heat conductive layer includes at least one material selected from the group consisting of diamond-like carbon, boron nitride, aluminum oxide, and aluminum nitride.

3. The semiconductor device according to claim 2, wherein: The thickness of the heat-conducting layer is greater than 580 nm.

4. The semiconductor device according to any one of claims 1 to 3, wherein: The thermally conductive layer is in contact with the entire region of a surface of the insulating layer opposite to a surface on which the device layer is arranged.

5. The semiconductor device according to any one of claims 1 to 4, wherein: A support substrate is further provided. The support substrate is arranged on a surface of the heat conductive layer opposite to a surface on which the insulating layer is arranged. The support substrate is thicker than the heat conductive layer and is made of an insulating material having a lower thermal conductivity than the heat conductive layer.

6. The semiconductor device according to claim 5, wherein: The support substrate has a thermal conductivity of 30 W / m·K or less.

7. The semiconductor device according to any one of claims 1 to 6, wherein: When the device layer is viewed from above, the first transistor does not overlap with any of the plurality of bumps, and the entire region of the first transistor is the non-overlapping portion.

8. The semiconductor device according to any one of claims 1 to 6, wherein: The first transistor includes an overlapping portion that partially overlaps at least one of the plurality of bumps when the device layer is viewed from above.

9. The semiconductor device according to claim 8, wherein: When the device layer is viewed from above, the area of ​​the non-overlapping portion is larger than the area of ​​the overlapping portion.

10. The semiconductor device according to claim 8 or 9, wherein: When the device layer is viewed from above, at least one of the plurality of bumps does not overlap with the first transistor and overlaps with the thermal conductive layer.

11. The semiconductor device according to any one of claims 1 to 10, wherein: The insulating layer is composed of a single layer or multiple layers.

12. The semiconductor device according to any one of claims 1 to 11, wherein: The heat conducting layer is composed of a single layer or multiple layers.

13. The semiconductor device according to claim 12, wherein: The heat conducting layer is composed of multiple layers. The insulating material forming a layer arranged relatively close to the insulating layer among the multiple layers constituting the heat conductive layer has a higher thermal conductivity than the insulating material forming a layer arranged relatively far from the insulating layer.

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