Receiver for processing load modulated analog input signals

Abstract

A receiver (36; a receiver (36, 43) configured to receive a load-modulated analog input signal (3) and configured to output digital data (4) detected in the input signal (3), the receiver (36, 43) comprising: a first in-phase correlator (38) and a second in-phase correlator (40), or a first quadrature-phase correlator (45) and a second quadrature-phase correlator (46), the first in-phase correlator (38) comprises a first in-phase subcarrier mixer (23-1) and a first subtraction stage (39) configured to subtract the output signal (28-2) of the second quadrature-phase subcarrier mixer (23-4) from the output signal (27-1) of the first in-phase subcarrier mixer (23-1), and an integrator (26) configured to integrate the output signal (28-2) of the second quadrature-phase subcarrier mixer (23-4) from the output signal (27-1) of the first in-phase subcarrier mixer (23-1). A first in-phase correlator (38) configured to continuously integrate an output signal of the first subtraction stage (39) over time during an integration window to provide an output signal of the first in-phase correlator (38); the second in-phase correlator (40) comprises a second in-phase subcarrier mixer (23-2) and a first addition stage (41) configured to add an output signal (27-2) of the second in-phase subcarrier mixer (23-2) with an output signal (28-1) of the first quadrature-phase subcarrier mixer (23-3), and an integrator (26) configured to integrate the output signal (27-2) of the second in-phase subcarrier mixer (23-2) with the output signal (28-1) of the first quadrature-phase subcarrier mixer (23-3). And a second in-phase correlator (40) configured to continuously integrate the output signal of the first addition stage (41) over time during an integration window to provide an output signal of the second in-phase correlator (40).

Description

Technical Field

[0001] The present invention relates to a receiver which receives a load-modulated analog input signal and outputs digital data detected in the input signal, the receiver comprising: an in-phase carrier mixer which mixes the input signal with an in-phase carrier frequency signal and provides an in-phase component of a down-converted input signal; an orthogonal phase carrier mixer which mixes the input signal with an orthogonal phase carrier frequency signal and provides an orthogonal phase component of the down-converted input signal; an amplifier which amplifies the in-phase component and the orthogonal phase component of the down-converted input signal; and a DC block filter which removes a DC component from the in-phase component and the orthogonal phase component. Background Art

[0002] Document EP 3 168 772 B discloses a receiver for communication between a radio frequency identification (RFID) device (such as an RFID reader) and an active or passive transponder. In a typical application, a passive transponder or tag stores the product identity of the product to which it is connected, and the reader is used to obtain this product information. The reader is powered and generates a magnetic field from its antenna. When the reader and the tag are close to each other, the magnetic field generated by the reader is induced into the antenna of the tag and used to power the tag. The tag also has a transceiver for receiving signals from the reader and sending responses back to the reader.

[0003] There are standards such as ISO / IEC 18000-3 or ISO / IEC 14.443 Class A and Class B or ISO 15.693 or ECMA-340 13.56 MHz Near Field Communication (NFC), or company standards such as Sony's Felica, which define the protocols and modulation types used to transmit information between tags and readers. Some or all of these standards define that the reader transmits data to the tag by varying the magnitude of its transmission power. The tag receives the transmitted signal and processes the received data. The activated tag then replies by sending data to the reader. A typical technique is to use load modulation, in which the tag changes the load impedance of its coil by changing its resonant frequency and quality factor. This operation results in a voltage change at the reader antenna. The method disclosed in document EP 3 168 772 B and described in the present patent application Figure 1 The receiver of the reader shown in processes this load modulated analog input signal to output digital data detected in the input signal.

[0004] Figure 1Such a known receiver 1 is shown, which is part of an RFID reader 2, constructed to receive a load modulated analog input signal 3 sent from a transponder or tag to the reader 2 and output digital data 4 detected in the input signal 3. The reader 2 according to the disclosed embodiment communicates with the tag according to the ECMA-340 13.56MHz Near Field Communication NFC standard, which is based on ISO / IEC 14.443 Class A and Class B and Sony's corporate standard Felica for cooperative communication. The reader 2 also includes a transmitter (not shown in the figure) for emitting a magnetic field via an antenna A and transmitting data to one or more tags. For example, such a tag is disclosed in document US 7,890,080 B2.

[0005] When the reader 2 and the tag are brought into proximity with each other, the magnetic field generated by the reader 2 is induced into the antenna of the tag and used to power the tag. The tag also has a transceiver for receiving a signal from the reader 2 and transmitting a load modulated response back to the reader 2, which receives the response from the tag as a load modulated analog input signal 3. The reader 2 includes an in-phase carrier mixer 5, which mixes the input signal 3 with an in-phase component 6 of a 13.56 MHz carrier frequency signal and provides an input in-phase component 7 of a down-converted input signal. The reader 2 also includes an orthogonal phase carrier mixer 8, which mixes the input signal 3 with an orthogonal phase carrier frequency signal 9 of a 13.56 MHz carrier frequency signal and provides an input orthogonal phase component 10 of the down-converted input signal.

[0006] The receiver 1 further comprises filters 11 and 12 for filtering out unwanted mixing products from the input in-phase component 7 and the input quadrature-phase component 10 of the load modulated analog input signal 3. Such unwanted mixing products are in particular at 0 Hz and 2 x 13.56 MHz.

[0007] The receiver 1 further comprises amplifiers 13 and 14 which are constructed to amplify the filtered input in-phase component and the filtered input quadrature-phase component of the down-converted input signal. As the typical modulation of the antenna signal is very small, considerable gain is required before further processing of the input in-phase component 7 and the input quadrature-phase component 10.

[0008] The receiver 1 also includes DC block filters 15 and 16, which are constructed to remove the DC component in the amplified input in-phase component and the amplified input quadrature-phase component. This DC component is particularly added by the amplifiers 13 and 14 and needs to be removed before further processing the in-phase component 24 and the quadrature-phase component 25.

[0009] The receiver 1 further comprises a first in-phase correlator 17 and a second in-phase correlator 18 and a first quadrature phase correlator 19 and a second quadrature phase correlator 20 for correlating the in-phase component 24 and the quadrature phase component 25 with the in-phase component 21 and the quadrature phase component 22 of the subcarrier or code clock frequency of the load modulated analog input signal 3. In the initial stage of communication, based on the NFC standard, the receiver 1 detects which standard of protocol is used by the tag approached by the reader 2. If it is determined at this stage that the reader 2 and the tag will communicate based on ISO14.443 Class A or Class B, a square wave representing a subcarrier frequency of 848kHz is used, and if it is determined at this stage that the reader 2 and the tag will communicate based on Felica, a square wave representing a Manchester clock frequency of 212kHz or 424kHz is used.

[0010] Each of the in-phase correlators 17 and 18 and the quadrature-phase correlators 19 and 20 includes subcarrier mixers 23-1 to 23-4 for mixing the in-phase component 24 and the quadrature-phase component 25 from the DC block filters 15 and 16 with the in-phase component 21 and the quadrature-phase component 22 of the subcarrier or code clock frequency. The first in-phase subcarrier mixer 23-1 is constructed to mix the in-phase component 24 with the in-phase component 21 of the subcarrier having a frequency of 848 kHz. The second in-phase subcarrier mixer 23-2 is constructed to mix the in-phase component 24 with the quadrature-phase component 22 of the subcarrier having a frequency of 848 kHz. The first quadrature-phase subcarrier mixer 23-3 is constructed to mix the quadrature-phase component 25 with the in-phase component 21 of the subcarrier having a frequency of 848 kHz. The second quadrature-phase subcarrier mixer 23 - 4 is designed to mix the quadrature-phase component 25 with the quadrature-phase component 22 of the subcarrier having a frequency of 848 kHz.

[0011] Each of the in-phase correlators 17 and 18 and the quadrature-phase correlators 19 and 20 further includes an integrator 26 for continuously integrating the in-phase components 27-1 and 27-2 and the quadrature-phase components 28-1 and 28-2 from the subcarrier mixers 23-1 to 23-4 over time during an integration window. The integration windows for different modulation types are fixed as follows:

[0012] ISO14.443 Type A - four subcarrier periods;

[0013] ISO14.443 Class B - eight subcarrier cycles, data rate 106 kbit / s;

[0014] ISO14.443 Class B - four subcarrier cycles, data rate 212 kbit / s;

[0015] ISO14.443 Class B - two subcarrier cycles, data rate 424 kbit / s;

[0016] ISO14.443 Class B - one subcarrier period, data rate 848 kbit / s;

[0017] Felica - One subcarrier period.

[0018] This means that, for example for ISO 14.443 Class A, the integrator 26 integrates the outputs of the subcarrier mixers 23 - 1 to 23 - 4 over an integration window or time period of four subcarrier periods (resulting in 4.2 μs).

[0019] The receiver 1 further comprises a combiner 29 for combining the four output signals 30, 31, 32 and 33 of the two in-phase correlators 17 and 18 and the two quadrature-phase correlators 19 and 20. The combiner 29 according to one embodiment disclosed in EP 3 168 772 B is constructed to add all four output signals 30, 31, 32 and 33 of the two in-phase correlators 17 and 18 and the two quadrature-phase correlators 19 and 20 to an output signal 34 of the combiner 29. This is a technically simple and robust solution that can use as much power and information as possible about the load modulated analog input signal 3 available in the four output signals 30, 31, 32 and 33.

[0020] The receiver 1 further comprises a clipper 35 which is constructed to sample the output signal 34 of the combiner 29 at a maximum energy level to output the digital data 4 detected in the load modulated analog input signal 3. If all four output signals 30, 31, 32 and 33 are added to the output signal 34 in the combiner 29, then sampling can be performed only at the maximum energy level of the output signal 34 of the combiner 29. In another disclosed prior art embodiment, only one or more of the output signals 30, 31, 32 and 33 are selected in the combiner 29, and this information from the combiner 29 is used to select a properly aligned bit clock in the clipper 35. For example, if the combiner 29 selects the two output signals 30 and 31 of the two in-phase correlators 17 and 18 (because these two output signals comprise a higher energy level compared to the two orthogonal phase correlators 19 and 20), then the clipper 35 selects the in-phase bit clock to generate samples and detect the digital data 4 in the output signal 34. This has the advantage that the sampling point is already close to the optimal value and only requires little further adjustment.

[0021] A disadvantage of the receiver disclosed in document EP 3 168 772 B is that the four integrators 26 occupy a large area on the chip and the post-processing of all four output signals 30 , 31 , 32 and 33 consumes a large amount of energy, which is always limited. Summary of the invention

[0022] It is an object of the invention to provide a receiver which requires less chip area and consumes less energy, while at the same time improving the quality of the provided digital data.

[0023] This object is achieved by a receiver comprising all the elements claimed in claim 1 .

[0024] The present invention is based on the following discovery, namely Figure 1 The four subcarrier mixers of receiver 1 shown in can be interpreted as the multiplication of two complex numbers:

[0025] (I in +iQ in )×(I SC +iQ SC )

[0026] The receiver 1 satisfies the following equation using four subcarrier mixers 23-1 to 23-4:

[0027] I in I SC +i Q in I SC +i I in Q SC -Q in Q SC

[0028] Among them I in is the in-phase component 24 in the subcarrier, I SC is the in-phase component 21 in the subcarrier, Q in is the quadrature phase component 25 in the subcarrier, Q SC is the quadrature phase component in the subcarrier 22. The above equation can be converted to the following equation, which provides a complex number with real and imaginary terms as the result of multiplication:

[0029] (I in I SC -Q in Q SC )+i(Q in I SC +I in Q SC )

[0030] According to the above findings, if the output signal of the subcarrier mixer without an integrator is added or subtracted from the output signals of other subcarrier mixers as described in claim 1, only two of the four integrators are required. This achieves Figure 2 and Figure 5 Two different embodiments of the invention are shown.

[0031] Both embodiments of the present invention include the advantage that only two integrators reduce complexity and occupy less chip area compared to four integrators of the prior art. Since only two output signals of the correlators need to be processed in the combiner and the clipper, complexity and power consumption are reduced. Since only the amplitude of the two correlator output signals is higher compared to the amplitude of the four correlator output signals, the quality of the digital data is improved. The reason for the increase in amplitude is that the four correlator output signals are combined into two. Specifically, the output signal 28-2 is subtracted from the output signal 27-1, and the output signal 28-1 is added to the output signal 27-2. The exact increase in amplitude depends on the phase relationship between the input signal 3 and the in-phase component 6 and the quadrature phase component 9 of the 13.56 MHz clock synchronized to the 13.56 MHz carrier frequency signal, and the phase relationship between the in-phase component 24 and the quadrature phase component 25 of the code clock frequency and the in-phase component 21 and the quadrature phase component 22. In the worst case, for example if the output signal 27-1 and the output signal 28-1 contain all the signal energy, no increase can be achieved. However, in a typical case, the signal energy is dispersed over all four output signals 27-1, 27-2, 28-1 and 28-2 of the subcarrier mixers 23-1 to 23-4. These and other aspects of the invention will become apparent and elucidated with reference to the embodiments described below. Those skilled in the art will appreciate that the various embodiments may be combined. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 A receiver for processing a load modulated analog input signal according to the prior art is shown.

[0033] Figure 2 A receiver for processing a load modulated analog input signal according to a first embodiment of the present invention is shown.

[0034] Figure 3 Show according to Figure 1 and Figure 2 signals of the receivers to compare their behavior.

[0035] Figure 4 Show according to Figure 1 and Figure 2 The packet error rates of receivers at different frequencies are used to compare the quality of the digital data received by these receivers.

[0036] Figure 5 A receiver for processing a load modulated analog input signal according to a second embodiment of the present invention is shown. DETAILED DESCRIPTION

[0037] Figure 2A receiver 36 is shown, which is part of an RFID reader 37, constructed to receive a load modulated analog input signal 3 sent from a transponder or tag to the reader 37, and constructed to output digital data 4 detected in the input signal 3. The reader 37 according to the first embodiment of the present invention communicates with the tag according to the ECMA-340 13.56MHz near field communication NFC standard, which is based on ISO / IEC 14.443 Class A and Class B and Sony's Felica company standard for cooperative communication. The reader 37 also includes a transmitter (not shown in the figure) for emitting a magnetic field through an antenna A and transmitting data to one or more tags. For example, such a tag is disclosed in document US 7,890,080 B2.

[0038] Most of the blocks in the receiver 36 are similar to those described above based on Figure 1 The blocks of the receiver 1 of the prior art explained are the same. Figure 1 description, and for Figure 2 , describing in detail those blocks that enable the present invention to be implemented with the receiver 36. The receiver 36 uses the output signal 27-1 of the first in-phase subcarrier mixer 23-1, the output signal 27-2 of the second in-phase subcarrier mixer 23-2, the output signal 28-1 of the first quadrature-phase subcarrier mixer 23-3, and the output signal 28-2 of the second quadrature-phase subcarrier mixer 23-4 in a manner different from the prior art receiver 1.

[0039] The receiver 36 includes only a first in-phase correlator 38 and a second in-phase correlator 40, but does not include an orthogonal phase correlator. The first in-phase correlator 38 includes a first in-phase subcarrier mixer 23-1 and a subtraction stage 39, which is configured to subtract the output signal 28-2 of the second orthogonal phase subcarrier mixer 23-4 from the output signal 27-1 of the first in-phase subcarrier mixer 23-1. The first in-phase correlator 38 also includes an integrator 26, which is configured to continuously integrate the output signal of the subtraction stage 39 over time during an integration window to provide an output signal of the first in-phase correlator 38.

[0040] The second in-phase correlator 40 includes a second in-phase subcarrier mixer 23-2 and an adding stage 41, the adding stage 41 being configured to add the output signal 27-2 of the second in-phase subcarrier mixer 23-2 to the output signal 28-1 of the first quadrature-phase subcarrier mixer 23-2. The second in-phase correlator 40 also includes an integrator 26, the integrator 26 being configured to continuously integrate the output signal of the adding stage 41 over time during an integration window to provide the output signal of the second in-phase correlator 40.

[0041] The combiner 49 is constructed to add the output signals of the first in-phase correlator 38 and the second in-phase correlator 40. in The definition of is the in-phase component 24 in the subcarrier, I SC is the in-phase component 21 in the subcarrier, Q in is the quadrature phase component 25 in the subcarrier, Q SC is the quadrature phase component 22 in the subcarrier, realizing the following complex equation with real and imaginary terms as a result of multiplication / addition / subtraction:

[0042] (I in I SC -Q in Q SC )+i(Q in I SC +I in Q SC )

[0043] According to these findings, if the output signal of a subcarrier mixer without an integrator is added or subtracted from the output signals of other subcarrier mixers as claimed in the claims, only Figure 1 Two of the four integrators 26 of the receiver 1 are implemented. Compared with the four integrators of the prior art, implementing only two integrators reduces complexity and occupies less chip area. Since only two output signals of the first in-phase correlator 38 and the second in-phase correlator 40 need to be processed in the combiner 49 and the clipper 35, complexity and power consumption are reduced. Since the amplitude of only two output signals of the correlators 38 and 40 is higher compared to the amplitude of the four output signals of the correlators 17 to 20, the quality of the digital data 4 is improved. The reason for the increase in amplitude is that the four correlator output signals are combined into two. Specifically, the output signal 28-2 is subtracted from the output signal 27-1, and the output signal 28-1 is added to the output signal 27-2. The exact increase in amplitude depends on the phase relationship between the input signal 3 and the in-phase component 6 and quadrature phase component 9 of the 13.56 MHz clock synchronized to the 13.56 MHz carrier frequency signal and the phase relationship between the in-phase component 24 and quadrature phase component 25 of the code clock frequency and the in-phase component 21 and quadrature phase component 22. In the worst case, for example, if the output signal 27-1 and the output signal 28-1 contain all the signal energy, no improvement can be achieved. However, in a typical case, the signal energy is dispersed over all four output signals 27-1, 27-2, 28-1 and 28-2 of the subcarrier mixers 23-1 to 23-4.

[0044] Figure 3 Show according to Figure 1 The receiver 1 of the prior art and the receiver according to the first embodiment of the present invention Figure 2 As an example of a noise-free ISO 14.443 Class B frame with a frame size of 1 byte in baseband (the frame is BPSK modulated), Figure 3 A shows the in-phase component 24 of the subcarrier with a frequency of 848 kHz. Figure 3 B shows the output signal 27-1 of the first in-phase subcarrier mixer 23-1. Since the in-phase component 21 of the subcarrier operates at a frequency of 848kHz, Figure 3 Any 848kHz component in A's baseband signal ultimately ends up at DC (0Hz). Once the baseband signal is phase shifted 180° due to BPSK modulation, the DC level changes. Figure 3 C shows that according to Figure 1 The prior art receiver 1 has a four-channel method with an output signal 27-1 of a first in-phase subcarrier mixer 23-1 and an output signal 27-2 of a second in-phase subcarrier mixer 23-2 and an output signal 28-1 of a first orthogonal phase subcarrier mixer 23-3 and an output signal 28-2 of a second orthogonal phase subcarrier mixer 23-4. Figure 3 D shows Figure 2 A dual channel method with an output signal 27-1 of a first in-phase subcarrier mixer 23-1 and an output signal 27-2 of a second in-phase subcarrier mixer 23-2 according to a receiver 36 of the first embodiment of the present invention. Figure 3 Compared with C, Figure 3 The increase in the amplitude of the output signals 27-1 and 27-2 in D illustrates the performance advantage of the dual channel approach, the magnitude of which depends on the phase of the baseband signals as described above.

[0045] Figure 4 Show according to Figure 1 A prior art receiver 1 and a Figure 2 The packet error rate of the receiver 36 of the first embodiment of the present invention is compared with the quality of the digital data 4 received by these receivers 1 and 36. Figure 4 Each point in represents the ratio of "failed frames" / "total frames". For a given signal-to-noise ratio SNR [dB], 100 random frames are sent to receivers 1 and 36, and the results are analyzed. If the data is not received correctly, the frame is marked as failed. Figure 4 It is shown that by switching from the known four-channel method (curve 42) to the dual-channel method of the present invention (curve 43), by enabling the channel combination of the first in-phase correlator 38 and the second in-phase correlator 40, the performance is significantly improved, which means that the quality of the received digital data 4 is improved.

[0046] Figure 54, which is a part of an RFID reader 44, is constructed to receive a load modulated analog input signal 3 sent from a transponder or tag to the reader 44, and is constructed to output digital data 4 detected in the input signal 3. Most of the blocks of the receiver 43 according to the second embodiment of the present invention are similar to those described above based on Figure 1 The blocks of the receiver 1 of the prior art explained are the same. Figure 1 description, and for Figure 5 , those blocks of the receiver 43 that enable the present invention to be implemented are described in detail. The receiver 43 uses the output signal 27-1 of the first in-phase subcarrier mixer 23-1 and the output signal 27-2 of the second in-phase subcarrier mixer 23-2 and the output signal 28-1 of the first orthogonal phase subcarrier mixer 23-3 and the output signal 28-2 of the second orthogonal phase subcarrier mixer 23-4 in a manner different from the receiver 1 according to the prior art.

[0047] The receiver 43 includes a first quadrature phase correlator 45 and a second quadrature phase correlator 46. The first quadrature phase correlator 45 includes a first quadrature phase subcarrier mixer 23-3 and an adding stage 47, which is configured to add an output signal 27-2 of the second in-phase subcarrier mixer 23-2 to an output signal 28-1 of the first quadrature phase subcarrier mixer 23-3. The first quadrature phase correlator 45 also includes an integrator 26, which is configured to continuously integrate the output signal of the adding stage 47 over time during an integration window to provide an output signal of the first quadrature phase correlator 45.

[0048] The second quadrature phase correlator 46 comprises a second quadrature phase subcarrier mixer 23-4 and a subtraction stage 48 for subtracting the output signal 27-1 of the first in-phase subcarrier mixer 23-1 from the output signal 28-2 of the second quadrature phase subcarrier mixer 23-4. The second quadrature phase correlator 46 further comprises an integrator 26 which is constructed to continuously integrate the output signal of the subtraction stage 48 over time during an integration window to provide the output signal of the second quadrature phase correlator 46. The receiver 43 of the second embodiment of the present invention achieves the same advantages as the receiver 36 of the first embodiment of the present invention.

[0049] As a result, the receiver 43 discloses a second embodiment of the invention as claimed. Both the receiver 36 and the receiver 43 implement the complex number with real and imaginary terms as described above by using two correlators, wherein the signals between the subcarrier mixers 23-1 to 23-4 and the integrator 26 are modified by the subtraction stages 39 and 47 and the addition stages 41 and 48.

[0050] In another embodiment of the present invention, the combiner 49 is constructed to select one of the two output signals of the first in-phase correlator 38 and the second in-phase correlator 40 or the first quadrature phase correlator 45 and the second quadrature phase correlator 46. For the case where BPSK modulation is used, this selection of one of the output signals of the integrator 26 is a preferred embodiment, while for amplitude modulation, the two correlator output signals are preferably added. In the case of selecting one of the two output signals, the clipper 35 is constructed to use the information from the combiner 49 which of the two output signals is selected to select the appropriately aligned bit clock to sample the output signal 34 of the combiner 49.

[0051] In another embodiment of the present invention, the combiner 49 is configured to interpret one of the output signals of the two correlators 38, 40, 45, 46 as a real term of a complex number, and to interpret the other of the two output signals of the two correlators 38, 40, 45, 46 as an imaginary term of a complex number, wherein the combiner 49 is configured to calculate and output the absolute value of the complex number based on the following formula:

[0052] The absolute value (or modulus or magnitude) of a complex number z=x+yi is

[11]

[0053]

[0054] And wherein the combiner 49 is constructed to calculate and output the phase of the complex number based on the following formula:

[0055]

[0056] The combiner 49 may output the absolute value and phase of the complex number. The advantage is that the combiner 49 uses both outputs of the correlator 26 to calculate the amplitude and phase, compared to selecting one of the outputs of the correlator 26. Therefore, no signal energy is lost by ignoring one of the outputs, and the signal quality is improved. The same applies to adding the two outputs of the correlator 26, and can be seen as a simpler alternative to calculating the amplitude.

Claims

1. A receiver (36; 43) configured to receive a load modulated analog input signal (3) and configured to output digital data (4) detected in the input signal (3), the receiver (36; 43) comprising: an in-phase carrier mixer (5) configured to mix the input signal (3) with an in-phase carrier frequency signal (6) and configured to provide an input in-phase component (7) of the down-converted input signal; a quadrature phase carrier mixer (8) configured to mix the input signal (3) with a quadrature phase carrier frequency signal (9) and configured to provide an input quadrature phase component (10) of the down-converted input signal; an amplifier (13, 14) configured to amplify an input in-phase component (7) and an input quadrature-phase component (10) of the down-converted input signal; A DC block filter (15) configured to remove a DC component of the input in-phase component (7) and the input quadrature-phase component (10), and configured to provide an in-phase component (24) and a quadrature-phase component (25); a first in-phase subcarrier mixer (23-1) configured to mix the in-phase component (24) with an in-phase component (21) of a subcarrier or code clock frequency; a second in-phase subcarrier mixer (23-2) configured to mix the in-phase component (24) with a quadrature phase component (22) of the subcarrier or code clock frequency; a first quadrature-phase subcarrier mixer (23-3) configured to mix the quadrature-phase component (25) with the in-phase component (21) of the subcarrier or code clock frequency; a second quadrature-phase subcarrier mixer (23-4) configured to mix the quadrature-phase component (25) with the quadrature-phase component (22) of the subcarrier or code clock frequency; a combiner (49) configured to combine output signals of the first in-phase correlator (38) and / or the second in-phase correlator (40) and / or the first quadrature-phase correlator (45) and / or the second quadrature-phase correlator (46) of the receiver (36; 43); a clipper (35) configured to sample the output signal (34) of the combiner (49) at a maximum energy level to output the digital data (4) detected in the input signal (3), The receiver (36; 43) comprises the first in-phase correlator (38) and the second in-phase correlator (40) or the first orthogonal phase correlator (45) and the second orthogonal phase correlator (46), The first in-phase correlator (38) comprises: the first in-phase subcarrier mixer (23-1) and a first subtraction stage (39), the first subtraction stage (39) being constructed to subtract an output signal (28-2) of the second quadrature-phase subcarrier mixer (23-4) from an output signal (27-1) of the first in-phase subcarrier mixer (23-1), and an integrator (26) configured to continuously integrate the output signal of the first subtraction stage (39) over time during an integration window to provide an output signal of the first in-phase correlator (38); The second in-phase correlator (40) comprises: the second in-phase subcarrier mixer (23-2) and a first adding stage (41), the first adding stage (41) being constructed to add an output signal (27-2) of the second in-phase subcarrier mixer (23-2) and an output signal (28-1) of the first quadrature-phase subcarrier mixer (23-3), and an integrator (26) configured to continuously integrate the output signal of the first summing stage (41) over time during an integration window to provide an output signal of the second in-phase correlator (40); The first orthogonal phase correlator (45) comprises: the first quadrature-phase subcarrier mixer (23-3) and a second adding stage (47), the second adding stage (47) being constructed to add an output signal (27-2) of the second in-phase subcarrier mixer (23-2) to an output signal (28-1) of the first quadrature-phase subcarrier mixer (23-3), and an integrator (26) configured to continuously integrate the output signal of the second summing stage (47) over time during an integration window to provide the output signal of the first quadrature phase correlator (45); The second orthogonal phase correlator (46) comprises: the second quadrature-phase subcarrier mixer (23-4) and a second subtraction stage (48), the second subtraction stage (48) being used to subtract the output signal (27-1) of the first in-phase subcarrier mixer (23-1) from the output signal (28-2) of the second quadrature-phase subcarrier mixer (23-4), and An integrator (26) is constructed to continuously integrate the output signal of the second subtraction stage (48) over time during an integration window to provide an output signal of the second quadrature phase correlator (46).

2. A receiver (36; 43) according to claim 1, wherein the duration of the integration window depends on the modulation type of the load modulated analog input signal (3) and is fixed for the modulation type as follows: ISO14.443 Type A - four subcarrier periods; ISO14.443 Class B - eight subcarrier cycles, data rate 106 kbit / s; ISO14.443 Class B - four subcarrier cycles, data rate 212 kbit / s; ISO14.443 Class B - two subcarrier cycles, data rate 424 kbit / s; ISO14.443 Class B - one subcarrier period, data rate 848 kbit / s; Felica - One subcarrier period.

3. A receiver (36; 43) according to claim 1 or 2, wherein the combiner (49) is constructed to add two output signals of the first in-phase correlator (38) and the second in-phase correlator (40) or the first orthogonal phase correlator (45) and the second orthogonal phase correlator (46).

4. A receiver (36; 43) according to claim 1 or 2, wherein the combiner (49) is constructed to select one of the two output signals of the first in-phase correlator (38) and the second in-phase correlator, or to select one of the two output signals of the first orthogonal phase correlator (45) and the second orthogonal phase correlator (46).

5. A receiver (36; 43) according to claim 4, wherein the clipper (35) is constructed to use information from the combiner (49) as to which of the two output signals has been selected to select a suitably aligned bit clock for sampling the output signal (34) of the combiner (49).

6. A receiver (36; 43) according to any one of claims 1 to 5, wherein the first and second in-phase correlators (38, 40) and the first and second quadrature-phase correlators (45, 46) correlate each of the in-phase component (24) and the quadrature-phase component (25) of the load modulated analog input signal (3) with the in-phase component (21) and the quadrature-phase component (22) of the subcarrier or code clock frequency according to the modulation type of the load modulated analog input signal (3), fixed for the modulation type as follows: ISO14.443 Class A and Class B, using a square wave to represent the subcarrier frequency; Felica, with a square wave representing the Manchester clock frequency.

7. A receiver (36; 43) according to any one of claims 1 to 6, comprising filters (11, 12) for filtering out unwanted mixing products from the in-phase component (7) and the quadrature-phase component (10) of the down-converted input signal.

8. The receiver (36; 43) according to any one of claims 1 to 7, wherein the combiner (49) is constructed to interpret one of the output signals of the two correlators (38, 40, 45, 46) as a real term of a complex number and to interpret the other of the two output signals of the two correlators (38, 40, 45, 46) as an imaginary term of the complex number, and wherein the combiner (49) is constructed to calculate and output the absolute value of the complex number based on the following formula: The absolute value (or modulus or magnitude) of a complex number z=x+yi is [11] And wherein the combiner (49) is constructed to calculate and output the phase of the complex number based on the following formula:

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