Semiconductor device and power amplification module

Abstract

The invention provides a semiconductor device and a power amplifier module capable of expanding a lower limit value of an operating temperature range. A semiconductor device includes a first semiconductor element (1) in which a plurality of transistors arranged in one direction are electrically connected in parallel, and second semiconductor elements provided at both ends of the first semiconductor element (1) in the arrangement direction of the transistors. The lower the ambient temperature is, the larger the current flowing through the second semiconductor element is.

Description

Technical Field

[0001] The invention relates to a semiconductor device and a power amplification module. Background Art

[0002] As a technology for improving the efficiency of a power amplifier circuit mounted on a wireless communication terminal, a semiconductor device is known in which a power amplifier is formed by electrically connecting multiple transistors in parallel on the same chip (for example, Patent Document 1). In addition, a multi-finger heterojunction bipolar transistor (HBT: Heterojunction Bipolar Transistor) that can operate at high efficiency is arranged in a row in the short side direction of the emitter finger and connected in parallel, thereby achieving both high output and miniaturization (for example, Patent Document 2). Patent Document 2 discloses a structure that takes into account the uneven heat generation within the HBT unit. Specifically, the emitter fingers in the center are affected by the heat from the emitter fingers in the peripheral portion, and thus become a higher temperature.

[0003] Prior Art Literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent No. 2580966

[0006] Patent Document 2: Japanese Patent Application Publication No. 2007-027269

[0007] In recent years, there has been a desire for a power amplifier device that can be used even in extremely cold places such as below -30°C (Celsius). Generally speaking, the withstand voltage of bipolar transistors such as HBTs decreases in low temperature environments. Therefore, for example, in an extremely low temperature environment below -30°C, the junction at the end of the device may become overvoltage. Summary of the invention

[0008] Problem that the invention aims to solve

[0009] The present disclosure is made in view of the above situation, and its object is to realize a semiconductor device and a power amplifier module that can expand the lower limit of the operating temperature range.

[0010] Technical solutions to solve problems

[0011] A semiconductor device according to one aspect of the present disclosure comprises: a first semiconductor element which electrically connects a plurality of transistors arranged in one direction in parallel; and a second semiconductor element which is arranged at both ends of the first semiconductor element in the arrangement direction of the transistors, wherein the lower the ambient temperature, the more the current flowing through the second semiconductor element increases relatively.

[0012] In this structure, the lower the ambient temperature, the more the heat generated by the second semiconductor element increases, and the junction temperature of the position corresponding to the junction of the second semiconductor element increases. In addition, the closer to the junction of the second semiconductor element, the higher the junction temperature of the position corresponding to each junction of the first semiconductor element increases.

[0013] A power amplifier module according to one aspect of the present disclosure comprises: the semiconductor device described above; a substrate for flip-chip mounting the semiconductor device; and a bump disposed between the semiconductor device and the substrate, wherein the bump is disposed in a region overlapping the first semiconductor element and is not disposed in a region overlapping the second semiconductor element when viewed from above.

[0014] In this structure, heat dissipation from the position corresponding to the junction of the second semiconductor element can be suppressed. Thus, the junction temperature of the position corresponding to the junction of the second semiconductor element can be increased.

[0015] A power amplifier module according to one aspect of the present disclosure comprises: the above-mentioned semiconductor device; and a substrate, on which the semiconductor device is mounted by wire bonding, wherein, in a plan view, the semiconductor device is provided with heat dissipation vias in a region overlapping with the first semiconductor element, and is not provided with heat dissipation vias in a region overlapping with the second semiconductor element.

[0016] In this structure, heat dissipation from the position corresponding to the junction of the second semiconductor element can be suppressed. Thus, the junction temperature of the position corresponding to the junction of the second semiconductor element can be increased.

[0017] Effects of the Invention

[0018] According to the present disclosure, a semiconductor device and a power amplifier module capable of extending the lower limit value of the operating temperature range can be realized. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 This is a schematic diagram showing an example of a power amplifier module.

[0020] Figure 2 It is a top perspective view of a semiconductor device.

[0021] Figure 3 is a diagram showing an example of an internal circuit structure of a semiconductor device.

[0022] Figure 4 This is a schematic diagram showing an example of the temperature characteristics of the bias current supplied to the semiconductor element.

[0023] Figure 5 is a schematic diagram showing the junction temperature of a semiconductor device in an extremely low temperature environment.

[0024] Figure 6 This is a top perspective view of the semiconductor device according to the first embodiment.

[0025] Figure 7 This is a diagram showing an example of the internal circuit structure of the semiconductor device according to the first embodiment.

[0026] Figure 8 It is a schematic diagram showing an example of the temperature characteristics of the bias current supplied to the second semiconductor element.

[0027] Fig. 9 This is a diagram showing an example of a change in junction temperature of the semiconductor device according to the first embodiment with respect to a change in ambient temperature.

[0028] Fig.10 This is a schematic diagram showing the junction temperature of the semiconductor device according to the first embodiment in an extremely low temperature environment.

[0029] Fig.11 This is a diagram showing an example of the internal circuit structure of a semiconductor device according to the second embodiment.

[0030] Fig. 12A This is a diagram showing an example of the internal circuit structure of a semiconductor device according to the third embodiment.

[0031] Fig. 12B This is a diagram showing an example of the internal circuit structure of a semiconductor device according to the third embodiment.

[0032] Fig.13 This is a cross-sectional view of the power amplifier module according to the fourth embodiment, taken along the X direction.

[0033] Fig.14 It is a cross-sectional view along the X direction of the power amplifier module according to the fifth embodiment.

[0034] Description of Reference Numerals

[0035] 1: Semiconductor components;

[0036] 1_n: junction (semiconductor element, first semiconductor element);

[0037] 2: Substrate;

[0038] 2_1, 2_2: junction (second semiconductor element);

[0039] 10, 10a, 10b: power amplifier module;

[0040] 20, 20a, 20b, 20c: semiconductor devices;

[0041] 21: dielectric layer;

[0042] 22: reference potential surface;

[0043] 23: through hole;

[0044] 24: Strip bump;

[0045] 25: heat dissipation vias;

[0046] 30, 40, 40a: bias circuit;

[0047] 50: temperature sensor;

[0048] 61: AD conversion circuit;

[0049] 62: control current generating circuit;

[0050] 63: storage circuit;

[0051] 100: power amplifier module;

[0052] 200: semiconductor devices;

[0053] D2_1, D2_2: diodes (second semiconductor elements);

[0054] Tr1_n: transistor (semiconductor element, first semiconductor element);

[0055] Tr2_1, Tr2_2: transistors (second semiconductor elements). DETAILED DESCRIPTION

[0056] Hereinafter, the semiconductor device and the power amplifier module involved in the embodiment are described in detail based on the accompanying drawings. In addition, the present disclosure is not limited to the embodiment. Each embodiment is an example, and it is self-evident that partial replacement or combination of the structures shown in different embodiments can be performed. After embodiment 2, the description of matters common to embodiment 1 is omitted, and only the differences are described. In particular, the same effects based on the same structure will not be mentioned one by one in each embodiment.

[0057] Figure 1 1 is a schematic diagram showing an example of a power amplifier module. The power amplifier module 100 amplifies a high-frequency input signal and outputs a high-frequency output signal. Figure 1 In the example, a power amplifier (PA) having a two-stage structure including a driver stage and a power stage is illustrated. Figure 1, a structure in which impedance matching circuits M / N are provided at a preceding stage of a driver stage power amplifier DRV, between the driver stage power amplifier DRV and the power stage power amplifier POWER, and at a subsequent stage of the power stage power amplifier POWER is illustrated.

[0058] In the present disclosure, the power amplifier module 100 is not limited to Figure 1 The power amplifier module 100 may be configured by a single-stage power amplifier or may be configured by connecting three or more amplifiers in multiple stages.

[0059] In addition, in the present disclosure, the power amplifier module 100 is, for example, an ultra-small integrated module in which multiple integrated circuits and various functional components are installed on a substrate 2 composed of a ceramic laminate substrate such as a low temperature co-fired ceramic (LTCC) substrate, a resin multilayer substrate, a thin film substrate, etc.

[0060] Figure 2 is a top-down perspective view of a semiconductor device. Figure 2 In the example, the composition Figure 1 A semiconductor device 200 of a power stage power amplifier POWER is shown. Figure 3 is a diagram showing an example of an internal circuit structure of a semiconductor device.

[0061] As the semiconductor device 200 , for example, a GaAs (gallium arsenide)-based heterojunction bipolar transistor (HBT: Heterojunction Bipolar Transistor) device (integrated circuit, IC: Integrated Circuit) can be exemplified.

[0062] In the present disclosure, a semiconductor device 200 includes a semiconductor element 1 having N (N is an integer greater than 2) junctions 1_n (n is an integer from 2 to N) arranged in the X direction. Specifically, the semiconductor element 1 is a bipolar transistor having a so-called multi-finger structure in which N transistors Tr1_n are electrically connected in parallel. Here, the so-called junction refers to a junction where a p-type semiconductor and an n-type semiconductor form a pn junction, and as an example, a junction between a base layer and a collector layer in a bipolar transistor can be shown. Figure 2 The nodes 1n and Figure 3 The transistors Tr1_n shown correspond to each other.

[0063] The emitter of each transistor Tr1_n is electrically connected to a reference potential. The reference potential may be, for example, the ground potential GND, but the present disclosure is not limited thereto.

[0064] The high frequency input signal RFin is input to the base of each transistor Tr1_n via the capacitor C. In addition, the current supplied from the bias circuit 30 flows through the base of each transistor Tr1_n via the resistor RB1. The total of the currents flowing through the bases of the transistors Tr1_n is equal to the bias current Ib1 supplied from the bias circuit 30.

[0065] A power supply potential VCC is applied to the collector of each transistor Tr1_n. The high-frequency signal that has been power-amplified by the semiconductor element 1 is output as a high-frequency output signal RFout.

[0066] exist Figure 3 In the structure shown in FIG. 1 , the resistance value of the resistor RB1 is set to 150Ω, for example. In addition, the capacitance value of the capacitor C is set to 0.8 pF, for example. Figure 3 In the illustrated structure, the resistance value of the resistor R31 of the bias circuit 30 is set to, for example, 100Ω.

[0067] The bias circuit 30 is applied with a bias power supply potential Vbat, and supplies a bias current Ib1 corresponding to a bias control current Ib1ctrl to the semiconductor element 1. The bias control current Ib1ctrl is supplied from a control circuit (not shown) provided inside or outside the power amplifier module 100, for example.

[0068] Figure 4 FIG. 1 is a schematic diagram showing an example of the temperature characteristics of the bias current supplied to the semiconductor element. Figure 4 As shown in FIG. 1 , the bias current Ib1 supplied to the semiconductor element 1 does not depend on the ambient temperature Ta and becomes a substantially constant value (at Figure 4 In the example shown, it is about 130 μA. Here, it is assumed that each transistor Tr1_n has substantially the same characteristics. In this case, the current flowing through the base of each transistor Tr1_n does not depend on the ambient temperature Ta and becomes substantially constant. At this time, the temperature change of the junction 1_n of each transistor Tr1_n relative to the change of the ambient temperature Ta becomes substantially constant.

[0069] Generally speaking, the withstand voltage of the bipolar transistor constituting the semiconductor device 200 decreases in a low temperature environment. Figure 5 is a schematic diagram showing the junction temperature of a semiconductor device in an extremely low temperature environment. Figure 5 In FIG. 1 , the junction temperature of a semiconductor device at an ambient temperature Ta = -30°C is exemplified. Figure 5 The horizontal axis shows Figure 2 The X direction is shown.

[0070] like Figure 5As shown, the junction temperature distribution in the semiconductor device 200 is biased. Specifically, the junction temperature near the end of the semiconductor device 200 is relatively low compared to the center of the semiconductor device 200 where the temperature is likely to rise due to thermal interference between the transistors Tr1_n. Figure 5 , the following example is shown, that is, the junction temperature Tj at the position corresponding to the junctions 1_1, 1_N of the transistors Tr1_1, Tr1_N near the end of the semiconductor device 200 is 15°C, and the junction temperature Tj at the position corresponding to the junction 1_N / 2 of the transistor Tr1_N / 2 near the center of the semiconductor device 200 is 25°C.

[0071] Due to the uneven heat dissipation of the semiconductor device 200, in a low temperature environment, the junction located at the end of the device may become overvoltage, and sometimes the required specifications of the operating temperature range cannot be met. The following describes the structure of a semiconductor device and a power amplifier device that can expand the lower limit of the operating temperature range.

[0072] (Implementation Method 1)

[0073] Figure 6 FIG. 1 is a perspective view of a semiconductor device according to Embodiment 1. Figure 6 In the example, the composition Figure 1 The semiconductor device 20 of the power stage power amplifier POWER shown in the figure. As the semiconductor device 20, the semiconductor device 20 described above can be exemplified. Figure 2 The HBT device has the same structure as shown. Figure 7 This is a diagram showing an example of the internal circuit structure of the semiconductor device according to the first embodiment.

[0074] In the semiconductor device 20 according to the first embodiment, the structure of the first semiconductor element 1 is substantially the same as that in Figure 2 as well as Figure 3 The structure of the semiconductor element 1 described in is the same.

[0075] The semiconductor device 20 according to the first embodiment includes a second semiconductor element having junctions 2_1 and 2_2 provided at both ends of the junctions 1_n in the arrangement direction (X direction) in addition to the first semiconductor element 1. In the first embodiment, the second semiconductor element is transistors Tr2_1 and Tr2_2. Figure 6 The nodes 2_1, 2_2 and Figure 7 The transistors Tr2_1 and Tr2_2 shown correspond to each other.

[0076] The emitters of transistors Tr2_1 and Tr2_2 are electrically connected to the reference potential. Bias currents Ib2_1 and Ib2_2 supplied from the bias circuit 40 flow through the bases of the transistors Tr2_1 and Tr2_2 via the resistor RB2. The power supply potential VCC is supplied to the collectors of the transistors Tr2_1 and Tr2_2 via the resistor RC. That is, the resistor RC is provided between the collectors of the transistors Tr1_n, which are the power supply points for supplying the power supply potential VCC to the first semiconductor element 1, and the collectors of the transistors Tr2_1 and Tr2_2, which are the power supply points for supplying the power supply potential VCC to the second semiconductor element.

[0077] exist Figure 7 In the structure shown, the resistance value of the resistor RB2 of the second semiconductor element (transistors Tr2_1 and Tr2_2) is set to, for example, 100Ω. In addition, the resistance value of the resistor RC is set to, for example, 1000Ω. Thus, the isolation between each transistor Tr1_n of the first semiconductor element 1 and the transistors Tr2_1 and Tr2_2 can be ensured.

[0078] In addition, Figure 7 In the structure shown, the resistance value of the resistor R41 of the bias circuit 40 is set to 350Ω, for example. The resistance value of the resistor R42 is set to 4500Ω, for example. The resistance values ​​of the resistors R43, R44, R45, and R46 are set to 1000Ω, for example. The resistance value of the resistor Ree is set to approximately 400Ω, for example.

[0079] Figure 8 It is a schematic diagram showing an example of the temperature characteristics of the bias current supplied to the second semiconductor element. Fig. 9 This is a diagram showing an example of a change in junction temperature of the semiconductor device according to the first embodiment with respect to a change in ambient temperature. Fig.10 This is a schematic diagram showing the junction temperature of the semiconductor device according to the first embodiment in an extremely low temperature environment.

[0080] exist Figure 8 In the figure, the solid line shows an example of temperature characteristics when the resistance value of the resistor Ree is 405Ω, the dotted line shows an example of temperature characteristics when the resistance value of the resistor Ree is 400Ω, and the single-dot chain line shows an example of temperature characteristics when the resistance value of the resistor Ree is 395Ω.

[0081] exist Fig. 9 In FIG. 1 , the solid line shows the change in the junction temperature at the position corresponding to the junctions 1_1 and 1_N near the end of the semiconductor device 20. Fig. 9 The dashed line shows the Figure 2 as well as Figure 3 The change of the junction temperature at the position corresponding to the junction 1_1 and 1_N near the end of the semiconductor device 200 of the structure shown in FIG. Fig. 9 In FIG. 1 , the single-dot chain line shows the change in junction temperature at a position corresponding to the junction portion 1_N / 2 near the center portion of the semiconductor device 20 having the structure according to the first embodiment.

[0082] exist Fig.10 In FIG. 1 , the junction temperature of the semiconductor device 20 at an ambient temperature Ta=-30° C. is exemplified. Fig.10 The horizontal axis shows Figure 6 The X direction is shown.

[0083] like Figure 4 As shown, the bias current Ib1 supplied to the first semiconductor element 1 is independent of the ambient temperature Ta and becomes a substantially constant value. In other words, the current flowing through the base of each transistor Tr1_n of the first semiconductor element 1 is independent of the ambient temperature Ta and becomes substantially constant. As a result, the current flowing through each transistor Tr1_n of the first semiconductor element 1 is independent of the ambient temperature Ta and becomes substantially constant. Therefore, the change in the heat generation of the first semiconductor element 1 caused by the change in the ambient temperature Ta is within a very small range.

[0084] In contrast, Figure 8 As shown, according to the temperature characteristics of the on-voltage in the active region of the transistor Tr42, the lower the ambient temperature Ta, the more the bias currents Ib2_1 and Ib2_2 supplied to the second semiconductor element (transistors Tr2_1 and Tr2_2) increase. More specifically, the lower the ambient temperature Ta, the greater the on-voltage in the active region of the transistor Tr42 becomes. If the base-emitter voltage of the transistors Tr2_1 and Tr2_2 and the transistors Tr43 and Tr44 that are Darlington-connected to the transistors Tr2_1 and Tr2_2 exceed the on-voltage, the bias currents Ib2_1 and Ib2_2 increase sharply. In conjunction with this, the lower the ambient temperature Ta, the more the current flowing through the transistors Tr2_1 and Tr2_2 increases relatively. As a result, the lower the ambient temperature Ta, the more the heat generated by the transistors Tr2_1 and Tr2_2 increases, and the junction temperature at the position corresponding to the junctions 2_1 and 2_2 of the second semiconductor element rises. As the junction temperature at the positions corresponding to the junctions 2_1 and 2_2 of the second semiconductor element increases, the junction temperature at the positions corresponding to the respective junctions 1_n of the first semiconductor element 1 increases as they are closer to the junctions 2_1 and 2_2 of the second semiconductor element.

[0085] exist Figure 7 In the structure shown in the figure, by appropriately setting the resistance values ​​of the resistor RB2 and the resistor RC of the second semiconductor element, and the resistance values ​​of the resistor R41, the resistor R42, the resistors R43, R44, R45, R46 and the resistor Ree of the bias circuit 40, for example, Fig. 9As shown in FIG. 1 , the junction temperature of the junctions 1_1 and 1_N of the transistors Tr1_1 and Tr1_N near the end of the semiconductor device 20 can be set to be consistent with the junction temperature of the junction 1_N / 2 of the transistor Tr1_N / 2 near the center of the semiconductor device 20 in an extremely low temperature environment (e.g., −30° C.). Thus, for example, Fig.10 As shown, in an extremely low temperature environment (eg, -30°C), the junction temperatures at positions corresponding to the respective junction portions 1_n of the first semiconductor element 1 can be made substantially uniform.

[0086] (Implementation Method 2)

[0087] Fig.11 1 is a diagram showing an example of the internal circuit structure of the semiconductor device according to Embodiment 2. In the semiconductor device 20a according to Embodiment 2, the structures of the first semiconductor element 1 and the second semiconductor element (transistors Tr2_1 and Tr2_2) are substantially the same as those of the semiconductor device 20 described in Embodiment 1.

[0088] In the second embodiment, the structure is set as follows, that is, it comprises: a temperature sensor (thermistor) 50 for sensing the ambient temperature; an AD conversion circuit 61 for digitally converting the detection value of the temperature sensor 50; a control current generating circuit 62 for generating a bias control current Ib2ctrl supplied to the bias circuit 40a; and a storage circuit 63 for maintaining the relationship between the temperature detection value obtained by the temperature sensor 50 and the bias control current Ib2ctrl as a current control table.

[0089] The control current generating circuit 62 refers to the current control table stored in the storage circuit 63 to generate the bias control current Ib2ctrl corresponding to the detection value of the temperature sensor 50. The bias circuit 40a supplies the bias current Ib2 corresponding to the bias control current Ib2ctrl to the second semiconductor element (transistors Tr2_1 and Tr2_2). This makes it easy to change the temperature setting.

[0090] (Implementation 3)

[0091] Fig. 12A as well as Fig. 12B 1 is a diagram showing an example of the internal circuit structure of a semiconductor device according to Embodiment 3. In semiconductor devices 20b and 20c according to Embodiment 3, the structure of the first semiconductor element 1 is substantially the same as the structure of the semiconductor device 20 described in Embodiment 1.

[0092] In the third embodiment, the second semiconductor element is a diode D2_1, D2_2. The junctions of the diodes D2_1, D2_2 are respectively connected to Figure 6 The knots 2_1 and 2_2 shown correspond. Fig. 12A In the structure shown in FIG. 1 , the resistance value of the resistor RD2 of the second semiconductor element (diodes D2_1 and D2_2) is set to 100Ω, for example. Fig. 12A In FIG. 1 , a structure is illustrated in which forward currents Id2_1 and Id2_2 are supplied to diodes D2_1 and D2_2, respectively. Fig. 12B , a configuration is illustrated in which a current Id2 which is the sum of forward currents of diodes D2_1 and D2_2 is supplied.

[0093] Even in Fig. 12A as well as Fig. 12B In each structure of the third embodiment shown, by applying the bias circuit 40 involved in the first embodiment and appropriately setting each resistance value, it is possible to set it so that, for example, in an extremely low temperature environment, the junction temperature of the junctions 1_1 and 1_N of the transistors Tr1_1 and Tr1_N near the ends of the semiconductor devices 20b and 20c is consistent with the junction temperature of the junction 1_N / 2 of the transistor Tr1_N / 2 near the center of the semiconductor devices 20b and 20c.

[0094] Or, moreover, even in Fig. 12A as well as Fig. 12B In each structure of the third embodiment shown, by applying the temperature sensor 50, the AD conversion circuit 61, the control current generation circuit 62, the storage circuit 63, and the bias circuit 40a according to the second embodiment, it becomes easy to change the temperature setting.

[0095] (Implementation 4)

[0096] Fig.13 1 is a cross-sectional view along the X direction of the power amplifier module according to Embodiment 4. In Embodiment 4, the internal circuit structure of the semiconductor devices 20, 20a, 20b, and 20c corresponds to the structure of each of the above-mentioned Embodiments 1, 2, and 3. In Embodiment 4, the semiconductor devices 20, 20a, 20b, and 20c are set to be flip-chip mounted on the substrate 2 of the power amplifier module 10a.

[0097] In the substrate 2 , reference potential planes 22 (GND layers) are provided with a plurality of dielectric layers 21 interposed therebetween, and the reference potential planes 22 are connected via through vias 23 to form a heat dissipation structure. Fig.13 The power amplifier module 10a involved in the fourth embodiment shown has the following structure, that is, a strip bump 24 long in the X direction is provided between the reference potential plane (GND layer provided on the chip surface) of the semiconductor devices 20, 20a, 20b, and 20c and the reference potential plane 22 provided on the component mounting surface of the substrate 2.

[0098] like Fig.13As shown, in the power amplifier module 10a according to the fourth embodiment, in a plan view of the substrate 2 in the Z direction, the stripe bumps 24 are provided in the region S1 overlapping with each junction 1_n of the first semiconductor element 1, and are not provided in the region S2 overlapping with the junctions 2_1 and 2_2 of the second semiconductor element. Thus, heat dissipation from the positions corresponding to the junctions 2_1 and 2_2 of the second semiconductor element can be suppressed. Thus, the junction temperature of the positions corresponding to the junctions 2_1 and 2_2 of the second semiconductor element can be increased.

[0099] (Implementation method 5)

[0100] Fig.14 1 is a cross-sectional view along the X direction of the power amplifier module according to Embodiment 5. In Embodiment 5, the internal circuit structure of the semiconductor devices 20, 20a, 20b, and 20c corresponds to the structure of each of the above-mentioned Embodiments 1, 2, and 3. In Embodiment 5, the semiconductor devices 20, 20a, 20b, and 20c are set to be mounted on the substrate 2 of the power amplifier module 10b by wire bonding.

[0101] The structure of the substrate 2 is the same as that of the fourth embodiment. Fig.14 As shown, in the semiconductor devices 20, 20a, 20b, and 20c of the power amplifier module 10b according to the fifth embodiment, in a plan view of the substrate 2 in the Z direction, a heat dissipation via 25 is provided in a region S1 overlapping with each junction 1_n of the first semiconductor element 1, and no heat dissipation via 25 is provided in a region S2 overlapping with the junctions 2_1 and 2_2 of the second semiconductor element. The so-called heat dissipation via 25 refers to a via that penetrates the semiconductor devices 20, 20a, 20b, and 20c. Thus, heat dissipation from the position corresponding to the junctions 2_1 and 2_2 of the second semiconductor element can be suppressed. Thus, the junction temperature of the position corresponding to the junctions 2_1 and 2_2 of the second semiconductor element can be increased.

[0102] In addition, in the above-mentioned embodiment, a bipolar transistor is exemplified as a transistor constituting the semiconductor device 200, but the present invention is not limited thereto, and for example, a mode consisting of a MOSFET may also be included. Even in this case, due to the uneven heat dissipation of the semiconductor device, an overvoltage may occur in the channel portion of the MOSFET located at the end of the device in a low temperature environment, and the required specifications of the operating temperature range may not be met.

[0103] In addition, the above-mentioned embodiments are for easy understanding of the present disclosure, and are not for limiting the present invention. The present disclosure can be changed / improved without departing from the gist thereof, and the present disclosure also includes its equivalents.

[0104] The present disclosure may have the following structures as described above or in place of the above.

[0105] (1) A semiconductor device according to one aspect of the present disclosure comprises: a first semiconductor element that electrically connects a plurality of transistors arranged in a direction in parallel; and a second semiconductor element that is arranged at both ends of the first semiconductor element in the direction in which the transistors are arranged, wherein the current flowing through the second semiconductor element relatively increases as the ambient temperature is lower.

[0106] In this structure, the lower the ambient temperature, the more the heat generated by the second semiconductor element increases, and the junction temperature of the position corresponding to the junction of the second semiconductor element increases. In addition, the closer to the junction of the second semiconductor element, the higher the junction temperature of the position corresponding to each junction of the first semiconductor element increases.

[0107] (2) In the semiconductor device of (1) above, the second semiconductor element is a transistor.

[0108] In this structure, as the ambient temperature drops, the heat generated by the transistor increases, and the junction temperature at the position corresponding to the junction of the transistor increases. Accordingly, the junction temperature at the position corresponding to each junction of the first semiconductor element increases as it approaches the junction of the transistor.

[0109] (3) In the semiconductor device of (2) above, a resistor is provided between a power supply point to the first semiconductor element and a power supply point to the second semiconductor element.

[0110] In this structure, the isolation between the first semiconductor element and the second semiconductor element can be ensured.

[0111] (4) In the semiconductor device of (1) above, the second semiconductor element is a diode.

[0112] In this structure, as the ambient temperature drops, the heat generated by the diode increases, and the junction temperature at the position corresponding to the junction of the diode increases. Accordingly, the junction temperature at the position corresponding to each junction of the first semiconductor element increases as it approaches the junction of the diode.

[0113] (5) A power amplifier module according to one aspect of the present disclosure comprises: the semiconductor device described above; a substrate on which the semiconductor device is flip-chip mounted; and a bump disposed between the semiconductor device and the substrate, wherein the bump is disposed in a region overlapping the first semiconductor element and is not disposed in a region overlapping the second semiconductor element when viewed from above.

[0114] In this structure, heat dissipation from the position corresponding to the junction of the second semiconductor element can be suppressed. Thus, the junction temperature of the position corresponding to the junction of the second semiconductor element can be increased.

[0115] (6) A power amplifier module according to one aspect of the present disclosure comprises: the above-mentioned semiconductor device; and a substrate, on which the semiconductor device is mounted by wire bonding, wherein, in a plan view, the semiconductor device has a heat dissipation via in a region overlapping with the first semiconductor element, and has no heat dissipation via in a region overlapping with the second semiconductor element.

[0116] In this structure, heat dissipation from the position corresponding to the junction of the second semiconductor element can be suppressed. Thus, the junction temperature of the position corresponding to the junction of the second semiconductor element can be increased.

[0117] The present disclosure can realize a semiconductor device and a power amplifier module that can extend the lower limit of the operating temperature range.

Claims

1. A semiconductor device comprising: A first semiconductor element electrically connects a plurality of transistors arranged in one direction in parallel; and a second semiconductor element provided at both ends of the first semiconductor element in the arrangement direction of the transistors; The lower the ambient temperature, the more the current flowing through the second semiconductor element increases relatively.

2. The semiconductor device according to claim 1, wherein The second semiconductor element is a transistor.

3. The semiconductor device according to claim 2, wherein: A resistor is provided between a power supply point for the first semiconductor element and a power supply point for the second semiconductor element.

4. The semiconductor device according to claim 1, wherein: The second semiconductor element is a diode.

5. A power amplifier module, comprising: The semiconductor device according to any one of claims 1 to 4; a substrate for performing flip chip mounting on the semiconductor device; and A bump is disposed between the semiconductor device and the substrate, In a plan view, the bump is provided in a region overlapping with the first semiconductor element, and is not provided in a region overlapping with the second semiconductor element.

6. A power amplifier module, comprising: The semiconductor device according to any one of claims 1 to 4; and a substrate for mounting the semiconductor device by wire bonding, In a plan view, the semiconductor device is provided with a heat dissipation via in a region overlapping with the first semiconductor element, and is not provided with a heat dissipation via in a region overlapping with the second semiconductor element.

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