FMC module based on RFSOC

Abstract

The invention discloses an FMC module based on an RFSOC, and relates to the technical field of communication, the FMC module comprises an RFSOC chip, the RFSOC chip is provided with a sub-module set along different chip sections, the sub-module set comprises RFSOC sub-modules which are all in communication connection with one another, and a clock sub-module and a power supply sub-module which are arranged on the periphery; the RFSOC submodule comprises an AD-DA conversion module, a programming module and a logic module; the clock sub-module comprises an ADCLK948 clock driving chip, an ADCLK925 clock driving chip, an ADCLK944 clock driving chip, a CDCLV1204 clock driving chip, a differential crystal oscillator and a single-ended crystal oscillator; the power supply sub-module comprises a 12V voltage source, an LTM4650 DC-DC power supply chip, an LTM4671 DC-DC power supply chip, a TPS51200 DDR power supply chip and a TPS7A8500 LDO power supply chip, wherein the power supply is kept by the 12V voltage source. According to the invention, the RFSOC chip is divided into a plurality of independent working modules, and the FMC + module, the clock module and the RFSOC chip are matched to work, so that the modules integrally support flexible combination and expansion with different external function support plates, and the system has the advantage of improving the flexible expansibility.

Description

Technical Field

[0001] The present invention relates to the field of communication technology, and in particular to an FMC module based on RFSOC. Background Art

[0002] There are two common RF_SOC layout modes on the market: the first mode is to use RF_SOC with power supply, FLASH, DDR circuit core interface module. Most of these boards are non-standard boards, and their business function interfaces such as AD, DA, I / O, etc. need to be led out through inter-board connectors, and then the circuit is expanded by the carrier board; the second mode is that RF_SOC and its peripheral circuits are all integrated on the board, which can be fully expanded and used, but because the whole board solidifies the solution, it cannot be freely matched with different functional carrier boards, which is very clumsy. Both existing solutions have flexibility problems caused by the inability of RF_SOC and its peripheral circuits to be fully integrated on standard small cards. These two solutions are difficult to quickly adapt to different carrier cards or expand functions when rapid development or diversified applications are required. Therefore, their adaptability in new application scenarios is limited, especially in the context of diversified needs, and rapid functional expansion cannot be effectively achieved. Summary of the invention

[0003] The present invention provides an FMC module based on RFSOC, which solves the problems of insufficient flexibility in matching functional carrier boards and poor adaptability on integrated standard small cards in the RF_SOC board layout mode of the prior art.

[0004] The present invention is achieved through the following technical solutions: An FMC module based on RFSOC includes an RFSOC chip, wherein the RFSOC chip is provided with submodule sets along different chip sections, wherein the submodule sets include RFSOC submodules, clock submodules, power submodules and FMC+ modules which are all interconnected and communicated with each other. The RFSOC submodule includes a programming module PS, a logic module PL and an AD-DA conversion module, and the AD / DA function of the AD-DA conversion module is led out in the form of an SMP RF connector; the AD-DA conversion element includes one BANK230 chip segment for digital-to-analog conversion and three BANK225~BANK227 chip segments for analog-to-digital conversion in the RFSOC chip; the SMP RF connector sends signals to the input end of the BANK225~BANK227 chip segment, and the BANK230 chip segment sends signals to the SMP RF connector; The clock submodule includes an ADCLK948 clock driver chip, an ADCLK925 clock driver chip, an ADCLK944 clock driver chip, a CDCLV1204 clock driver chip, an LMK61E2-SIAR programmable crystal oscillator, a 100MHz differential crystal oscillator with LVDS level output, and a 33.33MHz single-ended crystal oscillator with LVCMOS level output; The power submodule includes a 12V voltage source and an LTM4650 DC-DC power chip, an LTM4622 DC-DC power chip, an LTM4671 DC-DC power chip, a TPS51200 DDR power chip and a TPS7A8500 LDO power chip which are powered by the 12V voltage source.

[0005] Furthermore, the input end of the BANK88 chip section of the RFSOC chip is connected in parallel to the FMC+ module using 9 LVDS lines and 1 LVDS_CC line; the BANK128 and BANK129 chip sections of the RFSOC chip are connected in parallel to the FMC+ module using 8 MGT high-speed transceiver lines.

[0006] Furthermore, the LTM4650 DC-DC power supply chip is provided with a first power output end and a second power output end, the first power output end is connected with a first VCC port, the second power output end is connected with a second VCC port, a PHY chip power port and two parallel TPS7A8500 LDO power supply chips; the TPS51200 DDR power supply chip is connected with an output end of the second VCC port; the output ends of the two parallel TPS7A8500 LDO power supply chips are both connected with a third VCC port.

[0007] Furthermore, the LTM4622 DC-DC power chip is connected to a FLASH memory power supply and a first ADM7172 LDO power chip, and the output end of the first ADM7172 LDO power chip is connected to an analog-to-digital conversion VCC port in two parallel paths.

[0008] Further, the LTM4671 DC-DC power supply chip is provided with a first rectifier output end and a second rectifier output end, the second rectifier output end is connected to a fourth VCC port, the first rectifier output end is connected to two second ADM7172 LDO power supply chips and two TPS7A8500 LDO power supply chips, wherein the two second ADM7172 LDO power supply chips and the two TPS7A8500 LDO power supply chips are connected to the first rectifier output end in a two-way parallel arrangement.

[0009] Furthermore, the LTM4671 DC-DC power supply chip is also provided with a third rectifier output terminal and a fourth rectifier output terminal, the third rectifier output terminal is connected in parallel with a fourth VCC port, a fifth VCC port and a PHY storage power supply port; the fourth rectifier output terminal is connected with a third ADM7172 LDO power supply chip.

[0010] Furthermore, the output end of the ADCLK925 clock driver chip is simultaneously connected to the input end of the BANK65 chip section and the input end of the BANK128 chip section of the RFSOC chip; the output end of the ADCLK948 clock driver chip is simultaneously connected to the input end of the BANK65 chip section, the input end of the BANK230 chip section and the input end of the BANK128 chip.

[0011] Furthermore, the ADCLK948 chip is connected to the BANK225 chip segment via one RF digital-to-analog conversion clock line, is connected to the BANK226 chip segment via one RF digital-to-analog conversion clock line, and is connected to the BANK227 chip segment via one RF digital-to-analog conversion clock line.

[0012] Furthermore, the RFSOC submodule also includes a balun module; the SMP RF connector is connected to the AD-DA converter in the following manner: the output end of the BANK230 chip segment is connected in sequence to the ADCLK925 clock driver chip, the FMC+ module, the ADCLK944 clock driver chip, the CDCLVD1204 chip, the balun module, and the input end of the SMP RF connector; the output end of the SMP RF connector is connected in sequence to the CDCLVD1204 chip, the ADCLK944 clock driver chip, and the input end of the BANK225 chip segment.

[0013] Furthermore, the output end of the ADCLK948 clock driver chip is simultaneously connected to the input end of the BANK65 chip segment and the input ends of the BANK225, BANK226, and BANK227 chip segments.

[0014] Compared with the prior art, the present invention divides the RFSOC chip into multiple independently working modules, and through the cooperation of the FMC+ module, the clock module and the RFSOC chip, the module as a whole supports flexible combination and expansion with different external functional carrier boards, and through the integration of a multi-channel DC-DC power supply and an LDO power supply module, the interference of power supply noise on signal processing is effectively avoided, and the flexibility and expansibility of the system are improved while retaining the high integration of the RFSOC chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The drawings described herein are used to provide a further understanding of the embodiments of the present invention, constitute a part of this application, and do not constitute a limitation of the embodiments of the present invention. In the drawings: Figure 1 This is a functional block diagram of the system of the present invention; Figure 2 This is a power supply principle block diagram of the present invention; Figure 3 This is a block diagram of the clock principle of the present invention. DETAILED DESCRIPTION

[0016] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with embodiments and drawings. The exemplary embodiments of the present invention and their description are only used to explain the present invention and are not intended to limit the present invention. Example

[0017] like Figure 1 As shown, this embodiment is an FMC module based on RFSOC, including an RFSOC chip, wherein the RFSOC chip is provided with submodule sets along different chip sections, wherein the submodule sets include RFSOC submodules, clock submodules, power submodules and FMC+ modules which are all interconnected and communicated with each other. The RFSOC submodule includes a programming module PS, a logic module PL and an AD-DA conversion module, and the AD / DA function of the AD-DA conversion module is led out in the form of an SMP RF connector; the AD-DA conversion element includes one BANK230 chip segment for digital-to-analog conversion and three BANK225~BANK227 chip segments for analog-to-digital conversion in the RFSOC chip; the SMP RF connector sends signals to the input end of the BANK225~BANK227 chip segment, and the BANK230 chip segment sends signals to the SMP RF connector; The clock submodule includes an ADCLK948 clock driver chip, an ADCLK925 clock driver chip, an ADCLK944 clock driver chip, a CDCLV1204 clock driver chip, an LMK61E2-SIAR programmable crystal oscillator, a 100MHz differential crystal oscillator with LVDS level output, and a 33.33MHz single-ended crystal oscillator with LVCMOS level output; The power submodule includes a 12V voltage source and an LTM4650 DC-DC power chip, an LTM4622 DC-DC power chip, an LTM4671 DC-DC power chip, a TPS51200 DDR power chip and a TPS7A8500 LDO power chip which are powered by the 12V voltage source.

[0018] It should be noted that in the specific implementation, Figure 1 As shown, in this embodiment, the BANK65 chip segment can be equivalently replaced by the BANK66 chip segment; the BANK88 chip segment can be equivalently replaced by the BANK89 chip segment; the BANK128 chip segment can be equivalently replaced by the BANK129 chip segment. As a feasible implementation method, Figure 1 As shown, the programming module PS is provided with a DDR4 memory chip and connected to the BANK504 chip segment; in this embodiment, a JTAG debugging interface and an RS232 serial communication interface are also provided, and the JTAG debugging interface and the RS232 serial communication interface are connected to the BANK503 chip segment and the BANK500 chip segment respectively. Figure 1-Figure 3 As shown in the figure, if the devices in this embodiment have special connection specifications, such as the conversion lines, transmission lines, voltage values, current values ​​and other parameter identifiers required for connection, they are all indicated in the figure and will not be described in detail here. Figure 2 The port suffix numbers in the table represent the negative tolerance or voltage drop value of the voltage rail of the actual chip. Figure 1 The DDR4 of BANK65 and 66 is the external cache of RFSOC PL and is an independent device; the DDR4 of BANK504 is the external cache of RFSOCPS and is an independent device.

[0019] The meaning of setting up a submodule set based on different chip sections of the RFSOC chip means that inside the RFSOC chip, the chip is divided into multiple different chip sections or module areas according to different functions and circuit structures, each area realizes a specific function, and the submodules in these sections are interconnected and work together to form a complete system. The SMP RF connector is used to provide an external physical connection for analog signals. The BANK230 chip section and the BANK225 chip section are associated with the analog front end of the RFSOC, including analog signal acquisition, transmission and processing modules. In the RFSOC design, the BANK230 and 225 sections usually carry high-speed AD converters, DA converters and other signal processing modules. The combination of the SMP RF connector and the BANK225 section can be represented in a specific application. The BANK225 area will contain the front-end circuit of the signal, and the SMP RF connector is used to receive signals from external sensors or signal sources to ensure that the signal changes from a single-ended form to a differential form before entering the subsequent signal processing module. The SMP RF connector receives input signals from a signal source (such as an antenna, sensor, etc.), then amplifies and transmits them to the input end of the BANK225 chip segment; the BANK225 chip segment is usually responsible for further digital signal processing or conversion, such as analog to digital signal conversion. The signal output by the BANK230 chip segment is transmitted back to the SMP RF connector. In specific applications, BANK230 may include functions for modulating, sampling, or generating signals of a specific frequency, and the signal can be further amplified or processed after being returned to the low noise amplifier. The FMC+ module is used to be compatible with different external devices, providing a high-bandwidth, low-latency communication interface, so that the overall module supports flexible combination and expansion with different external functional carriers. The use of various standardized clock distribution chips in the clock synchronization module allows RFSOC to achieve accurate clock synchronization with different functional carriers, further enhancing the compatibility of the system. Through the built-in efficient clock synchronization and power management functions of RFSOC, system integration becomes easier, reducing the need for external components, reducing the complexity and integration difficulty of the system.

[0020] Among them, as a further implementation method, Figure 3As shown, the RFSOC submodule also includes a balun module; the SMP RF connector is connected to the AD-DA converter in the following manner: the output end of the BANK230 chip segment is connected in sequence to the ADCLK925 clock driver chip, the FMC+ module, the ADCLK944 clock driver chip, the CDCLVD1204 chip, the balun module, and the input end of the SMP RF connector; the output end of the SMP RF connector is connected in sequence to the CDCLVD1204 chip, the ADCLK944 clock driver chip, and the input end of the BANK225 chip segment.

[0021] The balun module is used to convert an asymmetric signal (such as a single-ended signal) into a symmetrical signal (differential signal), or to convert a differential signal into a single-ended signal. In the process of RF signal processing in this embodiment, the balun module can be used to ensure the symmetry of the signal, especially in the processing of high-frequency signals, it can ensure that the signal will not be subject to excessive interference or loss during transmission. The balun module converts the differential signal from the BANK230 chip segment into a signal suitable for subsequent single-ended processing, so as to communicate more efficiently with other modules. At the output end of the BANK230 chip segment, when the signal is transmitted, it first passes through the clock generator ADCLK925 clock driver chip to obtain a high-precision clock signal, and then the signal is transmitted in sequence to the FMC+ module connected to the external device, the clock generator ADCLK944 clock driver chip and the clock distributor CDCLVD1204 chip, and then the signal is converted into a single-ended signal through the balun module and transmitted to the SMP RF connector for output, and the output signal is then transmitted to the downstream module or device. As a feasible implementation method, Figure 1 As shown, a balun module is also connected between the SMP RF connector and the AD-DA converter, and its model is TCM2-33WX+ chip. The balun module is used to perform frequency conversion on the signal to ensure that the signal frequency sent to the conversion module is in the optimal operating frequency band of each chip segment in the AD-DA converter, reduce the sensitivity to high-frequency noise, and improve conversion accuracy and signal quality.

[0022] Further, as a feasible implementation method, Figure 1 As shown, the input end of the BANK88 chip section of the RFSOC chip is connected in parallel with the FMC+ module using 9 LVDS lines and 1 LVDS_CC line; the BANK128 and BANK129 chip sections of the RFSOC chip are connected in parallel with the FMC+ module using 8 MGT high-speed transceiver lines.

[0023] The LVDS line is a differential signal technology for high-speed digital signal transmission, with low power consumption, high speed and good anti-interference. It transmits signals by differential pairs, which can significantly reduce electromagnetic interference (EMI) and signal reflection. The MGT line is a serial transmission channel designed for extremely high data rates, and is usually used for multi-channel, high-speed data transmission in FPGAs or other integrated circuits. The 9-channel LVDS line is used to transmit multiple parallel data streams. Each LVDS signal is a differential pair (that is, two signal lines transmit mutually inverted signals), which means that multiple high-speed data channels can be transmitted in parallel, thereby providing a larger bandwidth; the 1-channel LVDS_CC line is used to provide a clock synchronization signal. The clock signal is transmitted through the LVDS differential signal to ensure that the channels of the data stream remain synchronized. The 9-channel LVDS line and the 1-channel LVDS_CC line are used between the BANK88 chip segment and the FMC+ module, which can effectively reduce interference and ensure signal integrity while providing a relatively high transmission rate. The 8-way MGT lines between the BANK128 and BANK129 chip segments and the FMC+ module can meet higher bandwidth and carry large-capacity data streams.

[0024] Further, as a feasible implementation method, Figure 2 As shown, the LTM4650 DC-DC power supply chip is provided with a first power output end and a second power output end, the first power output end is connected with a first VCC port, the second power output end is connected with a second VCC port, a PHY chip power port and two parallel TPS7A8500 LDO power supply chips; the TPS51200 DDR power supply chip is connected with an output end of the second VCC port; the output ends of the two parallel TPS7A8500 LDO power supply chips are both connected with a third VCC port.

[0025] The LTM4650 is a DC-DC power chip that can convert a high input voltage into a stable low voltage output. In this embodiment, two voltage outputs are provided to supply power to a lower power module and a module that requires a more stable voltage and a higher current. The LTM4650 DC-DC power chip provides voltage to the first VCC port through the first power output terminal to provide power for modules with low power consumption and low stability requirements in the circuit. The second power output terminal of the LTM4650 DC-DC power chip is connected to multiple subsequent modules, including the second VCC port, the PHY chip power port, and the TPS7A8500 LDO power chip connected in parallel with two channels. The second output terminal is used to provide power for modules that require higher current or more stable voltage, and provides clean power for some modules that are particularly sensitive to noise. Through the two-way parallel setting, redundancy and higher output capacity are provided to ensure that high-sensitivity modules can work stably. The TPS7A8500 is a low-noise regulator, which is mainly used to provide clean power for highly sensitive analog circuits or radio frequency circuits, and its output terminal is connected to the third VCC port. By using multiple TPS7A8500 LDO power chips in parallel, the design effectively provides low-noise power for noise-sensitive modules, ensuring that parts of the system that require high signal integrity (such as RF modules, precision analog circuits, etc.) are not disturbed by power noise. The TPS51200 low-noise regulator is used for multi-channel power management, and is usually used to provide stable power for multiple voltage rails at the same time, supporting multiple different voltage outputs, and providing multiple stable voltage output rails by connecting to the second VCC port. The use of the TPS51200 DDR power chip simplifies the management of multiple voltage rails, centrally manages multiple power outputs through one module, and improves the integration of the system.

[0026] Furthermore, if Figure 2 As shown, the LTM4622 DC-DC power chip is connected with a FLASH memory power supply and a first ADM7172 LDO power chip, and the output end of the first ADM7172 LDO power chip is connected with an analog-to-digital conversion VCC port in two parallel paths.

[0027] The LTM4622 DC-DC power chip is used to convert a higher input voltage into a stable low voltage output, and has a rectification function, which can effectively convert voltage while reducing power loss in the system. The LTM4622 DC-DC power chip provides a stable power supply for the FLASH memory power supply. The first ADM7172 LDO power chip is used to provide a stable low voltage output from a higher voltage source. The advantage of a low-dropout regulator is that it can maintain a small difference between the input voltage and the output voltage, and has a high-precision voltage regulation capability. The first ADM7172 LDO power chip adjusts and fine-tunes the voltage from the LTM4622 DC-DC power chip to ensure that a low-noise, high-stability voltage output is provided for subsequent circuits. Its output end is connected to the VCC port for analog-to-digital conversion to ensure that the ADC can obtain an accurate, low-noise power supply. The analog-to-digital conversion VCC port is used to convert analog signals into digital signals. Through the combination of LTM4622 DC-DC power chip and the first ADM7172 LDO power chip, the system can provide high-precision, low-noise power for analog-to-digital converters and other sensitive modules, ensuring the reliability of the system in high-precision applications. The two parallel first ADM7172 LDO power chips increase the reliability of the power supply and can provide higher current carrying capacity, ensuring that even under heavy loads, the analog-to-digital conversion VCC port can still obtain a stable voltage, avoiding instability or data errors caused by power problems.

[0028] Further, as a feasible implementation method, Figure 2 As shown, the LTM4671 DC-DC power supply chip is provided with a first rectifier output terminal and a second rectifier output terminal, the second rectifier output terminal is connected with a fourth VCC port, the first rectifier output terminal is connected with two second ADM7172 LDO power supply chips and two TPS7A8500 LDO power supply chips, wherein the two second ADM7172 LDO power supply chips and the two TPS7A8500 LDO power supply chips are connected to the first rectifier output terminal in a two-way parallel arrangement; the LTM4671 DC-DC power supply chip is also provided with a third rectifier output terminal and a fourth rectifier output terminal, the third rectifier output terminal is connected in parallel with a fourth VCC port, a fifth VCC port and a PHY storage power supply port; the fourth rectifier output terminal is connected with a third ADM7172 LDO power supply chip.

[0029] The LTM4671 DC-DC power chip converts a higher input voltage (such as 12V or 24V) into multiple required lower voltage outputs. Its main goal is to provide different voltage rails for various modules in the system to ensure the power supply stability of the system and the reliable operation of each module. The multiple rectifier output terminals of the LTM4671 DC-DC power chip are used to supply power to different voltage rails or modules, including VCC port, PHY storage power port, and power required by other modules. The third ADM7172 LDO power chip is used to convert a higher input voltage into a stable low voltage output. The two second ADM7172 LDO power chips are configured in parallel to improve the current carrying capacity of the power supply, and further ensure the stability of the power supply. The parallel configured voltage regulator ensures that the power supply can maintain a stable output even when the load is heavy. The TPS7A8500 LDO power chip is used to improve the output capacity of the voltage regulator, ensure that modules with large current requirements can obtain stable power, and further reduce power supply noise through parallel design. The first rectifier output terminal provides a stable power supply for a high-precision, low-noise module through a second ADM7172 LDO power chip and a TPS7A8500 LDO power chip arranged in parallel, while improving the current carrying capacity. The second rectifier output terminal provides power for the fourth VCC port to meet the needs of a specific module. The third rectifier output terminal provides multiple power outputs in parallel, including a fourth VCC port, a fifth VCC port and a PHY storage power port, to provide power for multiple modules. In this embodiment, as a specific application, the output ends of the two second ADM7172 LDO power chips are respectively connected to the digital-to-analog conversion VCC port and the clock VCC port that provides the TPS51200 DDR power chip voltage and storage voltage, and one of the output ends of the TPS7A8500 LDO power chip is connected to a clock VCC port that provides RS232 voltage.

[0030] Furthermore, the output end of the ADCLK925 clock driver chip is simultaneously connected to the input end of the BANK65 chip section and the input end of the BANK128 chip section of the RFSOC chip; the output end of the ADCLK948 clock driver chip is simultaneously connected to the input end of the BANK65 chip section, the input end of the BANK230 chip section and the input end of the BANK128 chip; the ADCLK948 chip is connected to the BANK225 chip section through a RF digital-to-analog conversion clock line, is connected to the BANK226 chip section through a RF digital-to-analog conversion clock line, and is connected to the BANK227 chip section through a RF digital-to-analog conversion clock line; the output end of the ADCLK948 clock driver chip is simultaneously connected to the input end of the BANK65 chip section and the input ends of the BANK225, BANK226, and BANK227 chip sections.

[0031] The ADCLK925 and ADCLK948 are clock source chips, which are usually used to generate high-precision clock signals and are widely used in high-speed data transmission and system synchronization. In this embodiment, the output end of the ADCLK925 clock driver chip is simultaneously connected to the input end of the BANK65 chip segment and the BANK230 chip segment. The ADCLK925 clock driver chip provides clock signals, which are transmitted to the BANK65 chip segment and the BANK230 chip segment at the same time, so the two chip segments will share the same clock signal to achieve clock synchronization, ensuring that the modules in the two segments can work synchronously under the same clock to avoid timing problems. The ADCLK948 clock driver chip is connected to the BANK225 chip segment through 3 RF digital-to-analog conversion clock lines. RF digital-to-analog conversion clock lines (RFDAC clock lines) are often used to convert clock signals from the digital domain to the analog domain, or to provide clock synchronization in high-frequency applications. The ADCLK948 clock driver chip provides clock signals for the BANK65 chip segment and the BANK128 chip segment to ensure that the modules in the segment can maintain synchronization. Through the multiple clock sources and precise clock transmission lines of the ADCLK925 clock driver chip and the ADCLK948 clock driver chip, the clock synchronization between multiple chip segments in the system can be ensured, and the coordinated work between different modules can be ensured.

[0032] In this embodiment, the setting form of the first VCC port is expressed as VCCINT / VCCINT_IO / VCCBRAM, which means that the first VCC port provides core voltage, I / O voltage and memory voltage to the RFSOC chip, and provides multi-voltage output. The setting form of the second VCC port is expressed as VCC_DDR / VCCIO_1V2, which means that the second VCC port provides DDR BANK voltage and I / O voltage to the RFSOC chip. The setting form of the third VCC port is expressed as VADC_AVCC, which means that the third VCC port provides a front power supply to the TPS7A8500 LDO power chip, and converts the analog-to-digital conversion voltage and analog voltage required by the RFSOC chip through it. The setting form of the fourth VCC port is expressed as VCCAUX / VMGTVCCAUX / VCC_PSDDR_PL / VCC_PSBATT, which means that the fourth VCC port provides auxiliary voltage, transmission voltage, storage voltage and low-power standby voltage to the RFSOC chip. The setting form of the fifth VCC port is expressed as VCC_PL / PS_IO, which means that the fifth VCC port provides a programmable logic voltage and an IO interface voltage to the RFSOC chip.

[0033] The specific implementation methods described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific implementation method of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. An FMC module based on RFSOC, comprising an RFSOC chip, wherein the RFSOC chip is provided with submodule sets along different chip sections, wherein the submodule sets include RFSOC submodules, clock submodules, power submodules and FMC+ modules which are all interconnected and communicated with each other, characterized in that: The RFSOC submodule includes a programming module PS, a logic module PL and an AD-DA conversion module, and the AD / DA function of the AD-DA conversion module is led out in the form of an SMP RF connector; the AD-DA conversion element includes one BANK230 chip segment for digital-to-analog conversion and three BANK225~BANK227 chip segments for analog-to-digital conversion in the RFSOC chip; the SMP RF connector sends signals to the input end of the BANK225~BANK227 chip segment, and the BANK230 chip segment sends signals to the SMP RF connector; The clock submodule includes an ADCLK948 clock driver chip, an ADCLK925 clock driver chip, an ADCLK944 clock driver chip, a CDCLV1204 clock driver chip, an LMK61E2-SIAR programmable crystal oscillator, a 100MHz differential crystal oscillator with LVDS level output, and a 33.33MHz single-ended crystal oscillator with LVCMOS level output; The power submodule includes a 12V voltage source and an LTM4650 DC-DC power chip, an LTM4622 DC-DC power chip, an LTM4671 DC-DC power chip, a TPS51200 DDR power chip and a TPS7A8500 LDO power chip which are powered by the 12V voltage source.

2. The FMC module based on RFSOC according to claim 1, characterized in that: The input end of the BANK88 chip section of the RFSOC chip is connected to the FMC+ module in parallel using 9 LVDS lines and 1 LVDS_CC line; the BANK128 and BANK129 chip sections of the RFSOC chip are connected to the FMC+ module in parallel using 8 MGT high-speed transceiver lines.

3. The FMC module based on RFSOC according to claim 1, characterized in that: The LTM4650 DC-DC power supply chip is provided with a first power output end and a second power output end, the first power output end is connected with a first VCC port, the second power output end is connected with a second VCC port, a PHY chip power port and two parallel TPS7A8500 LDO power supply chips; the TPS51200 DDR power supply chip is connected with an output end of the second VCC port; the output ends of the two parallel TPS7A8500 LDO power supply chips are both connected with a third VCC port.

4. The FMC module based on RFSOC according to claim 1, characterized in that: The LTM4622 DC-DC power chip is connected with a FLASH memory power supply and a first ADM7172 LDO power chip, and the output end of the first ADM7172 LDO power chip is connected with an analog-to-digital conversion VCC port in two parallel paths.

5. The FMC module based on RFSOC according to claim 1, characterized in that: The LTM4671 DC-DC power supply chip is provided with a first rectifier output end and a second rectifier output end, the second rectifier output end is connected with a fourth VCC port, the first rectifier output end is connected with two second ADM7172 LDO power supply chips and two TPS7A8500 LDO power supply chips, wherein the two second ADM7172 LDO power supply chips and the two TPS7A8500 LDO power supply chips are connected to the first rectifier output end in a two-way parallel arrangement.

6. The FMC module based on RFSOC according to claim 5, characterized in that: The LTM4671 DC-DC power supply chip is also provided with a third rectifier output terminal and a fourth rectifier output terminal, wherein the third rectifier output terminal is connected in parallel with a fourth VCC port, a fifth VCC port and a PHY storage power supply port; and the fourth rectifier output terminal is connected with a third ADM7172 LDO power supply chip.

7. The FMC module based on RFSOC according to claim 1, characterized in that: The output end of the ADCLK925 clock driver chip is simultaneously connected to the input end of the BANK65 chip section and the input end of the BANK128 chip section of the RFSOC chip; the output end of the ADCLK948 clock driver chip is simultaneously connected to the input end of the BANK65 chip section, the input end of the BANK230 chip section and the input end of the BANK128 chip.

8. The FMC module based on RFSOC according to claim 7, characterized in that: The ADCLK948 chip is connected to the BANK225 chip section via one RF digital-to-analog conversion clock line, is connected to the BANK226 chip section via one RF digital-to-analog conversion clock line, and is connected to the BANK227 chip section via one RF digital-to-analog conversion clock line.

9. The FMC module based on RFSOC according to claim 1, characterized in that: The RFSOC submodule also includes a balun module; the SMP RF connector is connected to the AD-DA converter in the following manner: the output end of the BANK230 chip segment is connected in sequence to the ADCLK925 clock driver chip, the FMC+ module, the ADCLK944 clock driver chip, the CDCLVD1204 chip, the balun module, and the input end of the SMP RF connector; the output end of the SMP RF connector is connected in sequence to the CDCLVD1204 chip, the ADCLK944 clock driver chip, and the input end of the BANK225 chip segment.

10. The FMC module based on RFSOC according to claim 9, characterized in that: The output end of the ADCLK948 clock driver chip is simultaneously connected to the input end of the BANK65 chip segment and the input ends of the BANK225, BANK226, and BANK227 chip segments.

Images