Semiconductor device, preparation method thereof and chip

Abstract

The invention provides a semiconductor device, a preparation method thereof and a chip, relates to the technical field of semiconductors, and aims to reduce the process difficulty. The preparation method of the semiconductor device comprises the following steps: forming a bottom electrode on a substrate; forming a dielectric layer by adopting a sputtering process, wherein the dielectric layer is positioned on one side, far away from the substrate, of the bottom electrode; a top electrode is formed and located on the side, away from the substrate, of the dielectric layer; wherein in the process of forming the dielectric layer, the substrate is heated, and the heating temperature ranges from 50 DEG C to 400 DEG C; moreover, in the process of forming the dielectric layer, direct current bias voltage is applied to the substrate, the change range of the direct current bias voltage is-500V to + 150V, or radio frequency bias power is applied to the substrate, and the change range of the radio frequency bias power is 50w to 400w. The semiconductor device can be applied to a memory chip or a sensor chip, the memory chip can be a nonvolatile memory, and the sensor chip can be a micro electro mechanical system pressure sensor.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for preparing the same, as well as a chip. Background Art

[0002] At present, in the semiconductor film formation process, in order to ensure the quality of the film, the film formation process temperature needs to be set relatively high (usually in the range of 600°C to 750°C), which limits the freedom of material use and process selection and increases the difficulty of the process. Summary of the invention

[0003] The present application proposes a semiconductor device and a method for manufacturing the same, and a chip, aiming to reduce the difficulty of the process.

[0004] In a first aspect, a method for preparing a semiconductor device is provided, the method comprising: forming a bottom electrode on a substrate; forming a dielectric layer by a sputtering process, the dielectric layer being located on a side of the bottom electrode away from the substrate; forming a top electrode, the top electrode being located on a side of the dielectric layer away from the substrate; wherein, in the process of forming the dielectric layer, the substrate is heated at a heating temperature in a range of 50°C to 400°C; and, in the process of forming the dielectric layer, a DC bias voltage is applied to the substrate, the DC bias voltage varies in a range of -500V to +150V, or a radio frequency bias power is applied to the substrate, the radio frequency bias power varies in a range of 50W to 400W.

[0005] The dielectric layer is formed by a sputtering process. During the process, a DC bias voltage is applied to the substrate. The DC bias voltage varies in the range of -500V to +150V. When the DC bias voltage is a negative voltage, positively charged ions in the vacuum chamber can be attracted to bombard the substrate. When the DC bias voltage is a positive voltage, negatively charged ions in the vacuum chamber can be attracted to bombard the substrate, generating plasma heat on the surface of the substrate, which can increase the surface temperature of the substrate and promote the crystal growth of the dielectric material. Therefore, even if the heating temperature of the substrate is reduced to the range of 50°C to 400°C, the film quality and characteristics of the dielectric layer can be guaranteed.

[0006] Alternatively, during the process, by applying RF bias power to the substrate, the RF bias power varies in the range of 50W to 400W. When the RF bias power is negative, positively charged ions in the vacuum chamber can be attracted to bombard the substrate. When the RF bias power is positive, negatively charged ions in the vacuum chamber can be attracted to bombard the substrate. The surface temperature of the substrate can also be increased to promote the crystal growth of the dielectric material. Therefore, even if the heating temperature of the substrate is reduced to the range of 50°C to 400°C, the film quality and characteristics of the dielectric layer can be guaranteed.

[0007] Moreover, compared with heating by a heater or plasma heat generated by target bombarding a substrate, the plasma heat generated by positive and negative ion bombarding a substrate can be controlled by controlling the change of DC bias voltage or RF bias power. This method is easy to control and has a good heating effect on the substrate.

[0008] In some embodiments, during the process of forming the dielectric layer, the substrate is heated at a heating temperature ranging from 100° C. to 400° C.

[0009] In some embodiments, before forming the dielectric layer, the substrate is preheated at a temperature ranging from 100° C. to 250° C.

[0010] In some embodiments, before forming the bottom electrode, an adhesion layer is formed, wherein the adhesion layer is in contact with the surface of the substrate; and the bottom electrode is formed, wherein the bottom electrode is located on a side of the adhesion layer away from the substrate.

[0011] In some embodiments, during the process of forming the adhesion layer and the bottom electrode, the substrate is heated at a heating temperature ranging from 100° C. to 250° C.

[0012] In some embodiments, a sputtering process is used to form a dielectric film, and the dielectric film is located on a side of the bottom electrode away from the substrate; and a photolithography process is used to etch the dielectric film to form the dielectric layer.

[0013] In some embodiments, the dielectric layer has a thickness ranging from 0.001 μm to 400 μm.

[0014] In some embodiments, during the process of forming the dielectric layer, the substrate is heated at a heating temperature of 250°C; and, during the process of forming the dielectric layer, a DC bias voltage is applied to the substrate, and the DC bias voltage is -250V, or, an RF bias power is applied to the substrate, and the RF bias power is 250W.

[0015] In some embodiments, the substrate includes a first surface and a second surface relative to each other, and the bottom electrode is formed on the first surface; before forming the bottom electrode, a bias electrode is set on the second surface, and the bias electrode is used to apply a DC bias voltage to the substrate, or apply a radio frequency bias power to the substrate.

[0016] In some embodiments, before forming the dielectric layer, a magnetic field source is disposed on the second surface.

[0017] On the other hand, a semiconductor device is provided. The semiconductor device is prepared by the preparation method described in any one of the above embodiments.

[0018] On the other hand, a chip is provided, which includes the semiconductor device described in the above embodiment.

[0019] The above-mentioned semiconductor device and chip have the same structure and beneficial technical effects as the preparation methods provided in some of the above-mentioned embodiments, which will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solution in the present application, the following is a brief introduction to the drawings required for use in some embodiments of the present application. Obviously, the drawings described below are only drawings of some embodiments of the present application. For ordinary technicians in this field, other drawings can also be obtained based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams, not the actual size of the product involved in the embodiments of the present application, or the actual process of the method.

[0021] Figure 1 An architectural diagram of a memory chip provided in an embodiment of the present application;

[0022] Figure 2 A structural diagram of a sensor chip provided in an embodiment of the present application;

[0023] Figure 3 A structural diagram of a semiconductor device provided in an embodiment of the present application;

[0024] Figure 4 A diagram showing the steps of setting a substrate for a semiconductor device according to an embodiment of the present application;

[0025] Figure 5 A diagram showing the steps for preparing a bottom electrode provided in an embodiment of the present application;

[0026] Figure 6 A diagram of a step for preparing a dielectric layer provided in an embodiment of the present application;

[0027] Figure 7 A parameter diagram of the operating voltage of the magnetron sputtering device provided in an embodiment of the present application;

[0028] Figure 8 Another step diagram for preparing a dielectric layer provided in an embodiment of the present application;

[0029] Fig. 9 A diagram showing the steps for preparing a top electrode provided in an embodiment of the present application. DETAILED DESCRIPTION

[0030] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments provided by the present application, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present application.

[0031] Unless the context requires otherwise, throughout the specification and claims, the term "comprising" is to be construed in an open, inclusive sense, ie, meaning "including, but not limited to."

[0032] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present application, unless otherwise specified, "plurality" means two or more.

[0033] When describing some embodiments, the term "connection" and its derivative expressions may be used. The term "connection" should be understood in a broad sense. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected through an intermediate medium. For example, when describing some embodiments, the term "connection" may be used to indicate that two or more components are in direct physical or electrical contact with each other.

[0034] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0035] It will be understood that when a layer or an element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present between the layer or element and the other layer or substrate.

[0036] Exemplary embodiments are described herein with reference to cross-sectional views that are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but include deviations in shape due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device, and are not intended to limit the scope of the exemplary embodiments.

[0037] An embodiment of the present application provides a chip, which may be a memory chip or a sensor chip. Figure 1 This is an architectural diagram of the memory chip provided in an embodiment of the present application.

[0038] See also Figure 1 In the case where the chip 1 is a memory chip, the memory chip may be a non-volatile memory. The non-volatile memory includes a plurality of memory cells 100 arranged in an array, and each memory cell 100 includes a ferroelectric capacitor.

[0039] Figure 2 This is a structural diagram of the sensor chip provided in an embodiment of the present application.

[0040] See also Figure 2 In the case where the chip 1 is a sensor chip, the sensor chip may be a micro-electro-mechanical system (MEMS) pressure sensor. The MEMS pressure sensor includes at least one sensor unit, and each sensor unit includes a piezoelectric device.

[0041] The above-mentioned ferroelectric capacitors and piezoelectric devices have the following characteristics: Figure 3 The semiconductor device shown is shown in Figure 3 The semiconductor device 10 includes a substrate 11, and a bottom electrode 12, a dielectric layer 13, and a top electrode 14 stacked on the substrate 11. When the semiconductor device 10 is a ferroelectric capacitor, the material of the dielectric layer 13 includes a ferroelectric material. Alternatively, when the semiconductor device 10 is a piezoelectric device, the material of the dielectric layer 13 includes a piezoelectric material.

[0042] Exemplarily, the semiconductor device 10 further includes an isolation layer 19 , which is disposed between the substrate 11 and the bottom electrode 12 . The isolation layer 19 is used to isolate the bottom electrode 12 from the substrate 11 to prevent alloying of the two and affecting the conductivity of the bottom electrode 12 .

[0043] Exemplarily, the semiconductor device 10 further includes a first adhesion layer 15, which is disposed between the substrate 11 and the bottom electrode 12, and is used to improve the adhesion between the bottom electrode 12 and the substrate 11. When the semiconductor device 10 further includes an isolation layer 19, the first adhesion layer 15 is disposed between the isolation layer 19 and the bottom electrode 12.

[0044] Exemplarily, the semiconductor device 10 further includes a second adhesion layer 18 , which is disposed between the dielectric layer 13 and the top electrode 14 , and is used to improve adhesion between the top electrode 14 and the dielectric layer 13 .

[0045] In the process of preparing the above-mentioned semiconductor device 10, a bottom electrode 12 is first formed on the substrate 11, and then a dielectric layer 13 is formed on the bottom electrode 12. In order to promote the crystal growth of the dielectric material, it is usually necessary to heat the substrate 11 to a high temperature of 500°C to 600°C. Due to the high heating temperature of the substrate 11, the material use of the substrate 11 and the freedom of process selection are limited, which increases the process difficulty of preparing the semiconductor device 10.

[0046] In order to solve the above problems, an embodiment of the present application further provides a method for preparing a semiconductor device. Figures 4 to 9 A diagram of the various steps of preparing a semiconductor device provided in an embodiment of the present application.

[0047] See also Figure 4 , place the substrate 11 in the vacuum chamber 2 of the magnetron sputtering equipment.

[0048] Exemplarily, the substrate 11 is a silicon substrate. In this case, the substrate 11 is first cleaned by Standard Cleaning 1 (SC-1), and the cleaning solution used includes ammonium hydroxide (chemical formula: NH4OH), hydrogen peroxide (chemical formula: H2O2) and water (chemical formula: H2O). Then, the substrate 11 is cleaned by Standard Cleaning 2 (SC-2), and the cleaning solution used includes hydrogen chloride (chemical formula: HCl), hydrogen peroxide (chemical formula: H2O2) and water (chemical formula: H2O). Finally, the substrate 11 is placed in the vacuum chamber 2 of the magnetron sputtering device, for example, the substrate 11 is placed on the carrier 3 in the vacuum chamber 2.

[0049] Exemplarily, the substrate 11 is a quartz substrate. In this case, the substrate 11 is first cleaned with an alkoxy cleaning solution, and then cleaned with a cleaning solution containing sulfuric acid (chemical formula: H2SO4) and hydrogen peroxide (chemical formula: H2O2). After the substrate 11 is dried, it is placed in the vacuum chamber 2 of the magnetron sputtering equipment. For example, the substrate 11 is placed on the carrier 3 in the vacuum chamber 2.

[0050] See also Figure 5 , a bottom electrode 12 is formed on the substrate 11.

[0051] Exemplarily, before forming the bottom electrode 12 on the substrate 11, an isolation layer 19 can be first formed on the substrate 11. The material of the isolation layer 19 may include at least one of silicon dioxide (chemical formula: SiO2), zirconium dioxide (chemical formula: ZrO2), silicon carbide (chemical formula: SiC), strontium ruthenate (chemical formula: SrRuO3), or strontium titanate (chemical formula: SrTiO3) or aluminum oxide (chemical formula: Al2O3). The film thickness of the isolation layer 19 ranges from 0.003μm to 1μm. The isolation layer 19 is used to isolate the bottom electrode 12 from the substrate 11 to prevent the two from alloying and affecting the conductive properties of the bottom electrode 12.

[0052] For example, when the material of the isolation layer 19 includes silicon dioxide, tetraethyl orthosilicate (TEOS) may be used to form a silicon dioxide film layer in a low temperature process.

[0053] Exemplarily, before forming the bottom electrode 12 on the substrate 11, the substrate 11 is heated, the heating temperature of the substrate 11 is in the range of 100°C to 250°C, and then a first adhesion layer 15 is formed on the substrate 11. The first adhesion layer 15 is used to improve the adhesion between the bottom electrode 12 and the substrate 11. The material of the first adhesion layer 15 may include at least one of titanium (chemical formula: Ti), iridium dioxide (chemical formula: IrO2), zirconium dioxide or chromium (chemical formula: Cr). The film thickness of the first adhesion layer 15 is in the range of 3nm to 200nm. Finally, the bottom electrode 12 is formed on the side of the first adhesion layer 15 away from the substrate 11.

[0054] For example, a magnetron sputtering process may be used to form the bottom electrode 12. Figure 5 As shown, the electrode target 16 is placed at the cathode of the magnetron sputtering device, and argon gas, or argon gas and oxygen gas, or argon gas and nitrogen gas are introduced into the vacuum chamber 2 through the gas inlet. A magnetic field is set near the electrode target 16, and the electrons in the magnetic field are acted on by the Lorentz force to make spiral motion, which can increase the number of collisions between electrons and argon molecules, and increase the number of argon ions generated by ionization of argon molecules, thereby increasing the density of plasma in the vacuum chamber 2. Argon ions are accelerated under the action of the electric field and bombard the surface of the electrode target 16, causing the target atoms to fall off and deposit on the substrate 11 to form the bottom electrode 12.

[0055] Furthermore, during the process of forming the bottom electrode 12 by magnetron sputtering, the stage 3 can be rotated to drive the substrate 11 to rotate, which is beneficial to improving the thickness uniformity of the bottom electrode 12 .

[0056] Exemplarily, the material of the bottom electrode 12 may include at least one of platinum (chemical formula: Pt), iridium (chemical formula: Ir), rhenium (chemical formula: Re), or ruthenium (chemical formula: Ru) or titanium nitride (chemical formula: TiN), and the film thickness of the bottom electrode 12 ranges from 10nm to 1500nm.

[0057] In some embodiments, see Figure 5 The substrate 11 includes a first surface 11a and a second surface 11b opposite to each other, and a bottom electrode 12 is formed on the first surface 11a of the substrate 11. Before forming the bottom electrode 12, a bias electrode 4 is also provided on the second surface 11b of the substrate 11. For example, the bias electrode 4 can be formed on the surface of the stage 3, and the bias electrode 4 is used to apply a DC bias voltage or a radio frequency bias power to the substrate 11.

[0058] See also Figure 6 The dielectric layer 13 is formed by sputtering process, and the dielectric layer 13 is located on the side of the bottom electrode 12 away from the substrate 11. In the process of forming the dielectric layer 13, the substrate 11 is heated, the heating temperature ranges from 50°C to 400°C, and a DC bias voltage is applied to the substrate 11 through the anode, and the DC bias voltage varies in the range of -500V to +150V.

[0059] For example, see Figure 7 The cathode of the magnetron sputtering equipment receives the target reference voltage, and the anode receives the DC bias voltage. The DC bias voltage varies in the range of -500V to +150V, ensuring that the DC bias voltage is always greater than the target reference voltage so that the argon ions are accelerated and bombard the target material under the action of the electric field, that is, the value of the target reference voltage should be less than the minimum value of the DC bias voltage -500V.

[0060] Illustratively, during the process of forming the dielectric layer 13, the heating temperature of the substrate 11 is 50° C., 100° C., 225° C., 250° C., 300° C., or 400° C. Illustratively, during the process of forming the dielectric layer 13, the DC bias voltage applied to the substrate 11 is -500V, -250V, -175V, +100V, or +150V.

[0061] For example, when the semiconductor device 10 is a piezoelectric device, the material of the dielectric layer 13 includes a piezoelectric material. During the formation of the dielectric layer 13 , the heating temperature of the substrate 11 is 250° C., and the DC bias voltage applied to the substrate 11 is −250V.

[0062] Alternatively, see Figure 8, a sputtering process is used to form a dielectric layer 13 on the side of the bottom electrode 12 away from the substrate 11. In the process of forming the dielectric layer 13, the substrate 11 is heated, the heating temperature of the substrate 11 ranges from 50°C to 400°C, and a radio frequency bias power is applied to the substrate 11 through the anode, and the radio frequency bias power varies in the range of 50W to 400W.

[0063] Illustratively, during the process of forming the dielectric layer 13, the heating temperature of the substrate 11 is 50° C., 100° C., 225° C., 250° C., 300° C., or 400° C. Illustratively, during the process of forming the dielectric layer 13, the RF bias power applied to the substrate 11 is 50W, 100W, 225W, 250W, or 400W.

[0064] For example, when the semiconductor device 10 is a piezoelectric device, the material of the dielectric layer 13 includes a piezoelectric material. During the formation of the dielectric layer 13 , the heating temperature of the substrate 11 is 250° C., and the RF bias power applied to the substrate 11 is 250 W.

[0065] In the above-mentioned embodiment of the present application, a sputtering process is adopted to form the dielectric layer 13. During the sputtering process, a DC bias voltage is applied to the substrate 11 through the anode, and the DC bias voltage varies in the range of -500V to +150V. It can be understood that when the DC bias voltage is a negative voltage, argon ions in the vacuum chamber 2 can be attracted to bombard the substrate 11. When the DC bias voltage is a positive voltage, electrons in the vacuum chamber 2 can be attracted to bombard the substrate 11, and plasma heat is generated on the surface of the substrate 11. The surface temperature of the substrate 11 can be increased, and the crystal growth of the dielectric material can be promoted. Therefore, even if the heating temperature of the substrate 11 is reduced to the range of 50°C to 400°C, the film quality and characteristics of the dielectric layer 13 can be guaranteed.

[0066] Alternatively, during the sputtering process, an RF bias power is applied to the substrate 11 through the anode, and the RF bias power varies in the range of 50W to 400W. It can be understood that when the RF bias power is negative, argon ions in the vacuum chamber 2 can be attracted to bombard the substrate 11, and when the RF bias power is positive, electrons in the vacuum chamber 2 can be attracted to bombard the substrate 11. The surface temperature of the substrate 11 can also be increased to promote the crystal growth of the dielectric material. Therefore, even if the heating temperature of the substrate 11 is reduced to the range of 50°C to 400°C, the film quality and characteristics of the dielectric layer 13 can be guaranteed.

[0067] Furthermore, compared to heating the substrate 11 with a heater or generating plasma heat when target atoms fall off and bombard the substrate 11, the plasma heat generated by argon ions and electrons bombarding the substrate 11 can be controlled by controlling the change of the DC bias voltage or the RF bias power. This method is easy to control and has a good heating effect on the substrate 11.

[0068] In addition, since the heating temperature of the substrate 11 is reduced during the process of forming the dielectric layer 13, the bottom electrode 12 is not easy to alloy with the substrate 11. Therefore, there is no need to form an isolation layer 19 on the substrate 11 before forming the first adhesion layer 15. The isolation layer 19 is not set between the first adhesion layer 15 and the substrate 11, that is, the first adhesion layer 15 can be in direct contact with the substrate 11, which can simplify the process and reduce the process cost.

[0069] For example, Figure 6 and Figure 8 As shown, a dielectric target 17 is placed at the cathode of a magnetron sputtering device, and argon gas, or argon gas and oxygen gas, or argon gas and nitrogen gas are introduced into the vacuum chamber 2 through the gas inlet. The composition of the gas introduced depends on the purpose of the dielectric layer 13 to be formed. Electrons are subjected to the Lorentz force in the magnetic field and perform spiral motion, which can increase the number of collisions between electrons and argon molecules, and increase the number of argon ions generated by ionization of argon molecules, thereby increasing the density of plasma in the vacuum chamber 2. Argon ions are accelerated and bombarded on the surface of the dielectric target 17 under the action of the electric field, causing the target atoms to fall off and deposit on the substrate 11, forming a dielectric film on the entire surface. Then, a photolithography process is used to pattern the dielectric film to form a dielectric layer 13.

[0070] In the above-mentioned embodiments of the present application, in the process of forming the dielectric thin film, the heating temperature of the substrate 11 can be reduced by applying a DC bias voltage or a radio frequency bias power to the substrate 11. After the film is formed, there is no need to perform high-temperature treatment on the substrate 11, so that the temperature of the substrate 11 can adapt to the temperature of the photolithography process. Therefore, after the dielectric thin film is formed, the photolithography process can be used to pattern the dielectric thin film to form a dielectric layer 13.

[0071] Illustratively, during the process of forming the dielectric layer 13 , the substrate 11 is heated at a temperature ranging from 100° C. to 400° C. When the heating temperature of the substrate 11 is lowered, the film quality and characteristics of the dielectric layer 13 can also be guaranteed.

[0072] Exemplarily, the film thickness of the dielectric layer 13 is different according to different uses. In the case where the semiconductor device 10 is a piezoelectric device, the material of the dielectric layer 13 includes a piezoelectric material, for example, the piezoelectric material may include at least one of lead zirconate titanate (PZT: PbTiO3 / PbZrO3) or lead niobate titanate (PNZT: PbTiO3 / PbZrO3 / PbNbO3), and the film thickness of the dielectric layer 13 ranges from 0.001 μm to 400 μm.

[0073] In some embodiments, before forming the dielectric layer 13 , the substrate 11 is preheated, and the preheating temperature of the substrate 11 is in a range of 100° C. to 250° C.

[0074] In the above-mentioned embodiments of the present application, since a DC bias voltage or a radio frequency bias power is applied to the substrate 11 during the process of forming the dielectric layer 13, and the DC bias voltage or the radio frequency bias power is dynamically switched between positive and negative values, argon ions and electrons in the vacuum chamber 2 can be attracted to bombard the substrate 11, thereby increasing the surface temperature of the substrate 11 and promoting the crystal growth of the dielectric material. Therefore, the preheating temperature of the substrate 11 before film formation of the dielectric layer 13 can be reduced, and the film quality and characteristics of the dielectric layer 13 can also be guaranteed.

[0075] Exemplarily, “preheating the substrate 11 ” may refer to heating the substrate 11 during the process of forming the first adhesion layer 15 and the bottom electrode 12 , and the heating temperature of the substrate 11 is in the range of 100 to 250° C.

[0076] In some embodiments, see Figure 6 and Figure 8 Before forming the dielectric layer 13, a magnetic field source may be provided on the second surface 11b of the substrate 11. By providing a magnetic field near the substrate 11, the number of collisions between electrons and argon molecules near the substrate 11 may be increased, the number of argon ions may be increased, and the density of plasma near the substrate 11 may be increased.

[0077] Based on this, in the process of forming the dielectric layer 13, by applying a DC bias voltage or a radio frequency bias power to the substrate 11, the number of argon ions and electrons bombarding the substrate 11 can be increased, the surface temperature of the substrate 11 can be further increased, and the crystal growth of the dielectric material can be promoted, which is beneficial to reducing the heating temperature of the substrate 11 and ensuring the film quality and characteristics of the dielectric layer 13.

[0078] See also Fig. 9 , a top electrode 14 is formed on a side of the dielectric layer 13 away from the substrate 11 , thereby completing the preparation of the semiconductor device 10 .

[0079] Exemplarily, before forming the top electrode 14 on the substrate 11, a second adhesion layer 18 is formed on the substrate 11. The second adhesion layer 18 is used to improve the adhesion between the top electrode 14 and the dielectric layer 13. The material of the second adhesion layer 18 may include at least one of titanium, iridium dioxide, zirconium dioxide or chromium. The film thickness of the second adhesion layer 18 ranges from 3nm to 200nm.

[0080] For example, a magnetron sputtering process may be used to form the top electrode 14. Fig. 9 As shown, the electrode target 16 is placed at the cathode of the magnetron sputtering device, and argon gas, or argon gas and oxygen gas, or argon gas and nitrogen gas are introduced into the vacuum chamber 2 through the gas inlet. A magnetic field is set near the electrode target 16, and the electrons in the magnetic field are subjected to the Lorentz force to make spiral motion, which can increase the number of collisions between the electrons and the argon molecules, and increase the number of argon ions generated by the ionization of the argon molecules, thereby increasing the density of the plasma in the vacuum chamber 2. Under the action of the electric field, the argon ions are accelerated and bombarded on the surface of the electrode target 16, causing the target atoms to fall off and deposit on the substrate 11 to form the top electrode 14.

[0081] Furthermore, during the process of forming the top electrode 14 by magnetron sputtering, the stage 3 can be rotated to drive the substrate 11 to rotate, which is beneficial to improving the thickness uniformity of the top electrode 14 .

[0082] Exemplarily, the material of the top electrode 14 may include at least one of platinum, iridium, rhenium or ruthenium, and the film thickness of the top electrode 14 is in the range of 10 nm to 1500 nm.

[0083] In order to verify the above embodiment, the inventors of the present application also conducted the following comparative experiments:

[0084] Comparative example: During the process of forming the dielectric layer, the substrate is heated at a temperature of 600° C., and no DC bias voltage is applied to the substrate.

[0085] Embodiment: During the process of forming the dielectric layer 13 , the substrate 11 is heated at a temperature of 250° C., and a DC bias voltage of −250V is applied to the substrate 11 .

[0086] The comparison between the comparative example and the embodiment can be achieved by obtaining the hysteresis loop (PE loop) of the dielectric layer 13, or observing the cross section of the dielectric layer 13 using a scanning electron microscope (SEM), or obtaining the XRD curve of the dielectric layer 13 using an X-ray diffractometer.

[0087] The results show that the film quality of the dielectric layer 13 in the comparative example and the embodiment is similar. It can be seen that by applying a DC bias voltage of -250V to the substrate 11, even if the substrate 11 is not heated to 600°C, the same crystal growth quality can be obtained by reducing the heating temperature of the substrate 11 to 250°C.

[0088] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that a person skilled in the art can think of within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A method for preparing a semiconductor device, characterized in that: include: forming a bottom electrode on the substrate; forming a dielectric layer by a sputtering process, wherein the dielectric layer is located on a side of the bottom electrode away from the substrate; forming a top electrode, wherein the top electrode is located on a side of the dielectric layer away from the substrate; Wherein, in the process of forming the dielectric layer, the substrate is heated, and the heating temperature ranges from 50° C. to 400° C.; Furthermore, during the process of forming the dielectric layer, a DC bias voltage is applied to the substrate, and the DC bias voltage varies in the range of -500V to +150V, or a radio frequency bias power is applied to the substrate, and the radio frequency bias power varies in the range of 50W to 400W.

2. The preparation method according to claim 1, characterized in that: During the process of forming the dielectric layer, the substrate is heated at a temperature ranging from 100°C to 400°C.

3. The preparation method according to claim 1, characterized in that: Before forming the dielectric layer, the substrate is preheated at a temperature ranging from 100° C. to 250° C.

4. The preparation method according to claim 3, characterized in that: Before forming the bottom electrode, forming an adhesion layer, wherein the adhesion layer is in contact with the surface of the substrate; The bottom electrode is formed, and the bottom electrode is located on a side of the adhesion layer away from the substrate.

5. The preparation method according to claim 4, characterized in that: In the process of forming the adhesion layer and the bottom electrode, the substrate is heated at a heating temperature ranging from 100° C. to 250° C.

6. The preparation method according to claim 1, characterized in that: forming a dielectric film by a sputtering process, wherein the dielectric film is located on a side of the bottom electrode away from the substrate; The dielectric film is etched by photolithography to form the dielectric layer.

7. The preparation method according to claim 1, characterized in that: The thickness of the dielectric layer ranges from 0.001 μm to 400 μm.

8. The preparation method according to claim 1, characterized in that: During the process of forming the dielectric layer, heating the substrate at a heating temperature of 250° C. Furthermore, during the process of forming the dielectric layer, a DC bias voltage is applied to the substrate, and the DC bias voltage is -250V, or a radio frequency bias power is applied to the substrate, and the radio frequency bias power is 250W.

9. The preparation method according to claim 1, characterized in that: The substrate comprises a first surface and a second surface opposite to each other, and the bottom electrode is formed on the first surface; Before forming the bottom electrode, a bias electrode is arranged on the second surface, and the bias electrode is used to apply a DC bias voltage to the substrate, or to apply a radio frequency bias power to the substrate.

10. The preparation method according to claim 9, characterized in that: Before forming the dielectric layer, a magnetic field source is disposed on the second surface.

11. A semiconductor device, characterized in that: The method is prepared according to any one of claims 1 to 10.

12. A chip, characterized in that: Comprising the semiconductor device as claimed in claim 11.

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