Implementation method of serial communication interface, equipment communication method and master control device

Abstract

The invention relates to the technical field of communication, and discloses an implementation method of a serial communication interface, an equipment communication method and a master control device, and the implementation method of the serial communication interface comprises the steps: configuring a timer in a master control module to be used for providing a clock signal of the serial communication interface; at least one direct storage access channel of the main control module is configured to be associated with the timer and configured with address mapping of the direct storage access channel so as to provide a data transmission channel of the serial communication interface; and configuring a first signal port of the main control module to be used for providing a chip selection signal of the serial communication interface. According to the implementation method of the serial communication interface, through existing hardware resources and software configuration of the main control module, software simulation of the non-blocking serial communication interface can be achieved on the premise that an external expansion communication interface chip does not need to be additionally added, and the problem that an original main control peripheral interface is insufficient can be solved.

Description

Technical Field

[0001] The present application relates to the technical field of communication interfaces, and in particular to a method for implementing a serial communication interface, a device communication method, and a main control device. Background Art

[0002] For scenarios where the main control needs to communicate with various peripheral devices in a serial manner, the SPI interface (Serial Peripheral Interface) is often used to achieve this. However, since the number of SPI interfaces on the main control is fixed and limited, when there are not enough SPI interfaces, the traditional approach is generally to reselect a main control with a sufficient number of SPI peripherals, or to redesign the hardware or use the GPIO (General-purpose input / output) interface to directly simulate the SPI interface to support the added functional modules. However, redesigning the hardware will increase costs and extend the R&D cycle, and the method of using the GPIO interface to directly simulate the SPI interface is prone to cause certain program blockages during data transmission, affecting the real-time performance of the system, and it is difficult to achieve continuous high-speed SPI communication. Summary of the invention

[0003] In view of this, the embodiments of the present application provide a method for implementing a serial communication interface, a device communication method, and a main control device, which can realize the expansion of a non-blocking high-speed serial communication interface.

[0004] In a first aspect, an embodiment of the present application provides a method for implementing a serial communication interface, including:

[0005] Configuring a timer in the main control module to provide a clock signal for the serial communication interface;

[0006] Configuring the first signal port of the main control module to provide a chip select signal of the serial communication interface;

[0007] At least one direct storage access channel of the main control module is configured to be associated with the timer and an address mapping of the direct storage access channel is configured to provide a data transmission channel of the serial communication interface.

[0008] In a first possible embodiment of the first aspect, configuring a timer in the main control module to provide a clock signal for the serial communication interface includes:

[0009] The working mode of the timer in the main control module is configured as a pulse width modulation output mode, and the clock frequency of the timer is configured as the working frequency of the serial communication interface, so that the timer outputs a clock signal for synchronous communication.

[0010] In a second possible embodiment of the first aspect, the method further includes:

[0011] Determining the number of direct storage access channels associated with the timer in the main control module according to the line type of the serial communication interface;

[0012] If the serial communication interface is a four-wire SPI interface, two direct storage access channels are configured; if the serial communication interface is a three-wire SPI interface, one direct storage access channel is configured.

[0013] In a third possible embodiment of the first aspect, if the serial communication interface is a four-wire SPI interface, configuring at least one direct storage access channel of the main control module to be associated with the timer and configuring an address mapping of the direct storage access channel to provide a data transmission channel of the serial communication interface includes:

[0014] configuring both of the two direct storage access channels of the main control module to be associated with the timer;

[0015] The memory address of the first direct storage access channel is configured to point to the sending buffer address and the peripheral address of the first direct storage access channel is associated with the second signal port of the main control module; the second signal port is used to provide the master device output and slave device input signals of the four-wire SPI interface;

[0016] The memory address of the second direct storage access channel is configured to point to the receiving buffer address and the peripheral address of the second direct storage access channel is associated with the third signal port of the main control module; the third signal port is configured as the master device input and slave device output signal of the four-wire SPI interface.

[0017] In a fourth possible embodiment of the first aspect, the method further includes:

[0018] The number of signal ports that need to be configured to provide chip select signals for each of the serial communication interfaces is determined according to the number of the multiple external devices that need to be connected; wherein one signal port is used to enable one of the external devices.

[0019] In a fifth possible embodiment of the first aspect, if the serial communication interface is a three-wire SPI interface, configuring a direct storage access channel associated with the timer in the main control module and an address mapping of the direct storage access channel to provide a data transmission channel of the serial communication interface includes:

[0020] configuring a single direct storage access channel associated with the timer in the main control module;

[0021] The memory address of the single direct storage access channel is configured to point to the send buffer address when data is sent, and to point to the receive buffer address when data is received;

[0022] The peripheral address of the single direct storage access channel is associated with the fourth signal port of the main control module; the fourth signal port is used to provide input and output bidirectional signals of the three-wire SPI interface.

[0023] In a sixth possible embodiment of the first aspect, when configuring the direct storage access memory associated with the timer in the main control module, the method further includes:

[0024] The data transmission length of the direct storage access channel is determined according to the data to be exchanged transmitted by the serial communication interface.

[0025] In a second aspect, an embodiment of the present application provides a device communication method, which is applied to a main control module, wherein the main control module simulates a serial communication interface through the above-mentioned implementation method of the serial communication interface, and the serial communication interface is used to connect an external device; the device communication method includes:

[0026] When data needs to be sent and / or received, enabling a first signal port for connecting a chip select signal of the external device;

[0027] A timer is started to generate a clock signal of the serial communication interface, and data transmission between the main control module and the external device is realized through each of the direct storage access channels.

[0028] In a third aspect, an embodiment of the present application provides a main control device, wherein the main control device is provided with a plurality of signal ports, a timer, a direct storage access channel and a memory;

[0029] The timer is configured to provide a clock signal for the serial communication interface;

[0030] At least one of the direct storage access channels is configured to be associated with the timer and to be configured for address mapping, so as to provide a data transmission channel of the serial communication interface;

[0031] The first signal port is configured to provide a chip select signal of the serial communication interface.

[0032] In a first possible embodiment of the third aspect, the operating mode of the timer is configured as a pulse width modulation output mode, and the clock frequency of the timer is configured as an operating frequency of the serial communication interface, so that the timer outputs a clock signal for synchronous communication.

[0033] In a second possible embodiment of the third aspect, the serial communication interface is a four-wire SPI interface, and both of the two direct storage access channels are configured to be associated with the timer;

[0034] The memory address of the first direct storage access channel is configured to point to the send buffer address and the peripheral address of the first direct storage access channel is associated with the second signal port of the master control device; the second signal port is used to provide the master device output and slave device input signals of the four-wire SPI interface;

[0035] The memory address of the second direct storage access channel is configured to point to the receiving buffer address and the peripheral address of the second direct storage access channel is associated with the third signal port of the main control device; the third signal port is used to provide the master device input and slave device output signals of the four-wire SPI interface.

[0036] In a third possible embodiment of the third aspect, the main control device is used to determine the number of signal ports that need to be configured to provide chip select signals for each of the serial communication interfaces according to the number of multiple external devices that need to be connected; wherein one of the signal ports is used to enable one of the external devices.

[0037] In a fourth possible embodiment of the third aspect, the serial communication interface is a three-wire SPI interface, and a single direct storage access channel is configured to be associated with the timer;

[0038] The memory address of the single direct storage access channel is configured to point to the send buffer address when data is sent, and to point to the receive buffer address when data is received;

[0039] The peripheral address of the single direct storage access channel is associated with the fourth signal port of the main control device; the fourth signal port is used to provide input and output bidirectional signals of the three-wire SPI interface.

[0040] In a fifth possible embodiment of the third aspect, the main control device is further used to determine the data transmission length of the corresponding direct storage access channel according to the data to be exchanged transmitted by the serial communication interface as needed.

[0041] The embodiments of the present application have the following beneficial effects:

[0042] The implementation method of the serial communication interface of the embodiment of the present application is to configure the timer in the main control module to provide the clock signal of the serial communication interface; configure the direct storage access channel associated with the timer in the main control module, and configure the address mapping of the direct storage access channel to provide the data transmission channel of the serial communication interface; and configure the first signal port of the main control module to provide the chip select signal of the serial communication interface. Based on the above scheme, the implementation method of the serial communication interface can realize the main control board molding, and when the functional module needs to be expanded, there is no need to modify the corresponding main control hardware. It only needs to configure the main control timer, direct storage access channel (DMA channel) and signal port, etc., to complete the corresponding serial communication interface simulation development requirements, which can not only save hardware costs and shorten the development cycle, but also the extended serial communication interface is close to the performance of the serial communication interface inside the main control module, and a non-blocking high-speed serial communication interface can be realized. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0044] Figure 1 A schematic diagram of a process flow of a method for implementing a serial communication interface according to an embodiment of the present application is shown;

[0045] Figure 2 A first structural schematic diagram of a simulated serial communication interface according to an embodiment of the present application is shown;

[0046] Figure 3 A second structural schematic diagram of the simulated serial communication interface according to an embodiment of the present application is shown;

[0047] Figure 4 A third structural schematic diagram of the simulated serial communication interface according to an embodiment of the present application is shown;

[0048] Figure 5 A fourth structural schematic diagram of a simulated serial communication interface according to an embodiment of the present application is shown;

[0049] Figure 6 A schematic diagram of a process flow of a device communication method according to an embodiment of the present application is shown;

[0050] Figure 7 A structural schematic diagram of a main control device according to an embodiment of the present application is shown. DETAILED DESCRIPTION

[0051] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments.

[0052] The components of the embodiments of the present application generally described and shown in the drawings herein may be arranged and designed in various configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the application claimed for protection, but merely represents the selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without making creative work belong to the scope of protection of the present application.

[0053] Hereinafter, the terms "including", "having" and their cognates that can be used in various embodiments of the present application are intended only to indicate specific features, numbers, steps, operations, elements, components or a combination of the foregoing items, and should not be understood as first excluding the existence of one or more other features, numbers, steps, operations, elements, components or a combination of the foregoing items or increasing the possibility of one or more features, numbers, steps, operations, elements, components or a combination of the foregoing items. In addition, the terms "first", "second", "third" and the like are only used to distinguish descriptions and cannot be understood as indicating or implying relative importance.

[0054] Unless otherwise defined, all terms (including technical terms and scientific terms) used herein have the same meanings as those generally understood by those skilled in the art to which the various embodiments of the present application belong. The terms (such as those defined in generally used dictionaries) will be interpreted as having the same meanings as the contextual meanings in the relevant technical field and will not be interpreted as having idealized meanings or overly formal meanings unless clearly defined in the various embodiments of the present application.

[0055] In conjunction with the accompanying drawings, some embodiments of the present application are described in detail below. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.

[0056] Considering that the traditional solution has many shortcomings such as the simulated interface cannot meet the clock frequency or there is blocking when solving the problem of insufficient communication interfaces such as SPI interface of the main control board, in order to solve this problem, the present application provides a method for simulating a serial communication interface, by configuring the timer, direct memory access (DMA) channel and signal port in the main control module accordingly, without adding additional serial peripheral expansion chips or replacing the main control board, the existing resources of the main control module can be used to realize the software simulation of the serial communication interface, and the serial communication interface simulated by the method can also realize non-blocking high-speed serial communication. It can be understood that the method of the present application will be mainly explained by taking the SPI interface as an example, but the technical idea of ​​realizing non-blocking high-speed communication by using the timer, DMA channel, etc. in the main control can be extended to other communication interfaces, especially serial communication interfaces that require higher clock frequencies and support high-speed communication.

[0057] The implementation method of the serial communication interface of the present application is described below. Here, the SPI interface is taken as an example to describe the implementation method of the serial communication interface.

[0058] The SPI interface is a master-slave interface that supports synchronization and full-duplex. There are two types of SPI bus lines: a three-wire SPI interface and a four-wire SPI interface.

[0059] (1) The three-wire SPI interface includes: CLK (clock signal) line, CS (chip select signal) line and DIO (bidirectional data) line. The three-wire SPI interface is suitable for simplex or half-duplex communication, that is, the master device can only send data or receive data at the same time.

[0060] (2) The four-wire SPI interface includes: CLK line, CS line, MOSI data line and MISO data line, where MOSI stands for Master Output Slave Input, and MISO stands for Master Input Slave Output. The four-wire SPI interface supports full-duplex communication, that is, the master and slave devices can send and receive data at the same time.

[0061] Figure 1 A flow chart of a method for implementing a serial communication interface according to an embodiment of the present application is shown.

[0062] Exemplarily, the implementation method of the serial communication interface includes the following steps:

[0063] S110, configuring a timer in the main control module to provide a clock signal for the serial communication interface.

[0064] In this application, the main control module can be regarded as a main control board, which usually includes a main control chip (such as a central processing unit CPU, a digital signal processor DSP, etc.) and related peripherals connected to the CPU for supporting the basic functions of the main control. For example, the peripherals may include, but are not limited to, various hardware resources such as timers, A / D converters, memories, I2C buses, UART interfaces, SPI interfaces, ROM memories, DMA (direct memory access) controllers, etc. Usually, different chip manufacturers have different peripheral configurations. It can be understood that the above-mentioned peripherals refer to peripheral hardware devices connected to the main control chip in the main control module.

[0065] Since the serial communication interface that needs software simulation, such as the SPI interface, includes a CLK clock signal for synchronous communication, the timer in the main control module is used to simulate the clock signal in this embodiment. In order to enable the timer to achieve a clock signal that meets the requirements, its configuration parameters mainly include setting the working mode, working frequency and cycle, etc.

[0066] In one embodiment, the working mode of the timer can be configured as a pulse width modulation (PWM) output mode, and the signal frequency of the timer is set to the frequency required when the serial communication interface works, so that the timer outputs a PWM signal, and the PWM signal is used to provide a clock signal of the serial communication interface, that is, a timing level signal for data transmission. Among them, PWM is a technology that adjusts the output power by controlling the duty cycle of the pulse waveform.

[0067] For example, assuming the SPI clock frequency is 10 MHz, the timer frequency should be set to 10 MHz, and correspondingly, the timer period is 100 ns.

[0068] Optionally, the configuration of the above-mentioned PWM output mode includes two types, one for generating a rising edge triggered PWM signal, or one for generating a falling edge triggered PWM signal, which can be specifically configured according to actual needs and is not limited here.

[0069] S120, configuring the first signal port of the main control module to provide a chip select signal of the serial communication interface.

[0070] Exemplarily, the first signal port of the main control module is configured to provide a chip select signal of the SPI interface. For example, the first signal port can be a general purpose input and output port, ie, a GPIO port, in the main control module.

[0071] S130: Configure at least one direct storage access channel of the main control module to be associated with the timer and configure address mapping of the direct storage access channel to provide a data transmission channel of the serial communication interface.

[0072] The DMA mechanism is a mechanism that can work independently of the main control CPU, which allows the external device connected to the main control module and the memory to directly transfer data through a channel. In this embodiment, at least one DMA channel is allocated to achieve efficient data transmission between the main control module (as a master device) and the connected peripheral device (as a slave device).

[0073] It can be understood that the number of direct memory access channels associated with the timer in the main control module can be determined according to the wire type of the serial communication interface, that is, for SPI interfaces of different wire types, different numbers of DMA channels can be flexibly configured due to different data transmission principles. For example, if it is a four-wire SPI interface, two direct memory access channels need to be configured; if it is a three-wire SPI interface, one direct memory access channel can be configured.

[0074] Exemplarily, the configuration of a DMA channel includes setting its memory address and peripheral address, and further, may include configuring the transmission direction of the DMA channel, etc.

[0075] Among them, the memory address of the DMA channel is used to point to the storage location of the interactive data transmitted by the DMA channel in the memory. For example, it can include a data receiving buffer and a data sending buffer, etc. The memory address needs to be pre-set before the DMA channel transmission so that the DMA controller can write or read interactive data into the memory. Among them, the peripheral address of the DMA channel is used to point to the address of the signal port of the external device connected to the DMA channel, that is, the DMA controller can send data to the corresponding connected external device or receive data sent by the external device through the address of the signal port.

[0076] It can be understood that when the memory address and peripheral address of the DMA channel are set, the DMA controller can directly transfer data between the master device (here refers to the main control module) and the slave device (here refers to the connected external device) without the intervention of the CPU, thereby improving the speed and efficiency of data transmission, and then realizing non-blocking continuous high-speed SPI communication.

[0077] The transmission direction of the DMA channel includes transmission from the memory to the external device and transmission from the external device to the memory. It can be understood that when there is only one DMA channel, its transmission direction needs to be dynamically adjusted according to the sending or receiving of data.

[0078] Taking the four-wire SPI interface as an example, in one implementation, the two DMA channels of the main control module are configured to be associated with the timer configured above for providing the clock signal. The above association can be understood as, when the timer generates a corresponding level signal, the two DMA channels can perform corresponding operations. In addition, the two DMA channels need to be configured to map internal and external addresses so that they can support the functions of the MOSI and MISO data lines in the SPI interface.

[0079] Exemplarily, the peripheral address of the first DMA channel is associated with the second signal port of the main control module, and the memory address of the first DMA channel is configured to point to the address of the sending buffer area, wherein the sending buffer area is used to temporarily store the output data of the master device. And, the peripheral address of the second DMA channel is associated with the third signal port of the main control chip, and the memory address of the second DMA channel is configured to point to the address of the receiving buffer area, wherein the receiving buffer area is used to temporarily store the output data of the slave device.

[0080] It can be understood that the first DMA channel is used to transmit data output from the master device and input from the slave device, and correspondingly, the second signal port is used to connect to the MOSI pin of the slave device. The second DMA channel is used to transmit data input from the master device and output from the slave device, and correspondingly, the third signal port is used to connect to the MISO pin of the slave device.

[0081] For example, in one embodiment, for the implementation of a four-wire SPI interface, Figure 2 As shown, a timer of the main control module is set to PWM mode to provide a clock signal for the SPI interface; the first signal port (such as GPIO1) of the main control module is used to provide a chip select signal for the SPI interface; the peripheral address of the first DMA channel is set to the address of the second signal port (such as GPIO2) of the main control module, and the memory address of the first DMA channel is set to point to the address of the sending buffer area divided in the memory; and the peripheral address of the second DMA channel is set to the address of the third signal port (such as GPIO3) of the main control module, and the memory address of the second DMA channel is set to point to the address of the receiving buffer area divided in the memory.

[0082] It can be understood that for the software simulation of the four-wire SPI interface, the method of bidirectionally transmitting data through the first DMA channel and the second DMA channel avoids the participation of the CPU, thereby greatly improving the communication efficiency.

[0083] Taking the three-wire SPI interface as an example, in one implementation, Figure 3As shown, the configuration method of the clock signal and the chip select signal remains unchanged, the main difference is that a DMA channel of the main control module is configured to be associated with the timer configured above for providing the clock signal; in addition, it is also necessary to configure the internal and external address mapping of this DMA channel so that it can support the function of the DIO data line in the three-wire SPI interface. Furthermore, the peripheral address of this DMA channel is associated with the fourth signal port of the main control module. It can be understood that the fourth signal port is used to connect the DIO pin of the slave device.

[0084] It is worth noting that since the three-wire SPI interface has only one DMA channel, if only unidirectional data transmission is performed, it is only necessary to set the transmission direction and a corresponding data buffer area and perform similar internal and external address mapping as mentioned above; if bidirectional data transmission is required, one or two data buffer areas can be set and the transmission direction can be dynamically adjusted when transmitting data.

[0085] Among them, when only one data buffer is set in the memory, if new data is input each time, the previously stored data will be overwritten. Conversely, if two data buffers are set in the memory, they can be used for data sending buffer and data receiving buffer respectively. Exemplarily, when the master device needs to send data, the memory address of the DMA channel is configured to point to the send buffer address, and, when receiving data, the memory address of the DMA channel is configured to point to the receive buffer address.

[0086] As an optional solution, the implementation method of the serial communication interface further includes: determining the data transmission length of the direct storage access channel according to the data to be exchanged transmitted by the serial communication interface as needed.

[0087] The data to be exchanged may include input data of the slave device and output data of the master device. Exemplarily, the input data of the slave device and / or the output data of the master device to be transmitted may be byte-divided and bit-decomposed to obtain the number of bits of the data to be transmitted, thereby determining the data transmission length of the corresponding DMA channel.

[0088] For example, for the scenario of sending data, the data to be sent by the communication SPI interface is obtained, and each byte of data is disassembled according to the bit, the number of bits of the data to be transmitted is obtained and saved in the data transmission buffer. For the scenario of receiving data, the number of bytes of data to be received by the communication SPI interface is obtained, and the number of bytes received by the DMA channel is the number of bytes of the received data multiplied by eight, that is, the corresponding number of bits.

[0089] It can be understood that SPI communication is a point-to-point communication method, in which one master device can be connected to multiple slave devices. As an optional solution, when the main control module needs to perform SPI communication with multiple slave devices, two methods can be used to achieve it.

[0090] Taking SPI communication as an example, in one solution, the main control module as the master device can implement multiple SPI interfaces according to the above implementation method to respectively connect to each slave device, such as Figure 4 As shown, 3 signal ports (GPIO1-GPIO3) and 1 timer (output PWM1 signal) are used as a group to simulate an SPI interface; when the number of slave devices is n, n PWM signals will be output accordingly. It can be understood that under this connection mode, each slave device can independently communicate with the master module in full-duplex.

[0091] In another solution, when the master device is connected to each slave device, the other three signal lines except the chip select signal are shared. When one of the slave devices wants to communicate with the master device, the master device can select the slave device through the signal port associated with its corresponding chip select signal and time-share the other three signal lines of the SPI interface. Figure 5 As shown, two signal ports (GPIO2-GPIO3) and one timer (outputting PWM1 signal) are shared, and the signal ports used to provide chip select signals are equal to the number of slave devices, such as Figure 5 GPIO1, GPIO4, etc. shown.

[0092] The implementation method of the serial communication interface of the present application utilizes existing resources such as timers, DMA controllers and memory in the main control module, and combines operations such as setting the timer to PWM output mode, setting the corresponding number of DMA channels and performing address mapping, and setting the corresponding data buffer area. In particular, for a four-wire SPI interface, serial communication between master and slave devices is performed through two DMA channels, so that the performance of the extended SPI interface is close to that of the internal SPI peripheral interface in the main control module, and non-blocking full-duplex SPI high-speed communication can be achieved without affecting the execution efficiency of the CPU and reducing the defects of the system real-time performance.

[0093] It is understandable that when the GPIO port, timer and other resources of the main control module are sufficient, the functional modules can be easily expanded. The implementation method of the serial communication interface of the present application can be specifically applied to scenarios such as photovoltaic energy storage systems that require communication and interaction with more functional modules.

[0094] For example, for a photovoltaic energy storage system, it consists of three main system modules: energy management system (EMS), battery management system (BMS) and energy storage alternator system (PCS). The EMS system needs to communicate and integrate various functional modules. For example, the EMS needs to communicate with the BMS system, PCS system, load management module, grid interface module, etc. to monitor and manage the operating status of the system, optimize energy storage and distribution, etc. When the number of existing SPI interfaces of the main control module in the EMS system is insufficient, the SPI interface can be expanded through the above-mentioned software simulation method, which can avoid the re-selection or modification of the hardware main control, save hardware costs and shorten the development cycle.

[0095] Figure 6 A flow chart of a device communication method according to an embodiment of the present application is shown. Exemplarily, the device communication method is applied to a main control module, and the main control module simulates a serial communication interface through the implementation method of the serial communication interface according to the above embodiment, wherein the serial communication interface is used to connect an external device; the device communication method includes:

[0096] S210, when it is necessary to send data and / or receive data, enable a first signal port for connecting a chip select signal of an external device.

[0097] For example, by setting the GPIO port associated with the chip select signal to a low level or high level state, it means that the chip select signal is valid, thereby allowing the connected external device to communicate with the main control module.

[0098] S220, start a timer to generate a clock signal of the serial communication interface.

[0099] S230, realizing data transmission between the main control module and the external device through each direct storage access channel.

[0100] Exemplarily, after the timer of the main control module is configured with the above working mode and signal frequency, the timer is started. At this time, the main control module will automatically execute the timing level of the simulated SPI interface and use the corresponding DMA channel to realize communication with the external device.

[0101] When using the corresponding DMA channel to achieve communication with the external device, in one embodiment, if data needs to be sent, the main control module stores the data to be sent in a sending buffer area, and then uses the first DMA channel whose memory address is configured to point to the sending buffer area address to send the data to the external device; if data needs to be received, the main control module uses the second DMA channel whose memory address is configured to point to the receiving buffer area address to receive the data from the external device, and stores it in the receiving buffer area.

[0102] It can be understood that the device communication method of this embodiment is implemented based on the implementation method of the serial communication interface of the above embodiment. Accordingly, the optional items in the above embodiment are also applicable to this embodiment and will not be described repeatedly here.

[0103] In addition, the present application also provides a main control device. For example, the main control device can be a main control chip of an energy management system, a main control-level device of a computer monitoring system, a main control machine of a communication signal system, and a main controller of an automation control system, etc., which is not limited here.

[0104] For example, Figure 7 As shown, the main control device is provided with a plurality of signal ports, a timer, a direct storage access channel and a memory; wherein the timer is configured to provide a clock signal for a serial communication interface; at least one DMA channel is configured to be associated with the timer and to perform address mapping configuration to provide a data transmission channel for the serial communication interface; and the first signal port is configured to provide a chip select signal for the serial communication interface.

[0105] In some embodiments, the operating mode of the timer is configured as a pulse width modulation output mode, and the clock frequency of the timer is configured as the operating frequency of the serial communication interface, so that the timer outputs a clock signal for synchronous communication.

[0106] In some embodiments, the number of direct storage access channels associated with the timer in the main control device can be determined according to the wire type of the serial communication interface; for example, the serial communication interface can be a four-wire SPI interface or a three-wire SPI interface. Further optionally, the data transmission length of the corresponding direct storage access channel can be determined according to the data to be transmitted by the serial communication interface as needed.

[0107] In some embodiments, when the serial communication interface is a four-wire SPI interface, the two DMA channels of the master control device are configured to be associated with a timer for generating a CLK signal; wherein the peripheral address of the first DMA channel is configured to be associated with a second signal port for generating a MOSI signal and the memory address of the first DMA channel is configured to point to a data sending buffer; the peripheral address of the second DMA channel is configured to be associated with a third signal port for generating a MISO signal and the memory address of the second DMA channel is configured to point to a data receiving buffer.

[0108] As an optional solution, if multiple external devices need to be connected, the number of signal ports that need to be configured to provide chip select signals for each serial communication interface is determined according to the number of external devices that need to be connected; wherein one signal port is used to enable one external device, thus forming a one-to-one correspondence.

[0109] In some embodiments, when the serial communication interface is a three-wire SPI interface, the single DMA channel of the master control device is configured to be associated with a timer for generating a CLK signal; wherein the memory address of the single DMA channel is configured to point to a sending buffer address when data is sent, and to point to a receiving buffer address when data is received, i.e., dynamically adjusted; and the peripheral address of the single direct storage access channel is configured to be associated with a fourth signal port of the master control device; wherein the fourth signal port is used to provide input and output bidirectional signals of the three-wire SPI interface.

[0110] It can be understood that the options for the implementation method of the serial communication interface in the above embodiment are also applicable to this embodiment and will not be described repeatedly here.

[0111] In several embodiments provided in the present application, it should be understood that the disclosed devices and methods can also be implemented in other ways. The device embodiments described above are merely schematic. For example, the flowcharts and structure diagrams in the accompanying drawings show the possible architecture, functions and operations of the devices, methods and computer program products according to multiple embodiments of the present application. In this regard, each box in the flowchart or block diagram can represent a module, a program segment or a part of a code, and the module, a program segment or a part of a code contains one or more executable instructions for implementing the specified logical function. It should also be noted that in an alternative implementation, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the structure diagram and / or the flow diagram, and the combination of boxes in the structure diagram and / or the flow diagram, can be implemented with a dedicated hardware-based system that performs a specified function or action, or can be implemented with a combination of dedicated hardware and computer instructions.

[0112] In addition, the functional modules or units in the various embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.

[0113] If the functions are implemented in the form of software function modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for a computer device (which can be a smart phone, a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods described in the various embodiments of the present application.

[0114] The above description is only a specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application.

Claims

1. A method for implementing a serial communication interface, characterized in that: include: Configuring a timer in the main control module to provide a clock signal for the serial communication interface; Configuring the first signal port of the main control module to provide a chip select signal of the serial communication interface; At least one direct storage access channel of the main control module is configured to be associated with the timer and an address mapping of the direct storage access channel is configured to provide a data transmission channel of the serial communication interface.

2. The method for implementing a serial communication interface according to claim 1, characterized in that: The step of configuring the timer in the main control module to provide a clock signal for the serial communication interface comprises: The working mode of the timer in the main control module is configured as a pulse width modulation output mode, and the clock frequency of the timer is configured as the working frequency of the serial communication interface, so that the timer outputs a clock signal for synchronous communication.

3. The method for implementing a serial communication interface according to claim 1, characterized in that: The method further comprises: Determining the number of direct storage access channels associated with the timer in the main control module according to the line type of the serial communication interface; If the serial communication interface is a four-wire SPI interface, two direct storage access channels are configured; if the serial communication interface is a three-wire SPI interface, one direct storage access channel is configured.

4. The method for implementing a serial communication interface according to claim 1 or 3, characterized in that: If the serial communication interface is a four-wire SPI interface, configuring at least one direct storage access channel of the main control module to be associated with the timer and configuring an address mapping of the direct storage access channel to provide a data transmission channel of the serial communication interface includes: configuring both of the two direct storage access channels of the main control module to be associated with the timer; The memory address of the first direct storage access channel is configured to point to the sending buffer address and the peripheral address of the first direct storage access channel is associated with the second signal port of the main control module; the second signal port is used to provide the master device output and slave device input signals of the four-wire SPI interface; The memory address of the second direct storage access channel is configured to point to the receiving buffer address and the peripheral address of the second direct storage access channel is associated with the third signal port of the main control module; the third signal port is configured as the master device input and slave device output signal of the four-wire SPI interface.

5. The method for implementing a serial communication interface according to claim 4, characterized in that: The method further comprises: The number of signal ports that need to be configured to provide chip select signals for each of the serial communication interfaces is determined according to the number of the multiple external devices that need to be connected; wherein one signal port is used to enable one of the external devices.

6. The method for implementing a serial communication interface according to claim 1 or 3, characterized in that: If the serial communication interface is a three-wire SPI interface, the configuration of the direct storage access channel associated with the timer in the main control module and the address mapping of the direct storage access channel to provide a data transmission channel of the serial communication interface includes: configuring a single direct storage access channel associated with the timer in the main control module; The memory address of the single direct storage access channel is configured to point to the send buffer address when data is sent, and to point to the receive buffer address when data is received; The peripheral address of the single direct storage access channel is associated with the fourth signal port of the main control module; the fourth signal port is used to provide input and output bidirectional signals of the three-wire SPI interface.

7. The method for implementing a serial communication interface according to claim 1, characterized in that: When configuring the direct storage access memory associated with the timer in the main control module, the method further includes: The data transmission length of the direct storage access channel is determined according to the data to be exchanged transmitted by the serial communication interface.

8. A device communication method, characterized in that: Applied to a main control module, the main control module simulates a serial communication interface by the implementation method of the serial communication interface according to any one of claims 1 to 7, and the serial communication interface is used to connect an external device; the device communication method includes: When data needs to be sent and / or received, enabling a first signal port for connecting a chip select signal of the external device; A timer is started to generate a clock signal of the serial communication interface, and data transmission between the main control module and the external device is realized through each of the direct storage access channels.

9. A main control device, characterized in that: The main control device is provided with a plurality of signal ports, a timer, a direct storage access channel and a memory; The timer is configured to provide a clock signal for the serial communication interface; At least one of the direct storage access channels is configured to be associated with the timer and to be configured for address mapping, so as to provide a data transmission channel of the serial communication interface; The first signal port is configured to provide a chip select signal of the serial communication interface.

10. The main control device according to claim 9, characterized in that: The operation mode of the timer is configured as a pulse width modulation output mode, and the clock frequency of the timer is configured as the operation frequency of the serial communication interface, so that the timer outputs a clock signal for synchronous communication.

11. The main control device according to claim 9, characterized in that: The serial communication interface is a four-wire SPI interface, and both of the two direct storage access channels are configured to be associated with the timer; The memory address of the first direct storage access channel is configured to point to the send buffer address and the peripheral address of the first direct storage access channel is associated with the second signal port of the master control device; the second signal port is used to provide the master device output and slave device input signals of the four-wire SPI interface; The memory address of the second direct storage access channel is configured to point to the receiving buffer address and the peripheral address of the second direct storage access channel is associated with the third signal port of the main control device; the third signal port is used to provide the master device input and slave device output signals of the four-wire SPI interface.

12. The main control device according to claim 11, characterized in that: The main control device is used to determine the number of signal ports that need to be configured to provide chip select signals for each of the serial communication interfaces according to the number of multiple external devices that need to be connected; wherein one signal port is used to enable one of the external devices.

13. The main control device according to claim 9, characterized in that: The serial communication interface is a three-wire SPI interface, and a single direct storage access channel is configured to be associated with the timer; The memory address of the single direct storage access channel is configured to point to the send buffer address when data is sent, and to point to the receive buffer address when data is received; The peripheral address of the single direct storage access channel is associated with the fourth signal port of the main control device; the fourth signal port is used to provide input and output bidirectional signals of the three-wire SPI interface.

14. The main control device according to claim 9, characterized in that: The main control device is also used to determine the data transmission length of the corresponding direct storage access channel according to the data to be exchanged transmitted by the serial communication interface as needed.

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