Design method of independent power supply signal channel in N12 chip design

Abstract

The invention provides a design method of an independent power supply signal channel in N12 chip design, which only needs to generate a block module as the independent power supply signal channel, does not need to additionally add an always on cell and replace the type of a Tapcell in a top layer, does not need to independently create a new power supply network to connect the always on cell and the Tapcell, does not need to change the original design flow, and is convenient to use. Therefore, the workload is greatly reduced, the design efficiency is improved, the design quality can be improved, subsequent maintenance is facilitated, if new modification needs to be carried out on the path of signals subsequently, only modification needs to be carried out in the block, winding in the top layer and cell distribution cannot be influenced, and the fault tolerance of the design is greatly improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor design, and in particular to a design method for a separate power supply signal channel in N12 chip design. Background Art

[0002] In many chip designs, a certain signal needs to be powered separately in order to maintain power or be powered by another power supply. In this case, an always on cell (a cell is the smallest unit in a chip) needs to be used in the design of this signal. This type of cell can maintain power when the current power domain stops supplying power. It is often used to keep the retention signal alive.

[0003] In the 12nm process, the always-on cells used are all common nwell type, which have a TVDDpin to connect to another always-on power to ensure the alive of this signal, and the Tapcell in the entire chip design needs to be replaced with a Tapcell with a VPP pin. Therefore, a separate power network needs to be created to connect to the TVDDpin to power these always-on cells. In addition, the VPP pin of the Tapcell needs to be connected to the new power network.

[0004] Specifically, Figure 3 As shown, assuming that a signal from the input port to the A pin of the internal IP of the chip needs to be powered separately so that it can be maintained in the always-on power supply state, it is necessary to use multiple always-oncells 2 to form a signal channel during design, and replace the Tapcell with a Tapcell 3 with a VPP pin. At the same time, it is necessary to create a new always-on power supply network 4 on the original power supply network to power these Tapcells and always-on cells.

[0005] In summary, existing design methods are time-consuming, labor-intensive, and inefficient. They will occupy a large amount of winding resources, and there may be new DRC violation problems at the connection between the power network and the TVDD pin. In addition, if the local netlist needs to be modified later, it will affect the original design, such as interfering with the winding around the original design. Summary of the invention

[0006] Based on this, in order to solve the above technical problems, a design method for a separate power supply signal channel in N12 chip design is provided.

[0007] The technical solution adopted by the present invention is as follows:

[0008] A design method for a separate power supply signal channel in an N12 chip design, characterized in that the method is based on a chip design tool and includes:

[0009] Obtaining a netlist file of the separate power supply signal;

[0010] Planning the route and shape of the separate power supply signal channel on the top layer according to the positions of the output end and the input end of the separate power supply signal on the top layer;

[0011] Read the netlist file, and generate a block module as the separate power supply signal channel according to the route and shape, wherein the routing area of ​​the block module is limited to the M1-M3 layer;

[0012] The block module is read into the top layer and connected to the normally open power domain of the top layer.

[0013] The present invention only needs to generate a block module as a separate power supply signal channel. There is no need to add an additional always on cell in the top layer and change the type of Tapcell. There is no need to create a new power supply network to connect these always on cells and Tapcells. There is no need to change the original design process. This greatly reduces the workload, improves the design efficiency, and can also improve the quality of the design, which is convenient for subsequent maintenance. If the signal needs to be modified later, it only needs to be modified inside the block, which will not affect the winding in the top layer and the distribution of cells, thereby greatly improving the fault tolerance of the design. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The present invention is described in detail below with reference to the accompanying drawings and specific embodiments:

[0015] Figure 1 A flow chart of a method for designing a separate power supply signal channel in an N12 chip design provided by an embodiment of the present invention;

[0016] Figure 2 is a schematic diagram of an embodiment of the present invention;

[0017] Figure 3 The following is a schematic diagram of the existing design method. DETAILED DESCRIPTION

[0018] The following will illustrate the implementation methods of the present invention in conjunction with the drawings in the specification. It should be noted that the implementation methods involved in this specification are not exhaustive and do not represent the only implementation methods of the present invention. The following corresponding embodiments are only for the purpose of clearly illustrating the invention content of the patent of the present invention, and are not intended to limit its implementation methods. For ordinary technicians in this field, different forms of changes and modifications can be made on the basis of the description of this embodiment. All obvious changes or modifications that belong to the technical concept and invention content of the present invention are also within the scope of protection of the present invention.

[0019] An embodiment of the present application provides a method for designing a separate power supply signal channel in an N12 chip design, and the method is based on a chip design tool, such as an ICC2 tool.

[0020] like Figure 1 As shown, the specific process of the method of the embodiment of the present application is as follows:

[0021] S101. Obtain a netlist file of a separate power supply signal.

[0022] The netlist file is generated during the chip front-end design process, and contains the logical connection relationship information of the above-mentioned separate power supply signals.

[0023] S102, planning the route and shape of the separate power supply signal channel on the top layer according to the positions of the output and input ends of the separate power supply signal on the top layer, so that the inlet and outlet of the channel correspond one-to-one with the above output and input ends respectively.

[0024] Generally, the route and shape of the nearest path planning channel that avoids other modules on the top layer can be selected according to the positions of the output and input ends.

[0025] S103 , reading the netlist file, and generating a block module as a separate power supply signal channel according to the above route and shape.

[0026] Among them, the wiring area of ​​the block module is limited to the M1-M3 layer, so that the wiring space of M4-M9 can be reserved for the top layer.

[0027] Specifically, after the netlist file is read in, the initialize_floorplan command in the ICC2 tool is used to design the frame shape of the block module, and complete the placement of the common power supply cells inside the block module and the connection between the common power supply cells.

[0028] S104, read the block module into the top layer, and connect it to the always on power domain of the top layer.

[0029] Specifically, use the set_ref_libs command in the ICC2 tool to read the module into the top level, and then use the create_pg_vias command to connect the top-level always on power and block modules.

[0030] like Figure 2 As shown, assuming that a separate power supply signal from the input port (the output end of the separate power supply signal) to the Apin (the input end of the separate power supply signal) of the internal IP of the chip needs to be powered separately, an L-shaped block module 11 can be generated as a channel for the signal. In this way, it is only necessary to connect the always on power on the top layer to our block module 11. There is no need to add additional always on cells in the top layer and change the type of Tapcell, nor is there a need to create a new power supply network to connect these always on cells and Tapcells. There is no need to change the original design process. This greatly reduces the workload, improves the design efficiency, and can also improve the quality of the design, which is convenient for subsequent maintenance. If this signal needs to be modified later, it only needs to be modified inside the block, which will not affect the winding in the top layer and the distribution of cells, thereby greatly improving the fault tolerance of the design.

[0031] From the above, it can be seen that the design method of a separate power supply signal channel in an N12 chip design provided in an embodiment of the present application reduces the workload, improves the design efficiency and quality, facilitates subsequent maintenance, and greatly improves the fault tolerance of the design.

[0032] Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims

1. A design method for a separate power supply signal channel in an N12 chip design, characterized in that: The method is based on chip design tools, which include: Obtaining a netlist file of the separate power supply signal; Planning the route and shape of the separate power supply signal channel on the top layer according to the positions of the output end and the input end of the separate power supply signal on the top layer; Read the netlist file, and generate a block module as the separate power supply signal channel according to the route and shape, wherein the routing area of ​​the block module is limited to the M1-M3 layers; The block module is read into the top layer and connected to the normally open power domain of the top layer.

2. The method for designing a separate power supply signal channel in an N12 chip design according to claim 1, characterized in that: The chip design tool adopts ICC2 tool.

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