Tensor calculation compiling optimization method and system based on hardware abstraction

Abstract

The invention relates to a tensor calculation compiling optimization method and system based on hardware abstraction. The method comprises the following steps: constructing a hardware model to describe hardware related information; constructing an optimization abstract method commonly used for operator optimization, and decomposing back-end optimization of an operator by a compiler into a flexible combination of a plurality of optimization abstract methods; on the basis of a hardware model and an optimization abstract method selection rule, selecting a proper optimization abstract method combination, and constructing a code generation skeleton; searching undetermined parameters in the code skeleton, pruning a parameter search space by using a hardware model, and storing optional parameters after pruning; and generating a target code suitable for the target computing platform according to the optimized intermediate representation compiled by adopting the optimization abstract method. Compared with the prior art, the method has the advantages of high adaptability, flexible optimization mechanism and efficient adjustment and optimization capability, and is particularly suitable for executing high-performance tensor calculation tasks on a multi-heterogeneous calculation platform.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a tensor computing compilation optimization method and system based on hardware abstraction. Background Art

[0002] With the increasing diversity of hardware architectures, how to efficiently perform deep learning tasks on multiple heterogeneous computing platforms has become a major challenge for current technology. The compiler community has successfully established a powerful modern compiler infrastructure, such as GCC (GNU Compiler Suite), MLIR (Multi-Level Intermediate Representation), and LLVM.

[0003] MLIR (Multi-Level Intermediate Representation) is a general compiler infrastructure that supports multi-level and multi-domain optimization in a modular and extensible way. The design of MLIR allows the construction of different kinds of intermediate representations (IR) at different levels, which makes it very suitable for tensor computing compilation optimization methods based on hardware abstraction. With MLIR, developers can define and use custom intermediate representations to describe hardware abstractions and optimization strategies, and can perform efficient optimizations across multiple levels during the compilation process. At the same time, the flexibility of MLIR enables it to easily adapt to the characteristics of different hardware architectures and achieve efficient code generation for specific hardware platforms, thereby greatly improving the execution efficiency of tensor computing tasks. MLIR is tightly integrated with LLVM and can use LLVM's backend tool chain for code generation. The low-level IR in MLIR can be further converted to LLVM IR, and with the help of LLVM's powerful backend support, highly optimized target code can be generated.

[0004] Modern compilers usually adopt a three-stage architecture, dividing the compiler into the front-end, mid-end, and back-end. The front-end and mid-end are often hardware-independent optimizations that can be reused when supporting new target architectures. However, back-end optimization is closely related to the hardware architecture and cannot be reused. Although this development model has improved the efficiency of compiler porting to a certain extent, for heterogeneous computing platforms, the differences between different hardware architectures are huge, resulting in complex and cumbersome back-end code generation and optimization. The back-end of existing compilers usually needs to be manually adapted for different hardware platforms and write specific optimization codes, which is not only time-consuming and labor-intensive, but also easily leads to poor reusability of optimization strategies between different platforms, reducing compilation efficiency.

[0005] In order to solve the above problems, there is an urgent need for a compilation optimization method that can automatically adapt to multiple heterogeneous computing platforms. Summary of the invention

[0006] In order to solve the above technical problems, the present invention provides a tensor computing compilation optimization method and system based on hardware abstraction to solve the tensor computing compilation optimization problem on multiple heterogeneous computing platforms in the prior art. By introducing hardware abstraction models and optimization abstraction technology, the present invention can flexibly adjust the optimization strategy on a variety of hardware platforms, improve the execution efficiency of tensor computing tasks and the adaptability of the compiler.

[0007] The technical solution of the present invention is: a tensor computing compilation optimization method based on hardware abstraction, comprising:

[0008] Step S1: construct a hardware model to describe hardware related information, wherein the hardware model includes two parts: a module unit description part and an overall unit description part;

[0009] Step S2: construct an optimization abstraction method commonly used for operator optimization. The optimization abstraction method includes the transformation rules for the intermediate representation and the conditions that the hardware needs to meet when using the optimization abstraction method. The compiler's back-end optimization of the operator is decomposed into a flexible combination of several optimization abstraction methods.

[0010] Step S3: Based on the hardware model and the optimization abstract method selection rule, a suitable combination of optimization abstract methods is selected to construct a code generation skeleton;

[0011] Step S4: searching for undetermined parameters in the code skeleton, pruning the parameter search space using the hardware model, and saving the pruned optional parameters;

[0012] Step S5: Generate target code suitable for the target computing platform according to the optimized intermediate representation compiled by using the optimization abstraction method.

[0013] Step S6: Evaluate all generated target codes and select the best configuration.

[0014] A tensor computing compilation optimization system based on hardware abstraction includes the following modules:

[0015] Hardware model building module: used to build a hardware model to describe hardware related information, the hardware model includes two parts: a module unit description part and an overall unit description part;

[0016] Optimization abstract construction module: used to define and construct optimization abstract methods. The optimization abstract methods contain the transformation rules for the intermediate representation and the conditions that the hardware needs to meet when using the optimization abstract methods. The compiler's back-end optimization of the operator is decomposed into a combination of several optimization abstract methods.

[0017] Code skeleton construction module: used to select appropriate optimization abstract method combinations based on the hardware model and the constructed optimization abstract method selection rules to build the code generation skeleton;

[0018] Parameter pruning module: used to search for undetermined parameters in the code generation skeleton, prune the parameter search space using the hardware model, and save the pruned optional parameters;

[0019] Backend code generation module: used to generate target code suitable for the target hardware platform based on the optimized intermediate representation, and to evaluate all generated target codes and select the best configuration.

[0020] Compared with the prior art, the present invention brings the following beneficial effects:

[0021] 1. When performing deep learning model compilation optimization, existing deep learning compilers often directly divide the compilation stack into two layers: hardware-independent optimization and hardware-related. Since the hardware-independent layer lacks hardware-related information, the optimization related to the compilation backend often requires one-to-one adaptation of the calculation and the backend, which not only brings complicated development workload, but also loses the ability to freely combine various optimization methods.

[0022] 2. When performing automatic operator tuning, the existing compilation framework needs to traverse a huge search space due to the lack of guidance from hardware information, and the search time is too long.

[0023] 3. The present invention introduces a hardware abstract model to uniformly describe the computing units and memory structures of different hardware platforms. At the same time, it combines the optimization abstraction technology to automatically adjust the optimization strategy according to the hardware characteristics during the compilation process, thereby improving the adaptability and optimization efficiency of the compiler. It not only simplifies the development process of the compiler backend, but also enables efficient tensor calculation optimization on different hardware platforms. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 It is a flowchart of a tensor computing compilation optimization method based on hardware abstraction in an embodiment of the present invention;

[0025] Figure 2 A diagram for constructing a hardware memory hierarchy in an embodiment of the present invention;

[0026] Figure 3 A schematic diagram of constructing a computing hierarchy in an embodiment of the present invention;

[0027] Figure 4 A schematic diagram of the overall hardware hierarchy in an embodiment of the present invention;

[0028] Figure 5 This is a schematic diagram of block optimization in an embodiment of the present invention;

[0029] Figure 6 A schematic diagram of memory localization optimization in an embodiment of the present invention;

[0030] Figure 7 It is a schematic diagram of pipeline optimization in an embodiment of the present invention;

[0031] Figure 8 A schematic diagram of generating high-performance target code suitable for a target computing platform in an embodiment of the present invention;

[0032] Fig. 9 It is a schematic block diagram of a tensor computing compilation optimization system based on hardware abstraction in an embodiment of the present invention. DETAILED DESCRIPTION

[0033] The present invention provides a tensor computing compilation optimization method and system based on hardware abstraction, designs a unified hardware abstraction applicable to different hardware, and builds a set of optimization pipelines based on it.

[0034] In order to make the purpose, technical solutions and advantages of the present invention more clear, the present invention is further described in detail below through specific implementations and in conjunction with the accompanying drawings.

[0035] Embodiment 1

[0036] like Figure 1 As shown, a tensor computing compilation optimization method based on hardware abstraction provided by an embodiment of the present invention includes the following steps:

[0037] Step S1: construct a hardware model to describe hardware related information, wherein the hardware model includes two parts: a module unit description part and an overall unit description part;

[0038] Step S2: construct an optimization abstraction method commonly used for operator optimization. The optimization abstraction method includes the transformation rules for the intermediate representation and the conditions that the hardware needs to meet when using the optimization abstraction method. The back-end optimization of the compiler for the operator is decomposed into a combination of several optimization abstraction methods.

[0039] Step S3: Based on the hardware model and the optimization abstract method selection rules, select a suitable combination of optimization abstract methods to build a code generation skeleton; wherein the optimization abstract method selection rules refer to selecting a suitable optimization abstraction based on the limitations of the hardware model, combined with the experience of experts and existing performance analysis results.

[0040] Step S4: searching for undetermined parameters in the code skeleton, pruning the parameter search space using the hardware model, and saving the pruned optional parameters;

[0041] Step S5: Generate target code suitable for the target computing platform according to the optimized intermediate representation compiled by using the optimization abstraction method.

[0042] Step S6: Evaluate all generated target codes and select the best configuration.

[0043] In one embodiment, the above step S1: constructing a hardware model to describe hardware related information, the hardware model includes two parts: a module unit description part and an overall unit description part, including: by analyzing the target hardware, a complete hardware model is obtained, specifically including:

[0044] Step S11: Analyze the basic component modules of the target hardware, including analysis of the computing unit level and analysis of the storage unit level.

[0045] Storage units play a vital role in hardware architecture, and their performance directly affects the computing efficiency of the entire system. Specifically, the properties of storage units include the following aspects:

[0046] Basic attributes: including the name and type of storage unit, such as cache, register, global memory, shared memory, etc. Each storage unit has its specific role and purpose and needs to be accurately identified and distinguished.

[0047] Size information: describes the capacity of the storage unit. The size of the storage unit directly affects how data is stored and its availability during computation. For example, a larger cache or global memory can store more data, but has a higher access latency; while a register has a small capacity but is very fast to access.

[0048] Storage bandwidth: refers to the data transfer capacity of a storage unit, usually measured in GB / s (gigabytes per second). Storage bandwidth affects the speed of data transfer and is critical to data-intensive tasks in high-performance computing.

[0049] Programmability of the storage hierarchy: This property describes whether storage units can be explicitly requested and managed. For example, some levels of storage (such as shared memory or registers) can be explicitly allocated and used by the programmer through a programming interface.

[0050] Concurrent read capability: The bank structure of a storage unit describes its concurrent access capability. Multiple banks allow multiple threads or computing units to access different data at the same time, thereby improving the parallelism and data throughput of the storage unit.

[0051] Computational units contain actual or logical computing units. Computational units usually have a multi-level organizational structure in the hardware architecture, which determines how computing tasks are divided and allocated to different hardware resources. In addition, the properties of the computing unit should also include a description of the nature of the hardware instructions:

[0052] Instruction vectorization width: The instruction vectorization width describes the number of data elements that a single instruction can act on simultaneously. Modern computing units usually support SIMD (Single Instruction, Multiple Data) instructions, which can process multiple data elements in one operation, thereby improving computing efficiency.

[0053] Instruction latency and throughput: Instruction latency refers to the time required from the issuance of an instruction to its completion, usually expressed in clock cycles. Different types of instructions have different latency characteristics. Complex instructions such as floating-point division usually have longer latency, while simple instructions such as addition have shorter latency. Instruction throughput refers to the number of instructions that a computing unit can complete per unit time. High throughput means that the computing unit can quickly process a large number of instructions, improving overall computing efficiency.

[0054] Instruction-level parallelism: Instruction-Level Parallelism (ILP) refers to the ability of a computing unit to execute multiple instructions in parallel within the same clock cycle when executing a program.

[0055] Step S12: construct the overall unit description part responsible for describing the hierarchical relationship between module units, based on the basic component modules of the target hardware analyzed in S11, and in combination with the design of the target hardware, construct the organizational information between the modules.

[0056] The overall unit description part is responsible for describing the hierarchical relationship and thread organization between module units. The hardware structure consists of multiple nested hardware blocks. In each layer of hardware blocks, the processing unit organization at the current level and the module unit information contained therein are described. The module unit description part describes the computing unit and memory unit conditions at this level, and constructs the parent and child blocks of the hardware block. At the same time, for the innermost processing unit, a complete description of the hardware instruction-related information is mounted on the block. After constructing the tree relationship between the hardware blocks, the access relationship between the hardware can be analyzed. The child hardware block can access the module unit of the parent hardware block, but not vice versa. Hardware blocks without a parent-child relationship cannot access each other's internal module units.

[0057] The following describes how to build a hardware model using NVIDIA GPU as an example.

[0058] Based on the above steps, the hardware model of NVIDIA GPU is constructed. NVIDIA GPU storage hierarchy is divided into three levels: global memory, shared memory, and register file. The properties of the three levels are as follows Figure 2 As shown in Figure 1. NVIDIA GPU is divided into computing levels such as thread grid, thread block, thread bundle, and thread. The properties of several computing levels are as follows: Figure 3Based on a comprehensive analysis of GPU hardware, the overall unit description of the hierarchical relationship between building block units is shown in Figure 4 shown.

[0059] Step S2: Construct an optimization abstraction method commonly used for operator optimization. The optimization abstraction method includes the transformation rules for the intermediate representation and the conditions that the hardware needs to meet when using the optimization abstraction method. The compiler's back-end optimization of the operator is decomposed into a flexible combination of several optimization abstraction methods.

[0060] In one embodiment, the above step S2 specifically includes:

[0061] Step S21: define an optimization abstraction, express the optimization abstraction as making specific modifications to the intermediate representation when a specific pattern in the intermediate representation is recognized; and set hardware requirements for using the optimization abstraction method.

[0062] The definition of optimization abstraction is to abstract the complex optimization process and express it as a mechanism to identify specific patterns in the intermediate representation (IR) and perform corresponding transformations. Therefore, when the optimization abstraction recognizes a certain pattern in the IR (such as matrix multiplication or data parallel operation), specific modifications are made to these patterns to improve computational efficiency, data locality, or resource utilization. Specific modifications are modifications to specific patterns, such as dividing the matrix multiplication into blocks when the pattern is to identify the operation of matrix multiplication. In addition, in order to ensure the availability of optimization, corresponding hardware requirements are also set. These requirements usually include support for specific instruction sets, hardware features (such as local memory, vectorization capabilities), or configuration of parallel computing resources.

[0063] In the process of building the optimization abstraction method, the present invention widely reuses components of various dialects in MLIR. The dialects in MLIR can be regarded as a set of operators and types that can provide support for specific fields or hardware architectures. When building the optimization abstraction, we give priority to hardware-independent dialects such as Linalg (for the description of linear algebra operations), SCF (for the representation of control flow), Vector (for the representation of vectorized operations), and Memref (for the description of memory references). Through these dialects, we can describe the logic and process of the optimization abstraction without relying on specific hardware implementations.

[0064] Step S22: construct a general optimization abstract method, including block optimization, local memory optimization, pipeline optimization, and vectorization optimization.

[0065] Defining data block optimization: Block optimization requires that there is no data dependency in the calculation of the block dimension. Block technology breaks down large data blocks into smaller sub-data blocks, so that these sub-data blocks can be stored in different levels of storage units and processed by different levels of computing units. Figure 5 The scenario of block optimization in optimizing matrix multiplication applications is demonstrated, and the matrix multiplication operator is divided into three levels: thread block, thread bundle, and instruction.

[0066] Defining data locality optimization: Data locality optimization requires the presence of local caches in the hardware unit. The optimization method is implemented by detecting reads and writes to higher-level memory in the IR, converting them to copies of higher-level memory to local memory, and converting reads and writes to higher-level memory in the IR to reads and writes to local memory. Figure 6 Shows the modifications to the IR caused by data locality optimization.

[0067] Define the optimization of the computing pipeline: Pipeline optimization requires hardware to support instruction set parallelism, allowing multiple instructions to be completed on different execution units in the same clock cycle, thereby achieving the purpose of delay masking. Figure 7 Demonstrated the application scenarios of computational pipeline optimization.

[0068] Vectorization optimization requires that the hardware computing unit supports vectorized instructions and can operate multiple data in a single instruction. By dividing the computing instructions or memory access instructions into blocks of vectorized computing size in the innermost layer of computing, vectorization optimization can be quickly implemented.

[0069] Step S23: According to different computing tasks, a specific optimization method for a specific task is implemented based on the construction method of the optimization abstract method. This step includes: for some specific optimization scenarios, the compiler staff constructs a new hardware-independent optimization according to the optimization abstract construction method proposed in step S21, and completes the supplementation of the new optimization.

[0070] In one embodiment, the above step S3: based on the hardware model and the optimization abstract method selection rule, selecting a suitable combination of optimization abstract methods to construct a code generation skeleton specifically includes:

[0071] Step S31: Traverse all available optimization abstraction methods. Optimization abstraction includes a series of technologies that have been proven to improve computing performance, such as data segmentation, instruction vectorization, data localization, and pipeline parallelism. Each optimization abstraction has its corresponding hardware requirements. For example, vectorization requires hardware support for the SIMD (Single Instruction, Multiple Data) instruction set, and data localization optimization requires the existence of low-latency local memory (such as shared memory or registers). During the traversal process, the system will evaluate each optimization abstraction method based on the characteristics of the current hardware model (such as the hardware's memory hierarchy, parallel computing capabilities, instruction set support, etc.), and screen out those optimization abstraction methods that are feasible under the current hardware environment.

[0072] Step S32: Construct the most original optimization abstract method selection rules based on the expert's experience, select the available optimization abstract method according to the optimization selection rules, and transform the intermediate representation to form a code skeleton. The system will construct the most original optimization abstract method selection rules based on the expert's experience and the existing performance analysis results. The rule set describes under what circumstances a specific combination of optimization abstract methods should be selected to maximize hardware performance. Specifically, these rules will guide the selection of optimization abstract methods based on hardware characteristics, the nature of the computing task, and the actual operating environment.

[0073] 1. When the computing task involves large-scale matrix operations or convolution operations, data block abstraction is preferred to make full use of the hardware's on-chip memory resources and reduce dependence on global memory.

[0074] 2. When there are frequently accessed intermediate data in a task, data localization abstraction should be selected and the data should be placed in the shared memory of the hardware to reduce the bottleneck of global memory access.

[0075] 3. Vectorization selection rules: For operations that can be performed on SIMD instructions (such as vector addition and multiplication), instruction vectorization abstraction is preferred to improve the parallelism of calculations and the efficiency of instruction execution.

[0076] 4. For complex computing tasks with clear dependencies that can be executed in stages (such as hierarchical operations in deep learning), pipeline parallel abstraction should be selected to fully utilize the multiple execution units of the hardware and improve throughput.

[0077] These rules will be dynamically adjusted in actual applications to form a more adaptable combination of optimization strategies. Through the combination of these optimization abstractions and rules, the IR is finally transformed to generate a code skeleton that conforms to the characteristics of the hardware, thereby maximizing the performance advantages of the hardware.

[0078] In one embodiment, the above step S4: searching for undetermined parameters in the code skeleton, pruning the parameter search space using the hardware model, and saving the pruned optional parameters specifically includes:

[0079] Step S41: Determine the parameter search space of the parameters to be optimized. First, identify the undetermined parameters in the code skeleton, which may include the calculation block size, the number of threads, the memory allocation strategy, etc. These parameters have an important impact on the performance of the final generated code, so it is necessary to define their initial parameter search space. The parameter search space should cover all possible parameter configurations and ensure that it matches the capacity and characteristics of hardware resources (such as registers, shared memory, etc.). At the same time, the computing requirements of the task should also be considered to define a sufficiently broad search space to ensure the flexibility and comprehensiveness of the optimization.

[0080] Step S42: Use the hardware model to prune the parameter search space and exclude parameter combinations that cannot effectively utilize hardware resources. Since the complete parameter search space is usually too large and direct search is inefficient, it is necessary to use the hardware model for pruning. The hardware model provides an abstract description of hardware characteristics and can predict the actual execution effect of different parameter combinations. By analyzing the hardware model, the system can identify those parameter combinations that cannot fully utilize hardware resources, such as those that cause memory overload or cannot fully utilize the configuration of the computing unit, and exclude these inappropriate combinations from the parameter search space. The pruned parameter search space is more compact, which reduces unnecessary computing overhead and improves optimization efficiency.

[0081] Step S43: Use the hardware model to evaluate by calculating the data reuse score at each memory level to obtain several configurations with higher data reuse scores. In the pruned parameter search space, the hardware model is further used to perform a detailed evaluation of different parameter configurations. The core indicator of the evaluation is the data reuse score, which reflects the efficiency of multiple uses of data at different memory levels. By calculating the data reuse score of each configuration, the system can determine which parameter configurations can maximize memory bandwidth utilization and reduce memory access latency. Finally, several configurations with higher data reuse scores are saved to ensure that the generated code can run efficiently on the target hardware. Here, higher refers to, for example, scores occupying the top 5%-10% of the positions, or other score configurations. Those skilled in the art can configure according to actual needs, and the present invention is not limited in this respect.

[0082] In one embodiment, the above step S5: generating target code suitable for the target computing platform according to compiling the optimized intermediate representation using the optimization abstraction method specifically includes the following steps:

[0083] You can refer to Figure 8 Understand the description of the following steps, Figure 8 Shows the transformation of hardware-independent IR to hardware-dependent IR.

[0084] Step S51: Map hardware-independent compute unit indexes to hardware-specific compute unit indexes. The compiler first analyzes the compute unit indexes in the hardware-independent intermediate representation (IR), such as logical threads, block indexes, etc. These indexes are hardware-independent and not bound to a specific hardware platform. Next, the compiler maps these abstract indexes to specific physical compute unit indexes on the target hardware platform. For example, in a GPU architecture, a logical thread may be mapped to a specific thread index, and a logical block may be mapped to a specific thread block index.

[0085] Step S52: Map hardware-independent computation and memory access instructions to computation and memory access instructions on specific hardware. The compiler converts the hardware-independent instructions in the intermediate representation into a low-level instruction set that is compatible with the target hardware platform. This includes mapping abstract computation instructions (such as matrix multiplication) to instructions supported by specific hardware (such as matrix multiplication plus mma instructions), and mapping abstract memory access operations (such as load and store) to memory access instructions of the target platform.

[0086] In one embodiment, the above step S6: evaluating all generated target codes and selecting the best configuration therein specifically includes:

[0087] Actual measurements are made on the generated code to find the optimal configuration, and the relevant information is used to optimize the abstract selection rules when the code skeleton is generated in step S3.

[0088] Embodiment 2

[0089] like Fig. 9 As shown, an embodiment of the present invention provides a tensor computing compilation optimization system based on hardware abstraction, including the following modules:

[0090] Hardware model building module 81: used to build a hardware model to describe hardware related information, the hardware model includes two parts: a module unit description part and an overall unit description part. This module builds a complete hardware model that reflects the hardware characteristics by analyzing the hardware computing unit and storage unit hierarchy, as well as the hierarchical relationship between module units.

[0091] Optimization abstract construction module 82: used to define and construct optimization abstract methods, which include transformation rules for intermediate representations and conditions that the hardware needs to meet when using the optimization abstract methods, and decompose the compiler's back-end optimization of operators into a combination of several optimization abstract methods. This module includes general optimization methods such as block optimization, local memory optimization, pipeline optimization, and vectorization optimization, and implements targeted optimization methods according to different computing tasks.

[0092] Code skeleton construction module 83: used to select appropriate optimization abstract method combinations based on the hardware model and the constructed optimization abstract method selection rules to construct a code generation skeleton. This module uses the experience of experts and optimization selection rules to select the optimization abstraction that best suits the current task and form an efficient code structure.

[0093] Parameter pruning module 84: used to search for undetermined parameters in the code generation skeleton, prune the parameter search space using the hardware model, and save the pruned optional parameters. This module uses the hardware model to evaluate the feasibility of the parameters, excludes those parameter combinations that cannot effectively utilize hardware resources, and optimizes the parameter configuration according to the data reuse score at the memory level.

[0094] Backend code generation module 85: used to generate target code suitable for the target hardware platform based on the optimized intermediate representation, and evaluate all generated target codes to select the best configuration. This module is responsible for mapping hardware-independent computing units and memory access instructions to specific computing and memory access instructions on specific hardware to ensure that the generated code can maximize the use of hardware resources.

[0095] The above embodiments are provided only for the purpose of describing the present invention, and are not intended to limit the scope of the present invention. The scope of the present invention is defined by the appended claims. Various equivalent substitutions and modifications made without departing from the spirit and principles of the present invention should all be included within the scope of the present invention.

Claims

1. A tensor computing compilation optimization method based on hardware abstraction, characterized in that: include: Step S1: construct a hardware model to describe hardware related information, wherein the hardware model includes two parts: a module unit description part and an overall unit description part; Step S2: construct an optimization abstraction method commonly used for operator optimization. The optimization abstraction method includes the transformation rules for the intermediate representation and the conditions that the hardware needs to meet when using the optimization abstraction method. The compiler's back-end optimization of the operator is decomposed into a flexible combination of several optimization abstraction methods. Step S3: Based on the hardware model and the optimization abstract method selection rule, a suitable combination of optimization abstract methods is selected to construct a code generation skeleton; Step S4: searching for undetermined parameters in the code skeleton, pruning the parameter search space using the hardware model, and saving the pruned optional parameters; Step S5: Generate target code suitable for the target computing platform according to the intermediate representation compiled by the optimization abstraction method; Step S6: Evaluate all generated target codes and select the best configuration.

2. The tensor computing compilation optimization method based on hardware abstraction according to claim 1, characterized in that: The step S1: constructing a hardware model to describe hardware related information, the hardware model comprises two parts: a module unit description part and an overall unit description part including: Step S11: analyzing the basic component modules of the target hardware, including analysis of the computing unit level and analysis of the storage unit level; Step S12: construct the overall unit description part responsible for describing the hierarchical relationship between module units; construct the organizational information between the modules based on the basic component modules of the target hardware analyzed in S11 and in combination with the design of the target hardware.

3. The tensor computing compilation optimization method based on hardware abstraction according to claim 1, characterized in that: The step S2: constructs an optimization abstraction method commonly used for operator optimization, wherein the optimization abstraction method includes transformation rules for intermediate representations and conditions that the hardware needs to meet when using the optimization abstraction method, and decomposes the back-end optimization of the operator by the compiler into a flexible combination of several optimization abstraction methods, including: Step S21: defining an optimization abstraction, expressing the optimization abstraction as a certain pattern recognized in the intermediate representation, making specific modifications to the intermediate representation, and setting hardware requirements that can use the optimization method; Step S22: constructing a general optimization abstract method, including block optimization, local memory optimization, pipeline optimization, and vectorization optimization; Step S23: According to different computing tasks, a specific optimization method for a certain task is implemented based on the construction method of the optimization abstract method.

4. The tensor computing compilation optimization method based on hardware abstraction according to claim 1, characterized in that: In step S3, based on the hardware model and the optimization abstract method selection rule, a suitable combination of optimization abstract methods is selected to construct a code generation skeleton, including: Step S31: traverse all available optimization abstraction methods, and select available optimization abstraction methods according to the requirements of the optimization abstraction methods on the hardware model; Step S32: Construct the most original optimization abstract method selection rule based on the expert's experience, select the available optimization abstract method according to the optimization selection rule, and transform the intermediate representation to form a code skeleton.

5. The tensor computing compilation optimization method based on hardware abstraction according to claim 1, characterized in that: The step S4: searching for undetermined parameters in the code skeleton, pruning the parameter search space using the hardware model, and saving the pruned optional parameters, includes: Step S41: determining a parameter search space of parameters to be optimized; Step S42: pruning the parameter search space using the hardware model to exclude parameter combinations that cannot effectively utilize hardware resources; Step S43: using the hardware model to evaluate at each memory level by calculating the data reuse score, and obtaining several configurations with higher data reuse scores.

6. The tensor computing compilation optimization method based on hardware abstraction according to claim 1, characterized in that: The step S5: generating target code suitable for the target computing platform according to the intermediate representation compiled by the optimization abstraction method, comprises: Step S51: Mapping the hardware-independent computing unit index to a hardware-specific computing unit index; Step S52: Mapping hardware-independent computing and memory access instructions to computing and memory access instructions on specific hardware.

7. A tensor computing compilation optimization system based on hardware abstraction, characterized in that: Includes the following modules: Hardware model building module: used to build a hardware model to describe hardware related information, the hardware model includes two parts: a module unit description part and an overall unit description part; Optimization abstract construction module: used to define and construct optimization abstract methods. The optimization abstract methods contain the transformation rules for the intermediate representation and the conditions that the hardware needs to meet when using the optimization abstract methods. The compiler's back-end optimization of the operator is decomposed into a combination of several optimization abstract methods. Code skeleton construction module: used to select appropriate optimization abstract method combinations based on the hardware model and the constructed optimization abstract method selection rules to build the code generation skeleton; Parameter pruning module: used to search for undetermined parameters in the code generation skeleton, prune the parameter search space using the hardware model, and save the pruned optional parameters; Backend code generation module: used to generate target code suitable for the target hardware platform based on the optimized intermediate representation, and to evaluate all generated target codes and select the best configuration.

Images